1PS8511A 02/06/01
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PI74AVC+16836
2.5V 20-Bit Universal Bus
Driver with 3-State Outputs
Logic Block Diagram
Product Features
•PI74AVC+16836 is designed for low voltage operation,
VCC = 1.65V to 3.6V
•True ±24mA Balanced Drive @ 3.3V
•IOFF supports partial power-down operation
•3.6V I/O Tolerant inputs and outputs
•Meets PC133 SDRAM Registered DIMM Specifications
• All outputs contain a patented DDC
(Dynamic Drive Control) circuit that reduces noise without
degrading propagation delay
• Industrial operation at –40°C to +85°C
• A vailable Packages:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductor’s PI74AVC+ series of logic circuits are
produced using the Company’s advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The 20-bit PI74AVC+16836 universal bus driver is designed
for 1.65V to 3.6V Vcc operation.
Data flow from A to Y is controlled by the Output Enable (OE) input.
The device operates in the transparent mode when the latch-enable
(LE) input is LOW. When LE is HIGH, the A data is latched if the
clock (CLK) input is held at a high or low logic level. If LE is HIGH,
the A data is stored in the latch/flip-flop on the low-to-high
transition of CLK. When OE is HIGH, the outputs are in the high-
impedance state, but all the inputs are enabled and data is capable
of being stored in the register.
To ensure the high-impedance state during power up or power
down, OE should be tied to Vcc through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
OE
CLK
LE
A1
1
56
29
55
1D
CLK
C1 Y1
2
V
TO 19 OTHER CHANNELS
PI74AVC+16836
2.5V 20-Bit Universal Bus
Driver with 3-State Outputs
2PS8511A 02/06/01
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Truth Table(1)
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
25
26
27
28
32
31
30
29
CLK
A1
A2
GND
A3
A4
VCC
A5
A6
A7
GND
A8
A9
A10
A11
A12
A13
GND
A14
A15
A16
VCC
A17
A18
GND
A19
A20
LE
OE
Y1
Y2
GND
Y3
Y4
VCC
Y5
Y6
Y7
GND
Y8
Y9
Y10
Y11
Y12
Y13
GND
Y14
Y15
Y16
VCC
Y17
Y18
GND
Y19
Y20
NC
56-Pin
A, K
Product Pin Description
Note:
1 H =High Signal Level
L =Low Signal Level
Z =High Impedance
↑=Transition LOW-to-HIGH
X =Irrelevant
2. Output level before the indicated steady-state input
conditions were established.
stupnI stuptuO Y
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LLXLL
LLXHH
LH↑LL
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ccVrewoP
PI74AVC+16836
2.5V 20-Bit Universal Bus
Driver with 3-State Outputs
3PS8511A 02/06/01
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Recommended Operating Conditions(1)
Notes:
1. All unused inputs must be held at VCC or GND to ensure proper device operation.
.niM.xaMstinU
V
CC
egatloVylppuS gnitarepO 56.16.3
V
ylnonoitneterataD 2.1
V
HI
egatloVtupnIlevel-hgiH
V
CC
V2.1= V
CC
V
CC
V59.1otV56.1= x56.0V
CC
V
CC
V7.2otV3.2= 7.1
V
CC
V6.3otV3= 2
V
LI
egatloVtupnIlevel-woL
V
CC
V2.1= dnG
V
CC
V59.1otV56.1= x53.0V
CC
V
CC
V7.2otV3.2= 7.0
V
CC
V6.3otV3= 8.0
V
I
egatloVtupnI 06.3
V
O
egatloVtuptuO etatSevitcA 0V
CC
etatS-3 06.3
I
HO
tnerructuptuolevel-hgiH
V
CC
V59.1otV56.1= 6–
Am
V
CC
V7.2otV3.2= 21–
V
CC
V6.3otV3= 42–
I
LO
tnerructuptuolevel-woL
V
CC
V59.1otV56.1= 6
V
CC
V7.2otV3.2= 21
V
CC
V6.3otV3= 42
∆t∆etarllafroesirnoitisnarttupnIv V
CC
V6.3otV56.1=5V/sn
T
A
erutarepmetria-eerfgnitarepO 04–58C°
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other
conditions above those indicated in the opera-
tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply voltage range, VCC ............................................................................................ –0.5V to +4.6V
Input voltage range, VI.................................................................................................... –0.5V to +4.6V
Voltage range applied to any output in the
high-impedance or power-off state, VO(1) ............................................................ –0.5V to +4.6V
Voltage range applied to any output in the
high or low state, VO(1,2)........................................................................................ –0.5V to V CC +0.5V
Input clamp current, IIK (VI <0) ............................................................................ –50mA
Output clamp current, IOK (VO <0) ...................................................................... –50mA
Continuous output current, IO...................................................................................................... ±50mA
Continuous current through each VCC or GN D .................................................±100mA
Package thermal impedance, θJA(3): package A.................................................... 64°C/W
package K ................................................... 48°C/W
Storage Temperature range, Tstg .............................................................................. –65°C to 150°C
Notes:
1. Input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed.
2. Output positive-voltage rating may be exceeded up to 4.6V maximum if theoutput current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
PI74AVC+16836
2.5V 20-Bit Universal Bus
Driver with 3-State Outputs
4PS8511A 02/06/01
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sretemaraPsnoitidnoCtseT
)1(
V
CC
.niM.xaMstinU
V
HO
I
HO
001–=µAV6.3otV56.1 V
CC
V2.0–
V
I
HO
6–=m VA
HI
V70.1=V56.12.1
I
HO
21–=m VA
HI
V7.1=V3.257.1
I
HO
42–=m VA
HI
V2=V30.2
V
LO
I
LO
001= µAV6.3otV56.12.0
I
LO
6=m VA
HI
V75.0=V56.154.0
I
LO
21=m VA
HI
V7.0= V3.255.0
I
LO
42=m VA
HI
V8.0=V38.0
I
I
stupnIlortnoCV
I
V=
CC
DNGroV6.35.2±
µA
I
FFO
V
I
Vro
O
V6.3=001±
I
ZO
V
I
V=
CC
DNGro V6.301±
I
CC
V
O
V=
CC
IDNGro
O
0=V6.304
C
I
stupnIlortnoC V
I
V=
CC
DNGro
V5.24
Fp
V3.34
stupnIataD V5.26
V3.36
C
O
stuptuOV
O
V=
CC
DNGro V5.28
V3.38
Note: Typical values are measured at TA = 25°C.
DC Electrical Characteristics (Over the Operating Range, TA = –40°C +85°C)
PI74AVC+16836
2.5V 20-Bit Universal Bus
Driver with 3-State Outputs
5PS8511A 02/06/01
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sretemaraP morF )tupnI( oT )tuptuO(
V
CC
V2.1= V
CC
V5.1= V1.0± V
CC
V8.1= V51.0± V
CC
V5.2= V2.0± V
CC
V3.3= V3.0± stinU
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Y
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t
ne
EO5.15.50.15.40.10.4
t
sid
EO5.10.50.15.40.10.4
Timing Requirements (Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4)
Switching Characteristics over recommended operating free-air temperature range
(unless otherwise noted, see Figures 1 thru 4)
Operating Characteristics, TA= 25°C
sretemaraP tseT snoitidnoC
V
CC
V8.1= V1.0± V
CC
V5.2= V2.0± V
CC
V3.3= V3.0± stinU
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C
dp
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L
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V2.1=ccV V5.1=ccV V1.0± V8.1=ccV V51.0± V5.2=ccV V2.0± V3.3=ccV V3.0±
stinU
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PI74AVC+16836
2.5V 20-Bit Universal Bus
Driver with 3-State Outputs
6PS8511A 02/06/01
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PARAMETER MEASUREMENT INFORMATION
VCC = 1.2V AND 1.5V ± 0.1V
Load Circuit
Voltage Waveforms
Propagation Delay Times Voltage Waveforms
Enable and Disable Times
Voltage Waveforms
Pulse Duration
tseT1S
t
dp
t
ZLP
t/
LZP
t
ZHP
t/
HZP
nepO Vx2
CC
DNG
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
Figure 1. Load Circuit and Voltage Waveforms
2Ω
2Ω
2xVCC
Open
GND
S1
From Output
Under Test
CL = 15pF
(See Note A)
t
PZL
Output
Control
(Low Level
Enabling) 0V
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
t
PLZ
t
PHZ
V
OL
V
CC
0V
t
PZH
+0.1V
–0.1V
Output
Waveform 1
S1 at 2 x V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OH
V
OH
V
OL
V
CC
Input
t
PLH
t
PHL
0V
Output
V
OH
V
OL
V
CC
/2 V
CC
/2
V
CC
/2
V
CC
VCC/2
Input
t
W
V
CC
/2
V
CC
V
CC
/2
0V
Data
Input
tsu th
VCC/2
VCC
VCC/2
0V
VCC
0V
Timing
Input VCC/2
Voltage Waveforms
Setup and Hold Times
PI74AVC+16836
2.5V 20-Bit Universal Bus
Driver with 3-State Outputs
7PS8511A 02/06/01
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PARAMETER MEASUREMENT INFORMATION
VCC = 1.8V ±0.15V
Load Circuit
Voltage Waveforms
Propagation Delay Times Voltage Waveforms
Enable and Disable Times
Voltage Waveforms
Pulse Duration
tseT1S
t
dp
t
ZLP
t/
LZP
t
ZHP
t/
HZP
nepO Vx2
CC
DNG
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having these characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
Figure 2. Load Circuit and Voltage Waveforms
2Ω
2Ω
2xVCC
Open
GND
S1
From Output
Under Test
CL = 15pF
(See Note A)
t
PZL
Output
Control
(Low Level
Enabling) 0V
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
t
PLZ
t
PHZ
V
OL
V
CC
0V
t
PZH
+0.1V
–0.1V
Output
Waveform 1
S1 at 2 x V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OH
V
OH
V
OL
V
CC
Input
t
PLH
t
PHL
0V
Output
V
OH
V
OL
V
CC
/2 V
CC
/2
V
CC
/2
V
CC
VCC/2
Input
t
W
V
CC
/2
V
CC
V
CC
/2
0V
Data
Input
tsu th
VCC/2
VCC
VCC/2
0V
VCC
0V
Timing
Input VCC/2
Voltage Waveforms
Setup and Hold Times
1 kΩ
1 kΩ
0.15V
0.15V
30
PI74AVC+16836
2.5V 20-Bit Universal Bus
Driver with 3-State Outputs
8PS8511A 02/06/01
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PARAMETER MEASUREMENT INFORMATION
VCC = 2.5V ± 0.2V
Load Circuit
Voltage Waveforms
Propagation Delay Times Voltage Waveforms
Enable and Disable Times
Voltage Waveforms
Pulse Duration
tseT1S
t
dp
t
ZLP
t/
LZP
t
ZHP
t/
HZP
nepO Vx2
CC
DNG
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having these characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
Figure 3. Load Circuit and Voltage Waveforms
2Ω
2Ω
2xVCC
Open
GND
S1
From Output
Under Test
CL = 15pF
(See Note A)
t
PZL
Output
Control
(Low Level
Enabling) 0V
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
t
PLZ
t
PHZ
V
OL
V
CC
0V
t
PZH
+0.15V
–0.15V
Output
Waveform 1
S1 at 2 x V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OH
V
OH
V
OL
V
CC
Input
t
PLH
t
PHL
0V
Output
V
OH
V
OL
V
CC
/2 V
CC
/2
V
CC
/2
V
CC
VCC/2
Input
t
W
V
CC
/2
V
CC
V
CC
/2
0V
Data
Input
tsu th
VCC/2
VCC
VCC/2
0V
VCC
0V
Timing
Input VCC/2
Voltage Waveforms
Setup and Hold Times
500Ω
500Ω
30
PI74AVC+16836
2.5V 20-Bit Universal Bus
Driver with 3-State Outputs
9PS8511A 02/06/01
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PARAMETER MEASUREMENT INFORMATION
VCC = 3.3V ± 0.3V
Load Circuit
Voltage Waveforms
Propagation Delay Times Voltage Waveforms
Enable and Disable Times
Voltage Waveforms
Pulse Duration
tseT1S
t
dp
t
ZLP
t/
LZP
t
ZHP
t/
HZP
nepO Vx2
CC
DNG
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having these characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
Figure 4. Load Circuit and Voltage Waveforms
2Ω
2Ω
2xVCC
Open
GND
S1
From Output
Under Test
CL = 15pF
(See Note A)
t
PZL
Output
Control
(Low Level
Enabling) 0V
V
CC
/2
V
CC
/2
V
CC
/2
V
CC
/2
t
PLZ
t
PHZ
V
OL
V
CC
0V
t
PZH
+0.1V
–0.1V
Output
Waveform 1
S1 at 2 x V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OH
V
OH
V
OL
V
CC
Input
t
PLH
t
PHL
0V
Output
V
OH
V
OL
V
CC
/2 V
CC
/2
V
CC
/2
V
CC
VCC/2
Input
t
W
V
CC
/2
V
CC
V
CC
/2
0V
Data
Input
tsu th
VCC/2
VCC
VCC/2
0V
VCC
0V
Timing
Input VCC/2
Voltage Waveforms
Setup and Hold Times
500Ω
500Ω
0.3V
0.3V
30
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
