DS96F172MQML, DS96F174MQML
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SNOSAS8A –APRIL 2011–REVISED APRIL 2013
DS96F172MQML/DS96F174MQML EIA-485/EIA-422 Quad Differential Drivers
Check for Samples: DS96F172MQML,DS96F174MQML
1FEATURES DESCRIPTION
The DS96F172 and the DS96F174 are high speed
2• Meets EIA-485 and EIA-422 Standards quad differential line drivers designed to meet EIA-
• Monotonic Differential Output Switching 485 Standards. The DS96F172 and the DS96F174
• TRI-STATE Outputs offer improved performance due to the use of L-FAST
bipolar technology. The use of LFAST technology
• Designed for Multipoint bus Transmission allows the DS96F172 and DS96F174 to operate at
• Common Mode Output Voltage Range: −7.0V higher speeds while minimizing power consumption.
to +12V The DS96F172 and the DS96F174 have TRI-STATE
• Operates from Single +5.0V Supply outputs and are optimized for balanced multipoint
• Reduced Power Consumption data bus transmission at rates up to 15 Mbps. The
• Thermal Shutdown Protection drivers have wide positive and negative common
mode range for multipoint applications in noisy
• DS96F172 and DS96F174 are Lead and environments. Positive and negative current-limiting
Function Compatible with the SN75172/174 or is provided which protects the drivers from line fault
the AM26LS31/MC3487 conditions over a +12V to −7.0V common mode
range. A thermal shutdown feature is also provided.
The DS96F172 features an active high and active low
Enable, common to all four drivers. The DS96F174
features separate active high Enables for each driver
pair.
Connection Diagrams
Figure 1. 16-Lead CDIP Package-Top View Figure 2. 16-Lead CDIP Package-Top View
DS96F172 DS96F174
(See Package Number NFE0016A) (See Package Number NFE0016A)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DS96F172MQML, DS96F174MQML
SNOSAS8A –APRIL 2011–REVISED APRIL 2013
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NC = No connection
Figure 3. 20-Lead LCCC Package-Top View Figure 4. 20-Lead LCCC Package-Top View
DS96F172 DS96F174
(see Package Number NAJ0020A) (see Package Number NAJ0020A)
Logic Diagrams
Figure 5. DS96F172 Figure 6. DS96F174
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SNOSAS8A –APRIL 2011–REVISED APRIL 2013
Function Tables (Each Driver)
Table 1. DS96F172(1)
Input Enable Outputs
A E E Y Z
H H X H L
L H X L H
H X L H L
L X L L H
X L H Z Z
(1) H = High Level
L = Low Level
X = Don't Care
Z = High Impedance (Off)
Table 2. DS96F174(1)
Input Enable Outputs
A E Y Z
H H H L
L H L H
X L Z Z
(1) H = High Level
L = Low Level
X = Don't Care
Z = High Impedance (Off)
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)
Storage Temperature Range (TStg)−65°C ≤TA≤+175°C
Lead Temperature (Soldering, 60 sec.) 300°C
Maximum Package Power Dissipation at 25°C(2)
LCCC package 2,000 mW
CDIP package 1,800 mW
Ceramic Flatpack package 1,000 mW
Supply Voltage 7.0V
Enable Input Voltage 5.5V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not verify specific performance limits. For verified specifications and test conditions, see the
Electrical Characteristics. The verified specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) Above TA= 25°C, derate LCCC package 13.3, CDIP package 12.5, Ceramic flatpack package 7.1 mW/°C
Recommended Operating Conditions Min Max Units
Supply Voltage (VCC) 4.50 5.50 V
Common Mode Output Voltage (VOC)−7.0 +12.0 V
Output Current High (IOH)−60 mA
Output Current Low (IOL) 60 mA
Operating Temperature (TA)−55 +125 °C
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Quality Conformance Inspection
Table 3. Mil-Std-883, Method 5005 - Group A
Subgroup Description Temp (°C)
1 Static tests at +25
2 Static tests at +125
3 Static tests at -55
4 Dynamic tests at +25
5 Dynamic tests at +125
6 Dynamic tests at -55
7 Functional tests at +25
8A Functional tests at +125
8B Functional tests at -55
9 Switching tests at +25
10 Switching tests at +125
11 Switching tests at -55
12 Settling time at +25
13 Settling time at +125
14 Settling time at -55
DS96F172/DS96F174 Electrical Characteristics AC/DC Parameters(1)
The following conditions apply, unless otherwise specified.
DC: VCC = 5.5V
AC: VCC = 5.0V Sub-
Parameter Test Conditions Notes Min Max Units groups
0.8 V 1
VIL Logical 0 Input Voltage 0.7 V 2, 3
VIH Logical 1 Input Voltage 2.0 V 1, 2, 3
VIC Input Clamp Voltage I = -18mA -1.5 V 1, 2, 3
VOD1 Differential Output Voltage IO= 0mA 6.0 V 1, 2, 3
1.5 V 1, 2
VCC = 4.5V, RL= 54Ω
VOD2 Differential Output Voltage Figure 7 See(2) 1.2 V 3
VOD2 Differential Output Voltage VCC = 4.5V, RL= 100Ω2.0 V 1, 2, 3
Figure 7 See(3) -200 200 mV 1, 2
ΔVOD1 Change In Magnitude of VOD2 VCC = 4.5V, RL= 54ΩSee(2)(3) -400 400 mV 3
See(3) -200 200 mV 1, 2
ΔVOD2 Change In Magnitude of VOD2 VCC = 4.5V, RL= 100ΩSee(2)(3) -400 400 mV 3
VOC Common Mode Output Voltage RL= 54Ω3.0 V 1, 2, 3
Figure 7
VOC Common Mode Output Voltage RL= 100Ω3.0 V 1, 2, 3
Figure 7
ΔVOC Change in Magnitude of VOC VCC = 4.5V, RL= 54Ω-200 200 mV 1, 2, 3
See(3)
Figure 7
ΔVOC Change in Magnitude of VOC VCC = 4.5V, RL= 100Ω-200 200 mV 1, 2, 3
See(4)
Figure 7
IOOutput Current With Power Off VCC = 0V, VO= -7V to 12V -50 50 µA 1, 2, 3
(1) All currents into the device pins are positive; all currents out of the device pins are negative. All voltages are reference to ground unless
otherwise specified.
(2) −55°C limit exceeds EIA standard RS−485 specification
(3) Δ|VOD| is the change in magnitude of VOD, that occurs when the input is changed between high and low levels.
(4) Δ|VOC| is the change in magnitude of the VOC that occurs when the input is changed between high and low levels.
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SNOSAS8A –APRIL 2011–REVISED APRIL 2013
DS96F172/DS96F174 Electrical Characteristics AC/DC Parameters(1) (continued)
The following conditions apply, unless otherwise specified.
DC: VCC = 5.5V
AC: VCC = 5.0V Sub-
Parameter Test Conditions Notes Min Max Units groups
IOZ High Impedance State Output Current VO= -7V to 12V -50 50 µA 1, 2, 3
IIH Logical 1 Input Current VI= 2.4V 20 µA 1, 2, 3
IIL Logical 0 Input Current VI= 0.4V -50 µA 1, 2, 3
ICC Supply Current Outputs Enabled 50 mA 1, 2, 3
ICCX Supply Current Outputs Disabled 30 mA 1, 2, 3
IOS1 Short Circuit Output Current VO= -7V See(5) -250 mA 1, 2, 3
IOS2 Short Circuit Output Current VO= 0V See(5) -150 mA 1, 2, 3
IOS3 Short Circuit Output Current VO= VCC See(5) 150 mA 1, 2, 3
IOS4 Short Circuit Output Current VO= 12V See(5) 250 mA 1, 2, 3
RL= 27Ω, CL= 15pF 25 ns 10, 11
tPLH Propagation Delay Lo to Hi level Figure 10 16 ns 9
RL= 27Ω, CL= 15pF 25 ns 10, 11
tPHL Propagation Delay Hi to Low Level Figure 10 16 ns 9
RL= 60Ω10 ns 10, 11
SKEW Output to Output Delay Time 4 ns 9
Output Disable Time From Low Level 40 ns 10, 11
RL= 110Ω, CL= 50pF
tLZ Figure 12 25 ns 9
Output Disable Time From High Level 80 ns 10, 11
RL= 110Ω, CL= 50pF
tHZ Figure 11 30 ns 9
Output Enable Time to Low Level RL= 110Ω, CL= 50pF 100 ns 10, 11
tZL Figure 12 40 ns 9
Output Enable Time to High Level RL= 110Ω, CL= 50pF 40 ns 10, 11
tZH Figure 10 32 ns 9
30 ns 10, 11
RL= 60Ω, CL= 15pF
tDD Differential Output Delay Time Figure 9 22 ns 9
Differential Output Transition Time 40 ns 10, 11
RL= 60Ω, CL= 15pF
tTD Figure 9 22 ns 9
(5) 0.2µF cap is connected between the output and Gnd to reduce oscillation.
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SNOSAS8A –APRIL 2011–REVISED APRIL 2013
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PARAMETER MEASUREMENT INFORMATION
Note 10: DS96F172 with active high and active low Enables is
Note 10: DS96F172 with active high and active low Enables is shown. DS96F174 has active high Enable only.
shown. DS96F174 has active high Enable only.
Figure 7. Differential and Common Mode Output Figure 8. Differential Output Voltage with Varying
Voltage Common Mode Voltage
Note 8:The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, duty cycle = 50%,
tr≤5.0 ns, tf≤5.0 ns, ZO= 50Ω.
Note 9:CLincludes probe and jig capacitance.
Note 10: DS96F172 with active high and active low Enables is shown. DS96F174 has active high Enable only.
Figure 9. Differential Output Delay and Transition Times
Note 8:The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, duty cycle = 50%,
tr≤5.0 ns, tf≤5.0 ns, ZO= 50Ω.
Note 9:CLincludes probe and jig capacitance.
Note 10: DS96F172 with active high and active low Enables is shown. DS96F174 has active high Enable only.
Figure 10. Propagation Delay Times
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SNOSAS8A –APRIL 2011–REVISED APRIL 2013
PARAMETER MEASUREMENT INFORMATION (continued)
Note 8:The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, duty cycle = 50%,
tr≤5.0 ns, tf≤5.0 ns, ZO= 50Ω.
Note 9:CLincludes probe and jig capacitance.
Note 11:To test the active low Enable E of DS96F172 ground E and apply an inverted waveform to E . DS96F174
has active high Enable only.
Figure 11. tZH and tHZ
Note 8:The input pulse is supplied by a generator having the following characteristics: f = 1.0 MHz, duty cycle = 50%,
tr≤5.0 ns, tf≤5.0 ns, ZO= 50Ω.
Note 9:CLincludes probe and jig capacitance.
Note 11:To test the active low Enable E of DS96F172 ground E and apply an inverted waveform to E . DS96F174
has active high Enable only.
Figure 12. tZL, tLZ, tLZL
NOTE
For more information see Application Bulletin, Contact Product Marketing.
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TYPICAL APPLICATION
The line length should be terminated at both ends in its characteristic impedance.
Stub lengths off the main line should be kept as short as possible.
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SNOSAS8A –APRIL 2011–REVISED APRIL 2013
REVISION HISTORY
Released Revision Section Changes
8–Apr-11 A New Release, Corporate format 2 MDS data sheets converted into one Corp. data
sheet format. MNDS96F172M-X Rev 1A0 &
MNDS96F174M-X Rev 1B0 will be archived.
Changes from Original (April 2013) to Revision A Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 8
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PACKAGE OPTION ADDENDUM
www.ti.com 25-Oct-2016
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9076501M2A ACTIVE LCCC NAJ 20 50 TBD Call TI Call TI -55 to 125 DS96F172ME
/883 Q
5962-90765
01M2A ACO
01M2A >T
5962-9076501MEA ACTIVE CDIP NFE 16 25 TBD Call TI Call TI -55 to 125 DS96F172MJ/883
5962-9076501MEA Q
5962-9076502M2A ACTIVE LCCC NAJ 20 50 TBD Call TI Call TI -55 to 125 DS96F174ME
/883 Q
5962-90765
02M2A ACO
02M2A >T
5962-9076502MEA ACTIVE CDIP NFE 16 25 TBD Call TI Call TI -55 to 125 DS96F174MJ/883
5962-9076502MEA Q
5962-9076502VEA ACTIVE CDIP NFE 16 25 TBD Call TI Call TI -55 to 125 DS96F174MJ-QMLV
5962-9076502VEA Q
DS96F172ME/883 ACTIVE LCCC NAJ 20 50 TBD Call TI Call TI -55 to 125 DS96F172ME
/883 Q
5962-90765
01M2A ACO
01M2A >T
DS96F172MJ/883 ACTIVE CDIP NFE 16 25 TBD Call TI Call TI -55 to 125 DS96F172MJ/883
5962-9076501MEA Q
DS96F174ME/883 ACTIVE LCCC NAJ 20 50 TBD Call TI Call TI -55 to 125 DS96F174ME
/883 Q
5962-90765
02M2A ACO
02M2A >T
DS96F174MJ-QMLV ACTIVE CDIP NFE 16 25 TBD Call TI Call TI -55 to 125 DS96F174MJ-QMLV
5962-9076502VEA Q
DS96F174MJ/883 ACTIVE CDIP NFE 16 25 TBD Call TI Call TI -55 to 125 DS96F174MJ/883
5962-9076502MEA Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DS96F174MQML, DS96F174MQML-SP :
•Military: DS96F174MQML
•Space: DS96F174MQML-SP
NOTE: Qualified Version Definitions:
•Military - QML certified for Military and Defense Applications
PACKAGE OPTION ADDENDUM
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Addendum-Page 3
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
MECHANICAL DATA
NAJ0020A
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E20A (Rev F)
MECHANICAL DATA
J0016A
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J16A (REV L)
NFE0016A
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