Features
•Serial Peripheral Interface (SPI) Compatible
•Supports SPI Modes 0 (0,0) and 3 (1,1)
•Data Sheet Describes Mode 0 Operation
•Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8V to 5.5V)
•20 MHz Clock Rate (5V)
•64-byte Page Mode and Byte Write Operation
•Block Write Protection
– Protect 1/4, 1/2, or Entire Array
•Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software
Data Protection
•Self-timed Write Cycle (5 ms Max)
•High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: >100 Years
•Green (Pb/Halide-free/RoHS Compliant) Packaging Options
•Die Sales: Wafer Form, Waffle Pack, and Bumped Die
Description
The AT25128B/256B provides 131,072/262,144 bits of serial electrically-erasable pro-
grammable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits
each. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available
in space saving 8-lead SOIC, 8-lead TSSOP, 8-ball VFBGA and 8-lead UDFN pack-
ages. In addition, the entire family is available in 1.8V (1.8V to 5.5V).
The AT25128B/256B is enabled through the Chip Select pin (CS) and accessed via a
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate Erase cycle is required before Write.
SPI Serial
EEPROMS
128K (16,384 x 8)
256K (32,768 x 8)
AT25128B
AT25256B
8698A–SEEPR–12/09
2
8698A–SEEPR–12/09
AT25128B/256B
Figure 0-1. Pin Configurations
Block Write protection is enabled by programming the status register with top ¼, top ½ or entire
array of write protection. Separate Program Enable and Program Disable instructions are pro-
vided for additional data protection. Hardware data protection is provided via the WP pin to
protect against inadvertent write attempts to the status register. The HOLD pin may be used to
suspend any serial communication without resetting the serial sequence.
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
8-lead SOIC
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
8-lead TSSOP
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
WP
GND
8-lead UDFN
VCC
HOLD
SCK
SI
CS
SO
WP
GND
1
2
3
4
8
7
6
5
8-ball dBGA2
Bottom View
Bottom View
Table 0-1. Pin Configurations
Pin Function
CS Chip Select
SCK Serial Data Clock
SI Serial Data Input
SO Serial Data Output
GND Ground
VCC Power Supply
WP Write Protect
HOLD Suspends Serial Input
NC No Connect
1. Absolute Maximum Ratings*
Operating Temperature ....................... –55°C to +125°C *NOTICE: Stresses beyond those listed under “Abso-
lute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress
rating only and functional operation of the
device at these or any other conditions
beyond those indicated in the operational
sections of this specification are not implied.
Exposure to absolute maximum rating con-
ditions for extended periods may affect
device reliability.
Storage Temperature ........................ –65°C to + 150°C
Voltage on Any Pin
with Respect to Ground............................. –1.0 V +7.0V
Maximum Operating Voltage.................................6.25V
DC Output Current ..............................................5.0 mA
3
8698A–SEEPR–12/09
AT25128B/256B
Figure 1-1. Block Diagram
Notes: 1. This parameter is characterized and is not 100% tested.
16384/32768 x 8
Table 1-1. Pin Capacitance (1)
Applicable over recommended operating range from TA= 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol Test Conditions Max Units Conditions
COUT Output Capacitance (SO) 8 pF VOUT = 0V
CIN Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN = 0V
4
8698A–SEEPR–12/09
AT25128B/256B
Notes: 1. VIL min and VIH max are reference only and are not tested.
Table 1-2. DC Characteristics
Applicable over recommended operating range from TA= −40°C to +85°C, VCC = +1.8V to +5.5V,
VCC = +1.8V to +5.5V(unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.8 5.5 V
VCC2 Supply Voltage 2.5 5.5 V
VCC3 Supply Voltage 4.5 5.5 V
ICC1 Supply Current VCC = 5.0V at 20 MHz, SO = Open, Read 9.0 10.0 mA
ICC2 Supply Current VCC = 5.0V at 10 MHz, SO = Open, Read, Write 5.0 7.0 mA
ICC3 Supply Current VCC = 5.0V at 1 MHz, SO = Open, Read, Write 2.2 3.5 mA
ISB1 Standby Current VCC = 1.8V, CS = VCC 0.2 3.0 µA
ISB2 Standby Current VCC = 2.5V, CS = VCC 0.5 3.0 µA
ISB3 Standby Current VCC = 5.0V, CS = VCC 2.0 5.0 µA
IIL Input Current VIN =0VtoV
CC –3.0 3.0 µA
IOL Output Leakage VIN =0VtoV
CC,T
AC = 0°C to 70°C –3.0 3.0 µA
VIL(1) Input Low-voltage –1.0 VCC x 0.3 V
VIH(1) Input High-voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low-voltage 3.6V ≤VCC ≤5.5V IOL = 3.0 mA 0.4 V
VOH1 Output High-voltage IOH =−1.6 mA VCC - 0.8 V
VOL2 Output Low-voltage 1.8V ≤VCC ≤3.6V IOL = 0.15 mA 0.2 V
VOH2 Output High-voltage IOH =−100 µA VCC - 0.2 V
Table 1-3. AC Characteristics
Applicable over recommended operating range from TA=–40°C to + 85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol Parameter Voltage Min Max Units
fSCK SCK Clock Frequency
4.5–5.5
2.5–5.5
1.8–5.5
0
0
0
20
10
5
MHz
tRI Input Rise Time
4.5–5.5
2.5–5.5
1.8–5.5
2
2
2
µs
tFI Input Fall Time
4.5–5.5
2.5–5.5
1.8–5.5
2
2
2
µs
tWH SCK High Time
4.5–5.5
2.5–5.5
1.8–5.5
20
40
80
ns
5
8698A–SEEPR–12/09
AT25128B/256B
Notes: 1. This parameter is characterized and is not 100% tested. Contact Atmel for further information.
tWL SCK Low Time
4.5–5.5
2.5–5.5
1.8–5.5
20
40
80
ns
tCS CS High Time
4.5–5.5
2.5–5.5
1.8–5.5
100
100
200
ns
tCSS CS Setup Time
4.5–5.5
2.5–5.5
1.8–5.5
100
100
200
ns
tCSH CS Hold Time
4.5–5.5
2.5–5.5
1.8–5.5
100
100
200
ns
tSU Data In Setup Time
4.5–5.5
2.5–5.5
1.8–5.5
5
10
20
ns
tHData In Hold Time
4.5–5.5
2.5–5.5
1.8–5.5
5
10
20
ns
tHD HOLD Setup Time
4.5–5.5
2.5–5.5
1.8–5.5
5
10
20
ns
tCD HOLD Hold Time
4.5–5.5
2.5–5.5
1.8–5.5
5
10
20
ns
tVOutput Valid
4.5–5.5
2.5–5.5
1.8–5.5
0
0
0
20
40
80
ns
tHO Output Hold Time
4.5–5.5
2.5–5.5
1.8–5.5
0
0
0
ns
tLZ HOLD to Output Low Z
4.5–5.5
2.5–5.5
1.8–5.5
0
0
0
25
50
100
ns
tHZ HOLD to Output High Z
4.5–5.5
2.5–5.5
1.8–5.5
25
50
100
ns
tDIS Output Disable Time
4.5–5.5
2.5–5.5
1.8–5.5
25
50
100
ns
tWC Write Cycle Time
4.5–5.5
2.5–5.5
1.8–5.5
5
5
5
ms
Endurance(1) 3.3V, 25°C, Page Mode 1M Write Cycles
Table 1-3. AC Characteristics (Continued)
Applicable over recommended operating range from TA=–40°C to + 85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol Parameter Voltage Min Max Units
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8698A–SEEPR–12/09
AT25128B/256B
1.1 Serial Interface Description
MASTER: The device that generates the serial clock.
SLAVE: Because the serial clock pin (SCK) is always an input, the AT25128B/256B always
operates as a slave.
TRANSMITTER/RECEIVER: The AT25128B/256B has separate pins designated for data
transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL-OP CODE: After the device is selected with CS going low, the first byte will be received. This byte
contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25128B/256B, and the serial output pin (SO) will remain in a high impedance state until the
falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25128B/256B is selected when the CS pin is low. When the device is not selected,
data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25128B/256B. When the
device is selected and a serial sequence is underway, HOLD can be used to pause the serial
communication with the master device without resetting the serial sequence. To pause, the HOLD pin must
be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high
while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the
SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high.
When the WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited.
WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has
already been initiated, WP going low will have no effect on any write operation to the status register. The
WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install
the AT25128B/256B in a system with the WP pin tied to ground and still be able to write to the status
register. All WP pin functions are enabled when the WPEN bit is set to “1”.
7
8698A–SEEPR–12/09
AT25128B/256B
Figure 1-2. SPI Serial Interface
2. Functional Description
The AT25128B/256B is designed to interface directly with the synchronous serial peripheral
interface (SPI) of the 6800 type series of microcontrollers.
The AT25128B/256B utilizes an 8-bit instruction register. The list of instructions and their opera-
tion codes are contained in Table 2-1. All instructions, addresses, and data are transferred with
the MSB first and start with a high-to-low CS transition.
AT25128B/256B
Table 2-1. Instruction Set for the AT25128B/256B
Instruction Name Instruction Format Operation
WREN 0000 X110 Set Write Enable Latch
WRDI 0000 X100 Reset Write Enable Register
RDSR 0000 X101 Read Status Register
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8698A–SEEPR–12/09
AT25128B/256B
WRITE ENABLE (WREN): The device will power-up in the write disable state when VCC is applied. All
programming instructions must therefore be preceded by a Write Enable instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction
disables all programming modes. The WRDI instruction is independent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status
register. The Ready/Busy and Write Enable status of the device can be determined by the RDSR
instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits
are set by using the WRSR instruction.
WRITESTATUSREGISTER(WRSR):The WRSR instruction allows the user to select one of four
levels of protection. The AT25128B/256B is divided into four array segments. Top quarter (1/4),
top half (1/2), or all of the memory segments can be protected. Any of the data within any
selected segment will therefore be read only. The block write protection levels and correspond-
ing status register control bits are shown in Table 2-4.
WRSR 0000 X001 Write Status Register
READ 0000 X011 Read Data from Memory Array
WRITE 0000 X 010 Write Data to Memory Array
Table 2-1. Instruction Set for the AT25128B/256B
Instruction Name Instruction Format Operation
Table 2-2. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WPEN X X X BP1 BP0 WEN RDY
Table 2-3. Read Status Register Bit Definition
Bit Definition
Bit0(
RDY) Bit 0 = “0” (RDY) indicates the device is ready.
Bit 0 = “1” indicates the write cycle is in progress.
Bit 1 (WEN) Bit1=0indicates the device is not write enabled.
Bit 1 = “1” indicates the device is write enabled.
Bit 2 (BP0) See Table 2-4 on page 9.
Bit 3 (BP1) See Table 2-4 on page 9.
Bits4–6are0swhen device is not an internal write cycle.
Bit 7 (WPEN) See Table 2-5 on page 9
Bits0–7are“1”s during an internal write cycle.
9
8698A–SEEPR–12/09
AT25128B/256B
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and
functions as the regular memory cells (e.g. WREN, tWC, RDSR).
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin
through the use of the write protect enable (WPEN) bit. Hardware write protection is enabled
when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when
either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected,
writes to the Status Register, including the Block Protect bits and the WPEN bit, and the block-
protected sections in the memory array are disabled. Writes are only allowed to sections of the
memory which are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as
long as the WP pin is held low.
READ SEQUENCE (READ): Reading the AT25128B/256B via the SO pin requires the following sequence.
After the CS line is pulled low to select a device, the Read op-code is transmitted via the SI line followed by
the byte address to be read (Table 2-6). Upon completion, any data on the SI line will be ignored. The data
(D7 - D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS
line should be driven high after the data comes out. The read sequence can be continued since the byte
address is automatically incremented and data will continue to be shifted out. When the highest address is
reached, the address counter will roll over to the lowest address allowing the entire memory to be read in
one continuous read cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25128B/256B, two separate instructions must be
executed. First, the device must be write enabled via the Write Enable (WREN) Instruction. Then a Write
instruction may be executed. Also, the address of the memory location(s) to be programmed must be
outside the protected address field location selected by the Block Write Protection Level. During an internal
write cycle, all commands will be ignored except the RDSR instruction.
A Write Instruction requires the following sequence. After the CS line is pulled low to select the
device, the Write op-code is transmitted via the SI line followed by the byte address and the data
Table 2-4. Block Write Protect Bits
Level Status Register Bits Array Addresses Protected
BP1 BP0 AT25128B AT25256B
0 0 0 None None
1 (1/4) 0 1 3000 – 3FFF 6000 – 7FFF
2 (1/2) 1 0 2000 – 3FFF 4000 – 7FFF
3 (All) 1 1 0000 – 3FFF 0000 – 7FFF
Table 2-5. WPEN Operation
WPEN WP WEN Protected Blocks
Unprotected
Blocks Status Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable
10
8698A–SEEPR–12/09
AT25128B/256B
(D7 - D0) to be programmed (see Table 2-6 for the address key). Programming will start after the
CS pin is brought high. (The Low-to-High transition of the CS pin must occur during the SCK low
time immediately after clocking in the D0 (LSB) data bit.
The Ready/Busy status of the device can be determined by initiating a Read Status Register
(RDSR) Instruction. If Bit 0 = 1, the Write cycle is still in progress. If Bit0=0,theWrite cycle has
ended. Only the Read Status Register instruction is enabled during the Write programming
cycle.
The AT25128B/256B is capable of a 64-byte Page Write operation. After each byte of data is
received, the six low order address bits are internally incremented by one; the high order bits of
the address will remain constant. If more than 64 bytes of data are transmitted, the address
counter will roll over and the previously written data will be overwritten. The AT25128B/256B is
automatically returned to the write disable state at the completion of a Write cycle.
Note: If the device is not write enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when
CS is brought high. A new CS falling edge is required to re-initiate the serial communication.
3. Timing Diagram (for SPI Mode 0 (0,0)
Figure 3-1. Synchronous Data Timing
Table 2-6. Address Key
Address AT25128B AT25256B
ANA13 −A
0A14 −A
0
Don’t Care Bits A15 −A
14 A15
SO
V
OH
V
OL
HI-Z HI-Z
t
V
VALID IN
SI
V
IH
V
IL
t
H
t
SU
t
DIS
SCK
V
IH
V
IL
t
WH
t
CSH
CS
V
IH
V
IL
t
CSS
t
CS
t
WL
tHO
11
8698A–SEEPR–12/09
AT25128B/256B
Figure 3-2. WREN Timing
Figure 3-3. WRDI Timing
Figure 3-4. RDSR Timing
CS
SCK
01234567891011121314
SI INSTRUCTION
SO 76543210
DATA OUT
MSB
HIGH IMPEDANCE
15
12
8698A–SEEPR–12/09
AT25128B/256B
Figure 3-5. WRSR Timing
Figure 3-6. READ Timing
Figure 3-7. WRITE Timing
13
8698A–SEEPR–12/09
AT25128B/256B
Figure 3-8. HOLD Timing
SO
SCK
HOLD
tCD
tHD
tHZ
tLZ
tCD
tHD
CS
14
8698A–SEEPR–12/09
AT25128B/256B
3.1 Catalog Numbering Scheme
15
8698A–SEEPR–12/09
AT25128B/256B
4. Package Ordering Information
4.1 AT25128B Ordering Information
Notes: 1. “U” designates Green package + RoHS compliant.
2. Available in waffle pack and wafer form; order as SL788 for wafer form. Bumped die available upon request. Please Contact
Serial Interface Marketing.
Table 4-1. AT25128B Ordering Information
Ordering Code Package Voltage Range Operation Range
AT25128B-SSHL-B(1) 8S1 1.8V to 5.5V
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
AT25128B-SSHL-T(2) 8S1 1.8V to 5.5V
AT25128B-XHL-B(1) 8A2 1.8V to 5.5V
AT25128B-XHL-T(2) 8A2 1.8V to 5.5V
AT25128B-MAHL-T(1) 8MA2 1.8V to 5.5V
AT25128B-CUL-T(2) 8U2-1 1.8V to 5.5V
AT25128B-W11L(2) Wafer 1.8V to 5.5V Industrial Temperature
(−40°C to 85°C)
AT25128B-WT11L Die in Tape 1.8V to 5.5V
Package Type
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8U2-1 8-ball, die Ball Grid Array Package (VFBGA)
8A2 8-lead, 4.40 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8MA2 8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Dual No Lead Package (UDFN)
16
8698A–SEEPR–12/09
AT25128B/256B
4.2 AT25256B Ordering Information
Notes: 1. “U” designates Green package + RoHS compliant.
2. Available in waffle pack and wafer form; order as SL788 for wafer form. Bumped die available upon request. Please contact
Serial Interface Marketing.
Table 4-2. AT25256B Ordering Information
Ordering Code Package Voltage Range Operation Range
AT25256B-SSHL-B(1) 8S1 1.8V to 5.5V
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
AT25256B-SSHL-T(2) 8S1 1.8V to 5.5V
AT25256B-SHL-B 8S2 1.8V to 5.5V
AT25256B-XHL-B(1) 8A2 1.8V to 5.5V
AT25256B-XHL-T(2) 8A2 1.8V to 5.5V
AT25256B-MAHL-T 8MA2 1.8V to 5.5V
AT25256B-CUL-T(1) 8U2-1 1.8V to 5.5V
AT25256B-W11L(2) Wafer 1.8V to 5.5V Industrial Temperature
(−40°C to 85°C)
AT25256B-WT11L Die in Tape 1.8V to 5.5V
Package Type
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8S2 8-lead, 0.209" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8U2-1 8-ball, die Ball Grid Array Package (VFBGA)
8A2 8-lead, 4.40 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8MA2 8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Dual No Lead Package (UDFN)
17
8698A–SEEPR–12/09
AT25128B/256B
5. AT25128B Part Markings
18
8698A–SEEPR–12/09
AT25128B/256B
19
8698A–SEEPR–12/09
AT25128B/256B
20
8698A–SEEPR–12/09
AT25128B/256B
6. AT25256B Part Markings
21
8698A–SEEPR–12/09
AT25128B/256B
22
8698A–SEEPR–12/09
AT25128B/256B
23
8698A–SEEPR–12/09
AT25128B/256B
7. Packaging Information
7.1 8S1 – JEDEC SOIC
TITLE DRAWING NO. GPC REV.
Package Drawing Contact:
packagedrawings@atmel.com 8S1SWB D
8S1, 8-lead (0.150” Wide Body), Plastic Gull
Wing Small Outline (JEDEC SOIC)
7/17/09
Note:
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
A 1.35 – 1.75
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.05
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
q 0° – 8°
Ø
Ø
E
E
1
1
N
N
TOP VIEW
TOP VIEW
C
C
E1
E1
END VIEW
A
A
b
b
L
L
A1
A1
e
e
D
D
SIDE VIEW
SIDE VIEW
24
8698A–SEEPR–12/09
AT25128B/256B
7.2 8S2 - EIAJ
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
10/7/03
8S2 C
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs are not included.
3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.
A 1.70 2.16
A1 0.05 0.25
b 0.35 0.48 5
C 0.15 0.35 5
D 5.13 5.35
E1 5.18 5.40 2, 3
E 7.70 8.26
L 0.51 0.85
∅
0° 8°
e 1.27 BSC 4
End View
Side View
eb
A
A1
D
E
N
1
C
E1
∅
L
Top View
25
8698A–SEEPR–12/09
AT25128B/256B
7.3 8U2-1 – VFBGA
TITLE DRAWING NO.GPC REV.
Package Drawing Contact:
packagedrawings@atmel.com 8U2-1GWW C
8U2-1, 8 ball, 2.35 x 3.73 mm Body, 0.75 mm pitch
VFBGA Package (VFBGA)
2/25/08
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.81 0.91 1.00
A1 0.15 0.20 0.25
A2 0.40 0.45 0.50
b 0.25 0.30 0.35
D 2.35 BSC
E 3.73 BSC
e 0.75 BSC
e1 0.74 REF
d 0.75 BSC
d1 0.80 REF
2. Dimension 'b' is measured at the maximum solder ball diameter.
1. This drawing is for general information.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
Notes:
26
8698A–SEEPR–12/09
AT25128B/256B
7.4 8A2 – TSSOP
TITLE DRAWING NO.GPC REV.
Package Drawing Contact:
packagedrawings@atmel.com 8A2TNR C
8A2, 8-lead, 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
10/29/08
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20
A2 0.80 1.00 1.05
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 RE3
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
Side View
End View
Top View
A2
A
L
L1
D
123
E1
N
b
Pin 1 indicator
this corner
E
e
27
8698A–SEEPR–12/09
AT25128B/256B
7.5 8MA2 - UDFN
TITLE DRAWING NO.GPC REV.
Package Drawing Contact:
packagedrawings@atmel.com 8MA2YNZ A
8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No
Lead Package (UDFN)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 2.00 BSC
E 3.00 BSC
D2 1.40 1.50 1.60
E2 1.20 1.30 1.40
A 0.50 0.55 0.60
A1 0.0 0.02 0.05
A2 – – 0.55
C 0.152 REF
L 0.30 0.35 0.40
e 0.50 BSC
b 0.18 0.25 0.30 3
K 0.20 – –
4/15/08
D2
E2
E
e (6x)
L (8x)
b (8x)
Pin#1 ID
(R0.10) 0.35
A
A1
A2
Pin 1 ID
D
C
K
8
7
6
5
1
2
3
4
1
2
3
4
8
7
6
5
28
8698A–SEEPR–12/09
AT25128B/256B
8. Revision History
Doc. Rev. Date Comments
8698A 12/2009 Initial document release.
8698A–SEEPR–12/09
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