CY7C1366C-166AXCT - Cypress Semiconductor

PRELIMINARY

9-Mbit (256K x 36/512K x 18) Pipelined DCD

Sync SRAM

CY7C1366C

CY7C1367C

Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 38-05542 Rev. *A Revised October 5, 2004

Features

• Supports bus operation up to 225 MHz

• Available speed grades are 225, 200 and 166 MHz

• Registered inputs and outputs for pipelined operation

•Optimal for performance (Double-Cycle deselect)

—Depth expansion without wait state

•3.3V –5% and +10% core power supply (VDD)

• 2.5V / 3.3V I/O operation

• Fast clock-to-output times

— 2.8 ns (for 225-MHz device)

— 3.0 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

• Provide high-performance 3-1-1-1 access rate

•User-selectable burst counter supporting Intel

Pentium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Available in Lead-Free 100 TQFP,119 BGA and 165 fBGA

packages

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

Functional Description[1]

The CY7C1366C/CY7C1367C SRAM integrates 262,144 x 36

and 524,288 x 18 SRAM cells with advanced synchronous

peripheral circuitry and a two-bit counter for internal burst

operation. All synchronous inputs are gated by registers

controlled by a positive-edge-triggered Clock Input (CLK). The

synchronous inputs include all addresses, all data inputs,

address-pipelining Chip Enable (CE1), depth-expansion Chip

Enables (CE2 and CE3

[2]), Burst Control inputs (ADSC, ADSP

and ADV), Write Enables (BWX, and BWE), and Global Write

(GW). Asynchronous inputs include the Output Enable (OE)

and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as

controlled by the byte write control inputs. GW active LOW

causes all bytes to be written. This device incorporates an

additional pipelined enable register which delays turning off

the output buffers an additional cycle when a deselect is

executed.This feature allows depth expansion without penal-

izing system performance.

The CY7C1366C/CY7C1367C operates from a +3.3V core

power supply while all outputs operate with a +3.3V or a +2.5V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Selection Guide

225 MHz 200 MHz 166 MHz Unit

Maximum Access Time 2.8 3.0 3.5 ns

Maximum Operating Current 250 220 180 mA

Maximum CMOS Standby Current 30 30 30 mA

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

Notes:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE3 is for TQFP and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.

PRELIMINARY

CY7C1366C

CY7C1367C

Document #: 38-05542 Rev. *A Page 2 of 27

ADDRESS

ADV

CLK

BURST

COUNTER AND

LOGIC

CLR

ADSP

ADSC

MODE

BWE

DQP

BYTE

WRITE REGISTER

,DQP

BYTE

WRITE REGISTER

,DQP

BYTE

WRITE REGISTER

DQP

BYTE

WRITE REGISTER

ENABLE

OUTPUT

REGISTERS

SENSE

AMPS

MEMORY

ARRAY

OUTPUT

BUFFERS

DQP

BYTE

WRITE DRIVER

,DQP

BYTE

WRITE DRIVER

,DQP

BYTE

WRITE DRIVER

DQP

BYTE

WRITE DRIVER

INPUT

REGISTERS

0,A1,A

A[1:0]

SLEEP

CONTROL

DQs

DQP

Logic Block Diagram – CY7C1366C (256K x 36)

ADDRESS

ADV

CLK

BURST

COUNTER AND

LOGIC

CLR

ADSC

BWB

BWA

DQP

BYTE

WRITE REGISTER

A ,

DQP

BYTE

WRITE REGISTER

ENABLE

SENSE

AMPS

MEMORY

ARRAY

ADSP

[1:0]

MODE

BWE

PIPELINED

ENABLE

DQP

OUTPUT

REGISTERS

INPUT

REGISTERS

OUTPUT

BUFFERS

B ,

DQP

BYTE

WRITE DRIVER

DQPA

BYTE

WRITE DRIVER

SLEEP

CONTROL

0, A1, A

Logic Block Diagram – CY7C1367C (512K x 18)

PRELIMINARY

CY7C1366C

CY7C1367C

Document #: 38-05542 Rev. *A Page 3 of 27

Pin Configurations

NC / 72M

NC / 36M

NC / 18M

DQP

DDQ

SSQ

DDQ

SSQ

DDQ

DQP

DDQ

SSQ

DDQ

SSQ

DDQ

DQP

CLK

BWE

ADSC

ADSP

ADV

100

MODE

CY7C1366C

(256K X 36)

NC / 72M

NC / 36M

NC / 18M

DDQ

SSQ

DQP

SSQ

DDQ

SSQ

DDQ

SSQ

DDQ

SSQ

DQP

SSQ

DDQ

CLK

BWE

ADSC

ADSP

ADV

100

MODE

CY7C1367C

(512K x 18)

100-pin TQFP Pinout (3 Chip Enables)

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CY7C1366C

CY7C1367C

Document #: 38-05542 Rev. *A Page 4 of 27

Pin Configurations (continued)

2345671

VDDQ

DQPC

DQC

DQD

DQC

DQD

AA AA

ADSP VDDQ

CE2A

DQC

VDDQ

DQC

VDDQ

DQD

VDDQ

VDD

CLK

VDD

VSS

TDOTCKTDITMS

NCNC

VDDQ

AAA

DQA

DQC

DQA

DQB

DQA

DQB

VDD

DQC

VDD

DQD

ADSC

CE1

ADV

VSS

VSS DQPA

MODE

DQPD

DQPB

BWB

BWC

NC VDD NC

BWA

BWE

BWD

2345671

VDDQ

NCDQB

DQB

AA AA

ADSP VDDQ

CE2A

VDDQ

VDD

CLK

VDD

VSS

TDOTCKTDITMS

VDDQ

ANCA

DQA

DQB

DQA

VDD

DQB

VDD

DQB

ADSC

CE1

ADV

VSS

VSS NC

MODE

DQPB

DQPA

VSS

BWB

NC VDD NC

BWA

BWE

VSS

CY7C1367C (512K x 18)

CY7C1366C (256K x 36)

119-ball BGA (2 Chip Enable with JTAG)

PRELIMINARY

CY7C1366C

CY7C1367C

Document #: 38-05542 Rev. *A Page 5 of 27

Pin Configurations (continued)

165-ball fBGA (3 Chip Enable)

CY7C1366C (256K x 36)

234 5671

TDO

NC / 288M

DQP

CE3

BWE

ACE

MODE

NC / 36M

NC / 72M

DDQ

CLK GW

DDQ

NC / 18M

DDQ

TCK

TDI

DDQ

TMS

891011

ADV

ADSC

OE ADSP

ANC / 144M

DDQ

NC DQP

DDQ

DQP

DDQ

CY7C1367C (512K x 18)

234 5671

TDO

NC / 288M

DQP

ACE

BWE

ACE

MODE

NC / 36M

NC / 72M

DDQ

NC BW

CLK GW

DDQ

NC / 18M

DDQ

‘V

TCKA0

TDI

NC V

DDQ

TMS

891011

ADV

ADSC

OE ADSP

ANC / 144M

DDQ

NC DQP

DDQ

NCV

DDQ

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CY7C1366C

CY7C1367C

Document #: 38-05542 Rev. *A Page 6 of 27

Pin Definitions

Name I/O Description

A0, A1, A Input-

Synchronous

Address Inputs used to select one of the address locations. Sampled at the rising edge of

the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 [2]are sampled active. A1: A0

are fed to the two-bit counter.

BWA,BWB

BWC,BWD

Input-

Synchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.

Sampled on the rising edge of CLK.

GW Input-

Synchronous

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a

global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE).

BWE Input-

Synchronous

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must

be asserted LOW to conduct a byte write.

CLK Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the

burst counter when ADV is asserted LOW, during a burst operation.

CE1

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE2 and CE3[2] to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is

sampled only when a new external address is loaded.

CE2Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction

with CE1 and CE3[2] to select/deselect the device.CE2 is sampled only when a new external

address is loaded.

CE3[2] Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE1 and CE2 to select/deselect the device.Not connected for BGA. Where referenced,

CE3[2] is assumed active throughout this document for BGA.

CE3 is sampled only when a new external address is loaded.

OE Input-

Asynchronous

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When

LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ pins are three-stated, and

act as input data pins. OE is masked during the first clock of a read cycle when emerging from

a deselected state.

ADV Input-

Synchronous

Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it

automatically increments the address in a burst cycle.

ADSP Input-

Synchronous

Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When

asserted LOW, addresses presented to the device are captured in the address registers. A1:

A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP

is recognized. ASDP is ignored when CE1 is deasserted HIGH.

ADSC Input-

Synchronous

Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When

asserted LOW, addresses presented to the device are captured in the address registers. A1:

A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP

is recognized.

ZZ Input-

Asynchronous

ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical

“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or

left floating. ZZ pin has an internal pull-down.

DQs,

DQPs

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by the addresses presented during the previous clock rise of the read cycle. The

direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.

When HIGH, DQs and DQPX are placed in a three-state condition.

VDD Power Supply Power supply inputs to the core of the device.

VSS Ground Ground for the core of the device.

VSSQ I/O Ground Ground for the I/O circuitry.

VDDQ I/O Power Supply Power supply for the I/O circuitry.

MODE Input-

Static

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or

left floating selects interleaved burst sequence. This is a strap pin and should remain static

during device operation. Mode Pin has an internal pull-up.

TDO JTAG serial output

Synchronous

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG

feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP

packages.

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CY7C1366C

CY7C1367C

Document #: 38-05542 Rev. *A Page 7 of 27

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

The CY7C1366C/CY7C1367C supports secondary cache in

systems utilizing either a linear or interleaved burst sequence.

The interleaved burst order supports Pentium and i486

processors. The linear burst sequence is suited for processors

that utilize a linear burst sequence. The burst order is user

selectable, and is determined by sampling the MODE input.

Accesses can be initiated with either the Processor Address

Strobe (ADSP) or the Controller Address Strobe (ADSC).

Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

Byte write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BWX) inputs. A Global Write

Enable (GW) overrides all byte write inputs and writes data to

all four bytes. All writes are simplified with on-chip

synchronous self-timed write circuitry.

Synchronous Chip Selects CE1, CE2, CE3[2] and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. ADSP is ignored if

CE1 is HIGH.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)

chip selects are all asserted active, and (3) the write signals

(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1

is HIGH. The address presented to the address inputs is

stored into the address advancement logic and the Address

sponding data is allowed to propagate to the input of the

Output Registers. At the rising edge of the next clock the data

is allowed to propagate through the output register and onto

the data bus within tco if OE is active LOW. The only exception

occurs when the SRAM is emerging from a deselected state

to a selected state, its outputs are always three-stated during

the first cycle of the access. After the first cycle of the access,

the outputs are controlled by the OE signal. Consecutive

single read cycles are supported.

The CY7C1366C/CY7C1367C is a double-cycle deselect part.

Once the SRAM is deselected at clock rise by the chip select

and either ADSP or ADSC signals, its output will three-state

immediately after the next clock rise.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)

chip select is asserted active. The address presented is

loaded into the address register and the address

advancement logic while being delivered to the memory core.

The write signals (GW, BWE, and BWX) and ADV inputs are

ignored during this first cycle.

ADSP triggered write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQx inputs is written into the corre-

sponding address location in the memory core. If GW is HIGH,

then the write operation is controlled by BWE and BWX

signals. The CY7C1366C/CY7C1367C provides byte write

capability that is described in the Write Cycle Description table.

Asserting the Byte Write Enable input (BWE) with the selected

Byte Write input will selectively write to only the desired bytes.

Bytes not selected during a byte write operation will remain

unaltered. A synchronous self-timed write mechanism has

been provided to simplify the write operations.

Because the CY7C1366C/CY7C1367C is a common I/O

device, the Output Enable (OE) must be deasserted HIGH

before presenting data to the DQ inputs. Doing so will

three-state the output drivers. As a safety precaution, DQ are

automatically three-stated whenever a write cycle is detected,

regardless of the state of OE.

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deasserted HIGH, (3) chip select is asserted active, and (4)

the appropriate combination of the write inputs (GW, BWE,

and BWX) are asserted active to conduct a write to the desired

byte(s). ADSC triggered write accesses require a single clock

cycle to complete. The address presented is loaded into the

address register and the address advancement logic while

being delivered to the memory core. The ADV input is ignored

during this cycle. If a global write is conducted, the data

presented to the DQX is written into the corresponding address

location in the memory core. If a byte write is conducted, only

the selected bytes are written. Bytes not selected during a byte

write operation will remain unaltered. A synchronous

self-timed write mechanism has been provided to simplify the

write operations.

Because the CY7C1366C/CY7C1367C is a common I/O

device, the Output Enable (OE) must be deasserted HIGH

before presenting data to the DQX inputs. Doing so will

three-state the output drivers. As a safety precaution, DQX are

TDI JTAG serial input

Synchronous

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is

not being utilized, this pin can be disconnected or connected to VDD. This pin is not available

on TQFP packages.

TMS JTAG serial input

Synchronous

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is

not being utilized, this pin can be disconnected or connected to VDD. This pin is not available

on TQFP packages.

TCK JTAG-

Clock

Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be

connected to VSS. This pin is not available on TQFP packages.

NC – No Connects. Not internally connected to the die.

Pin Definitions (continued)

Name I/O Description

PRELIMINARY

CY7C1366C

CY7C1367C

Document #: 38-05542 Rev. *A Page 8 of 27

automatically three-stated whenever a write cycle is detected,

regardless of the state of OE.

Burst Sequences

The CY7C1366C/CY7C1367C provides a two-bit wraparound

counter, fed by A[1:0], that implements either an interleaved or

linear burst sequence. The interleaved burst sequence is

designed specifically to support Intel® Pentium applications.

The linear burst sequence is designed to support processors

that follow a linear burst sequence. The burst sequence is user

selectable through the MODE input. Both read and write burst

operations are supported.

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both read and write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the “sleep” mode. CEs, ADSP, and ADSC must remain

inactive for the duration of tZZREC after the ZZ input returns

LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table (MODE = GND)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

Partial Truth Table for Read/Write[5, 10]

Function (CY7C1366C) GW BWE BWDBWCBWBBWA

Read HHXXXX

Read HLHHHH

Write Byte A – (DQA and DQPA) HLHHHL

Write Byte B – (DQB and DQPB)HLHHLH

Write Bytes B, A H L H H L L

Write Byte C – (DQC and DQPC) HLHLHH

Write Bytes C, A H L H L H L

Write Bytes C, B H L H L L H

Write Bytes C, B, A H L H L L L

Write Byte D – (DQD and DQPD) HL LHHH

Write Bytes D, A H L L H H L

Write Bytes D, B H L L H L H

Write Bytes D, B, A H L L H L L

Write Bytes D, C H L L L H H

Write Bytes D, C, A H L L L H L

Write Bytes D, C, B HLLLLH

Write All Bytes HLLLLL

Write All Bytes LXXXXX

Truth Table for Read/Write[5, 10]

Function (CY7C1367C) GW BWEBWBBWA

Read H H X X

Read H L H H

Write Byte A – (DQA and DQPA)HLHL

Write Byte B – (DQB and DQPB)HLLH

Write All Bytes H L L L

Write All Bytes L X X X

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CY7C1367C

Document #: 38-05542 Rev. *A Page 9 of 27

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1366C/CY7C1367C incorporates a serial boundary

scan test access port (TAP)in the BGA package only. The

TQFP package does not offer this functionality. This part

operates in accordance with IEEE Standard 1149.1-1900, but

doesn’t have the set of functions required for full 1149.1

compliance. These functions from the IEEE specification are

excluded because their inclusion places an added delay in the

critical speed path of the SRAM. Note the TAP controller

functions in a manner that does not conflict with the operation

of other devices using 1149.1 fully compliant TAPs. The TAP

operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.

The CY7C1366C/CY7C1367C contains a TAP controller,

instruction register, boundary scan register, bypass register,

and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(VSS) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

be connected to VDD through a pull-up resistor. TDO should be

left unconnected. Upon power-up, the device will come up in

a reset state which will not interfere with the operation of the

device.

TAP Controller State Diagram

The 0/1 next to each state represents the value of TMS at the

rising edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this ball unconnected if the TAP is not used. The ball is

pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. For

information on loading the instruction register, see Figure .

TDI is internally pulled up and can be unconnected if the TAP

is unused in an application. TDI is connected to the most

significant bit (MSB) of any register. (See Tap Controller Block

Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine. The output changes on the

falling edge of TCK. TDO is connected to the least significant

bit (LSB) of any register. (See Tap Controller State Diagram.)

TAP Controller Block Diagram

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD) for five

rising edges of TCK. This RESET does not affect the operation

of the SRAM and may be performed while the SRAM is

operating.

At power-up, the TAP is reset internally to ensure that TDO

comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and

allow data to be scanned into and out of the SRAM test

circuitry. Only one register can be selected at a time through

the instruction register. Data is serially loaded into the TDI ball

on the rising edge of TCK. Data is output on the TDO ball on

the falling edge of TCK.

TEST-LOGIC

RESET

RUN-TEST/

IDLE SELECT

DR-SCAN SELECT

IR-SCAN

CAPTURE-DR

SHIFT-DR

CAPTURE-IR

SHIFT-IR

EXIT1-DR

PAUSE-DR

EXIT1-IR

PAUSE-IR

EXIT2-DR

UPDATE-DR

EXIT2-IR

UPDATE-IR

1 1

0 0

1 1

0 0

1 0

Bypass Register

Instruction Register

012

Identification Register

012293031 ...

Boundary Scan Register

012..x ...

Selection

Circuitry

Selection

Circuitry

TCK

MS TAP CONTROLLER

TDI TD

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CY7C1367C

Document #: 38-05542 Rev. *A Page 10 of 27

Instruction Register

Three-bit instructions can be serially loaded into the instruction

TDI and TDO balls as shown in the Tap Controller Block

Diagram. Upon power-up, the instruction register is loaded

with the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in the previous section.

When the TAP controller is in the Capture-IR state, the two

least significant bits are loaded with a binary “01” pattern to

allow for fault isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

TDI and TDO balls. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

(VSS) when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and

bidirectional balls on the SRAM.

The boundary scan register is loaded with the contents of the

RAM I/O ring when the TAP controller is in the Capture-DR

state and is then placed between the TDI and TDO balls when

the controller is moved to the Shift-DR state. The EXTEST,

SAMPLE/PRELOAD and SAMPLE Z instructions can be used

to capture the contents of the I/O ring.

The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

TAP Instruction Set

Overview

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in the

Instruction Codes table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.

The TAP controller used in this SRAM is not fully compliant to

the 1149.1 convention because some of the mandatory 1149.1

instructions are not fully implemented.

The TAP controller cannot be used to load address data or

control signals into the SRAM and cannot preload the I/O

buffers. The SRAM does not implement the 1149.1 commands

EXTEST or INTEST or the PRELOAD portion of

SAMPLE/PRELOAD; rather, it performs a capture of the I/O

ring when these instructions are executed.

Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

through the instruction register through the TDI and TDO balls.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be

executed whenever the instruction register is loaded with all

0s. EXTEST is not implemented in this SRAM TAP controller,

and therefore this device is not compliant to 1149.1. The TAP

controller does recognize an all-0 instruction.

When an EXTEST instruction is loaded into the instruction

instruction has been loaded. There is one difference between

the two instructions. Unlike the SAMPLE/PRELOAD

instruction, EXTEST places the SRAM outputs in a High-Z

state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO balls and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction register

upon power-up or whenever the TAP controller is given a test

logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO balls when the TAP

controller is in a Shift-DR state. It also places all SRAM outputs

into a High-Z state.

SAMPLE/PRELOAD

SAMPLE / PRELOAD is a 1149.1 mandatory instruction.

When the SAMPLE / PRELOAD instructions are loaded into

the instruction register and the TAP controller is in the Cap-

ture-DR state, a snapshot of data on the inputs and output pins

is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 20 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is possi-

ble that during the Capture-DR state, an input or output will

undergo a transition. The TAP may then try to capture a signal

while in transition (metastable state). This will not harm the

device, but there is no guarantee as to the value that will be

captured. Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture set-up plus

hold times (tCS and tCH). The SRAM clock input might not be

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE / PRELOAD instruction. If

this is an issue, it is still possible to capture all other signals

and simply ignore the value of the CK and CK# captured in the

boundary scan register.

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CY7C1367C

Document #: 38-05542 Rev. *A Page 11 of 27

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the bound-

ary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells pri-

or to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases

can occur concurrently when required - that is, while data

captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

TAP Timing

TAP AC Switching Characteristics Over the operating Range[3, 4]

Parameter Symbol Min Max Unit

Clock

TCK Clock Cycle Time tTCYC 50 ns

TCK Clock Frequency tTF 20 MHz

TCK Clock HIGH time tTH 25 ns

TCK Clock LOW time tTL 25 ns

Output Times

TCK Clock LOW to TDO Valid tTDOV 5ns

TCK Clock LOW to TDO Invalid tTDOX 0ns

Setup Times

TMS Set-Up to TCK Clock Rise tTMSS 5ns

TDI Set-Up to TCK Clock Rise tTDIS 5ns

Capture Set-Up to TCK Rise tCS 5

Hold Times

TMS hold after TCK Clock Rise tTMSH 5ns

TDI Hold after Clock Rise tTDIH 5ns

Capture Hold after Clock Rise tCH 5ns

tTL

Test Clock

(TCK)

123456

est Mode Select

(TMS)

tTH

Test Data-Out

(TDO)

tCYC

Test Data-In

(TDI)

tTMSH

tTMSS

tTDIH

tTDIS

tTDOX

tTDOV

DON’T CARE UNDEFINED

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Document #: 38-05542 Rev. *A Page 12 of 27

Notes:

3. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

4. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.

TAP AC Switching Characteristics Over the operating Range[3, 4]

Parameter Symbol Min Max Unit

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Document #: 38-05542 Rev. *A Page 13 of 27

3.3V TAP AC Test Conditions

Input pulse levels ....... ........................................VSS to 3.3V

Input rise and fall times...................... ..............................1ns

Input timing reference levels ...........................................1.5V

Output reference levels...................................................1.5V

Test load termination supply voltage...............................1.5V

3.3V TAP AC Output Load Equivalent

2.5V TAP AC Test Conditions

Input pulse levels ........................................ VSS to 2.5V

Input rise and fall time ......................................................1ns

Input timing reference levels................... ......................1.25V

Output reference levels .................. ..............................1.25V

Test load termination supply voltage .................... ........1.25V

2.5V TAP AC Output Load Equivalent

1.5V

20p

Z = 50Ω

50Ω

1.25V

20p

Z = 50Ω

50Ω

TAP DC Electrical Characteristics And Operating Conditions

(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)[5]

Parameter Description Conditions Min. Max. Unit

VOH1 Output HIGH Voltage IOH = –4.0 mA VDDQ = 3.3V 2.4 V

IOH = –1.0 mA VDDQ = 2.5V 2.0 V

VOH2 Output HIGH Voltage IOH = –100 µA VDDQ = 3.3V 2.9 V

VDDQ = 2.5V 2.1 V

VOL1 Output LOW Voltage IOL = 8.0 mA VDDQ = 3.3V 0.4 V

IOL = 8.0 mA VDDQ = 2.5V 0.4 V

VOL2 Output LOW Voltage IOL = 100 µA VDDQ = 3.3V 0.2 V

VDDQ = 2.5V 0.2 V

VIH Input HIGH Voltage VDDQ = 3.3V 2.0 VDD + 0.3 V

VDDQ = 2.5V 1.7 VDD + 0.3 V

VIL Input LOW Voltage VDDQ = 3.3V –0.5 0.7 V

VDDQ = 2.5V –0.3 0.7 V

IXInput Load Current GND < VIN < VDDQ –5 5 µA

Identification Register Definitions

Instruction Field

CY7C1366C

(256K x36)

CY7C1367C

(512K x18) Description

Revision Number (31:29) 000 000 Describes the version number.

Device Depth (28:24)[6] 01011 01011 Reserved for Internal Use

Device Width (23:18) 000110 000110 Defines memory type and architecture

Cypress Device ID (17:12) 100110 010110 Defines width and density

Cypress JEDEC ID Code (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor.

ID Register Presence Indicator (0) 11

Indicates the presence of an ID register.

Note:

5. All voltages referenced to VSS (GND).

6. Bit #24 is “1” in the Register Definitions for both 2.5v and 3.3v versions of this device.

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Document #: 38-05542 Rev. *A Page 14 of 27

Scan Register Sizes

Instruction 3 3

Bypass 1 1

ID 32 32

Boundary Scan Order (119-ball BGA package) 71 71

Boundary Scan Order (165-ball fBGA package) 71 71

Identification Codes

Instruction Code Description

EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM outputs to High-Z state.

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and

TDO. This operation does not affect SRAM operations.

SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Does not affect SRAM operation.

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

119-Ball BGA Boundary Scan Order

CY7C1366C (256K x 36) CY7C1367C (512K x 18)

BIT#

BALL

Signal

Name BIT# BALL ID

Signal

Name BIT# BALL ID

Signal

Name BIT# BALL ID

Signal

Name

1K4 CLK 37 P4 A0 1 K4 CLK 37 P4 A0

2H4 GW38 N4 A1 2 H4 GW 38 N4 A1

3M4BWE

39 R6 A 3 M4 BWE 39 R6 A

4F4 OE40 T5 A 4 F4 OE 40 T5 A

5B4ADSC

41 T3 A 5 B4 ADSC 41 T3 A

6A4ADSP

42 R2 A 6 A4 ADSP 42 R2 A

7G4ADV

43 R3 MODE 7 G4 ADV 43 R3 MODE

8C3 A 44 P2 DQP

D8 C3 A 44 Internal Internal

9B3 A 45 P1 DQ

D9 B3 A 45 Internal Internal

10 D6 DQPB46 L2 DQD10 T2 A 46 Internal Internal

11 H7 DQB47 K1 DQD11 Internal Internal 47 Internal Internal

12 G6 DQB48 N2 DQD12 Internal Internal 48 P2 DQPB

13 E6 DQB49 N1 DQD13 Internal Internal 49 N1 DQB

14 D7 DQB50 M2 DQD14 D6 DQPA50 M2 DQB

15 E7 DQB51 L1 DQD15 E7 DQA51 L1 DQB

16 F6 DQB52 K2 DQD16 F6 DQA52 K2 DQB

17 G7 DQB53 Internal Internal 17 G7 DQA53 Internal Internal

18 H6 DQB54 H1 DQC18 H6 DQA54 H1 DQB

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19 T7 ZZ 55 G2 DQC19 T7 ZZ 55 G2 DQB

20 K7 DQA56 E2 DQC20 K7 DQA56 E2 DQB

21 L6 DQA57 D1 DQC21 L6 DQA57 D1 DQB

22 N6 DQA58 H2 DQC22 N6 DQA58 Internal Internal

23 P7 DQA59 G1 DQC23 P7 DQA59 Internal Internal

24 N7 DQA60 F2 DQC24 Internal Internal 60 Internal Internal

25 M6 DQA61 E1 DQC25 Internal Internal 61 Internal Internal

26 L7 DQA62 D2 DQPC26 Internal Internal 62 Internal Internal

27 K6 DQA63 C2 A 27 Internal Internal 63 C2 A

28 P6 DQPA64 A2 A 28 Internal Internal 64 A2 A

29 T4 A 65 E4 CE129 T6 A 65 E4 CE1

30 A3 A 66 B2 CE230 A3 A 66 B2 CE2

31 C5 A 67 L3 BWD31 C5 A 67 Internal Internal

32 B5 A 68 G3 BWC32 B5 A 68 Internal Internal

33 A5 A 69 G5 BWB33 A5 A 69 G3 BWB

34 C6 A 70 L5 BWA34 C6 A 70 L5 BWA

35 A6 A 71 Internal Internal 35 A6 A 71 Internal Internal

36 B6 A 36 B6 A

165-Ball fBGA Boundary Scan Order

CY7C1366C (256K x 36) CY7C1367C (512K x 18)

BIT# BALL ID

Signal

Name BIT# BALL ID

Signal

Name BIT# BALL ID

Signal

Name BIT# BALL ID

Signal

Name

1 B6 CLK 37 R6 A0 1 B6 CLK 37 R6 A0

2B7GW

38 P6 A1 2 B7 GW 38 P6 A1

3A7BWE

39 R4 A 3 A7 BWE 39 R4 A

4B8OE

40 P4 A 4 B8 OE 40 P4 A

5A8ADSC

41 R3 A 5 A8 ADSC 41 R3 A

6B9ADSP

42 P3 A 6 B9 ADSP 42 P3 A

7A9ADV

43 R1 MODE 7 A9 ADV 43 R1 MODE

8B10 A 44 N1 DQP

D8 B10 A 44 Internal Internal

9A10 A 45 L2 DQ

D9 A10 A 45 Internal Internal

10 C11 DQPB46 K2 DQD10 A11 A 46 Internal Internal

11 E10 DQB47 J2 DQD11 Internal Internal 47 Internal Internal

12 F10 DQB48 M2 DQD12 Internal Internal 48 N1 DQPB

13 G10 DQB49 M1 DQD13 Internal Internal 49 M1 DQB

14 D10 DQB50 L1 DQD14 C11 DQPA50 L1 DQB

15 D11 DQB51 K1 DQD15 D11 DQA51 K1 DQB

16 E11 DQB52 J1 DQD16 E11 DQA52 J1 DQB

17 F11 DQB53 Internal Internal 17 F11 DQA53 Internal Internal

119-Ball BGA Boundary Scan Order (continued)

CY7C1366C (256K x 36) CY7C1367C (512K x 18)

BIT#

BALL

Signal

Name BIT# BALL ID

Signal

Name BIT# BALL ID

Signal

Name BIT# BALL ID

Signal

Name

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CY7C1367C

Document #: 38-05542 Rev. *A Page 16 of 27

18 G11 DQB54 G2 DQC18 G11 DQA54 G2 DQB

19 H11 ZZ 55 F2 DQC19 H11 ZZ 55 F2 DQB

20 J10 DQA56 E2 DQC20 J10 DQA56 E2 DQB

21 K10 DQA57 D2 DQC21 K10 DQA57 D2 DQB

22 L10 DQA58 G1 DQC22 L10 DQA58 Internal Internal

23 M10 DQA59 F1 DQC23 M10 DQA59 Internal Internal

24 J11 DQA60 E1 DQC24 Internal Internal 60 Internal Internal

25 K11 DQA61 D1 DQC25 Internal Internal 61 Internal Internal

26 L11 DQA62 C1 DQPC26 Internal Internal 62 Internal Internal

27 M11 DQA63 B2 A 27 Internal Internal 63 B2 A

28 N11 DQPA64 A2 A 28 Internal Internal 64 A2 A

29 R11 A 65 A3 CE129 R11 A 65 A3 CE1

30 R10 A 66 B3 CE230 R10 A 66 B3 CE2

31 P10 A 67 B4 BWD31 P10 A 67 Internal Internal

32 R9 A 68 A4 BWC32 R9 A 68 Internal Internal

33 P9 A 69 A5 BWB33 P9 A 69 A4 BWB

34 R8 A 70 B5 BWA34 R8 A 70 B5 BWA

35 P8 A 71 A6 CE335 P8 A 71 A6 CE3

36 P11 A 36 P11 A

165-Ball fBGA Boundary Scan Order (continued)

CY7C1366C (256K x 36) CY7C1367C (512K x 18)

BIT# BALL ID

Signal

Name BIT# BALL ID

Signal

Name BIT# BALL ID

Signal

Name BIT# BALL ID

Signal

Name

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CY7C1367C

Document #: 38-05542 Rev. *A Page 17 of 27

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V

DC Voltage Applied to Outputs

in three-state ....................................... –0.5V to VDDQ + 0.5V

DC Input Voltage....................................–0.5V to VDD + 0.5V

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-up Current..................................................... >200 mA

Operating Range

Range

Ambient

Temperature VDD VDDQ

Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%

to VDD

Industrial –40°C to +85°C

Electrical Characteristics Over the Operating Range [7, 8]

Parameter Description Test Conditions Min. Max. Unit

VDD Power Supply Voltage 3.135 3.6 V

VDDQ I/O Supply Voltage VDDQ = 3.3V 3.135 VDD V

VDDQ = 2.5V 2.375 2.625 V

VOH Output HIGH Voltage VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA 2.4 V

VDDQ = 2.5V, VDD = Min., IOH= –1.0 mA 2.0 V

VOL Output LOW Voltage VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA 0.4 V

VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA 0.4 V

VIH Input HIGH Voltage[7] VDDQ = 3.3V 2.0 VDD + 0.3V V

VDDQ = 2.5V 1.7 VDD + 0.3V V

VIL Input LOW Voltage[7] VDDQ = 3.3V –0.3 0.8 V

VDDQ = 2.5V –0.3 0.7 V

IXInput Load Current

except ZZ and MODE

GND ≤ VI ≤ VDDQ –5 5 µA

Input Current of MODE Input = VSS –30 µA

Input = VDD 5µA

Input Current of ZZ Input = VSS –5 µA

Input = VDD 30 µA

IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled –5 5 µA

IDD VDD Operating Supply

Current

VDD = Max., IOUT = 0 mA,

f = fMAX = 1/tCYC

4.4-ns cycle, 225 MHz 250 mA

5-ns cycle, 200 MHz 220 mA

6-ns cycle, 166 MHz 180 mA

ISB1 Automatic CE

Power-down

Current—TTL Inputs

VDD = Max, Device Deselected,

VIN ≥ VIH or VIN ≤ VIL

f = fMAX = 1/tCYC

All speeds 50 mA

ISB2 Automatic CE

Power-down

Current—CMOS Inputs

VDD = Max, Device Deselected,

VIN ≤ 0.3V or VIN > VDDQ – 0.3V,

f = 0

All speeds 30 mA

ISB3 Automatic CE

Power-down

Current—CMOS Inputs

VDD = Max, Device Deselected, or

VIN ≤ 0.3V or VIN > VDDQ – 0.3V

f = fMAX = 1/tCYC

All speeds 50 mA

ISB4 Automatic CE

Power-down

Current—TTL Inputs

VDD = Max, Device Deselected,

VIN ≥ VIH or VIN ≤ VIL, f = 0

All Speeds 40 mA

Shaded areas contain advance information.

Notes:

7. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2).

8. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD\

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Document #: 38-05542 Rev. *A Page 18 of 27

Note:

9. Tested initially and after any design or process change that may affect these parameters.

Thermal Resistance[9]

Parameter Description Test Conditions

TQFP

Package

BGA

Package

fBGA

Package Unit

ΘJA Thermal Resistance

(Junction to Ambient)

Test conditions follow standard

test methods and procedures

for measuring thermal

impedance, per EIA / JESD51.

25 25 27 °C/W

ΘJC Thermal Resistance

(Junction to Case)

966°C/W

Capacitance[9]

Parameter Description Test Conditions

TQFP

Package

BGA

Package

fBGA

Package Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VDD = 3.3V.

VDDQ = 2.5V

555pF

CCLK Clock Input Capacitance 5 5 5 pF

CI/O Input/Output Capacitance 5 7 7 pF

AC Test Loads and Waveforms

OUTPUT

R = 317Ω

R = 351Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

= 1.5V

3.3V ALL INPUT PULSES

VDDQ

GND

90%

10%

90%

10%

≤1ns ≤1ns

(c)

OUTPUT

R = 1667Ω

R =1538Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

VT= 1.25V

2.5V ALL INPUT PULSES

VDDQ

GND

90%

10%

90%

10%

≤1ns ≤1ns

(c)

3.3V I/O Test Load

2.5V I/O Test Load

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Document #: 38-05542 Rev. *A Page 19 of 27

Switching Characteristics Over the Operating Range[14, 15]

Parameter Description

225 MHz 200 MHz 166 MHz

Unit

Min. Max Min. Max Min. Max

tPOWER VDD(Typical) to the first Access[10] 1 1 1ms

Clock

tCYC Clock Cycle Time 4.4 5.0 6.0 ns

tCH Clock HIGH 1.8 2.0 2.4 ns

tCL Clock LOW 1.8 2.0 2.4 ns

Output Times

tCO Data Output Valid After CLK Rise 2.8 3.0 3.5 ns

tDOH Data Output Hold After CLK Rise 1.25 1.25 1.25 ns

tCLZ Clock to Low-Z[11, 12, 13] 1.25 1.25 1.25 ns

tCHZ Clock to High-Z[11, 12, 13] 1.25 2.8 1.25 3.0 1.25 3.5 ns

tOEV OE LOW to Output Valid 2.8 3.0 3.5 ns

tOELZ OE LOW to Output Low-Z[11, 12, 13] 0 0 0ns

tOEHZ OE HIGH to Output High-Z[11, 12, 13] 2.8 3.0 3.5 ns

Set-up Times

tAS Address Set-up Before CLK Rise 1.4 1.5 1.5 ns

tADS ADSC, ADSP Set-up Before CLK Rise 1.4 1.5 1.5 ns

tADVS ADV Set-up Before CLK Rise 1.4 1.5 1.5 ns

tWES GW, BWE, BWX Set-up Before CLK Rise 1.4 1.5 1.5 ns

tDS Data Input Set-up Before CLK Rise 1.4 1.5 1.5 ns

tCES Chip Enable Set-Up Before CLK Rise 1.4 1.5 1.5 ns

Hold Times

tAH Address Hold After CLK Rise 0.4 0.5 0.5 ns

tADH ADSP , ADSC Hold After CLK Rise 0.4 0.5 0.5 ns

tADVH ADV Hold After CLK Rise 0.4 0.5 0.5 ns

tWEH GW,BWE, BWX Hold After CLK Rise 0.4 0.5 0.5 ns

tDH Data Input Hold After CLK Rise 0.4 0.5 0.5 ns

tCEH Chip Enable Hold After CLK Rise 0.4 0.5 0.5 ns

Shaded areas contain advance information.

Notes:

10. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation

can be initiated.

11. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

12. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions

13. This parameter is sampled and not 100% tested.

14. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.

15. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

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Document #: 38-05542 Rev. *A Page 20 of 27

Switching Waveforms

Read Cycle Timing[16]

Notes:

16. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

GW, BWE,BW

Data Out (DQ) High-Z

tDOH

tCO

ADV

tOEHZ

tCO

Single READ BURST READ

tOEV

tOELZ tCHZ

Burst wraps around

to its initial state

tADVH

tADVS

tWEH

tWES

tADH

tADS

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A1) Q(A2)

Q(A2 + 1)

Q(A3)

Q(A2 + 3)

A2 A3

Deselect

cycle

Burst continued with

new base address

ADV suspends burst

DON’T CARE UNDEFINED

CLZ

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Document #: 38-05542 Rev. *A Page 21 of 27

Write Cycle Timing[16, 17]

Note:

17. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

BWE,

ADV

BURST READ BURST WRITE

D(A2)

D(A2 + 1)

D(A3)

D(A3 + 1)

D(A3 + 2)

D(A2 + 3)

A2 A3

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

OEHZ

tADVH

tADVS

tWEH

tWES

tDH

tDS

tWEH

tWES

Byte write signals are ignored for first cycle when

ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE UNDEFINED

D(A1)

High-Z

Data in (D)

Data Out (Q)

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Document #: 38-05542 Rev. *A Page 22 of 27

Read/Write Cycle Timing[16, 18, 19]

Notes:

18. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

19. GW is HIGH.

Switching Waveforms (continued)

CYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

ata Out (Q) High-Z

ADV

Single WRITE

D(A3)

A4 A5 A6

D(A5) D(A6)

Data In (D)

BURST READ

Back-to-Back READs

High-Z

Q(A2)Q(A1) Q(A4)

Q(A4+1) Q(A4+2)

tWEH

tWES

Q(A4+3)

tOEHZ

tDH

tDS

tOELZ

tCLZ

tCO

Back-to-Back

WRITEs

BWE, BW

DON’T CARE UNDEFINED

PRELIMINARY

CY7C1366C

CY7C1367C

Document #: 38-05542 Rev. *A Page 23 of 27

Switching Waveforms (continued)

tZZ

SUPPLY

CLK

tZZREC

LL INPUTS

(except ZZ)

DON’T CARE

IDDZZ

tZZI

tRZZI

Outputs (Q)

High-Z

DESELECT or READ Only

Z Mode Timing

[20

21]

Ordering Information

Speed

(MHz) Ordering Code

Package

Name Part and Package Type

Operating

Range

225

CY7C1366C-225AXC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

3 Chip Enables

Commercial

CY7C1367C-225AXC

CY7C1366C-225AXI A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

3 Chip Enables

Industrial

CY7C1367C-225AXI

CY7C1366C-225BGC BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with

JTAG

Commercial

CY7C1367C-225BGC

CY7C1366C-225BGI BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with

JTAG

Industrial

CY7C1367C-225BGI

CY7C1366C-225BZC BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)

3 Chip Enables with JTAG

Commercial

CY7C1367C-225BZC

CY7C1366C-225BZI BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)

3 Chip Enables with JTAG

Industrial

CY7C1367C-225BZI

200 CY7C1366C-200AXC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

3 Chip Enables

Commercial

CY7C1367C-200AXC

CY7C1366C-200AXI A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

3 Chip Enables

Industrial

CY7C1367C-200AXI

CY7C1366C-200BGC BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with

JTAG

Commercial

CY7C1367C-200BGC

CY7C1366C-200BGI BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with

JTAG

Industrial

CY7C1367C-200BGI

CY7C1366C-200BZC BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)

3 Chip Enables with JTAG

Commercial

CY7C1367C-200BZC

CY7C1366C-200BZI BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)

3 Chip Enables with JTAG

Industrial

CY7C1367C-200BZI

Notes:

20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

21. DQs are in high-Z when exiting ZZ sleep mode.

PRELIMINARY

CY7C1366C

CY7C1367C

Document #: 38-05542 Rev. *A Page 24 of 27

166 CY7C1366C-166AXC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

3 Chip Enables

Commercial

CY7C1367C-166AXC

CY7C1366C-166AXI A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

3 Chip Enables

Industrial

CY7C1367C-166AXI

CY7C1366C-166BGC BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with

JTAG

Commercial

CY7C1367C-166BGC

CY7C1366C-166BGI BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with

JTAG

Industrial

CY7C1367C-166BGI

CY7C1366C-166BZC BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)

3 Chip Enables with JTAG

Commercial

CY7C1367C-166BGC

CY7C1366C-166BZI BB165D 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)

3 Chip Enables with JTAG

Industrial

CY7C1367C-166BGI

Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.Lead-free BG and BZ packages (Ordering

code:BGX,BZX) will be available in 2005.

Package Diagrams

Ordering Information (continued)

Speed

(MHz) Ordering Code

Package

Name Part and Package Type

Operating

Range

DIMENSIONS ARE IN MILLIMETERS.

0.30±0.08

0.65

20.00±0.10

22.00±0.20

1.40±0.05

12°±1°

1.60 MAX.

0.05 MIN.

0.60±0.15

0° MIN.

0.25

0°-7°

(8X)

STAND-OFF

R 0.08 MIN.

TYP.

0.20 MAX.

0.15 MAX.

0.20 MAX.

R0.08MIN.

0.20 MAX.

14.00±0.10

16.00±0.20

0.10

SEE DETAIL A

DETAIL A

100

31 50

GAUGE PLANE

1.00 REF.

0.20 MIN.

SEATING PLANE

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

51-85050-*A

PRELIMINARY

CY7C1366C

CY7C1367C

Document #: 38-05542 Rev. *A Page 25 of 27

Package Diagrams (continued)

51-85115-*B

119-Lead PBGA (14 x 22 x 2.4 mm) BG119

PRELIMINARY

CY7C1366C

CY7C1367C

Document #: 38-05542 Rev. *A Page 26 of 27

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM

Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

Package Diagrams (continued)

51-85180-**

165 FBGA 13 x 15 x 1.40 MM BB165D

PRELIMINARY

CY7C1366C

CY7C1367C

Document #: 38-05542 Rev. *A Page 27 of 27

Document History Page

Document Title: CY7C1366C/CY7C1367C 9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM (Preliminary)

Document Number: 38-05542

REV. ECN NO. Issue Date

Orig. of

Change Description of Change

** 241690 See ECN RKF New data sheet

*A 278969 See ECN RKF Changed Boundary Scan order to match the B rev of these devices.