SY89858U Precision Low Power 1:8 LVPECL Fanout Buffer with Internal Termination General Description The SY89858U is a 2.5V/3.3V precision, highspeed, fully differential LVPECL 1:8 fanout buffer optimized to provide eight identical output copies with less than 30ps of skew and less than 10pspp total jitter. It can process clock signals as fast as 2.0GHz. The differential input includes Micrel's unique, 3-pin input termination architecture that allows the SY89858U to directly interface to LVPECL, CML, and LVDS differential signals (AC- or DC-coupled) as small as 100mV without any level shifting or termination resistor networks in the signal path. The result is a clean, stub-free, low-jitter interface solution. The LVPECL (100k temperature compensated) outputs feature 800mV typical swing into 50 loads, and provide fast rise/fall times guaranteed to be less than 200ps. The SY89858U operates from a 2.5V 5% supply or 3.3V 10% supply and is guaranteed over the full industrial temperature range of -40C to +85C. For applications that require a higher speed fanout buffer, consider the SY58032U. The SY89858U is (R) part of Micrel's high-speed, Precision Edge product line. All support documentation can be found on Micrel's web site at: www.micrel.com. Precision Edge (R) Features * Precision 1:8, LVPECL fanout buffer * Low power: 238mW (2.5V) * Guaranteed AC performance over temperature and supply voltage: - Wide operating frequency: DC to 2.0GHz - <380ps In-to-Out tpd - <200ps tr/tf - <30ps skew * Ultra-low jitter design: - <1psRMS random jitter - <1psRMS cycle-to-cycle jitter - <10psPPtotal jitter * 100k LVPECL compatible outputs * Fully differential inputs/outputs * Accepts an input signal as low as 100mV (200mVpp) * Unique patent pending input termination and VT pin accepts DC-coupled and AC-coupled differential inputs (LVPECL, LVDS, and CML) * Power supply 2.5V 5% or 3.3V 10% * -40C to +85C industrial temperature range * Available in 32-pin (5mm x 5mm) QFN package Applications * * * * All SONET and GigE clock distribution All Fibre Channel clock and data distribution Network routing engine timing distribution High-end, low-skew multiprocessor synchronous clock distribution Markets * * * * LAN/WAN Enterprise servers ATE Test and measurement Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com August 2007 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89858U Typical Application August 2007 2 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89858U Ordering Information(1) Part Number Package Type Operating Range Package Marking SY89858UMG QFN-32 Industrial SY89858 with Pb-Free bar-line indicator NiPdAu Pb-Free QFN-32 Industrial SY89858 with Pb-Free bar-line indicator NiPdAu Pb-Free (2) SY89858UMGTR Lead Finish Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals Only. 2. Tape and Reel. Pin Configuration 32-Pin QFN Pin Description Pin Number Pin Name Pin Function IN, /IN Differential Input: This differential input accepts AC- or DC-coupled signals as small as 100mV (200mVPP). Each pin of this pair internally terminates to a VT pin through 50. Note that these inputs will default to an indeterminate state if left open. Please refer to the "Input Interface Applications" section for more details. VT Input Termination Center-Tap: Each side of the differential input pair terminates to this VT pin. The VT pin provides a center-tap to a termination network for maximum interface flexibility. See the "Input Interface Applications" section for more details. 5 VREF-AC Reference Voltage: This output biases to VCC-1.2V (typical). It is used for ACcoupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01uF low ESR capacitor to VCC. Maximum sink/source capability is 1.5mA. 1, 8, 9, 16, 18, 23, 25, 32 VCC Positive Power Supply: Bypass with 0.1F//0.01F low ESR capacitors as close to the VCC pins as possible. 31, 30, 29, 28, 27, 26, 22, 21, 20, 19, 15, 14, 13, 12, 11, 10 Q0, /Q0, Q1, /Q1, Q2, /Q2, Q3, /Q3, Q4, /Q4, Q5, /Q5, Q6, /Q6, Q7, /Q7 100k LVPECL Differential Outputs: Differential buffered output copy of the input signal. The LVPECL output swing is typically 800mV into to 50 V CC-2V. Unused output pairs may be left floating with no impact on jitter. See "LVPECL Output" section. 2, 7, 17, 24 GND Exposed Pad Ground: Ground pins and exposed pad must be connected to the same ground plane. 3, 6 4 August 2007 3 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89858U Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC) .......................... -0.5V to +4.0V Input Voltage (VIN) ..................................-0.5V to VCC Termination Current Source or sink current on VT .................. 100mA (3) Reference Current Source or sink current on VREF-AC ............ 1.5mA LVPECL Output Current (IOUT) Continuous ................................................. 50mA Surge ........................................................ 100mA Lead Temperature (soldering, 20 sec.) .......... +260C Storage Temperature (Ts) ..................-65C to 150C Supply Voltage (VCC).................. +2.375V to +2.625V ......................................................+3.0V to +3.6V Ambient Temperature (TA) ................ -40C to +85C (4) Package Thermal Resistance QFN (JA) Still-Air ..................................................... 35C/W QFN (JB) Junction-to-Board .................................... 20C/W DC Electrical Characteristics(5) TA = -40C to +85C, unless otherwise stated. Symbol Parameter VCC Power Supply Condition Min Typ Max Units 2.375 2.5 2.625 V 3.0 3.3 3.6 V 95 150 mA ICC Power Supply Current RIN Input Resistance (IN-to-VT) No load, max. VCC 45 50 55 RDIFF_IN Differential Input Resistance (IN-to-/IN) 90 100 110 VIH Input High Voltage (IN, /IN) VCC -1.6 VCC V VIL Input Low Voltage (IN, /IN) 0 VIH-0.1 V VIN Input Voltage Swing (IN, /IN) See Figure 1a. 0.1 1.7 V VDIFF_IN Differential Input Voltage Swing |IN-/IN| See Figure 1b. VT_IN IN-to-VT (IN, /IN) VREF-AC Output Reference Voltage Note 6 0.2 VCC-1.3V V VCC-1.2V 1.28 V VCC-1.1V V Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Due to the limited drive capability use for input of the same package only. 4. Package Thermal Resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. JA and JB values are determined for a 4-layer board in still air, unless otherwise stated. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. VIH (min) not lower than 1.2V. August 2007 4 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89858U LVPECL Outputs DC Electrical Characteristics(7) VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C; RL = 50 to VCC -2V, unless otherwise stated. Symbol Parameter Condition Min Typ Max Units VOH Output HIGH Voltage Q, /Q VCC-1.145 VCC-0.895 V VOL Output LOW Voltage Q, /Q VCC-1.945 VCC-1.695 V VOUT Output Voltage Swing Q, /Q See Figure 1a. 500 800 mV VDIFF-OUT Differential Output Voltage Swing Q, /Q See Figure 1b. 1000 1600 mV Note: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. AC Electrical Characteristics(8) VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C, RL = 50 to VCC -2V, unless otherwise stated. Symbol Parameter Condition Min Typ fMAX Maximum Operating Frequency VOUT 400mV 2.0 3.0 tPD Propagation Delay (IN-to-Q) 180 260 Tpd Tempco Differential Propagation Delay Temperature Coefficient Tskew tJitter tR, tF Max Units GHz 380 ps o fs/ C 115 Output-to-Output Skew Note 9 30 Part-to-Part Skew Note 10 150 Random Jitter (RJ) Note 11 1 psRMS Deterministic Jitter (DJ) Note 12 10 psPP Cycle-to-Cycle Jitter Note 13 1 psPP Total Jitter Note 14 10 psPP Output Rise/Fall Time (20% to 80%) At full output swing. 200 ps 75 130 ps Notes: 8. High-frequency AC-parameters are guaranteed by design and characterization. 9. Output-to-output skew is measured between outputs under identical conditions. 10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. Part-to-part skew includes variation in tpd. 11. Random jitter is measured with a K28.7 character pattern, measured at 2.5Gbps. 12. Deterministic Jitter is measured at 2.5Gbps, with both K28.5 and 223 - 1 PRBS pattern. 13. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, Tn - Tn-1 where T is the time between rising edges of the output signal. 14. Total jitter definition: With an ideal clock input of frequency <fMAX, no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. August 2007 5 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89858U Typical Operating Characteristics Output Swing vs. Frequency Propagation Delay vs. Input Swing 900 270 800 265 700 600 260 500 255 400 300 250 200 245 100 0 240 0 200 400 600 800 1000 INPUT SWING (mV) FREQUENCY (MHz) Functional Characteristics August 2007 6 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89858U Singled-Ended and Differential Swings Figure 1a. Single-Ended Voltage Swing Figure 1b. Differential Voltage Swing Timing Diagram Input and Output Stages Figure 2b. Simplified LVPECL Output Stage Figure 2a. Simplified Differential Input Stage August 2007 7 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89858U Input Interface Applications Option: may connect VT to VCC Figure 3a. LVPECL Interface (DC-Coupled) Figure 3d. CML Interface (AC-Coupled) August 2007 Figure 3b. LVPECL Interface (AC-Coupled) Figure 3e. LVDS Interface (DC-Coupled) 8 Figure 3c. CML Interface (DC-Coupled) Figure 3f. LVDS Interface (AC-Coupled) M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89858U Termination-Thevenin Equivalent, Parallel Termination (3-resistor), and AC-coupled Termination. Unused output pairs may be left floating. However, single-ended outputs must be terminated, or balanced. LVPECL Output Interface Applications LVPECL has high input impedance, and very low output impedance (open emitter), and small signal swing which results in low EMI. LVPECL is ideal for driving 50 and 100 controlled impedance transmission lines. There are several techniques for terminating the LVPECL output: Parallel Figure 4a. Parallel Termination-Thevenin Equivalent Figure 4b. Parallel Termination (3-Resistor) Related Product and Support Documentation Part Number Function Datasheet Link SY58032U Ultra-Precision 1:8 LVPECL Fanout Buffer w/Internal Termination www.micrel.com/product-info/products/sy58032u.shtml HBW Solutions New Products and Applications www.micrel.com/product-info/products/solutions.shtml August 2007 9 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89858U Package Information 32-Pin (5mm x 5mm) Package Notes: 1. Package meets Level 2 Moisture Sensitivity Classification. 2. All parts are dry-packaged before shipment. 3. Exposed pad must be soldered to a ground for proper thermal management. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2004 Micrel, Incorporated. August 2007 10 M9999-082907-C hbwhelp@micrel.com or (408) 955-1690