MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DLow Supply-Voltage Range, 1.8 V to 3.6 V
DUltralow-Power Consumption:
− Active Mode: 300 μA at 1 MHz, 2.2 V
− Standby Mode: 1.1 μA
− Off Mode (RAM Retention): 0.1 μA
DFive Power Saving Modes
DWake-Up From Standby Mode in Less
Than 6 μs
D16-Bit RISC Architecture,
125-ns Instruction Cycle Time
DSingle-Channel Internal DMA
D12-Bit A/D Converter With Internal
Reference, Sample-and-Hold and
Autoscan Feature
DThree Configurable Operational Amplifiers
DDual 12-Bit D/A Converters With
Synchronization
D16-Bit Timer_A With Three
Capture/Compare Registers
D16-Bit Timer_B With Three
Capture/Compare-With-Shadow Registers
DOn-Chip Comparator
DSerial Communication Interface (USART),
Select Asynchronous UART or
Synchronous SPI by Software
DBrownout Detector
DSupply Voltage Supervisor/Monitor With
Programmable Level Detection
DBootstrap Loader
DSerial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
DIntegrated LCD Driver for Up to
128 Segments
DFamily Members Include:
− MSP430FG437:
32KB+256B Flash Memory,
1KB RAM
− MSP430FG438:
48KB+256B Flash Memory,
2KB RAM
− MSP430FG439:
60KB+256B Flash Memory,
2KB RAM
DFor Complete Module Descriptions, See
The MSP430x4xx Family User’s Guide,
Literature Number SLAU056
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6μs.
The MSP430FG43x series are microcontroller configurations with two 16-bit timers, a high performance 12-bit
A/D converter, dual 12-bit D/A converters, three configurable operational amplifiers, one universal
synchronous/asynchronous communication interface (USART), DMA, 48 I/O pins, and a liquid crystal display
(LCD) driver.
Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, hand-held meters, etc.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2004 − 2007, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGED DEVICES
TAPLASTIC 80-PIN QFP
(PN)
−40°C to 85°C
MSP430FG437IPN
MSP430FG438IPN
MSP430FG439IPN
pin designation, MSP430FG437IPN, MSP430FG438IPN, MSP430FG439IPN
22 23
P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
P2.4/UTXD0
P2.5/URXD0
DVSS2
DVCC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P3.0/STE0/S31
P3.1/SIMO0/S30
P3.2/SOMI0/S29
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DVCC1
P6.3/A3/OA1I1/OA1O
P6.4/A4/OA1I0
P6.5/A5/OA2I1/OA2O
P6.6/A6/DAC0/OA2I0
P6.7/A7/DAC1/SVSIN
VREF+
XIN
XOUT
VeREF+/DAC0
VREF−/VeREF−
P5.1/S0/A12/DAC1
P5.0/S1/A13
P4.7/S2/A14
P4.6/S3/A15
P4.5/S4
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
25 26 27 28
PN PACKAGE
(TOP VIEW)
TDO/TDI
79 78 77 76 7580 74
P6.1/A1/OA0O
P6.0/A0/OA0I0
RST/NMI
TCK
TMS
P2.6/CAOUT/S19
S21
S15
S16
S17
72 71 7073
29 30 31 32 33
69 68
21
P4.0/S9
XT2OUT
67 66 65 64
34 35 36 37
S22
S23
P3.7/S24
P3.6/S25/DMAE0
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P3.5/S26
P3.4/S27
38 39 40
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
63 62 61
TDI/TCLK
XT2IN
P1.6/CA0
S10
S20
P3.3/UCLK0/S28
S11
S12
S13
S14
P2.7/ADC12CLK/S18
P6.2/A2/OA0I1
MSP430FG43xIPN
AVCC
DVSS1
AVSS
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430FG43x functional block diagram
Comparator_
A
DVCC1/2 DVSS1/2 AVCC AVSS
RST/NMI
P2
Flash
60KB
48KB
32KB
RAM
2KB
1KB
Watchdog
Timer
WDT
15/16-Bit
Port 2
8 I/O
Interrupt
Capability
POR/
SVS/
Brownout
Basic
Timer 1
1 Interrupt
Vector
LCD
128
Segments
1,2,3,4 MUX
fLCD
8
MCLK
XOUT
JTAG
Interface
XIN
SMCLK
ACLK
MDB
MAB
Emulation
P3
Port 3
8 I/O
8
Module Timer_A3
3 CC Reg
P1
Port 1
8 I/O
Interrupt
Capability
8
P4
Port 4
8 I/O
8
Timer_B3
3 CC Reg
Shadow
Reg
USART0
UART Mode
SPI Mode
XT2IN
XT2OUT ADC12
12-Biit
12 Channels
<10μs Conv.
Oscillator
FLL+
8 MHz
CPU
incl. 16
Registers
OA0, OA1
OA2
3 Op Amps
DAC12
12-Bit
2 Channels
Voltage Out
DMA
Controller
1 Channel
P5
Port 5
8 I/O
8
P6
Port 6
8 I/O
8
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430FG43x Terminal Functions
TERMINAL
PN
I/O
DESCRIPTION
NAME NO. I/O
DESCRIPTION
DVCC1 1Digital supply voltage, positive terminal.
P6.3/A3/OA1I1/OA1O 2 I/O General-purpose digital I/O / analog input a3—12-bit ADC / OA1 output and/or input multiplexer on
+terminal and −terminal
P6.4/A4/OA1I0 3 I/O General-purpose digital I/O / analog input a4—12-bit ADC / OA1 input multiplexer on +terminal and
−terminal
P6.5/A5/OA2I1/OA2O 4 I/O General-purpose digital I/O / analog input a5—12-bit ADC / OA2 output and/or input multiplexer on
+terminal and −terminal
P6.6/A6/DAC0/OA2I0 5 I/O General-purpose digital I/O / analog input a6—12-bit ADC / DAC12.0 output / OA2 input multiplexer
on +terminal and −terminal
P6.7/A7/DAC1/
SVSIN
6 I/O General-purpose digital I/O / analog input a7—12-bit ADC / DAC12.1 output/analog input to supply
voltage supervisor
VREF+ 7 O Positive output terminal of the reference voltage in the ADC
XIN 8 I Input terminal of crystal oscillator XT1
XOUT 9 O Output terminal of crystal oscillator XT1
VeREF+/DAC0 10 I/O Positive input terminal for an external reference voltage to the 12-bit ADC/DAC12.0 output
VREF−/VeREF− 11 INegative terminal for the 12-bit ADC’s reference voltage for both sources, the internal reference
voltage or an external applied reference voltage to the 12-bit ADC.
P5.1/S0/A12/DAC1 12 I/O General-purpose digital I/O / LCD segment output 0/ analog input a12—12-bit ADC/DAC12.1 output
P5.0/S1/A13 13 I/O General-purpose digital I/O / LCD segment output 1/ analog input a13—12-bit ADC
P4.7/S2/A14 14 I/O General-purpose digital I/O / LCD segment output 2/ analog input a14—12-bit ADC
P4.6/S3/A15 15 I/O General-purpose digital I/O / LCD segment output 3/ analog input a15—12-bit ADC
P4.5/S4 16 I/O General-purpose digital I/O / LCD segment output 4
P4.4/S5 17 I/O General-purpose digital I/O / LCD segment output 5
P4.3/S6 18 I/O General-purpose digital I/O / LCD segment output 6
P4.2/S7 19 I/O General-purpose digital I/O / LCD segment output 7
P4.1/S8 20 I/O General-purpose digital I/O / LCD segment output 8
P4.0/S9 21 I/O General-purpose digital I/O / LCD segment output 9
S10 22 O LCD segment output 10
S11 23 O LCD segment output 11
S12 24 O LCD segment output 12
S13 25 O LCD segment output 13
S14 26 O LCD segment output 14
S15 27 O LCD segment output 15
S16 28 O LCD segment output 16
S17 29 O LCD segment output 17
P2.7/ADC12CLK/S18 30 I/O General-purpose digital I/O / conversion clock—12-bit ADC / LCD segment output 18
P2.6/CAOUT/S19 31 I/O General-purpose digital I/O / Comparator_A output / LCD segment output 19
S20 32 O LCD segment output 20
S21 33 O LCD segment output 21
S22 34 O LCD segment output 22
S23 35 O LCD segment output 23
P3.7/S24 36 I/O General-purpose digital I/O / LCD segment output 24
P3.6/S25/DMAE0 37 I/O General-purpose digital I/O / LCD segment output 25/DMA Channel 0 external trigger
P3.5/S26 38 I/O General-purpose digital I/O / LCD segment output 26
P3.4/S27 39 I/O General-purpose digital I/O / LCD segment output 27
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430FG43x Terminal Functions (Continued)
TERMINAL
PN
I/O
DESCRIPTION
NAME NO. I/O
DESCRIPTION
P3.3/UCLK0/S28 40 I/O General-purpose digital I/O / ext. clock i/p—USART0/UART or SPI mode, clock o/p—USART0/SPI mode
/ LCD segment output 28
P3.2/SOMI0/S29 41 I/O General-purpose digital I/O / slave out/master in of USART0/SPI mode / LCD segment output 29
P3.1/SIMO0/S30 42 I/O General-purpose digital I/O / slave out/master out of USART0/SPI mode / LCD segment output 30
P3.0/STE0/S31 43 I/O General-purpose digital I/O / slave transmit enable-USART0/SPI mode / LCD segment output 31
COM0 44 O Common output, COM0−3 are used for LCD backplanes.
P5.2/COM1 45 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.3/COM2 46 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.4/COM3 47 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
R03 48 I Input port of fourth positive (lowest) analog LCD level (V5)
P5.5/R13 49 I/O General-purpose digital I/O / input port of third most positive analog LCD level (V4 or V3)
P5.6/R23 50 I/O General-purpose digital I/O / input port of second most positive analog LCD level (V2)
P5.7/R33 51 I/O General-purpose digital I/O / output port of most positive analog LCD level (V1)
DVCC2 52 Digital supply voltage, positive terminal.
DVSS2 53 Digital supply voltage, negative terminal.
P2.5/URXD0 54 I/O General-purpose digital I/O / receive data in—USART0/UART mode
P2.4/UTXD0 55 I/O General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2 56 I/O General-purpose digital I/O / Timer_B3 CCR2.
Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1 57 I/O General-purpose digital I/O / Timer_B3 CCR1.
Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0 58 I/O General-purpose digital I/O / Timer_B3 CCR0.
Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2 59 I/O General-purpose digital I/O / Timer_A
Capture: CCI2A input, compare: Out2 output
P1.7/CA13 60 I/O General-purpose digital I/O / Comparator_A input
P1.6/CA0 61 I/O General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK 62 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8)
P1.4/TBCLK/
SMCLK 63 I/O General-purpose digital I/O / input clock TBCLK—Timer_B3 / submain system clock SMCLK output
P1.3/TBOUTH/
SVSOUT 64 I/O General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B3 TB0 to TB2
/ SVS: output of SVS comparator
P1.2/TA1 65 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A, compare: Out1 output
P1.1/TA0/MCLK 66 I/O General-purpose digital I/O / Timer_A. Capture: CCI0B / MCLK output. Note: TA0 is only an input on this
pin / BSL receive
P1.0/TA0 67 I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit
XT2OUT 68 O Output terminal of crystal oscillator XT2
XT2IN 69 I Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI 70 I/O Test data output port. TDO/TDI data output or programming data input terminal
TDI/TCLK 71 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TMS 72 I Test mode select. TMS is used as an input port for device programming and test.
TCK 73 I Test clock. TCK is the clock input port for device programming and test.
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430FG43x Terminal Functions (Continued)
TERMINAL
PN
I/O
DESCRIPTION
NAME NO. I/O
DESCRIPTION
RST/NMI 74 I Reset or nonmaskable interrupt input
P6.0/A0/OA0I0 75 I/O General-purpose digital I/O / analog input a0 − 12-bit ADC / OA0 input multiplexer on +terminal and
− terminal
P6.1/A1/OA0O 76 I/O General-purpose digital I/O / analog input a1 − 12-bit ADC / OA0 output
P6.2/A2/OA0I1 77 I/O General-purpose digital I/O / analog input a2 − 12-bit ADC / OA0 input multiplexer on + terminal and
− terminal
AVSS 78 Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_A, port 1,
and LCD resistive divider circuitry.
DVSS1 79 Digital supply voltage, negative terminal.
AVCC 80 Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_A, port 1,
and LCD resistive divider circuitry; must not power up prior to DVCC1/DVCC2.
General-Purpose Register
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R12
R13
General-Purpose Register
General-Purpose Register
R6
R7
General-Purpose Register
General-Purpose Register
R8
R9
General-Purpose Register
General-Purpose Register
R10
R11
General-Purpose Register
General-Purpose Register
R14
R15
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
Table 1. Instruction Word Formats
Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 −−−> R5
Single operands, destination only e.g. CALL R8 PC −−>(TOS), R8−−> PC
Relative jump, un/conditional e.g. JNE Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register FFMOV Rs,Rd MOV R10,R11 R10 —> R11
Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)—> M(6+R6)
Symbolic (PC relative) F F MOV EDE,TONI M(EDE) —> M(TONI)
Absolute F F MOV &MEM, &TCDAT M(MEM) —> M(TCDAT)
Indirect FMOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) —> M(Tab+R6)
Indirect
autoincrement FMOV @Rn+,Rm MOV @R10+,R11 M(R10) —> R11
R10 + 2—> R10
Immediate FMOV #X,TONI MOV #45,TONI #45 —> M(TONI)
NOTE: S = source D = destination
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
DActive mode (AM)
− All clocks are active
DLow-power mode 0 (LPM0)
− CPU is disabled
ACLK and SMCLK remain active, MCLK is disabled
FLL+ loop control remains active
DLow-power mode 1 (LPM1);
− CPU is disabled
FLL+ loop control is disabled
ACLK and SMCLK remain active, MCLK is disabled
DLow-power mode 2 (LPM2)
− CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
DLow-power mode 3 (LPM3)
− CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
DLow-power mode 4 (LPM4)
− CPU is disabled
ACLK is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD
ADDRESS PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
WDTIFG
KEYV
(see Note 1)
Reset 0FFFEh 15, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh 14
Timer_B3 TBCCR0 CCIFG0 (see Note 2) Maskable 0FFFAh 13
Timer_B3 TBCCR1 CCIFG1, TBCCR2 CCIFG2,
TBIFG (see Notes 1 and 2) Maskable 0FFF8h 12
Comparator_A CAIFG Maskable 0FFF6h 11
Watchdog Timer WDTIFG Maskable 0FFF4h 10
USART0 Receive URXIFG0 Maskable 0FFF2h 9
USART0 Transmit UTXIFG0 Maskable 0FFF0h 8
ADC12 ADC12IFG (see Notes 1 and 2) Maskable 0FFEEh 7
Timer_A3 TACCR0 CCIFG0 (see Note 2) Maskable 0FFECh 6
Timer_A3 TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (see Notes 1 and 2) Maskable 0FFEAh 5
I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0FFE8h 4
DAC12
DMA
DAC12.0IFG, DAC12.1IFG,
DMA0IFG (see Notes 1 and 2)
Maskable 0FFE6h 3
0FFE4h 2
I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0FFE2h 1
Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot
disable it.
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
special function registers
The MSP430 special function registers(SFR) are located in the lowest address space, and are organized as
byte mode registers. SFRs should be accessed with byte instructions.
interrupt enable 1 and 2
7654 0
UTXIE0 OFIE WDTIE
321
rw–0 rw–0 rw–0
Address
0h URXIE0 ACCVIE NMIIE
rw–0 rw–0 rw–0
WDTIE: Watchdog-timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as a general-purpose timer.
OFIE: Oscillator-fault-interrupt enable
NMIIE: Nonmaskable-interrupt enable
ACCVIE: Flash access violation interrupt enable
URXIE0: USART0: UART and SPI receive-interrupt enable
UTXIE0: USART0: UART and SPI transmit-interrupt enable
7654 0321
Address
01h
rw–0
BTIE
BTIE: Basic timer interrupt enable
interrupt flag register 1 and 2
7654 0
UTXIFG0 OFIFG WDTIFG
321
rw–0 rw–1 rw–(0)
Address
02h URXIFG0 NMIIFG
rw–1 rw–0
WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode
OFIFG: Flag set on oscillator fault
NMIIFG: Set via RST/NMI pin
URXIFG0: USART0: UART and SPI receive flag
UTXIFG0: USART0: UART and SPI transmit flag
7654 0321
Address
03h BTIFG
rw–0
BTIFG: Basic timer flag
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
module enable registers 1 and 2
7654 0
UTXE0
321
rw–0 rw–0
Address
04h URXE0
USPIE0
URXE0: USART0: UART mode receive enable
UTXE0: USART0: UART mode transmit enable
USPIE0: USART0: SPI mode transmit and receive enable
7654 0321
Address
05h
rw–0,1:
Legend: rw: Bit Can Be Read and Written
Bit Can Be Read and Written. It Is Reset or Set by PUC.
Bit Can Be Read and Written. It Is Reset or Set by POR.
SFR Bit Not Present in Device
rw–(0,1):
memory organization
MSP430FG437 MSP430FG438 MSP430FG439
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
32KB
0FFFFh − 0FFE0h
0FFFFh − 08000h
48KB
0FFFFh − 0FFE0h
0FFFFh − 04000h
60KB
0FFFFh − 0FFE0h
0FFFFh − 01100h
Information memory Size
Flash
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Boot memory Size
ROM
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
RAM Size 1KB
05FFh − 0200h
2KB
09FFh − 0200h
2KB
09FFh − 0200h
Peripherals 16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
BSL Function PN Package Pins
Data Transmit 67 − P1.0
Data Receive 66 − P1.1
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
DFlash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
DSegments 0 to n may be erased in one step, or each segment may be individually erased.
DSegments A and B can be erased individually, or as a group with segments 0−n.
Segments A and B are also called information memory.
DNew devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
Segment 0
w/ Interrupt Vectors
Segment 1
Segment 2
Segment n-1
Segment n†
Segment A
Segment B
Main
Memory
Information
Memory
32KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
48KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
60KB
0FFFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
08400h
083FFh
08200h
081FFh
08000h
010FFh
01080h
0107Fh
01000h
04400h
043FFh
04200h
041FFh
04000h
010FFh
01080h
0107Fh
01000h
01400h
013FFh
01200h
011FFh
01100h
010FFh
01080h
0107Fh
01000h
†MSP430FG439 flash segment n = 256 bytes.
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, Literature
Number SLAU056.
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to
or from a peripheral.
oscillator and system clock
The clock system in the MSP430FG43x family of devices is supported by the FLL+ module that includes support
for a 32768 Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency
crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and
low-power consumption. The FLL+ features digital frequency locked loop (FLL) hardware which in conjunction
with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.
The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The FLL+ module
provides the following clock signals:
DAuxiliary clock (ACLK), sourced from a 32768 Hz watch crystal or a high frequency crystal.
DMain clock (MCLK), the system clock used by the CPU.
DSub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
DACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on
and power-off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6:
DAll individual I/O bits are independently programmable.
DAny combination of input, output, and interrupt conditions is possible.
DEdge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
DRead/write access to port-control registers is supported by all instructions.
Basic Timer1
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and
clock for the LCD module.
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
LCD drive
The LCD driver generates the segment and common signals required to drive an LCD display. The LCD
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
OA
The MSP430FG43x has three configurable low-current general-purpose operational amplifiers. Each OA input
and output terminal is software-selectable and offers a flexible choice of connections for various applications.
The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
USART0
The MSP430FG43x has one hardware universal synchronous/asynchronous receive transmit (USART)
peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or 4
pin) and asynchronous UART communication protocols, using double-buffered transmit and receive channels.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number Device Input Module Input Module Module Output Output Pin Number
PN
Device
Input
Signal
Module
Input
Name
Module
Block
Module
Output
Signal PN
62 - P1.5 TACLK TACLK
ACLK ACLK
Timer
NA
SMCLK SMCLK Timer NA
62 - P1.5 TACLK INCLK
67 - P1.0 TA0 CCI0A 67 - P1.0
66 - P1.1 TA0 CCI0B
CCR0
TA0
DVSS GND CCR0 TA0
DVCC VCC
65 - P1.2 TA1 CCI1A 65 - P1.2
CAOUT (internal) CCI1B
CCR1
TA1
ADC12 (internal)
DVSS GND CCR1 TA1
DVCC VCC
59 - P2.0 TA2 CCI2A 59 - P2.0
ACLK (internal) CCI2B
CCR2
TA2
DVSS GND CCR2 TA2
DVCC VCC
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_B3 Signal Connections
Input Pin Number Device Input Module Input Module Module Output Output Pin Number
PN
Device
Input
Signal
Module
Input
Name
Module
Block
Module
Output
Signal PN
63 - P1.4 TBCLK TBCLK
ACLK ACLK
Timer
NA
SMCLK SMCLK Timer NA
63 - P1.4 TBCLK INCLK
58 - P2.1 TB0 CCI0A 58 - P2.1
58 - P2.1 TB0 CCI0B
CCR0
TB0
ADC12 (internal)
DVSS GND CCR0 TB0
DVCC VCC
57 - P2.2 TB1 CCI1A 57 - P2.2
57 - P2.2 TB1 CCI1B
CCR1
TB1
ADC12 (internal)
DVSS GND CCR1 TB1
DVCC VCC
56 - P2.3 TB2 CCI2A 56 - P2.3
56 - P2.3 TB2 CCI2B
CCR2
TB2
DVSS GND CCR2 TB2
DVCC VCC
comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
ADC12
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
DAC12
The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode,
and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may
be grouped together for synchronous operation.
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog Watchdog timer control WDTCTL 0120h
Timer_B3 Capture/compare register 2 TBCCR2 0196h
_
Capture/compare register 1 TBCCR1 0194h
Capture/compare register 0 TBCCR0 0192h
Timer_B register TBR 0190h
Capture/compare control 2 TBCCTL2 0186h
Capture/compare control 1 TBCCTL1 0184h
Capture/compare control 0 TBCCTL0 0182h
Timer_B control TBCTL 0180h
Timer_B interrupt vector TBIV 011Eh
Timer_A3 Capture/compare register 2 TACCR2 0176h
_
Capture/compare register 1 TACCR1 0174h
Capture/compare register 0 TACCR0 0172h
Timer_A register TAR 0170h
Capture/compare control 2 TACCTL2 0166h
Capture/compare control 1 TACCTL1 0164h
Capture/compare control 0 TACCTL0 0162h
Timer_A control TACTL 0160h
Timer_A interrupt vector TAIV 012Eh
Flash Flash control 3 FCTL3 012Ch
Flash control 2 FCTL2 012Ah
Flash control 1 FCTL1 0128h
DMA DMA module control 0 DMACTL0 0122h
DMA module control 1 DMACTL1 0124h
DMA channel 0 control DMA0CTL 01E0h
DMA channel 0 source address DMA0SA 01E2h
DMA channel 0 destination address DMA0DA 01E4h
DMA channel 0 transfer size DMA0SZ 01E6h
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
17
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peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED)
ADC12 Conversion memory 15 ADC12MEM15 015Eh
See also Peripherals Conversion memory 14 ADC12MEM14 015Ch
See
also
Peripherals
with Byte Access Conversion memory 13 ADC12MEM13 015Ah
y
Conversion memory 12 ADC12MEM12 0158h
Conversion memory 11 ADC12MEM11 0156h
Conversion memory 10 ADC12MEM10 0154h
Conversion memory 9 ADC12MEM9 0152h
Conversion memory 8 ADC12MEM8 0150h
Conversion memory 7 ADC12MEM7 014Eh
Conversion memory 6 ADC12MEM6 014Ch
Conversion memory 5 ADC12MEM5 014Ah
Conversion memory 4 ADC12MEM4 0148h
Conversion memory 3 ADC12MEM3 0146h
Conversion memory 2 ADC12MEM2 0144h
Conversion memory 1 ADC12MEM1 0142h
Conversion memory 0 ADC12MEM0 0140h
Interrupt-vector-word register ADC12IV 01A8h
Inerrupt-enable register ADC12IE 01A6h
Inerrupt-flag register ADC12IFG 01A4h
Control register 1 ADC12CTL1 01A2h
Control register 0 ADC12CTL0 01A0h
DAC12 DAC12_1 data DAC12_1DAT 01CAh
DAC12_1 control DAC12_1CTL 01C2h
DAC12_0 data DAC12_0DAT 01C8h
DAC12_0 control DAC12_0CTL 01C0h
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS
OA2 Operational Amplifier 2 control register 1
Operational Amplifier 2 control register 0
OA2CTL1
OA2CTL0
0C5h
0C4h
OA1 Operational Amplifier 1 control register 1
Operational Amplifier 1 control register 0
OA1CTL1
OA1CTL0
0C3h
0C2h
OA0 Operational Amplifier 0 control register 1
Operational Amplifier 0 control register 0
OA0CTL1
OA0CTL0
0C1h
0C0h
LCD LCD memory 20
:
LCD memory 16
LCD memory 15
:
LCD memory 1
LCD control and mode
LCDM20
:
LCDM16
LCDM15
:
LCDM1
LCDCTL
0A4h
:
0A0h
09Fh
:
091h
090h
ADC12 ADC memory-control register 15 ADC12MCTL15 08Fh
(Memory control
registers require byte
ADC memory-control register 14 ADC12MCTL14 08Eh
registers require byte
access)
ADC memory-control register 13 ADC12MCTL13 08Dh
access
)
ADC memory-control register 12 ADC12MCTL12 08Ch
ADC memory-control register 11 ADC12MCTL11 08Bh
ADC memory-control register 10 ADC12MCTL10 08Ah
ADC memory-control register 9 ADC12MCTL9 089h
ADC memory-control register 8 ADC12MCTL8 088h
ADC memory-control register 7 ADC12MCTL7 087h
ADC memory-control register 6 ADC12MCTL6 086h
ADC memory-control register 5 ADC12MCTL5 085h
ADC memory-control register 4 ADC12MCTL4 084h
ADC memory-control register 3 ADC12MCTL3 083h
ADC memory-control register 2 ADC12MCTL2 082h
ADC memory-control register 1 ADC12MCTL1 081h
ADC memory-control register 0 ADC12MCTL0 080h
USART0 Transmit buffer U0TXBUF 077h
(UART or SPI mode) Receive buffer U0RXBUF 076h
Baud rate U0BR1 075h
Baud rate U0BR0 074h
Modulation control U0MCTL 073h
Receive control U0RCTL 072h
Transmit control U0TCTL 071h
USART control U0CTL 070h
Comparator_A Comparator_A port disable CAPD 05Bh
p
_
Comparator_A control 2 CACTL2 05Ah
Comparator_A control 1 CACTL1 059h
BrownOUT, SVS SVS control register (Reset by brownout signal) SVSCTL 056h
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
FLL+ Clock FLL+ Control 1 FLL_CTL1 054h
FLL+ Control 0 FLL_CTL0 053h
System clock frequency control SCFQCTL 052h
System clock frequency integrator SCFI1 051h
System clock frequency integrator SCFI0 050h
Basic Timer1 BT counter 2
BT counter 1
BT control
BTCNT2
BTCNT1
BTCTL
047h
046h
040h
Port P6 Port P6 selection P6SEL 037h
Port P6 direction P6DIR 036h
Port P6 output P6OUT 035h
Port P6 input P6IN 034h
Port P5 Port P5 selection P5SEL 033h
Port P5 direction P5DIR 032h
Port P5 output P5OUT 031h
Port P5 input P5IN 030h
Port P4 Port P4 selection P4SEL 01Fh
Port P4 direction P4DIR 01Eh
Port P4 output P4OUT 01Dh
Port P4 input P4IN 01Ch
Port P3 Port P3 selection P3SEL 01Bh
Port P3 direction P3DIR 01Ah
Port P3 output P3OUT 019h
Port P3 input P3IN 018h
Port P2 Port P2 selection P2SEL 02Eh
Port P2 interrupt enable P2IE 02Dh
Port P2 interrupt-edge select P2IES 02Ch
Port P2 interrupt flag P2IFG 02Bh
Port P2 direction P2DIR 02Ah
Port P2 output P2OUT 029h
Port P2 input P2IN 028h
Port P1 Port P1 selection P1SEL 026h
Port P1 interrupt enable P1IE 025h
Port P1 interrupt-edge select P1IES 024h
Port P1 interrupt flag P1IFG 023h
Port P1 direction P1DIR 022h
Port P1 output P1OUT 021h
Port P1 input P1IN 020h
Special functions SFR module enable 2 ME2 005h
p
SFR module enable 1 ME1 004h
SFR interrupt flag 2 IFG2 003h
SFR interrupt flag 1 IFG1 002h
SFR interrupt enable 2 IE2 001h
SFR interrupt enable 1 IE1 000h
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Voltage applied at VCC to VSS −0.3 V to 4.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to any pin (see Note) −0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diode current at any device terminal . ±2 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, Tstg: (unprogrammed device) −55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(programmed device) −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied
to the TDI/TCLK pin when blowing the JTAG fuse.
recommended operating conditions
MIN NOM MAX UNITS
Supply voltage during program execution (see Note 1), VCC (AVCC = DVCC1/2 = VCC) 1.8 3.6 V
Supply voltage during program execution, SVS enabled, PORON=1
(see Note 1 and Note 2), VCC (AVCC = DVCC1/2 = VCC)2 3.6 V
Supply voltage during flash memory programming (see Note 1),
VCC (AVCC = DVCC1/2 = VCC)2.7 3.6 V
Supply voltage, VSS (AVSS = DVSS1/2 = VSS) 0 0 V
Operating free-air temperature range, TA−40 85 °C
LF selected,
XTS_FLL=0 Watch crystal 32.768 kHz
LFXT1 crystal frequency, f(LFXT1)
(see Note 3)
XT1 selected,
XTS_FLL=1 Ceramic resonator 450 8000 kHz
(see
Note
3)
XT1 selected,
XTS_FLL=1 Crystal 1000 8000 kHz
XT2 crystal frequency f
Ceramic resonator 450 8000
kHz
XT2 crystal frequency, f(XT2) Crystal 1000 8000 kHz
Processor frequency (signal MCLK) f
VCC = 1.8 V DC 4.15
MHz
Processor frequency (signal MCLK), f(System) VCC = 3.6 V DC 8 MHz
NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V betweeen AVCC and DVCC can
be tolerated during power up and operation.
2. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply
voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS
circuitry.
3. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
1.8 3.62.7 3
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
4.15 MHz
8 MHz
Supply Voltage − V
Supply voltage range, MSP430FG43x,
during flash memory programming
Supply voltage range,
MSP430FG43x, during
program execution
f(System) MHz
Figure 1. Frequency vs Supply Voltage, typical characteristic
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC + DVCC1/2 excluding external current
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
I
Active mode, (see Note 1)
f
(MCLK)
= f
(SMCLK)
= 1 MHz,
T40°Cto85°C
VCC = 2.2 V 300 370
A
I(AM)
f(MCLK)
=
f(SMCLK)
=
1
MHz
,
f(ACLK) = 32,768 Hz
XTS_FLL=0, SELM=(0,1)
TA = −40°C to 85°C
VCC = 3 V 470 570
μA
I
Low-power mode, (LPM0)
T40°Cto85°C
VCC = 2.2 V 55 70
A
I(LPM0)
Low power
mode
,
(LPM0)
(see Note 1 and Note 4) TA = −40°C to 85°CVCC = 3 V 95 110 μA
I
Low-power mode, (LPM2),
f
(
MCLK
)
= f
(
SMCLK
)
= 0 MHz,
T40°Cto85°C
VCC = 2.2 V 11 14
A
I(LPM2)
f(MCLK)
=
f
(SMCLK)
=
0
MHz
,
f(ACLK) = 32,768 Hz, SCG0 = 0
(see Note 2 and Note 4)
TA = −40°C to 85°C
VCC = 3 V 17 22
μA
TA = −40°C 1 2.0
TA = 25°C
V22V
1.1 2.0
Low-power mode, (LPM3)
f(MCLK) =f
(SMCLK) = 0 MHz
TA = 60°CVCC = 2.2 V 2 3
I
f(MCLK) = f(SMCLK) = 0 MHz,
f
(ACLK)
= 32
,
768 Hz
,
SCG0 = 1 TA = 85°C 3.5 6
A
I(LPM3)
f(ACLK)
=
32
,
768
Hz
,
SCG0
=
1
(see Note 2, Note 3, and Note 4) TA = −40°C 1.8 2.8 μA
(,, )
TA = 25°C
V3V
1.6 2.7
TA = 60°CVCC = 3 V 2.5 3.5
TA = 85°C 4.2 7.5
TA = −40°C 0.1 0.5
TA = 25°C
V22V
0.1 0.5
TA = 60°CVCC = 2.2 V 0.7 1.1
I
Low-power mode, (LPM4)
f0 MHz f 0 MHz
TA = 85°C 1.7 3
A
I(LPM4) f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz,
f
(ACLK)
=
0
Hz
,
SCG0
= 1
(see
N
o
t
e
2
a
n
d
N
o
t
e
4
)
TA = −40°C 0.1 0.8 μA
f
(ACLK) =
0
Hz
,
SCG0
=
1
(see
Note
2
and
Note
4)
TA = 25°C
V3V
0.1 0.8
TA = 60°CVCC = 3 V 0.8 1.2
TA = 85°C 1.9 3.5
NOTES: 1. Timer_B is clocked by f(DCOCLK) = f(DCO) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
2. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
3. The current consumption in LPM3 is measured with active Basic Timer1 and LCD (ACLK selected). The current consumption of the
Comparator_A and the SVS module are specified in the respective sections. The LPM3 currents are characterized with a KDS
Daishinku DT−38 (6 pF) crystal and OSCCAPx=01h.
4. Current for brownout included.
Current consumption of active mode versus system frequency
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
Current consumption of active mode versus supply voltage
I(AM) = I(AM) [3 V] + 175 μA/V × (VCC – 3 V)
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SCHMITT-trigger inputs − Ports P1, P2, P3, P4, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
Positive going input threshold voltage
VCC = 2.2 V 1.1 1.55
V
VIT+ Positive-going input threshold voltage VCC = 3 V 1.5 1.98 V
V
Negative going input threshold voltage
VCC = 2.2 V 0.4 0.9
V
VIT− Negative-going input threshold voltage VCC = 3 V 0.9 1.3 V
V
Input voltage hysteresis (V V )
VCC = 2.2 V 0.3 1.1
V
Vhys Input voltage hysteresis (VIT+ − VIT−)VCC = 3 V 0.5 1 V
inputs Px.x, TAx, TBx
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
t
External interrupt timing
Port P1, P2: P1.x to P2.x, external trigger signal 2.2 V 62
ns
t(int) External interrupt timing
Port
P1,
P2:
P1.x
to
P2.x,
external
trigger
signal
for the interrupt flag, (see Note 1) 3 V 50 ns
t
Timer_A, Timer_B capture TA0, TA1, TA2 2.2 V 62
ns
t(cap)
Timer
_
A,
Timer
_
B
capture
timing TB0, TB1, TB2 3 V 50 ns
f(TAext) Timer_A, Timer_B clock
frequency externally applied
TACLK TBCLK INCLK: t=t
2.2 V 8
MHz
f(TBext)
frequency externally applied
to pin
TACLK, TBCLK, INCLK: t(H) = t(L) 3 V 10 MHz
f(TAint) Timer_A, Timer_B clock
SMCLK or ACLK signal selected
2.2 V 8
MHz
f(TBint)
Timer
_
A,
Timer
_
B
clock
frequency SMCLK or ACLK signal selected 3 V 10 MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It may be set even with trigger signals
shorter than t(int).
leakage current − Ports P1, P2, P3, P4, P5, and P6 (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Ilkg(Px.y) Leakage
current Port Px V(Px.y) (see Note 2) VCC = 2.2 V/3 V ±50 nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as input.
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1, P2, P3, P4, P5, and P6
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOH(max) = −1.5 mA, VCC = 2.2 V, See Note 1 VCC−0.25 VCC
V
High level output voltage
IOH(max) = −6 mA, VCC = 2.2 V, See Note 2 VCC−0.6 VCC
V
VOH High-level output voltage IOH(max) = −1.5 mA, VCC = 3 V, See Note 1 VCC−0.25 VCC V
IOH(max) = −6 mA, VCC = 3 V, See Note 2 VCC−0.6 VCC
IOL(max) = 1.5 mA, VCC = 2.2 V, See Note 1 VSS VSS+0.25
V
Low level output voltage
IOL(max) = 6 mA, VCC = 2.2 V, See Note 2 VSS VSS+0.6
V
VOL Low-level output voltage IOL(max) = 1.5 mA, VCC = 3 V, See Note 1 VSS VSS+0.25 V
IOL(max) = 6 mA, VCC = 3 V, See Note 2 VSS VSS+0.6
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum
specified voltage drop.
output frequency
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(Px.y) (1 ≤ x ≤ 6, 0 ≤ y ≤ 7) CL = 20 pF,
IL = ±1.5 mA VCC = 2.2 V / 3 V DC fSystem MHz
f(MCLK) P1.1/TA0/MCLK,
f(SMCLK) P1.4/TBCLK/SMCLK, CL = 20 pF fS
y
stem MHz
f(ACLK) P1.5/TACLK/ACLK
CL
20
pF
fSystem
MHz
P1.5/TACLK/ACLK,
f(ACLK) = f(LFXT1) = f(XT1) 40% 60%
P1
.
5/TACLK/ACLK
,
CL = 20 pF f(ACLK) = f(LFXT1) = f(LF) 30% 70%
CL
20
pF
VCC = 2.2 V / 3 V f(ACLK) = f(LFXT1) 50%
P1.1/TA0/MCLK
,
f(MCLK) = f(XT1) 40% 60%
t(Xdc) Duty cycle of output frequency
P1
.
1/TA0/MCLK
,
CL = 20 pF,
VCC = 2.2 V / 3 V f(MCLK) = f(DCOCLK) 50%−
15 ns 50% 50%+
15 ns
P1.4/TBCLK/SMCLK
,
f(SMCLK) = f(XT2) 40% 60%
P1
.
4/TBCLK/SMCLK
,
CL = 20 pF,
VCC = 2.2 V / 3 V f(SMCLK) = f(DCOCLK) 50%−
15 ns 50% 50%+
15 ns
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1, P2, P3, P4, P5, and P6 (continued)
Figure 2
VOL − Low-Level Output Voltage − V
0
2
4
6
8
10
12
14
16
0.0 0.5 1.0 1.5 2.0 2.5
VCC = 2.2 V
P2.7
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OL
I− Typical Low-level Output Current − mA
Figure 3
VOL − Low-Level Output Voltage − V
0
5
10
15
20
25
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = 3 V
P2.7
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OL
I− Typical Low-level Output Current − mA
Figure 4
VOH − High-Level Output Voltage − V
−14
−12
−10
−8
−6
−4
−2
0
0.0 0.5 1.0 1.5 2.0 2.5
VCC = 2.2 V
P2.7
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OL
I− Typical High-level Output Current − mA
Figure 5
VOH − High-Level Output Voltage − V
−30
−25
−20
−15
−10
−5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VCC = 3 V
P2.7
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TA = 25°C
TA = 85°C
OL
I− Typical High-level Output Current − mA
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
wake-up LPM3
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f = 1 MHz 6
td
(
LPM3
)
Delay time f = 2 MHz VCC = 2.2 V/3 V 6μs
td(LPM3)
Delay
time
f = 3 MHz
VCC
2.2
V/3
V
6
μs
RAM
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRAMh CPU halted (see Note 1) 1.6 V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
LCD
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(33) Voltage at P5.7/R33 2.5 VCC + 0.2
V(23)
Analog voltage
Voltage at P5.6/R23
V3V
[V(33)−V(03)] × 2/3 + V(03)
V
V(13) Analog voltage Voltage at P5.5/R13 VCC = 3 V [V(33)−V(03)] × 1/3 + V(03) V
V(33) − V(03) Voltage at R33 to R03 2.5 VCC + 0.2
I(R03) R03 = VSS No load at all ±20
I(R13) Input leakage P5.5/R13 = VCC/3 segment and
common lines
±20 nA
I(R23)
pg
P5.6/R23 = 2 × VCC/3 common
li
nes,
VCC = 3 V ±20
V(Sxx0) V(03) V(03) − 0.1
V(Sxx1) Se
g
ment line
I=3μA
V=3V
V(13) V(13) − 0.1
V
V(Sxx2)
Segment
line
voltage I(Sxx) = −3 μA, VCC = 3 V V(23) V(23) − 0.1 V
V(Sxx3) V(33) V(33) + 0.1
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Comparator_A (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
CAON 1 CARSEL 0 CAREF 0
VCC = 2.2 V 25 40
A
I(CC) CAON=1, CARSEL=0, CAREF=0 VCC = 3 V 45 60 μA
I
CAON=1, CARSEL=0, CAREF=1/2/3,
No load at P1 6/CA0 and
VCC = 2.2 V 30 50
A
I(Refladder/RefDiode) No load at P1.6/CA0 and
P1.7/CA1 VCC = 3 V 45 71 μA
V(Ref025)
Voltage @ 0.25 VCC node
VCC
PCA0=1, CARSEL=1, CAREF=1,
No load at P1.6/CA0 and P1.7/CA1 VCC = 2.2 V / 3 V 0.23 0.24 0.25
V(Ref050)
Voltage @ 0.5 VCC node
VCC
PCA0=1, CARSEL=1, CAREF=2,
No load at P1.6/CA0 and P1.7/CA1 VCC = 2.2V / 3 V 0.47 0.48 0.5
V
see Figure 6 and Figure 7
PCA0=1, CARSEL=1, CAREF=3,
No load at P1 6/CA0 and P1 7/CA1;
VCC = 2.2 V 390 480 540
mV
V(RefVT) see Figure 6 and Figure 7 No load at P1.6/CA0 and P1.7/CA1;
TA = 85°CVCC = 3 V 400 490 550 mV
VIC Common-mode input
voltage range CAON=1 VCC = 2.2 V / 3 V 0 VCC−1 V
Vp−VSOffset voltage See Note 2 VCC = 2.2 V / 3 V −30 30 mV
Vhys Input hysteresis CAON = 1 VCC = 2.2 V / 3 V 0 0.7 1.4 mV
TA = 25°C, VCC = 2.2 V 160 210 300
ns
t
TA
=
25 C
,
Overdrive 10 mV, without filter: CAF = 0 VCC = 3 V 80 150 240 ns
t(response LH) TA = 25°CVCC = 2.2 V 1.4 1.9 3.4
s
TA
=
25 C
Overdrive 10 mV, with filter: CAF = 1 VCC = 3 V 0.9 1.5 2.6 μs
TA = 25°CVCC = 2.2 V 130 210 300
ns
t
TA
=
25 C
Overdrive 10 mV, without filter: CAF = 0 VCC = 3 V 80 150 240 ns
t(response HL) TA = 25°C, VCC = 2.2 V 1.4 1.9 3.4
s
TA
=
25 C
,
Overdrive 10 mV, with filter: CAF = 1 VCC = 3 V 0.9 1.5 2.6 μs
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical characteristics
TA − Free-Air Temperature − °C
400
450
500
550
600
650
−45 −25 −5 15 35 55 75 95
VCC = 3 V
Figure 6. V
(
RefVT
)
vs Temperature
VREF − Reference Voltage − mV
Typical
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
Figure 7. V
(
RefVT
)
vs Temperature
TA − Free-Air Temperature − °C
400
450
500
550
600
650
−45 −25 −5 15 35 55 75 95
VCC = 2.2 V
Typical
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
VREF − Reference Voltage − mV
_
+
CAON
0
1
V+ 0
1
CAF
Low-Pass Filter
τ ≈ 2 μs
To Internal
Modules
Set CAIFG
Flag
CAOUT
V−
VCC
1
0 V
0
Figure 8. Block Diagram of Comparator_A Module
Overdrive VCAOUT
t(response)
V+
V−
400 mV
Figure 9. Overdrive Definition
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
POR/brownout reset (BOR) (see Note 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(BOR) 2000 μs
VCC(start) dVCC/dt ≤ 3 V/s (see Figure 10) 0.7 × V(B_IT−) V
V(B_IT−) Brownout dVCC/dt ≤ 3 V/s (see Figure 10 through Figure 12) 1.71 V
Vhys(B_IT−) (see Note 2) dVCC/dt ≤ 3 V/s (see Figure 10) 70 130 180 mV
t(reset) Pulse length needed at RST/NMI pin to accepted reset internally,
VCC = 2.2 V/3 V 2μs
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level
V(B_IT−) + Vhys(B_IT−) is ≤ 1.8V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT−) + Vhys(B_IT−). The default
FLL+ settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired
operating frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout/SVS circuit.
typical characteristics
0
1
td(BOR)
VCC
V(B_IT−)
Vhys(B_IT−)
VCC(start)
Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage
VCC
3 V
tpw
0
0.5
1
1.5
2
0.001 1 1000
Typical Conditions
1 ns 1 ns
tpw − Pulse Width − μst
pw − Pulse Width − μs
VCC = 3 V
VCC(drop) − V
VCC(drop)
Figure 11. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical characteristics
VCC
0
0.5
1
1.5
2
tpw
tpw − Pulse Width − μs
3 V
0.001 1 1000 tftr
tpw − Pulse Width − μs
tf = tr
Typical Conditions
VCC = 3 V
VCC(drop) − V
VCC(drop)
Figure 12. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
SVS (supply voltage supervisor/monitor)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
t
dVCC/dt > 30 V/ms (see Figure 13) 5 150 μs
t(SVSR) dVCC/dt ≤ 30 V/ms 2000 μs
td(SVSon) SVSon, switch from VLD=0 to VLD ≠ 0, VCC = 3 V 20 150 μs
tsettle VLD ≠ 0‡12 μs
V(SVSstart) VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 13) 1.55 1.7 V
VLD = 1 70 120 155 mV
Vh
y
s
(
SVS_IT−
)
VCC/dt ≤ 3 V/s (see Figure 13) VLD = 2 .. 14 V(SVS_IT−)
x 0.001
V(SVS_IT−)
x 0.016
Vhys(SVS
_
IT
−
)
VCC/dt ≤ 3 V/s (see Figure 13), external voltage applied
on A7 VLD = 15 4.4 20 mV
VLD = 1 1.8 1.9 2.05
VLD = 2 1.94 2.1 2.23
VLD = 3 2.05 2.2 2.35
VLD = 4 2.14 2.3 2.46
VLD = 5 2.24 2.4 2.58
VLD = 6 2.33 2.5 2.69
V/dt ≤3 V/s (see Figure 13)
VLD = 7 2.46 2.65 2.84
V(SVS IT )
VCC/dt ≤ 3 V/s (see Figure 13) VLD = 8 2.58 2.8 2.97
V
V
(SVS_IT−) VLD = 9 2.69 2.9 3.10
V
VLD = 10 2.83 3.05 3.26
VLD = 11 2.94 3.2 3.39
VLD = 12 3.11 3.35 3.58†
VLD = 13 3.24 3.5 3.73†
VLD = 14 3.43 3.7†3.96†
VCC/dt ≤ 3 V/s (see Figure 13), external voltage applied
on A7 VLD = 15 1.1 1.2 1.3
ICC(SVS)
(see Note 1) VLD ≠ 0, VCC = 2.2 V/3 V 10 15 μA
†The recommended operating voltage range is limited to 3.6 V.
‡tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 1: The current consumption of the SVS module is not included in the ICC current consumption data.
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical characteristics
VCC(start)
VCC
V(B_IT−)
Brownout
Region
V(SVSstart)
V(SVS_IT−)
Software Sets VLD>0:
SVS is Active
td(SVSR)
undefined
Vhys(SVS_IT−)
0
1
td(BOR)
Brownout
0
1
td(SVSon)
td(BOR)
0
1
Set POR
Brown-
Out
Region
SVS Circuit is Active From VLD > to VCC < V(B_IT−)
SVSOut
Vhys(B_IT−)
Figure 13. SVS Reset (SVSR) vs Supply Voltage
0
0.5
1
1.5
2
VCC
VCC
1 ns 1 ns
tpw
tpw − Pulse Width − μs
3 V
1 10 1000
tftr
t − Pulse Width − μs
100
tpw
3 V
tf = tr
Rectangular Drop
Triangular Drop
VCC(drop) − V
VCC(drop)
VCC(drop)
Figure 14. VCC(drop) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
DCO
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
f(DCOCLK) N(DCO)=01Eh, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0,
fCrystal = 32.738 kHz 2.2 V/3 V 1 MHz
f
FN 8 FN 4 FN 3 FN 2 0 ; DCOPLUS 1
2.2 V 0.3 0.65 1.25
MHz
f(DCO=2) FN_8=FN_4=FN_3=FN_2=0 ; DCOPLUS = 1 3 V 0.3 0.7 1.3 MHz
f
FN 8 FN 4 FN 3 FN 2 0; DCOPLUS 1
2.2 V 2.5 5.6 10.5
MHz
f(DCO=27) FN_8=FN_4=FN_3=FN_2=0; DCOPLUS = 1 3 V 2.7 6.1 11.3 MHz
f
FN 8 FN 4 FN 3 0 FN 2 1; DCOPLUS 1
2.2 V 0.7 1.3 2.3
MHz
f(DCO=2) FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1 3 V 0.8 1.5 2.5 MHz
f
FN 8 FN 4 FN 3 0 FN 2 1; DCOPLUS 1
2.2 V 5.7 10.8 18
MHz
f(DCO=27) FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1 3 V 6.5 12.1 20 MHz
f
FN 8 FN 4 0 FN 3 1 FN 2 x; DCOPLUS 1
2.2 V 1.2 2 3
MHz
f(DCO=2) FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1 3 V 1.3 2.2 3.5 MHz
f
FN 8 FN 4 0 FN 3 1 FN 2 x; DCOPLUS 1
2.2 V 9 15.5 25
MHz
f(DCO=27) FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1 3 V 10.3 17.9 28.5 MHz
f
FN 8 0 FN 4 1 FN 3 FN 2 x; DCOPLUS 1
2.2 V 1.8 2.8 4.2
MHz
f(DCO=2) FN_8=0, FN_4= 1, FN_3= FN_2=x; DCOPLUS = 1 3 V 2.1 3.4 5.2 MHz
f
FN 8 0 FN 4 1 FN 3 FN 2 x; DCOPLUS 1
2.2 V 13.5 21.5 33
MHz
f(DCO=27) FN_8=0, FN_4=1, FN_3= FN_2=x; DCOPLUS = 1 3 V 16 26.6 41 MHz
f
FN 8 1 FN 4 FN 3 FN 2 x; DCOPLUS 1
2.2 V 2.8 4.2 6.2
MHz
f(DCO=2) FN_8=1, FN_4=FN_3=FN_2=x; DCOPLUS = 1 3 V 4.2 6.3 9.2 MHz
f
FN 8 1 FN 4 FN 3 FN 2 x; DCOPLUS 1
2.2 V 21 32 46
MHz
f(DCO=27) FN_8=1,FN_4=FN_3=FN_2=x; DCOPLUS = 1 3 V 30 46 70 MHz
S
Step size between adjacent DCO taps: 1 < TAP ≤ 20 1.06 1.11
Sn
Step
size
between
adjacent
DCO
taps:
Sn = fDCO(Tap n+1) / fDCO(Tap n) (see Figure 16 for taps 21 to 27) TAP = 27 1.07 1.17
D
Temperature drift, N
(
D
CO)
= 01Eh, FN_8=FN_4=FN_3=FN_2=0 2.2 V –0.2 –0.3 –0.4
%/_C
Dt
Temperature
drift
,
N(DCO)
=
01Eh
,
FN
_
8=FN
_
4=FN
_
3=FN
_
2=0
D = 2; DCOPLUS = 0 3 V –0.2 –0.3 –0.4 %/_C
DVDrift with VCC variation, N(DCO) = 01Eh, FN_8=FN_4=FN_3=FN_2=0
D = 2; DCOPLUS = 0 2.2 V/ 3 V 0 5 15 %/V
TA − °CVCC − V
f(DCO)
f(DCO205C)
f(DCO)
f(DCO3V)
1.8 3.02.4 3.6
1.0
20 6040 85
1.0
0−20−400
Figure 15. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
12720
1.11
1.17
DCO Tap
Sn - Stepsize Ratio between DCO Taps
Min
Max
1.07
1.06
Figure 16. DCO Tap Step Size
DCO Frequency
Adjusted by Bits
29 to 25 in SCFI1 {N{DCO}}
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Legend
Tolerance at Tap 27
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
f(DCO)
Figure 17. Five Overlapping DCO Ranges Controlled by FN_x Bits
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OSCCAPx = 0h, VCC = 2.2 V / 3 V 0
C
Inte
g
rated input capacitance OSCCAPx = 1h, VCC = 2.2 V / 3 V 10
pF
CXIN
Integrated
input
capacitance
(see Note 4) OSCCAPx = 2h, VCC = 2.2 V / 3 V 14 pF
OSCCAPx = 3h, VCC = 2.2 V / 3 V 18
OSCCAPx = 0h, VCC = 2.2 V / 3 V 0
C
Inte
g
rated output capacitance OSCCAPx = 1h, VCC = 2.2 V / 3 V 10
pF
CXOUT
Integrated
output
capacitance
(see Note 4) OSCCAPx = 2h, VCC = 2.2 V / 3 V 14 pF
OSCCAPx = 3h, VCC = 2.2 V / 3 V 18
VIL
Input levels at XIN
V2 2 V/3 V (see Note 3)
VSS 0.2×VCC
V
VIH Input levels at XIN VCC = 2.2 V/3 V (see Note 3) 0.8×VCC VCC V
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is
(CXIN xC
XOUT) / (CXIN + CXOUT). This is independent of XTS_FLL.
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
− Keep as short of a trace as possible between the ’FG43x and the crystal.
− Design a good ground plane around the oscillator pins.
− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.
4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h.
crystal oscillator, XT2 oscillator (see Note 1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
CXT2IN Integrated input capacitance VCC = 2.2 V/3 V 2 pF
CXT2OUT Integrated output capacitance VCC = 2.2 V/3 V 2 pF
VIL
Input levels at XT2IN
VCC = 2 2 V/3 V (see Note 2)
VSS 0.2 × VCC V
VIH
Input levels at XT2IN VCC = 2.2 V/3 V (see Note 2) 0.8 × VCC VCC V
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
USART0 (see Note 1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
t( )
USART0: deglitch time
VCC = 2.2 V, SYNC = 0 , UART mode 200 430 800
ns
t(τ)USART0: deglitch time VCC = 3 V, SYNC = 0 , UART mode 150 280 500 ns
NOTES: 1. The signal applied to the USART0 receive signal/terminal (URXD0) should meet the timing requirements of t(τ) to ensure that the
URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating
conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative
transitions on the URXD0 line.
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, power supply and input range conditions (see Note 1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
AVCC Analog supply voltage
AVCC and DVCC are connected together
AVSS and DVSS are connected together
V(AVSS) = V(DVSS) = 0 V
2.2 3.6 V
V(P6.x/Ax) Analog input voltage
range (see Note 2)
All external Ax terminals. Analog inputs
selected in ADC12MCTLx register and P6Sel.x=1
V(AVSS) ≤ VAx ≤ V(AVCC)
0 VAVCC V
I
Operating supply current
into AV terminal
fADC12CLK = 5.0 MHz
ADC12ON 1 REFON 0
VCC = 2.2 V 0.65 1.3
mA
IADC12 into AVCC terminal
(see Note 3)
ADC12ON = 1, REFON = 0
SHT0=0, SHT1=0, ADC12DIV=0 VCC = 3 V 0.8 1.6 mA
I
Operating supply current
it AV til
fADC12CLK = 5.0 MHz
ADC12ON = 0,
REFON = 1, REF2_5V = 1
VCC = 3 V 0.5 0.8 mA
IREF+ into AVCC terminal
(see Note 4) fADC12CLK = 5.0 MHz
ADC12ON 0
VCC = 2.2 V 0.5 0.8
mA
(see
Note
4)
ADC12ON = 0,
REFON = 1, REF2_5V = 0 VCC = 3 V 0.5 0.8 mA
CIInput capacitance Only one terminal can be selected
at one time, Ax VCC = 2.2 V 40 pF
RIInput MUX ON resistance 0V ≤ VAx ≤ VAVCC VCC = 3 V 2000 Ω
NOTES: 1. The leakage current is defined in the leakage current table with Ax parameter.
2. The analog input voltage range must be within the selected reference voltage range VR+ to VR− for valid conversion results.
3. The internal reference supply current is not included in current consumption parameter IADC12.
4. The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
12-bit ADC, external reference (see Note 1)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
VeREF+ Positive external
reference voltage input
VeREF+ > VREF−/VeREF−
(see Note 2) 1.4 VAVCC V
VREF− /VeREF− Negative external
reference voltage input
VeREF+ > VREF−/VeREF−
(see Note 3) 0 1.2 V
(VeREF+ −
VREF−/VeREF−)
Differential external
reference voltage input
VeREF+ > VREF−/VeREF−
(see Note 4) 1.4 VAVCC V
IVeREF+ Static input current 0V ≤VeREF+ ≤ VAVCC VCC = 2.2 V/3 V ±1μA
IVREF−/VeREF− Static input current 0V ≤ VeREF− ≤ VAVCC VCC = 2.2 V/3 V ±1μA
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, built-in reference
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
V
Positive built-in reference
REF2_5V = 1 for 2.5 V
IVREF+max ≤IVREF+≤IVREF+min VCC = 3 V 2.4 2.5 2.6
V
VREF+
Positive
built in
reference
voltage output REF2_5V = 0 for 1.5 V
IVREF+max ≤IVREF+≤IVREF+min VCC = 2.2 V/3 V 1.44 1.5 1.56
V
AVCC minimum voltage,
REF2_5V = 0, IVREF+max ≤IVREF+≤IVREF+min 2.2
AVCC
(
min
)
AV
CC
minimum
voltage
,
Positive built-in reference REF2_5V = 1, IVREF+min ≥IVREF+≥−0.5mA 2.8 V
AVCC(min)
Positive
built in
reference
active REF2_5V = 1, IVREF+min ≥IVREF+≥ −1mA 2.9
V
I
Load current out of VREF+ VCC = 2.2 V 0.01 −0.5
mA
IVREF+
Load
current
out
of
VREF
+
terminal VCC = 3 V 0.01 −1 mA
IVREF+ = 500 μA +/− 100 μA
Analog input voltage 0 75 V;
VCC = 2.2 V ±2
LSB
I
Load-current re
g
ulation
Analog input voltage ~0.75 V;
REF2_5V = 0 VCC = 3 V ±2LSB
IL(VREF)+
Load current
regulation
VREF+ terminal IVREF+ = 500 μA ± 100 μA
Analog input voltage ~1.25 V;
REF2_5V = 1
VCC = 3 V ±2 LSB
I
Load current re
g
ulation IVREF+ =100 μA → 900 μA,
C 5 μF ax 05xV
V3V
20
ns
IDL(VREF) +
Load
current
regulation
VREF+ terminal CVREF+=5 μF, ax ~0.5 x VREF+
Error of conversion result ≤ 1 LSB
VCC = 3 V 20 ns
CVREF+ Capacitance at pin VREF+
(see Note 1)
REFON =1,
0 mA ≤ IVREF+ ≤IVREF+max VCC = 2.2 V/3 V 5 10 μF
TREF+ Temperature coefficient of
built-in reference
IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ 1 mA VCC = 2.2 V/3 V ±100 ppm/°C
tREFON
Settle time of internal
reference voltage (see
Figure 18 and Note 2)
IVREF+ = 0.5 mA, CVREF+ = 10 μF,
VREF+ = 1.5 V, VAVCC = 2.2 V 17 ms
NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses
two capacitors between pins VREF+ and AVSS and VREF−/VeREF− and AVSS: 10 μF tantalum and 100 nF ceramic.
2. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
CVREF+
1 μF
0
1 ms 10 ms 100 ms tREFON
tREFON ≈.66 x CVREF+ [ms] with CVREF+ in μF
100 μF
10 μF
Figure 18. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
+
−
10 μF 100 nF
AVSS
MSP430FG43x
+
−
+
−
10 μF 100 nF
10 μF 100 nF
AVCC
10 μF 100 nF
DVSS1/2
DVCC1/2
From
Power
Supply
Apply
External
Reference
+
−
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]VREF+ or VeREF+
VREF−/VeREF−
Figure 19. Supply Voltage and Reference Voltage Design VREF−/VeREF− External Supply
+
−
10 μF 100 nF
AVSS
MSP430FG43x
+
−
10 μF 100 nF
AVCC
10 μF 100 nF
DVSS1/2
DVCC1/2
From
Power
Supply +
−
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]VREF+ or VeREF+
VREF−/VeREF−
Reference Is Internally
Switched to AVSS
Figure 20. Supply Voltage and Reference Voltage Design VREF−/VeREF− = AVSS, Internally Connected
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, timing parameters
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
fADC12CLK For specified performance of
ADC12 linearity parameters
VCC =
2.2V/3 V 0.45 5 6.3 MHz
fADC12OSC Internal ADC12
oscillator
ADC12DIV=0,
fADC12CLK=fADC12OSC
VCC =
2.2 V/ 3 V 3.7 5 6.3 MHz
t
Conversion time
CVREF+ ≥ 5 μF, Internal oscillator,
fADC12OSC = 3.7 MHz to 6.3 MHz
VCC =
2.2 V/ 3 V 2.06 3.51 μs
tCONVERT Conversion time External fADC12CLK from ACLK, MCLK or SMCLK:
ADC12SSEL ≠ 0
13×ADC12DIV×
1/fADC12CLK μs
tADC12ON Turn on settling time of
the ADC (see Note 1) 100 ns
R
S
= 400 Ω, RI = 1000 Ω, VCC = 3 V 1220
tSample Sampling time
RS
=
400
Ω
,
RI
=
1000
Ω
,
CI = 30 pF, τ = [RS + RI] x CI
(see Note 2) VCC =
2.2 V 1400 ns
NOTES: 1. The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
2. Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns where n = ADC resolution = 12, RS = external source resistance.
12-bit ADC, linearity parameters
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
E
Integral linearity error
1.4 V ≤ (VeREF+ − VREF−/VeREF−) min ≤ 1.6 V V
CC
= ±2
LSB
EIIntegral linearity error 1.6 V < (VeREF+ − VREF−/VeREF−) min ≤ [VAVCC]
VCC
=
2.2 V/3 V ±1.7 LSB
EDDifferential linearity
error
(VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 μF (tantalum) and 100 nF (ceramic)
VCC =
2.2 V/3 V ±1 LSB
EOOffset error
(VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
Internal impedance of source RS < 100 Ω,
CVREF+ = 10 μF (tantalum) and 100 nF (ceramic)
VCC =
2.2 V/3 V ±2±4 LSB
EGGain error (VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 μF (tantalum) and 100 nF (ceramic)
VCC =
2.2 V/3 V ±1.1 ±2 LSB
ETTotal unadjusted
error
(VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 μF (tantalum) and 100 nF (ceramic)
VCC =
2.2 V/3 V ±2±5 LSB
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, temperature sensor and built-in VMID
PARAMETER TEST CONDITIONS VCC MIN NOM MAX UNIT
I
Operatin
g
suppl
y
current into REFON = 0, INCH = 0Ah, 2.2 V 40 120
A
ISENSOR
Operating
supply
current
into
AVCC terminal (see Note 1)
REFON
=
0
,
INCH
=
0Ah
,
ADC12ON=NA, TA = 25_C3 V 60 160 μA
V
(see Note 2)
ADC12ON = 1, INCH = 0Ah, 2.2 V/
986
mV
VSENSOR (see Note 2)
ADC12ON
=
1
,
INCH
=
0Ah
,
TA = 0°C
2
.
2
V/
3 V 986 mV
TC
ADC12ON 1 INCH 0Ah
2.2 V/
355±3%
mV/°C
TCSENSOR ADC12ON = 1, INCH = 0Ah
2
.
2
V/
3 V 3.55±3% mV/°C
t
Sample time required if
channel 10 is selected
ADC12ON = 1, INCH = 0Ah, 2.2 V 30
s
tSENSOR(sample) channel 10 is selected
(see Note 3)
ADC12ON
=
1
,
INCH
=
0Ah
,
Error of conversion result ≤1 LSB 3 V 30 μs
I
Current into divider at
ADC12ON 1 INCH 0Bh
2.2 V NA
A
IVMID
Current
into
divider
at
channel 11 (see Note 4) ADC12ON = 1, INCH = 0Bh, 3 V NA μA
V
AV divider at channel 11
ADC12ON = 1, INCH = 0Bh, 2.2 V 1.1 1.1±0.04
V
VMID AVCC divider at channel 11
ADC12ON
=
1
,
INCH
=
0Bh
,
VMID is ~0.5 x VAVCC 3 V 1.5 1.50±0.04 V
t
Sample time required if
channel 11 is selected
ADC12ON = 1, INCH = 0Bh, 2.2 V 1400
ns
tVMID(sample) channel 11 is selected
(see Note 5)
ADC12ON
=
1
,
INCH
=
0Bh
,
Error of conversion result ≤ 1 LSB 3 V 1220 ns
NOTES: 1. The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON=1), or (ADC12ON=1 AND INCH=0Ah and sample signal
is high). When REFON = 1, ISENSOR is already included in IREF+.
2. The temperature sensor offset can be as much as ±20_C. A single-point calibration is recommended in order to minimize the offset
error of the built-in temperature sensor.
3. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
4. No additional current is needed. The VMID is used during sampling.
5. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
12-bit DAC, supply specifications
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
AVCC Analog supply voltage AVCC = DVCC,
AVSS = DVSS =0 V 2.20 3.60 V
DAC12AMPx=2, DAC12IR=0,
DAC12_xDAT=0800h 2.2V/3V 50 110
I
Supply Current:
Single DAC Channel
DAC12AMPx=2, DAC12IR=1,
DAC12_xDAT=0800h , VeREF+=VREF+= AVCC 2.2V/3V 50 110
A
IDD Single DAC Channel
(see Notes 1 and 2) DAC12AMPx=5, DAC12IR=1,
DAC12_xDAT=0800h, VeREF+=VREF+= AVCC 2.2V/3V 200 440
μA
DAC12AMPx=7, DAC12IR=1,
DAC12_xDAT=0800h, VeREF+=VREF+= AVCC 2.2V/3V 700 1500
PSRR
Power supply
rejection ratio
DAC12_xDAT = 800h, VREF = 1.5 V
ΔAVCC = 100mV 2.2V
70
dB
PSRR rejection ratio
(see Notes 3 and 4) DAC12_xDAT = 800h, VREF = 1.5 V or 2.5 V
ΔAVCC = 100mV 3V
70 dB
NOTES: 1. No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
2. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input
specifications.
3. PSRR = 20*log{ΔAVCC/ΔVDAC12_xOUT}.
4. VREF is applied externally. The internal reference is not used.
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (see Figure 21)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Resolution (12-bit Monotonic) 12 bits
INL
Integral nonlinearity
Vref = 1.5 V
DAC12AMPx = 7, DAC12IR = 1 2.2V
±20
±80
LSB
INL
Integral
nonlinearity
(see Note 1) Vref = 2.5 V
DAC12AMPx = 7, DAC12IR = 1 3V
±2.0 ±8.0 LSB
DNL
Differential nonlinearity
Vref = 1.5 V
DAC12AMPx = 7, DAC12IR = 1 2.2V
±04
±10
LSB
DNL
Differential
nonlinearity
(see Note 1) Vref = 2.5 V
DAC12AMPx = 7, DAC12IR = 1 3V
±0.4 ±1.0 LSB
Offset voltage w/o
calibration
Vref = 1.5 V
DAC12AMPx = 7, DAC12IR = 1 2.2V
±21
EO
calibration
(see Notes 1, 2) Vref = 2.5 V
DAC12AMPx = 7, DAC12IR = 1 3V
±21
mV
Offset voltage with
calibration
Vref = 1.5 V
DAC12AMPx = 7, DAC12IR = 1 2.2V
±25
mV
calibration
(see Notes 1, 2) Vref = 2.5 V
DAC12AMPx = 7, DAC12IR = 1 3V
±2.5
dE(O)/dTOffset error
temperature coefficient
(see Note 1)
2.2V/3V ±30 μV/C
E
Gain error (see Note 1)
VREF = 1.5 V 2.2V
±350
% FSR
EGGain error (see Note 1) VREF = 2.5 V 3V ±3.50 % FSR
dE(G)/dT
Gain temperature
coefficient (see Note 1) 2.2V/3V 10 ppm of
FSR/°C
Time for offset calibration
DAC12AMPx=2 2.2V/3V 100
tOffset_Cal
Time for offset calibration
(see Note 3)
DAC12AMPx=3,5 2.2V/3V 32 ms
tOffset
_
Cal
(see Note 3) DAC12AMPx=4,6,7 2.2V/3V 6
ms
NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and
“b” of the first order equation: y = a + b*x. VDAC12_xOUT = EO + (1 + EG) * (VeREF+/4095) * DAC12_xDAT, DAC12IR = 1.
2. The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx
={0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may
effect accuracy and is not recommended.
Positive
Negative
VR+
Gain Error
Offset Error
DAC Code
DAC VOUT
Ideal transfer
function
RLoad =
AV CC
CLoad = 100pF
2
DAC Output
Figure 21. Linearity Test Load Conditions and Gain/Offset Definition
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (continued)
DAC12_xDAT − Digital Code
−4
−3
−2
−1
0
1
2
3
4
0 512 1024 1536 2048 2560 3072 3584
VCC = 2.2 V, VREF = 1.5V
DAC12AMPx = 7
DAC12IR = 1
TYPICAL INL ERROR
vs
DIGITAL INPUT DATA
4095
INL − Integral Nonlinearity Error − LSB
DAC12_xDAT − Digital Code
−2.0
−1.5
−1.0
−0.5
0.0
0.5
1.0
1.5
2.0
0 512 1024 1536 2048 2560 3072 3584
VCC = 2.2 V, VREF = 1.5V
DAC12AMPx = 7
DAC12IR = 1
TYPICAL DNL ERROR
vs
DIGITAL INPUT DATA
4095
DNL − Differential Nonlinearity Error − LSB
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, output specifications
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
2.2V/3V 0 0.005
V
Output voltage
range
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
2.2V/3V AVCC−0.05 AVCC
V
VO
range
(see Note 1,
Figure 24)
RLoad= 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
2.2V/3V 0 0.1
V
RLoad= 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
2.2V/3V AVCC−0.13 AVCC
CL(DAC12)
Max DAC12
load capacitance 2.2V/3V 100 pF
I
Max DAC12 2.2V −0.5 +0.5
mA
IL(DAC12)
Max
DAC12
load current 3V −1.0 +1.0 mA
RLoad= 3 kΩ, VO/P(DAC12) < 0.3 V,
DAC12AMPx = 7,
DAC12_xDAT = 0h
2.2V/3V 150 250
RO/P(DAC12)
Output
Resistance
(see Figure 24)
RLoad= 3 kΩ,
VO/P(DAC12) > AVCC−0.3 V
DAC12AMPx = 7,
DAC12_xDAT = 0FFFh
2.2V/3V 150 250 Ω
RLoad= 3 kΩ,
0.3V ≤ VO/P(DAC12) ≤ AVCC − 0.3V
DAC12AMPx = 7
2.2V/3V 1 4
NOTES: 1. Data is valid after the offset calibration of the output amplifier.
RO/P(DAC12_x)
Max
0.3
AV CC
AV CC
−0.3V VOUT
Min
RLoad
AV CC
CLoad
= 100pF
2
ILoad
DAC12
O/P(DAC12_x)
Figure 24. DAC12_x Output Resistance Tests
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12-bit DAC, reference input specifications
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Ve
Reference input DAC12IR=0, (see Notes 1 and 2) 2.2V/3V AVCC/3 AVCC+0.2
V
VeREF+
Reference
input
voltage range DAC12IR=1, (see Notes 3 and 4) 2.2V/3V AVcc AVcc+0.2 V
DAC12_0 IR=DAC12_1 IR =0 2.2V/3V 20 MΩ
DAC12_0 IR=1, DAC12_1 IR = 0 2.2V/3V
40
48
56
kΩ
Ri(VREF+),Reference input DAC12_0 IR=0, DAC12_1 IR = 1 2.2V/3V 40 48 56 kΩ
(VREF+),
Ri(VeREF+)
p
resistance DAC12_0 IR=DAC12_1 IR =1
DAC12_0 SREFx = DAC12_1 SREFx
(see Note 5)
2.2V/3V 20 24 28 kΩ
NOTES: 1. For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
2. The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC − VE(O)] / [3*(1 + EG)].
3. For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
4. The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC − VE(O)] / (1 + EG).
5. When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
12-bit DAC, dynamic specifications; Vref = VCC, DAC12IR = 1 (see Figure 25 and Figure 26)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
DAC12 on
DAC12_xDAT = 800h, DAC12AMPx=0 → {2, 3, 4} 2.2V/3V 60 120
tON
DAC12 on-
time
DAC12
_
xDAT
=
800h
,
ErrorV(O) < ±0.5 LSB DAC12AMPx=0 → {5, 6} 2.2V/3V 15 30 μs
tON
time
ErrorV(O)
<
±0.5
LSB
(see Note 1,Figure 25) DAC12AMPx=0 → 7 2.2V/3V 6 12
μs
Settling
DAC12 xDAT
DAC12AMPx=2 2.2V/3V 100 200
tS
(
FS
)
Settling
time full-scale
DAC12_xDAT =
80h→F7Fh→80h
DAC12AMPx=3,5 2.2V/3V 40 80 μs
tS(FS)
time,full-scale 80h→ F7Fh→ 80h DAC12AMPx=4,6,7 2.2V/3V 15 30
μs
Settling time
DAC12_xDAT = DAC12AMPx=2 2.2V/3V 5
tS
(
C-C
)
Settling time,
code to code
DAC12
_
xDAT
=
3F8h→ 408h→ 3F8h DAC12AMPx=3,5 2.2V/3V 2 μs
tS(C
-
C)
code to code
3F8h→
408h→
3F8h
BF8h→ C08h→ BF8h DAC12AMPx=4,6,7 2.2V/3V 1
μs
DAC12 xDAT
DAC12AMPx=2 2.2V/3V 0.05 0.12
SR Slew Rate DAC12_xDAT =
80h→F7Fh→80h
DAC12AMPx=3,5 2.2V/3V 0.35 0.7 V/μs
SR
Slew
Rate
80h→ F7Fh→ 80h DAC12AMPx=4,6,7 2.2V/3V 1.5 2.7
V/μs
DAC12 xDAT
DAC12AMPx=2 2.2V/3V 10
Glitch energy: full-scale DAC12_xDAT =
80h→F7Fh→80h
DAC12AMPx=3,5 2.2V/3V 10 nV-s
Glitch
energy:
full scale
80h→ F7Fh→ 80h DAC12AMPx=4,6,7 2.2V/3V 10
nV s
NOTES: 1. RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 25.
2. Slew rate applies to output voltage steps >= 200mV.
RLoad
AV CC
CLoad = 100pF
2
DAC Output
RO/P(DAC12.x)
ILoad
Conversion 1 Conversion 2
VOUT
Conversion 3
Glitch
Energy
+/− 1/2 LSB
+/− 1/2 LSB
tsettleLH tsettleHL
= 3 kΩ
Figure 25. Settling Time and Glitch Energy Testing
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Conversion 1 Conversion 2
VOUT
Conversion 3
10%
tSRLH tSRHL
90%
10%
90%
Figure 26. Slew Rate Testing
12-bit DAC, dynamic specifications continued (TA = 25°C unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
3 dB b d idth
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h 2.2V/3V 40
BW−3dB
3-dB bandwidth,
VDC=1.5V, VAC=0.1VPP
(see Figure 27)
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h 2.2V/3V 180 kHz
(see Figure 27) DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h 2.2V/3V 550
DAC12_0DAT = 800h, No Load,
DAC12_1DAT = 80h<−>F7Fh, RLoad = 3kΩ
fDAC12_1OUT = 10kHz @ 50/50 duty cycle
2.2V/3V −80
dB
Channel-to-channel crosstalk
(see Note 1 and Figure 28) DAC12_0DAT = 80h<−>F7Fh, RLoad = 3kΩ,
DAC12_1DAT = 800h, No Load
fDAC12_0OUT = 10kHz @ 50/50 duty cycle
2.2V/3V −80
dB
NOTES: 1. RLOAD = 3 kΩ, CLOAD = 100 pF
VeREF+
AC
DC
RLoad
AV CC
CLoad
= 100pF
2
ILoad
DAC12_x
DACx
= 3 kΩ
Figure 27. Test Conditions for 3-dB Bandwidth Specification
DAC12_xDAT 080h
VOUT
fToggle
7F7h
VDAC12_yOUT
080h 7F7h 080h
VDAC12_xOUT
e
REF+ RLoad
AV CC
CLoad
= 100pF
2
ILoad
DAC12_1
RLoad
AV CC
CLoad
= 100pF
2
ILoad
DAC12_0 DAC0
DAC1
V
Figure 28. Crosstalk Test Conditions
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
operational amplifier OA, supply specifications
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VCC Supply voltage — 2.2 3.6 V
Fast Mode RRIP OFF
2 2 V/3 V
180
290
Fast Mode, RRIP OFF 2.2 V/3 V 180 290
Medium Mode RRIP OFF
2 2 V/3 V
110
190
Medium Mode, RRIP OFF 2.2 V/3 V 110 190
I
Su
pp
l
y
current Slow Mode, RRIP OFF 2.2 V/3 V 50 80
A
ICC
Supply
current
(see Note 1)
Fast Mode RRIP ON
2 2 V/3 V
300
490
μA
ICC
(
see
N
o
t
e
1)
Fast Mode, RRIP ON 2.2 V/3 V 300 490
μA
Medium Mode RRIP ON
2 2 V/3 V
190
350
Medium Mode, RRIP ON 2.2 V/3 V 190 350
Slow Mode RRIP ON
2 2 V/3 V
90
190
Slow Mode, RRIP ON 2.2 V/3 V 90 190
PSRR Power supply rejection ratio Non-inverting 2.2 V/3 V 70 dB
NOTES: 1. P6SEL.x = 1 for each corresponding pin when used in OA input or OA output mode.
operational amplifier OA, input/output specifications
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
V
Voltage supply I/P
RRIP OFF — −0.1 VCC−1.2 V
VI/P Voltage supply, I/P RRIP ON — −0.1 VCC+0.1 V
I
Input leaka
g
e current, I/P TA = −40 to +55_C — −5 ±0.5 5 nA
IIkg
Input
leakage
current
,
I/P
(see Notes 1 and 2) TA = +55 to +85_C — −20 ±5 20 nA
Fast Mode — 50
Medium Mode fV
(
I/P
)
= 1 kHz — 80
V
Voltage noise density I/P
Slow Mode
fV(I/P)
1
kHz
— 140
nV/√Hz
VnVoltage noise density, I/P Fast Mode — 30 nV/√Hz
Medium Mode fV
(
I/P
)
= 10 kHz — 50
Slow Mode
fV(I/P)
10
kHz
— 65
V
Offset voltage I/P
2 2 V/3 V
±10
mV
VIO Offset voltage, I/P 2.2 V/3 V ±10 mV
Offset temperature drift, I/P see Note 3 2.2 V/3 V ±10 μV/°C
Offset voltage drift
with supply, I/P
0.3V ≤ VIN ≤ VCC−0.3V
ΔVCC≤ ± 10%, TA = 25°C2.2 V/3 V ±1.5 mV/V
V
High level output voltage O/P
Fast Mode, ISOURCE ≤ −500μA2.2 V VCC−0.2 VCC
V
VOH High-level output voltage, O/P Slow Mode,ISOURCE ≤ −150μA3 V VCC−0.1 VCC V
V
Low level output voltage O/P
Fast Mode, ISOURCE ≤ +500μA2.2 V VSS 0.2
V
VOL Low-level output voltage, O/P Slow Mode,ISOURCE ≤ +150μA3 V VSS 0.1 V
RLoad= 3 kΩ, CLoad = 50pF, RRIP ON,
VO/P(OAx) < 0.2 V 2.2 V/3 V 150 250
RO/P
(OAx)
Output
Resistance
(see Figure 29 and Note 4)
RLoad= 3 kΩ, CLoad = 50pF, RRIP ON,
VO/P(OAx) > AVCC − 0.2 V 2.2 V/3 V 150 250 Ω
(OAx)
(
see
Fi
gure
29
an
d
N
o
t
e
4)
RLoad= 3 kΩ, CLoad = 50pF, RRIP ON,
0.2 V ≤ VO/P(OAx) ≤ AVCC − 0.2 V 2.2 V/3 V 0.1 4
CMRR Common-mode rejection ratio Non-inverting 2.2 V/3 V 70 dB
NOTES: 1. ESD damage can degrade input current leakage.
2. The input bias current is overridden by the input leakage current.
3. Calculated using the box method.
4. Specification valid for voltage-follower OAx configuration.
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
45
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
RO/P(OAx)
Max
0.2V AV CC
AV CC
−0.2V VOUT
Min
RLoad
AV CC
CLoad
2
ILoad
OAx
O/P(OAx)
Figure 29. OAx Output Resistance Tests
operational amplifier OA, dynamic specifications
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Fast Mode — 1.2
SR Slew rate Medium Mode — 0.8 V/μs
SR
Slew
rate
Slow Mode — 0.3
V/μs
Open-loop voltage gain — 100 dB
φmPhase margin CL = 50 pF — 60 deg
Gain margin CL = 50 pF — 20 dB
Non inverting Fast Mode R 47kΩC50pF
2 2 V/3 V
22
Gain
-
Bandwidth Product
Non−inverting, Fast Mode, RL = 47kΩ, CL = 50pF 2.2 V/3 V 2.2
GBW
Gain
-
Bandwidth
Product
(see Figure 30
Non inverting Medium Mode R 300kΩC50pF
2 2 V/3 V
14
MHz
GBW (see Figure 30 Non−inverting, Medium Mode, RL =300kΩ, CL = 50pF 2.2 V/3 V 1.4 MHz
GBW
(see
Figure
30
a
n
d
Fi
gu
r
e
3
1
)
Non inverting Slow Mode R 300kΩC50pF
2 2 V/3 V
05
MHz
and
Figure
31)
Non−inverting, Slow Mode, RL =300kΩ, CL = 50pF 2.2 V/3 V 0.5
ten(on) Enable time on ton, non-inverting, Gain = 1 2.2 V/3 V 10 20 μs
ten(off) Enable time off 2.2 V/3 V 1μs
Figure 30
Input Frequency − kHz
−80
−60
−40
−20
0
20
40
60
80
100
120
140
TYPICAL OPEN-LOOP GAIN vs FREQUENCY
Slow Mode
Fast Mode
Gain − dB
Medium Mode
0.001 0.01 0.1 1 10 100 1000 10000
Figure 31
Input Frequency − kHz
−250
−200
−150
−100
−50
0
1 10 100 1000 10000
TYPICAL PHASE vs FREQUENCY
Phase − degrees
Slow Mode
Fast Mode
Medium Mode
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Flash Memory
PARAMETER TEST
CONDITIONS VCC MIN NOM MAX UNIT
VCC(PGM/
ERASE) Program and Erase supply voltage 2.7 3.6 V
fFTG Flash Timing Generator frequency 257 476 kHz
IPGM Supply current from DVCC during program 2.7 V/ 3.6 V 3 5 mA
IERASE Supply current from DVCC during erase 2.7 V/ 3.6 V 3 7 mA
tCPT Cumulative program time see Note 1 2.7 V/ 3.6 V 10 ms
tCMErase Cumulative mass erase time see Note 2 2.7 V/ 3.6 V 200 ms
Program/Erase endurance 104105cycles
tRetention Data retention duration TJ = 25°C 100 years
tWord Word or byte program time 35
tBlock, 0Block program time for 1st byte or word 30
tBlock, 1-63 Block program time for each additional byte or word
see Note 3
21
t
tBlock, End Block program end-sequence wait time see Note 3 6tFTG
tMass Erase Mass erase time 5297
tSeg Erase Segment erase time 4819
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
JTAG Interface
PARAMETER TEST
CONDITIONS VCC MIN NOM MAX UNIT
f
TCK input frequency
see Note 1
2.2 V 0 5 MHz
fTCK TCK input frequency see Note 1 3 V 0 10 MHz
RInternal Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2 2.2 V/ 3 V 25 60 90 kΩ
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG Fuse (see Note 1)
PARAMETER TEST
CONDITIONS VCC MIN NOM MAX UNIT
VCC(FB) Supply voltage during fuse-blow condition TA = 25°C 2.5 V
VFB Voltage level on TDI/TCLK for fuse-blow: F versions 6 7 V
IFB Supply current into TDI/TCLK during fuse blow 100 mA
tFB Time to blow fuse 1 ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
47
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
input/output schematic
Port P1, P1.0 to P1.5, input/output with Schmitt-trigger
P1OUT.x
Module X OUT
P1SEL.x
Direction Control
From Module
CAPD.x
D
EN
Interrupt
Edge
Select
P1IES.x P1SEL.x
P1IE.x
P1IFG.x
P1IRQ.x EN
Set
Q
0
1
1
0
PnSEL.x PnDIR.x Dir. Control
from module PnOUT.x Module X
OUT PnIN.x PnIE.x PnIFG.x PnIES.xModule X IN
P1SEL.1 P1DIR.1 P1OUT.1 P1IN.1 P1IE.1 P1IFG.1 P1IES.1
P1SEL.2 P1DIR.2 P1OUT.2 P1IN.2 P1IE.2 P1IFG.2 P1IES.2
P1SEL.0 P1DIR.0 P1OUT0 P1IN.0 P1IE.0 P1IFG.0 P1IES.0Out0 sig. CCI0AP1DIR.0
MCLK
DVSS
Module X IN
P1IN.x
Pad Logic
0: Input
1: Output
Bus
Keeper
Out1 sig. CCI1A
CCI0B
DVSS
†
‡
†
Note: 0 ≤ x ≤ 5
Note: Port function is active if CAPD.x = 0
P1DIR.x
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1SEL.4 P1DIR.4 P1OUT.4 P1IN.4 P1IE.4 P1IFG.4 P1IES.4
P1SEL.5 P1DIR.5 P1OUT.5 P1IN.5 P1IE.5 P1IFG.5 P1IES.5
P1SEL.3 P1DIR.3 P1OUT.3 P1IN.3 P1IE.3 P1IFG.3 P1IES.3SVSOUT TBOUTHP1DIR.3
SMCLK
ACLK TACLK
TBCLK
†
†
‡
P1DIR.1
P1DIR.4
P1DIR.2
P1DIR5
†
†
†Timer_A
‡Timer_B
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
Port P1, P1.6, P1.7, input/output with Schmitt-trigger
P1OUT.7
P1DIR.7
P1SEL.7
D
EN
Interrupt
Edge
Select
P1IES.7 P1SEL.7
P1IE.7
P1IFG.7
P1IRQ.07 EN
Set
Q
0
1
1
0
CAPD.7
P1OUT.6
P1DIR.6
P1SEL.6
D
EN
Interrupt
Edge
Select
P1IES.x P1SEL.x
P1IE.7
P1IFG.7
P1IRQ.07
P1.6/
CA0
EN
Set
Q
0
1
1
0
CAPD.6 Note: Port function is active if CAPD.6 = 0
P1IN.6
unused
P1.7/
CA1
Comparator_A
Reference Block
CCI1B
CAF
CAREF
P2CA
CAEX
CAREF
to Timer_Ax −
+
2
AVcc
CA0
CA1
Pad Logic
0: Input
1: Output
Bus
Keeper
Pad Logic
0: input
1: output
Bus
keeper
P1DIR.6
P1DIR.7
P1IN.7
unused
Note: Port function is active if CAPD.7 = 0
DVSS
DVSS
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
49
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
port P2, P2.0, P2.4 to P2.5, input/output with Schmitt-trigger
P2OUT.x
Module X OUT
P2DIR.x
Direction Control
From Module
P2SEL.x
D
EN
Interrupt
Edge
Select
P2IES.x P2SEL.x
P2IE.x
P2IFG.x
P2IRQ.x EN
Set
Q
0
1
1
0
PnSel.x PnDIR.x Dir. Control
from module PnOUT.x Module X
OUT PnIN.x PnIE.x PnIFG.x PnIES.xModule X IN
P2Sel.4 P2DIR.4 P2OUT.4 P2IN.4 P2IE.4 P2IFG.4 P2IES.4
P2Sel.5 P2DIR.5 P2OUT.5 P2IN.5 P2IE.5 P2IFG.5 P2IES.5
P2Sel.0 P2DIR.0 P2OUT.0 P2IN.0 P2IE.0 P2IFG.0 P2IES.0Out2 sig. CCI2AP2DIR.0
UTXD0
DVSS
P2.5/URXD0
P2.0/TA2
P2.4/UTXD0
Module X IN
P2IN.x
x {0,4,5}Note:
Pad Logic
0: Input
1: Output
Bus
Keeper
DVCC
DVSS DVSS URXD0
unused
DVSS
†Timer_A
‡USART0
†
‡
†
‡
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
port P2, P2.1 to P2.3, input/output with Schmitt-trigger
P2OUT.x
Module X OUT
P2DIR.x
Direction Control
From Module
P2SEL.x
D
EN
Interrupt
Edge
Select
P2IES.x P2SEL.x
P2IE.x
P2IFG.x
P2IRQ.x EN
Set
Q
0
1
1
0
PnSel.x PnDIR.x Dir. Control
from module PnOUT.x Module X
OUT PnIN.x PnIE.x PnIFG.x PnIES.xModule X IN
P2Sel.1 P2DIR.1 P2OUT.1 P2IN.1 P2IE.1 P2IFG.1 P2IES.1
P2Sel.2 P2DIR.2 P2OUT.2 P2IN.2 P2IE.2 P2IFG.2 P2IES.2
P2Sel.3 P2DIR.3 P2OUT.3 P2IN.3 P2IE.3 P2IFG.3 P2IES.3
P2DIR.1
P2DIR.2
P2.1/TB0
P2.2/TB1
P2.3/TB2
Out0 sig.
Module X IN
P2IN.x
1< x< 3Note:
Pad Logic
0: Input
1: Output
Bus
Keeper
P2DIR.3 Out2 sig.
Out1 sig.
CCI0A
CCI0B
CCI1A
CCI1B
CCI2A
CCI2B
DVSS
DVSS
Module IN of pin
P1.3/TBOUTH/SVSOUT
P1SEL.3
P1DIR.3
†Timer_B
†
†
†
†
†
†
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
51
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
port P2, P2.6 to P2.7, input/output with Schmitt-trigger
P2OUT.x
Module X OUT
P2DIR.x
Direction Control
From Module
P2SEL.x
D
EN
Interrupt
Edge
Select
P2IES.x P2SEL.x
P2IE.x
P2IFG.x
P2IRQ.x EN
Set
Q
0
1
1
0
PnSel.x PnDIR.x Dir. Control
from module PnOUT.x Module X
OUT PnIN.x PnIE.x PnIFG.x PnIES.xModule X IN
0: Port active
1: Segment xx function active
P2Sel.6 P2DIR.6
P2Sel.7 P2DIR.7
P2DIR.6
P2DIR.7
P2OUT.6
P2OUT.7
P2IN.6
P2IN.7 unused
CAOUT
ADC12CLK
P2IE.6
P2IE.7
P2IFG.6
P2IFG.7
P2IES.6
P2IES.7
Module X IN
P2IN.x
6< x< 7Note:
Pad Logic
0: Input
1: Output
Bus
Keeper
unused
Port/LCD
0: LCDM<40h
0: LCDM<40h
Port/LCD‡
Segment xx‡
P2.6/CAOUT/S19
P2.7/ADC12CLK/S18
†
§
† Comparator_A
§ ADC12
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
port P3, P3.0 to P3.3, input/output with Schmitt-trigger
P3OUT.x
Module X OUT
P3DIR.x
Direction Control
From Module
P3SEL.x
D
EN
0
1
1
0
PnSel.x PnDIR.x PnOUT.x Module X
OUT PnIN.x Module X IN
P3Sel.1 P3DIR.1 P3OUT.1 P3IN.1
P3Sel.2 P3DIR.2 P3OUT.2 P3IN.2
P3Sel.3 P3DIR.3 P3OUT.3 P3IN.3
P3Sel.0 P3DIR.0 P3OUT.0 P3IN.0
UCLK0(out)
SOMIO(out)
DCM_SIMO0
DCM_SOMI0
DCM_UCLK0
Segment xx
0: Port active
1: Segment xx function active
SIMO0(out)
UCLK0(in)
SOMI0(in)
SIMO0(in)
STE0(in)
Module X IN
P3IN.x
Pad Logic
0: Input
1: Output
Bus
Keeper
LCDM.5
LCDM.6
LCDM.7
Direction
From Module
Control
DVSS
DVSS
MSP430x43xIPN (80-Pin) Only
x43xIPZ and x44xIPZ have not segment
Function on Port P3: Both lines are low.
P3.0/STE0/S31
P3.1/SIMO0/S30
P3.2/SOMI0/S29
P3.3/UCLK0/S28
Note: 0 ≤ x ≤ 3
SYNC
MM
STC
STE
SYNC
MM
STC
STE
DCM_SOMI0
DCM_SIMO0
DCM_UCLK0
Direction Control for SOMI0
Direction Control for SIMO0 and UCLK0
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
53
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
port P3, P3.4 to P3.7, input/output with Schmitt-trigger
P3OUT.x
Module X OUT
P3DIR.x
Direction Control
From Module
P3SEL.x
D
EN
0
1
1
0
PnSel.x PnDIR.x Dir. Control
from module PnOUT.x Module X
OUT PnIN.x Module X IN
0: Port active
1: Segment xx function active
P3SEL.4 P3DIR.4
P3SEL.5 P3DIR.5
P3DIR.4
P3DIR.5
P3OUT.4
P3OUT.5
P3IN.4
P3IN.5 unused
DVSS
DVSS
Module X IN
P3IN.x
4< x< 7Note:
Pad Logic
0: Input
1: Output
Bus
Keeper
unused
Segment xx
P3.4/S27
P3.5/S26
P3.6/S25/DMAE0
P3.7/S24
LCDM.7
P3SEL.6 P3DIR.6
P3SEL.7 P3DIR.7
P3DIR.6
P3DIR.7
P3OUT.6
P3OUT.7
P3IN.6
P3IN.7 unused
DVSS
DVSS
DMAE0
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
port P4, P4.0 to P4.5, input/output with Schmitt-trigger
P4OUT.x
Module X OUT
P4DIR.x
Direction Control
From Module
P4SEL.x
D
EN
0
1
1
0
PnSEL.x PnDIR.x PnOUT.x Module X
OUT PnIN.x Module X IN
P4SEL.1 P4DIR.1 P4OUT.1 P4IN.1
P4SEL.2 P4DIR.2 P4OUT.2 P4IN.2
P4SEL.3 P4DIR.3 P4OUT.3 P4IN.3
P4SEL.4 P4DIR.4 P4OUT.4 P4IN.4
P4SEL.5 P4DIR.5 P4OUT.5 P4IN.5
P4SEL.0 P4DIR.0 P4OUT.0 P4IN.0
Segment xx
0: Port active
1: Segment xx function active
Module X IN
P4IN.x
0< x< 5Note:
Pad Logic
0: Input
1: Output
Bus
Keeper
Direction
From Module
Control
DVSS
DVSS
DVSS
Port/LCD
P4.0/S9
P4.1/S8
P4.2/S7
P4.3/S6
P4.4/S5
P4.5/S4
P4DIR.0
P4DIR.1
P4DIR.2
P4DIR.3
P4DIR.4
P4DIR.5
DVSS
DVSS
DVSS
unused
unused
unused
unused
unused
unused
DEVICE PORT BITS PORT FUNCTION LCD SEG. FUNCTION
xG43xIPN 80-pin QFP P4.0 to P4.5 LCDM < 020h LCDM ≥ 020h
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
55
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
port P4, P4.6, input/output with Schmitt-trigger
PnSEL.x PnDIR.x PnOUT.x Module X
OUT PnIN.x Module X IN
P4SEL.6 P4DIR.6 P4DIR.6 P4OUT.6 P4IN.6 unused
Direction
From Module
Control
DVSS
P4OUT.6
Module XOUT
P4DIR.6
Direction Control
From Module
P4SEL.6
D
EN
0
1
1
0
Segment S3
1, if LCDM > 020h
0: Segment S3 disabled
1: Segment S3 enabled
Module X IN
P4IN.6
Pad Logic
0: input
1: output
Bus
keeper P4.6/S3/A15
INCH=15#
a15 #
#Signal from or to ADC12
DEVICE PORT BITS PORT FUNCTION LCD SEG. FUNCTION
xG43xIPN 80-pin QFP P4.6 LCDM < 020h LCDM ≥ 020h
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
port P4, P4.7, input/output with Schmitt-trigger
PnSel.x PnDIR.x PnOUT.x Module X
OUT PnIN.x Module X IN
P4Sel.7 P4DIR.7 P4DIR.7 P4OUT.7 P4IN.7 Unused
Direction
From Module
Control
DVSS
P4OUT.7
Module XOUT
P4DIR.7
Direction Control
From Module
P4SEL.7
D
EN
0
1
1
0
Segment S2
1, if LCDM > 020h
0: Segment S2 disabled
1: Segment S2 enabled
Module X IN
P4IN.7
Pad Logic
0: input
1: output
Bus
keeper P4.7/S2/A14
INCH=14#
a14#
#Signal from or to ADC12
OAADC0
DEVICE PORT BITS PORT FUNCTION LCD SEG. FUNCTION
xG43xIPN 80-pin QFP P4.7 LCDM < 020h LCDM ≥ 020h
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
57
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
port P5, P5.0, input/output with Schmitt-trigger
PnSEL.x PnDIR.x PnOUT.x Module X
OUT PnIN.x Module X IN
P5SEL.0 P5DIR.0 P5DIR.0 P5OUT.0 P5IN.0 unused
Direction
From Module
Control
DVSS
P5OUT.0
Module XOUT
P5DIR.0
Direction Control
From Module
P5SEL.0
D
EN
0
1
1
0
Segment S1
1, if LCDM > 020h
0: Segment S1 disabled
1: Segment S1 enabled
Module X IN
P5IN.0
Pad Logic
0: input
1: output
Bus
keeper P5.0/S1/A13
INCH=13#
a13 #
#Signal from or to ADC12
OAADC0
DEVICE PORT BITS PORT FUNCTION LCD SEG. FUNCTION
xG43xIPN 80-pin QFP P5.0 LCDM < 020h LCDM ≥ 020h
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
58 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
port P5, P5.1, input/output with Schmitt-trigger
P5OUT.1
Module XOUT
P5DIR.1
Direction Control
From Module
P5SEL.1
D
EN
0
1
1
0
Segment S0
1, if LCDM > 020h
0: Segment S0 disabled
1: Segment S0 enabled
Module X IN
P5IN.1
Pad Logic
0: input
1: output
Bus
keeper P5.1/S0/
A12/DAC1
INCH=12#
a12
#
#Signal from or to ADC12
1
0
’0’, if DAC12.1CALON=0 AND
DAC12.1AMPx>1 AND DAC12.1OPS=1
’1’, if DAC12.1AMPx=1
’1’, if DAC12.1AMPx>1
+
−
DAC12.1OPS
DAC12.1OPS
P6.7/A7/
DAC1/SVSIN
DAC1_2_OA
DAC12.1OPS
0
1
OAADC0
Function Description P5SEL.1 LCDM DAC12.1OPS DAC12.1AMPx
DAC12 3-State
0 V
DAC1 output
(the o/p voltage can be converted with ADC12, channel A12)
X
X
X
X
X
X
1
1
1
= 0
= 1
> 1
ADC12 Channel 12, A12 1 X 0 X
LCD Segment S0, initial state 0≥ 20h 0 X
Port P5.1 0 < 20h 0 X
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
59
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
port P5, P5.1, input/output with Schmitt-trigger (continued)
PnSEL.x PnDIR.x Dir. Control
from Module PnOUT.x Module X
OUT PnIN.x Module X
IN Segment Port/LCD
P5SEL.1 P5DIR.1 P5DIR.1 P5OUT.1 DVSS P5IN.1 Unused S0 0: LCDM<20h
port P5, P5.2 to P5.4, input/output with Schmitt-trigger
P5OUT.x
Module X OUT
P5DIR.x
Direction Control
From Module
P5SEL.x
D
EN
0
1
1
0
PnSel.x PnDIR.x Dir. Control
from module PnOUT.x Module X
OUT PnIN.x Module X IN
P5Sel.2 P5DIR.2 P5OUT.2 P5IN.2
P5Sel.3 P5DIR.3 P5OUT.3 P5IN.3
P5Sel.4 P5DIR.4 P5OUT.4 P5IN.4
DVSS
DVSS
DVSS
LCD signal
0: Port active
1: LCD function active
LCD signal
Unused
Unused
Unused
Module X IN
P5IN.x
2< x< 4Note:
Pad Logic
0: Input
1: Output
Bus
Keeper
P5DIR.3
P5DIR.2
P5DIR.4
Port/LCD
Port/LCD
P5.2/COM1
P5.3/COM2
P5.4/COM3
COM1
COM2
COM3
P5SEL.2
P5SEL.3
P5SEL.4
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
60 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
port P5, P5.5 to P5.7, input/output with Schmitt-trigger
P5OUT.x
Module X OUT
P5DIR.x
Direction Control
From Module
P5SEL.x
D
EN
0
1
1
0
PnSel.x PnDIR.x Dir. Control
from module PnOUT.x Module X
OUT PnIN.x Module X IN
P5Sel.5 P5DIR.5 P5OUT.5 P5IN.5
P5Sel.6 P5DIR.6 P5OUT.6 P5IN.6
P5Sel.7 P5DIR.7 P5OUT.7 P5IN.7
DVSS
DVSS
DVSS
LCD signal
0: Port active
1: LCD function active
LCD signal
Unused
Unused
Unused
Module X IN
P5IN.x
5< x< 7Note:
Pad Logic
0: Input
1: Output
Bus
Keeper
P5DIR.6
P5DIR.5
P5DIR.7
Port/LCD
Port/LCD
R13 P5SEL.5
P5.5/R13
P5.6/R23
P5.7/R33
R23
R33
P5SEL.6
P5SEL.7
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
61
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
port P6, P6.0, P6.2, and P6.4, input/output with Schmitt-trigger
P6OUT.x
Module XOUT
P6DIR.x
Direction Control
From Module
P6SEL.x
D
EN
0
1
1
0
Module X IN
P6IN.x
Pad Logic
0: input
1: output
Bus
keeper P6.0/A0/OA0I0
P6.2/A2/OA0I1
P6.4/A4/OA1I0
INCH=x
ax
#Signal from or to ADC12
+
−
†x = {0, 2, 4}
†
†, #
†
†
†, #
†
†
OA0 / OA1
PnSel.x PnDIR.x Dir. Control
From Module PnOUT.x Module X OUT PnIN.x Module X IN
P6Sel.0 P6DIR.0 P6DIR.0 P6OUT.0 DVSS P6IN.0 unused
P6Sel.2 P6DIR.2 P6DIR.2 P6OUT.2 DVSS P6IN.2 unused
P6Sel.4 P6DIR.4 P6DIR.4 P6OUT.4 DVSS P6IN.4 unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
62 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
port P6, P6.1, input/output with Schmitt-trigger
P6OUT.1
Module XOUT
P6DIR.1
Direction Control
From Module
P6SEL.1
D
EN
0
1
1
0
Module X IN
P6IN.1
Pad Logic
0: input
1: output
Bus
keeper P6.1/A1/OA0O
INCH=1#
a1 #
#Signal from or to ADC12
OA0
0
1
’1’, if OAADC1 = 1 OR OAFCx = 0
+
−
OA0
PnSel.x PnDIR.x Dir. Control
From Module PnOUT.x Module X OUT PnIN.x Module X IN
P6Sel.1 P6DIR.1 P6DIR.1 P6OUT.1 DVSS P6IN.1 unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
63
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
port P6, P6.3, input/output with Schmitt-trigger
P6OUT.3
Module XOUT
P6DIR.3
Direction Control
From Module
P6SEL.3
D
EN
0
1
1
0
Module X IN
P6IN.3
Pad Logic
0: input
1: output
Bus
keeper P6.3/A3/OA1I1/OA1O
INCH=3#
a3 #
#Signal from or to ADC12
OA1
0
1
’1’, if OAADC1 = 1 OR OAFCx = 0
+
−
OA1
PnSel.x PnDIR.x Dir. Control
From Module PnOUT.x Module X OUT PnIN.x Module X IN
P6Sel.3 P6DIR.3 P6DIR.3 P6OUT.3 DVSS P6IN.3 unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
port P6, P6.5, input/output with Schmitt-trigger
P6OUT.5
Module XOUT
P6DIR.5
Direction Control
From Module
P6SEL.5
D
EN
0
1
1
0
Module X IN
P6IN.5
Pad Logic
0: input
1: output
Bus
keeper P6.5/A5/OA2I1/OA2O
INCH=5#
a5 #
#Signal from or to ADC12
OA2
0
1
’1’, if OAADC1 = 1 OR OAFCx = 0
+
−
OA2
PnSel.x PnDIR.x Dir. Control
From Module PnOUT.x Module X OUT PnIN.x Module X IN
P6Sel.5 P6DIR.5 P6DIR.5 P6OUT.5 DVSS P6IN.5 unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
65
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
port P6, P6.6, input/output with Schmitt-trigger
P6OUT.6
DVSS
P6DIR.6
P6DIR.6
P6SEL.6
D
EN
0
1
1
0
INCH=6#
0: Port active, T−Switch off
1: T−Switch is on, Port disabled
P6IN.6
a6 #
Pad Logic
0: input
1: output
Bus
keeper
#Signal from or to ADC12
’1’, if DAC12.0AMP>0
P6.6/A6/DAC0/OA2I0
1
0
’0’, if DAC12CALON = 0 AND
DAC12AMPx>1 AND DAC12OPS = 0
’1’, if DAC12AMPx=1
’1’, if DAC12AMPx>1
+
−
DAC12OPS
DAC0_2_OA
DAC12OPS
1
0
Ve REF+/DAC0
DAC12.0OPS
PnSel.x PnDIR.x Dir. Control
From Module PnOUT.x Module X OUT PnIN.x Module X IN
P6Sel.6 P6DIR.6 P6DIR.6 P6OUT.6 DVSS P6IN.6 unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
66 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
port P6, P6.7, input/output with Schmitt-trigger
P6OUT.7
DVSS
P6DIR.7
P6DIR.7
P6SEL.7
D
EN
0
1
1
0
INCH=7#
0: Port active, T−Switch off
1: T−Switch is on, Port disabled
P6.7/A7/
DAC1/SVSIN
P6IN.7
a7 #
Pad Logic
0: input
1: output
Bus
keeper
#Signal from or to ADC12
’1’, if DAC12.1AMP>0
To SVS Mux (15) $
$Signal to SVS block, selected if VLD=15
’1’, if VLD=15 *
*VLD control bits are located in SVS
1
0
+
−
P5.1/S0/
A12/DAC1
DAC1_2_OA
1
0
DAC12.1OPS
’0’, if DAC12CALON = 0 AND
DAC12AMPx>1 AND DAC12OPS = 0
’1’, if DAC12AMPx=1
’1’, if DAC12AMPx>1
DAC12OPS
DAC12OPS
PnSel.x PnDIR.x Dir. Control
From Module PnOUT.x Module X OUT PnIN.x Module X IN
P6Sel.7 P6DIR.7 P6DIR.7 P6OUT.7 DVSS P6IN.7 unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
The signal at pin P6.7/A7/SVSIN is also connected to the input multiplexer in the module brownout/supply voltage supervisor.
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
67
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
VeREF+/DAC0
Ve REF+ /DAC0
#
Reference Voltage to ADC12
1
0
’0’, if DAC12CALON = 0
DAC12AMPx>1 AND DAC12OPS=1
’1’, if DAC12AMPx=1
’1’, if DAC12AMPx>1
+
−
DAC12OPS
Reference Voltage to DAC1
Reference Voltage to DAC0
If the reference of DAC0 is taken from pin VeREF+ /DAC0, unpredictable voltage levels will be on pin.
In this situation, the DAC0 output is fed back to its own reference input.
#
DAC0_2_OA
DAC12.0OPS
1
0
P6.6/A6/DAC0/OA2I0
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
68 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
input/output schematic (continued)
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
TDI
TDO
TMS
TDI/TCLK
TDO/TDI
Controlled
by JTAG
TCK
TMS
TCK
DVCC
Controlled by JTAG
Test
JTAG
and
Emulation
Module
DVCC
DVCC
Burn and Test
Fuse
RST/NMI
G
D
S
U
G
D
S
U
TCK
Tau ~ 50 ns
Brownout
Controlled by JTAG
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
69
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current (I(TF)) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 32). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition). The JTAG pins are terminated internally and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
I(TF)
ITDI/TCLK
Figure 32. Fuse Check Mode Current
MSP430FG43x
MIXED SIGNAL MICROCONTROLLER
SLAS380B − APRIL 2004 − REVISED JUNE 2007
70 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Data Sheet Revision History
Literature
Number Summary
SLAS380B
Updated functional block diagram (page 3)
Corrected I/O column for VeREF+/DAC0 in MSP430FG43x Terminal Functions table; changed from I to I/O (page 4)
Clarified test conditions in recommended operating conditions table (page 20)
Clarified test conditions in electrical characteristics table (page 21)
Corrected y-axis unit on Figures 6 and 7; changed from V to mV (page 27)
Clarified test conditions in DCO table (page 31)
Clarified test conditions in USART0 table (page 33)
Changed tCPT maximum value from 4 ms to 10 ms in Flash memory table (page 46)
Added OAADC0 to input/output schematics for P4.7, P5.0 (pages 57 and 58)
NOTE: Page and figure numbers refer to the respective document revision.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
MSP430A018IPN ACTIVE LQFP PN 80 119 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430A018IPNR ACTIVE LQFP PN 80 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430FG437IPN ACTIVE LQFP PN 80 119 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430FG437IPNR ACTIVE LQFP PN 80 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430FG438IPN ACTIVE LQFP PN 80 119 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430FG438IPNR ACTIVE LQFP PN 80 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430FG439IPN ACTIVE LQFP PN 80 119 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
MSP430FG439IPNR ACTIVE LQFP PN 80 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 1-Aug-2007
Addendum-Page 1
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PN (S-PQFP-G80) PLASTIC QUAD FLATPACK
4040135 /B 1 1/96
0,17
0,27
0,13 NOM
40
21
0,25
0,45
0,75
0,05 MIN
Seating Plane
Gage Plane
41
60
61
80
20
SQ
SQ
1
13,80
14,20
12,20
9,50 TYP
11,80
1,45
1,35
1,60 MAX 0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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