LTC3815
1
3815fa
For more information www.linear.com/LTC3815
FEATURES DESCRIPTION
6A Monolithic Synchronous
DC/DC Step-Down Converter with
Digital Power System Management
The LT C
®
3815 is a high efficiency, 6A monolithic synchro-
nous buck regulator using a phase lockable controlled
on-time, current mode architecture. The output voltage
is programmable from 0.4V to 72% of VIN with a single
external resistor or an external voltage reference through
the reference input (REF) pin. The output voltage can be
margined up or down up to ±25% with 0.1% resolution
via a PMBus-compliant serial interface. The serial interface
can also be used to read back fault status and both time-
averaged (~4ms) and peak input/output current, input/
output voltage and temperature. System configuration
and monitoring is supported by the LTpowerPlay
®
devel-
opment system.
The architecture provides extremely fast transient response
and allows operation at the very low on-times required to
regulate low output voltages at high switching frequencies.
The operating frequency is programmable from 400kHz
to 3MHz with an external resistor or for noise sensitive
applications, it can be synchronized to an external clock
over the same range. The operating supply voltage range
is from 2.25V to 5.5V making it suitable for operation from
2.5V, 3.3V or 5V rails or Lithium-Ion batteries.
L, LT , LT C , LT M , Linear Technology, the Linear logo and LTpowerPlay are registered
trademarks of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. Patents including 5481178, 5705919, 5929620, 6144194,
6177787, 6580258, 5408150, 7420359. Licensed under U.S. Patent 7000125 and other related
patents worldwide.
APPLICATIONS
n Intelligent Energy Efficient Power Conversion
n ASIC/FPGA/Processor Power
n Distributed Power Systems
n Point of Load Power Conversion
TYPICAL APPLICATION
Efficiency and Power Loss
vs Load Current
n 2.25V to 5.5V Input Voltage Range
n ±1% Total Output Voltage Accuracy Over
Temperature at VIN = 3.3V or 5V
n Single Resistor-Programmable Output Voltage
n PMBus Compliant Serial Interface:
n Programmable Output Voltage Margining:
Up to ±25% VOUT Range with 0.1% Resolution
n Read back of Average and Peak Temperature,
Current, and Voltage (25Hz Refresh Rate)
n Fault Status
n Phase-Lockable Fixed Frequency Up to 3MHz
n Less Than 1ms Power-Up Time
n Integrated 13-Bit ADC
n Optional External Reference Input
n Pin Selectable Fast-Margining of the Output Voltage
n Power Good Flag with Pin Programmable Thresholds
and Filter Delay
n Differential Remote Output Voltage Sensing
n Master Shutdown Mode: <1μA Supply Current
n Clock Out for 2-Phase Operation (12A Output Current)
n Available in a Thermally-Enhanced 38-Lead
4mm × 6mm QFN Package
VIN
2.25V TO 5.5V
VOUT
0.4V TO 0.72*VIN
6A
PGOOD
WP
SW
LTC3815
PGLIM
TRACK/SS
RUN_STBYRUN_MSTR
CLKOUT
CSLEW
MARGIN VCC_SENSE
VSS_SENSE
REF
ASEL PGFD
DAOUT
FB
RT
ITH
MODE/SYNC
SCL, SDA, ALERT
PVIN VIN
PMBUS
3815 TA01a
L
RC2
RC1
CC2
COUT
CIN
LOAD CURRENT (mA)
30
EFFICIENCY (%)
POWER LOSS (W)
90
100
20
10
80
50
70
60
40
10 100 1000 10000
3815 TA01b
0 0
10
1
0.1
EFFICIENCY
VOUT = 1.8V
VIN = 2.8V
VIN = 3.3V
VIN = 5V
POWER LOSS
LTC3815
2
3815fa
For more information www.linear.com/LTC3815
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
VIN, PVIN....................................................... –0.3V to 6V
VCC_SENSE, VSS_SENSE, CSLEW, RT, ITH, MODE/SYNC,
REF, TRACK/SS, PGFD, PGLIM, ASEL, DAOUT, MARGIN,
RUN_STBY, FB .............................. –0.3V to (VIN + 0.3V)
RUN_MSTR, PGOOD, ALERT, SCL,
SDA Voltage ............................................. –0.3V to 6V
WP ............................................................ –0.3V to 2.5V
Operating Junction Temperature Range
(Notes 2, 3) ............................................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
(Notes 1, 7)
13 14 15 16
TOP VIEW
39
PGND
UFE PACKAGE
38-LEAD (4mm × 6mm) PLASTIC QFN
17 18 19
38 37 36 35 34 33 32
24
24
26
27
28
29
30
31
8
7
6
5
4
3
2
1RT
ASEL
MARGIN
WP
ALERT
CLKOUT
SDA
SCL
MODE/SYNC
SW
SW
NC
VSS_SENSE
TRACK/SS
PGOOD
CSLEW
RUN_STBY
RUN_MSTR
PGFD
VIN
SW
SW
SW
NC
SGND
PGLIM
REF
FB
ITH
DAOUT
VCC_SENSE
SW
SW
PVIN
PVIN
PVIN
SW
SW
23
22
21
20
9
10
11
12
TJMAX = 125°C, θJA = 38°C/W
EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3815EUFE#PBF LTC3815EUFE#TRPBF 3815 38-Lead (4mm × 6mm) Plastic QFN –40°C to 125°C
LTC3815IUFE#PBF LTC3815IUFE#TRPBF 3815 38-Lead (4mm × 6mm) Plastic QFN –40°C to 125°C
Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
(http://www.linear.com/product/LTC3815#orderinfo)
LTC3815
3
3815fa
For more information www.linear.com/LTC3815
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input Supply Range l2.25 5.5 V
VOUT Output Voltage Programming Range l0.4 72% of VIN V
IQVIN Supply Current
Normal Mode
Standby
Shutdown
VRUN_MSTR > 1V (Note 4)
VRUN_STBY = 0V, VRUN_MSIR > 1V
VRUN_MSTR = 0V, VSDA = VSCL ≥ VIN
5
120
1
8
200
mA
µA
µA
VUVLO VIN Undervoltage Reset
Hysterisis
VIN Rising
VIN Falling
2.05 2.15
0.2
2.25 V
V
IREF Reference Current (Note 10) l99.2
99.5
100
100
100.8
100.5
µA
µA
ΔIREF,LINE Reference Current Line Regulation VIN = 2.5V to 5.5V (Note 10) l0.05 0.2 %/V
ΔVOUT,OFFSET Regulation Accuracy
ΔVOUT,OFFSET = (VCC_SEN – VSS_SEN) – VREF
VREF = 1.5V (Notes 5, 10) l–0.5 0.5 %
ΔVOUT,MARGIN Maximum Margining Range
Set Point Accuracy
Resolution
LSD Step Size
MFR_VOUT_COMMAND = –25% to
25%, VREF = 1.5V (Note 5)
l
–25
–0.5
9
0.1
25
0.5
%
%
Bits
%
NL_VOUT DAC Nonlinearity ±1 LSB
AEA Error Amplifier Open Loop Gain ITH = 1V (Note 5) 80 dB
fBW Error Amp Gain Bandwidth Product (Note 6) 20 MHz
RIN Differential Amplier Input Resistance Measured at VCC_SEN Pin 160 kΩ
tSS Internal Soft-Start Time/VREF External CSS = Float 1 ms/V
ICSLEW CSLEW Pull-Up Current VCSLEW = 0V –10 µA
ILIM SW Valley Current Limit Sourcing (Note 8)
Sinking
l5.5 6.5
–6
7.5 A
A
IRUN_STBY Regulator On Source Current VRUN_STBY = 0V –2.5 µA
VRUN_MSTR Regulator On Threshold (Master Shutdown)
Regulator On Hysterisis
Regulator Power-Down Threshold
Rising Edge
Falling Edge
IQ < 10μA
0.9 1
0.1
0.65
1.1 V
V
V
VRUN_STBY Regulator On Threshold (Standby Mode) 0.7 1 1.2 V
IASEL ASEL Programming Current 10 µA
IPGFD PGFD Programming Current 10 µA
ISS SS Current VSS = 0V 4 5 6 µA
VIH,MARGIN
VIL,MARGIN
MARGIN High Voltage
MARGIN Low Voltage
1.2
0.4
V
V
IWP WP Pin Pull-Up Current WP = 0V 10 µA
SRMARGIN Reference Slew Rate During Margin Change CSLEW = 1nF
CSLEW = OPEN
CSLEW = SVIN
0.1
23
10
%/ms
%/ms
%/µs
tINIT Initialization Time Delay from Power Applied Until
VOUT Ramp Up
1 2 ms
Oscillator and Power Switch
fOSC Oscillator Frequency RT = 25.5k
RT = SVIN
l0.85
0.85
1.0
1.0
1.15
1.15
MHz
MHz
VSYNC SYNC Level High
SYNC Level Low
1.2
0.3
V
V
The l denotes the specifications which apply over the specified operating
junction temperature range, VIN = 3.3V unless otherwise noted. (Note 2)
LTC3815
4
3815fa
For more information www.linear.com/LTC3815
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VMODE Discontinuous Mode Threshold 1 V
tON(MIN) Minimum On-Time 75 ns
tOFF(MIN) Minimum Off-Time 100 ns
RTOP Top Power PMOS On Resistance 35 mΩ
RBOTTOM Bottom Power NMOS On Resistance 20 mΩ
θCLKOUT Relative Phase of CLKOUT MODE/SYNC = 0V 180 Deg
PGOOD
VPGOOD,DEFAULT Default PGOOD Threshold VPGLIM = VIN, VOUT >1V ±8 ±10 ±12 %
VPGOOD,PROGRAM Program PGOOD Threshold VPGLIM/VREF = 0.19, VOUT ≥ 1V
VPGLIM/VREF = 0.38
±6
±13
±10
±30
±9
±17
%
%
ILEAK PGOOD Leakage Current ±5 µA
VOL PGOOD Output Low Voltage IOUT = 3mA 0.1 0.3 V
tPGFD PGOOD Filter Delay PGFD = 0V
PGFD = 0.65V
PGFD = VIN
150
1.0
17
190
1.6
24
250
2.2
32.5
µs
ms
ms
Output Voltage Readback
N Resolution
LSB Step Size
13
0.5
Bits
mV
VF/S Full Scale Output Voltage (Note 9) 16.4 V
VOUT_TUE Total Unadjusted Error l±0.75
±0.5
%
%
tCONVERT Conversion Time 40 ms
Input Voltage Readback
N Resolution
LSB Step Size
13
4
Bits
mV
VF/S Full Scale Input Voltage (Note 9) 131 V
VIN_TUE Total Unadjusted Error l±1.5 %
tCONVERT Conversion Time 40 ms
Output Current Readback
N Resolution
LSB Step Size
13
10
Bits
mA
VF/S Full Scale Output Current ±82 A
IOUT_TUE Total Unadjusted Error ±3 %
tCONVERT Conversion Time 40 ms
Input Current Readback
N Resolution
LSB Step Size
13
10
Bits
mA
VF/S Full Scale Input Current ±82 A
IIN_TUE Total Unadjusted Error ±3 %
tCONVERT Conversion Time 40 ms
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, VIN = 3.3V unless otherwise noted. (Note 2)
LTC3815
5
3815fa
For more information www.linear.com/LTC3815
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, VIN = 3.3V unless otherwise noted. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Temperature Readback
N Resolution
LSB Step Size
9
1
Bits
°C
VF/S Full Scale Temperature ±256 °C
TTUE Total Unadjusted Error ±3 °C
tCONVERT Conversion Time 40 ms
PMBus Interface Parameters
VIH, SDA, SCL Input High Voltage 2.1 V
VIL, SDA, SCL Input Low Voltage 0.8 V
IIH, SDA, SCL Input Leakage Current 0V ≤ VPIN ≤ 5.5V –5 5 µA
VOL, SDA Output Low Voltage (SDA) ISDA = 3mA 0.4 V
VOL, ALERT Output Low Voltage (ALERT) IALERT = 1mA 0.4 V
fSCL Serial Bus Operating Frequency 10 400 kHz
tBUF Bus Free Time Between Stop and Start
Condition
1.3 µs
tHD_SDA Hold Time After (Repeated) Start Condition 0.6 µs
tSU_SDA Repeated Start Condition Setup Time 0.6 µs
tSU_STO Stop Condition Setup Time 0.6 µs
tHD_DAT(OUT) Data Hold Time 300 900 ns
tHD_DAT(IN) Input Data Hold Time 0 ns
tSU_DAT Data Set-Up Time 100 ns
tLOW Clock Low Period 1.3 10000 µs
tHIGH Clock High Period 0.6 µs
tTIMEOUT_SMB Stuck PMBus Timer Measured from last PMBus start
event
30 ms
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3815 is tested under pulsed load conditions such that TJ ≈ TA.
The LTC3815E is guaranteed to meet specifications from 0°C to 85°C
junction temperature. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3815I is guaranteed
over the –40°C to 125°C operating junction temperature range. Note that
the maximum ambient temperature consistent with these specifications
is determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors.
Note 3: The junction temperature (TJ, in °C) is calculated from the ambient
temperature (TA, in °C) and power dissipation (PD, in Watts) according to
the formula:
TJ = TA + (PD • θJA)
where θJA (in °C/W) is the package thermal impedance.
Note 4 : The dynamic input supply current is higher due to power
MOSFET gate charging (QG × fOSC). See applications Information for more
information.
Note 5: The LTC3815 is tested in a feedback loop that servos VFB to a
referenced voltage with the ITH pin forced to a voltage between 0.6V and
1V.
Note 6: Guaranteed by design, not subject to test.
Note 7: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum junction temperature
may impair device reliability or permanently damage the device.
Note 8: The LTC3815 uses valley current mode control so the current
limits specified correspond to the valley of the inductor current waveform.
Maximum load current is higher and equals the valley current limit ILIM
plus one half of the inductor ripple current.
Note 9: The maximum input and output voltage is 5.5V.
Note 10: Total output accuracy is the sum of the tolerances of IREF,
RREF(EXTERNAL), ΔVOUT,OFFSET, and ΔIREF,LINE • ΔVIN.
LTC3815
6
3815fa
For more information www.linear.com/LTC3815
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step
(Discontinuous Mode) Output Margining Load Regulation
Line Regulation Discontinuous Mode Operation
Forced Continuous Mode
Operation
Efficiency vs Load Current Efficiency vs Input Voltage
Load Step
(Forced Continuous Mode)
V
IN
= 3.3V, V
OUT
= 1.8V
f
SW
= 1MHz
CCM Mode
DCM Mode
LOAD CURRENT (A)
0.01
0.1
1
10
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
3815 G01
V
OUT
= 1.0V
CCM Mode
LOAD = 1A, f = 1MHz
LOAD = 6A, f = 1MHz
LOAD = 1A, f = 2MHz
LOAD = 6A, f = 2MHz
INPUT VOLTAGE (V)
2
3
4
5
6
50
60
70
80
90
100
EFFICIENCY (%)
3815 G02
10µs/DIV
VOUT
50mV/DIV
VOUT = 1V
ILOAD = 0A TO 5A
CCM MODE
FRONT PAGE CIRCUIT
ILOAD
5A/DIV
3815 G03
10µs/DIV
VOUT
50mV/DIV
VOUT = 1V
ILOAD = 0A TO 5A
DCM MODE
FRONT PAGE CIRCUIT
ILOAD
5A/DIV
3815 G04
1ms/DIV
MARGIN REGISTERS PRE-LOADED
TO 10% AND –10%
CSLEW = 10pF
MARGIN
2V/DIV
VOUT
200mV/DIV
CSLEW
1V/DIV
3815 G05
V
IN
= 3.3V
LOAD CURRENT (A)
–6
–4
–2
0
2
4
6
–0.20
–0.10
0
0.10
0.20
V
OUT
ERROR (%)
3815 G06
I
OUT
= 6A
CCM MODE
FRONT PAGE CIRCUIT
INPUT VOLTAGE (V)
2
3
4
5
6
–0.20
–0.10
0
0.10
0.20
V
OUT
ERROR (%)
3815 G07
5µs/DIV
VOUT
20mV/DIV
VOUT = 1.8V
ILOAD = 100mA
VMODE = 3.3V
FRONT PAGE CIRCUIT
IL
1A/DIV
3815 G08
1µs/DIV
VOUT
20mV/DIV
VOUT = 1.8V
ILOAD = 100mA
VMODE = 0V
FRONT PAGE CIRCUIT
IL
1A/DIV
3815 G09
LTC3815
7
3815fa
For more information www.linear.com/LTC3815
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency
vs Temperature
Oscillator Frequency vs Input
Voltage
Quiescent Current vs Input
Voltage
Shutdown Current vs Input
Voltage Standby Current vs Input Voltage
Valley Current Limit
vs Input Voltage
Current Sense Threshold
vs ITH Voltage
Valley Current Limit vs
Temperature
INPUT VOLTAGE (V)
2
3
4
5
6
5.6
5.7
5.8
5.9
6.0
6.1
6.2
6.3
6.4
CURRENT LIMIT (A)
3815 G10
ITH VOLTAGE (V)
0
0.2
0.4
0.6
0.8
1.0
1.2
–8
–6
–4
–2
0
2
4
6
8
CURRENT LIMIT (A)
3815 G11
TEMPERATURE (°C)
–50
0
50
100
150
–3
–2
–1
0
1
2
3
FREQUENCY VARIATION (%)
3815 G13
INPUT VOLTAGE (V)
2
3
4
5
6
–4
–3
–2
–1
0
1
2
3
4
FREQUENCY VARIATION (%)
3815 G14
–50°C
25°C
125°C
INPUT VOLTAGE (V)
2
3
4
5
6
0
2
4
6
8
10
SUPPLY CURRENT (mA)
3815 G15
–50°C
25°C
125°C
INPUT VOLTAGE (V)
2
3
4
5
6
0
1
2
3
4
5
SHUTDOWN CURRENT (µA)
3815 G16
–50°C
25°C
125°C
INPUT VOLTAGE (V)
2
3
4
5
6
0
50
100
150
200
STANDBY CURRENT (µA)
3815 G17
R
T
(kΩ)
0
20
40
60
80
100
0.2
1
3
FREQUENCY (MHz)
3815 G18
TEMPERATURE (°C)
–50
0
50
100
150
5.0
5.5
6.0
6.5
7.0
CURRENT LIMIT (A)
3815 G12
Oscillator Frequency vs RT
LTC3815
8
3815fa
For more information www.linear.com/LTC3815
TYPICAL PERFORMANCE CHARACTERISTICS
IREF vs Input Voltage
IOUT Measurement Error vs IOUT IIN Measurement Error vs IIN
IREF vs Temperature
VOUT Measurement Error vs VOUT VOUT Command INL VOUT Command DNL
V
IN
= 5V
OUTPUT VOLTAGE (V)
0
1
2
3
4
5
–1.0
–0.5
0
0.5
1.0
MEASUREMENT ERROR (%)
3815 G19
3.5V to 1.0V
CCM MODE
FRONT PAGE CIRCUIT
OUTPUT CURRENT (A)
–2
0
2
4
6
–0.10
–0.05
0
0.05
0.10
MEASUREMENT ERROR (A)
3815 G22
3.5V TO 1.8V
CCM MODE
FRONT PAGE CIRCUIT
I
OUT
= 0 TO 6A
INPUT CURRENT (A)
0
0.5
1
1.5
2
2.5
3
–0.10
–0.05
0
0.05
0.10
MEASUREMENT ERROR (A)
3815 G23
INPUT VOLTAGE (V)
2
3
4
5
6
–0.5
–0.4
–0.3
–0.1
0
MEASUREMENT ERROR (%)
3815 G25
TEMPERATURE (°C)
–50
0
50
100
150
–0.2
–0.1
0
0.1
0.2
I
REF
VARIATION (%)
3815 G26
INPUT VOLTAGE (V)
2
3
4
5
6
–0.50
–0.25
0
0.25
0.50
I
REF
VARIATION (%)
3815 G27
MFR_VOUT_COMMAND VALUE (%)
–25
–12.5
0
12.5
25
–0.50
–0.25
0
0.25
0.50
INL (LSB)
3815 G20
MFR_VOUT_COMMAND VALUE (%)
–25
–12.5
0
12.5
25
–0.50
–0.25
0
0.25
0.50
DNL (LSB)
3815 G21
IIN, IOUT Measurement Error vs
Temperature, VIN and Frequency
VIN Measurement Error vs VIN
V
IN
= 2.5V, 1MHz
V
IN
= 3.3V, 1MHz
V
IN
= 5V, 1MHz
V
IN
= 3.3V, 2MHz
V
IN
= 5V, 2MHz
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
–4
–2
0
2
4
MEASUREMENT ERROR (%)
3815 G24
LTC3815
9
3815fa
For more information www.linear.com/LTC3815
TYPICAL PERFORMANCE CHARACTERISTICS
Switch On-Resistance
vs Input Voltage
Switch On-Resistance
vs Temperature
Switch Leakage
vs Temperature, Main Switch
Switch Leakage vs Temperature,
Synchronous Switch
Dynamic Supply Current
vs Input Voltage
Normal Start-Up Start-Up Into Pre-Biased Output VOUT Short and Recovery
500µs/DIV
RUN
2V/DIV
VOUT
0.5V/DIV
VOUT = 1V
MODE = 0
FRONT PAGE CIRCUIT
IL
1A/DIV
PGOOD
2V/DIV
3815 G27
500µs/DIV
RUN
2V/DIV
VOUT
0.5V/DIV
VOUT = 1V
MODE = 0
FRONT PAGE CIRCUIT
IL
1A/DIV
PGOOD
2V/DIV
3815 G28
500µs/DIV
VOUT
0.5V/DIV
IL
5A/DIV
3815 G29
SYNCHRONOUS SWITCH
MAIN SWITCH
INPUT VOLTAGE (v)
2
3
4
5
6
0
10
20
30
40
50
60
R
DS(ON)
(mΩ)
3815 G30
SYNCHRONOUS SWITCH
MAIN SWITCH
TEMPERATURE (°C)
–50
0
50
100
150
0
10
20
30
40
50
60
R
DS(ON)
(mΩ)
3815 G31
TEMPERATURE (°C)
–50
0
50
100
150
0
1
3
4
5
6
8
9
10
SWITCH LEAKAGE (µA)
3815 G32
1MHz
2MHz
INPUT VOLTAGE (v)
2
3
4
5
6
0
7
13
20
27
33
40
SUPPLY CURRENT (mA)
3815 G34
TEMPERATURE (°C)
–50
0
50
100
150
0
2
3
5
6
8
9
11
12
SWITCH LEAKAGE (µA)
3815 G33
Minimum VIN vs Load, VOUT and
Frequency
V
OUT
=1.2V, 1MHz
V
OUT
=1.2V, 2MHz
V
OUT
=1.8V, 1MHz
V
OUT
=1.8V, 2MHz
LOAD CURRENT (A)
0
1
2
3
4
5
6
1.5
2.0
2.5
3.0
3.5
MINIMUM V
IN
(V)
3815 G35
LTC3815
10
3815fa
For more information www.linear.com/LTC3815
PIN FUNCTIONS
RT (Pin 1): Oscillator Frequency. This pin provides two
modes of setting the constant switching frequency. Con-
nect a resistor from RT pin to ground to program the
switching frequency from 400kHz to 3MHz. Tying this
pin to VIN enables the internal 1MHz oscillator frequency.
ASEL (Pin 2): Serial Bus Address Configuration Input.
Connect a ±1% resistor from this pin to ground in order
to select the 3 LSBs of the serial bus interface address.
(see Table 5).
MARGIN (Pin 3): Fast Margining Select. In the default
mode when this pin is floating, the reference voltage margin
offset is changed with MFR_VOUT_COMMAND through
the serial interface. If this pin is pulled high, the reference
voltage margin offset is immediately ramped to the value
pre-stored in the MFR_VOUT_MARGIN_HIGH register.
If this pin is pulled low, the reference voltage margin
offset is immediately ramped to the value pre-stored in
MFR_VOUT_MARGIN_LOW register.
WP (Pin 4): Write Protect Pin. Pulling this pin high disables
writes to MFR_VOUT_COMMAND, MFR_VOUT_MARGIN_
HIGH, and MFR_VOUT_MARGIN_LOW. When this pin is
grounded, there are no write restrictions.
ALERT (Pin 5): Open Drain Digital Output. Connect the
system SMBALERT interrupt signal to this pin. A pull-up
resistor is required in the application.
CLKOUT (Pin 6): Clock Out Signal for 2-Phase Operation.
The phase of this clock is 180° with respect to the internal
clock. Signal swing is from VIN to GND.
SDA (Pin 7): Serial Bus Data Input and Output. A pull-up
resistor is required in the application.
SCL (Pin 8): Serial Bus Clock Input. A pull-up resistor is
required in the application.
MODE/SYNC (Pin 9): Mode Selection and External Clock
Input. If this pin is tied to VIN, discontinuous mode is
enabled at light loads. If this pin is connected to ground,
forced continuous mode is selected. Driving the MODE/
SYNC pin with an external clock signal will synchronize
the switching frequency to the applied frequency. There
is an internal 20k resistor to ground on this pin.
SW (Pins 10, 11, 13, 14, 18, 19, 21, 22, 23): Switching
Node. This pin connects to the drains of the internal main
and synchronous power MOSFET switches.
NC (Pins 12, 20): No Connection. Can be connected to
ground or left open. This pin does not connect to any
internal circuitry.
PVIN (Pins 15-17): Power Input Supply. PVIN connects to
the source of the internal P-channel power MOSFET. This
pin is independent of VIN and may be connected to the
same voltage or to a lower voltage supply.
PGOOD (Pin 29): Power Good. This open-drain output
is pulled down to SGND on start-up and while the output
voltage is outside the power good window set by the PGLIM
pin. If the output voltage increases and stays inside the
power good window for more than the delay programmed
at the PGFD pin, the PGOOD pin is released. If the output
voltage leaves the power good window for more than 16
switching cycles the PGOOD pin is pulled down.
VIN (Pin 24): Signal Input Supply. Decouple this pin to
SGND with a capacitor. This pin powers the internal control
circuitry. This pin is independent of PVIN and may be con-
nected to the same voltage or to a higher supply voltage.
PGFD (Pin 25): PGOOD Deglitch Filter Delay Select. The
voltage at this pin sets the delay that the output must be
in regulation before the PGOOD flag is asserted. The delay
can be programmed to one of seven discrete values where
tDELAY = 200μs • 2N (N = 0 to 5, 7).
RUN_MSTR (Pin 26): Master Run. The power up threshold
is set at 1V. When forced below 0.4V, all circuitry is shut
off and the IC is put into a low current shutdown mode
(IQ < 1μA).
RUN_STBY (Pin 27): Standby Mode Off. The regulator
power up threshold is set at 1V. When forced below 0.4V,
only the voltage regulator is shut off while the ADC and
PMBus interface are still active. When shut off, the ADC
refresh rate is reduced to 1Hz and the IC quiescent current
is reduced to 120μA. This pin sources 2.5μA. Do not pull
up with a low impedance (<10kΩ).
LTC3815
11
3815fa
For more information www.linear.com/LTC3815
PIN FUNCTIONS
CSLEW (Pin 28): Slew Rate Control. Add a capacitor to
program the VOUT transition slew rate during margining.
The slew rate is equal to 0.1% per ms per nF slew rate
capacitance. With a 1nF capacitor, the slew rate is 0.1%/
ms. Tw o default slew rates are also available when this
pin is open or shorted to VIN.
TRACK/SS (Pin 30): Tracking/Soft-Start Input. For soft-
start, a capacitor to ground at this pin sets the ramp rate
of the output voltage (approximately 5V/sec/μF). For
coincident tracking, connect this pin to a resistive divider
between the voltage to be tracked and ground.
VSS_SENSE (Pin 31): VOUT Negative Terminal Voltage Sense.
The internal unity gain differential gain amplifier connects
to the VOUT negative terminal through this pin. Tying this
pin to the VIN pin forces the IC to operate as a slave in a
two-phase configuration.
VCC_SENSE (Pin 32): VOUT Positive Terminal Voltage Sense.
The internal unity gain differential gain amplifier connects
to the VOUT positive terminal through this pin.
DAOUT (Pin 33): Differential Amplifier Output.
ITH (Pin 34): Error Amplifier Output and Switching Regu-
lator Compensation Point. The current comparator’s trip
threshold is linearly proportional to this voltage. Use an RC
network between the ITH pin and the VFB pin to compensate
the feedback loop for optimum transient response.
FB (Pin 35): Error Amplifier Input. FB will be servoed to
the REF pin voltage plus or minus any margining offset
set through the serial interface.
REF (Pin 36): Reference Input and Programming Pin. The
voltage at this pin is the default reference that the output
is regulated to. The PMBus interface allows margining
around this default voltage by up to ±25%. This pin can
be driven by an external voltage or can be programmed
with a resistor to ground. An internal accurate low drift
100μA current source times the external resistor sets the
reference voltage.
PGLIM (Pin 37): PGOOD Threshold Programming Pin.
The voltage difference ΔV between this pin and SGND
sets the VOUT overvoltage threshold to VREF +0.4 • ΔV and
the undervoltage threshold to VREF –0.4 • ΔV. Tying this
pin to VIN sets the threshold to its default value of ±10%.
SGND (Pin 38): Signal Ground. Reference setting resistor,
slew rate control capacitor, and frequency setting resistor
connections should return to SGND. For optimum load
regulation, the SGND pin should be kelvin-connected to
the PCB location between the negative terminals of the
output capacitors and should not be connected through
the PGND plane.
PGND (Exposed Pad Pin 39): Power Ground. Must be
soldered to PCB for electrical connection and rated thermal
performance.
LTC3815
12
3815fa
For more information www.linear.com/LTC3815
BLOCK DIAGRAM
6A
–6A
0.4
REF REF 10µA
PGFD PGOOD
REF+∆V/2.5
REF–∆V/2.5
±25%
TO EA
FAULT
STATUS
ON/OFF
10µA
REF+∆V/2.5
∆V
+
–
VIN
VOUT
TEMP
IOUT
IIN
100µA
RREF
PVIN
PVIN
VIN
L
VIN
SW
PGND
TG ON
FORCED
CONTINUOUS
ICMP
MODE/SYNC
RUN_STBY
TRACK/SS
PWM ON/OFF
1.0V
80k
80k
80k80k
REF
SGND
TEMP
2.5µA
5µA
1.0V
0.4V
VOUT
COUT
CIN
RUV/OV
PGLIM
–
+
PPG
+
–
NPG
+
–
OVP
+–
IREV
PGOOD
FILTER
LOGIC
+
+
–EA
+
–
–
+
–
+
CHIP ON/OFF
DAMP
SDA
SCL
ALERT
WP
ASEL
MARGIN
CLKOUT
RT
CSLEW
+
++
–
+
+
+
CIN
QT
QB
+
+
CURRENT
SENSE
S
RQ
IIN, IOUT
VON OST
VIN
VSS_SENSE
VCC_SENSE
RUN_MSTR
VIN
FB
DAOUT
DAOUT
RC1
RC2
RC3
CC3
CC2
CC1
ITH
CSS
ITON
tON =
V
ON
ITON
(0.64pF)
DAC
A/D
RAM/
COUNTER
PMBus
INTERFACE
MUX
TEMPERATURE
SENSE
OSC
PLL
SYNC
1k
OFF
3815 BD
LTC3815
13
3815fa
For more information www.linear.com/LTC3815
OPERATION
Table 1. LTC3815 Supported PMBus Commands
PMBUS
COMMAND
CODE COMMAND NAME
PMBUS-DEFINED SMBUS
TRANSACTION TYPE SCALING
DATA
BYTES DESCRIPTION
0x01 OPERATION R/W Byte 1 On/Off Command and Set Output to MFR_VOUT_
MARGIN_HIGH or MFR_VOUT_MARGIN_LOW value
0x20 VOUT_MODE Read Byte 1 or 2 Read Data Format for MFR_VOUT_COMMAND
Hard-wired to VID format (0x3E), not writable
0x79 STATUS_WORD R/W Word 2 Read Fault Status: Communication fault, PGOOD, VIN
UV, VOUT OV, overtemperature, VIN fault, VOUT fault
Individual faults are reset by writing a '1' to the bit
position of the fault to be reset
0x88 READ_VIN R Word 4mV/Bit 2 Read VIN
0x89 READ_IIN R Word 10mA/Bit 2 Read IIN
0x8B READ_VOUT R Word 0.5mV/Bit 2 Read VOUT
0x8C READ_IOUT R Word 10mA/Bit 2 Read IOUT
0x8D READ_TEMPERATURE_1 R Word 1°C/Bit 2 Read Die Temperature (°C)
0X98 PMBUS_REVISION Read Byte 1 or 2 Read PMBus Revision = 0x22 for Rev 1.2
0xD7 MFR_IOUT_PEAK R/W Word 10mA/Bit 2 Read highest output current observed since last restart
Write will restart peak monitor routine
0xDD MFR_VOUT_PEAK R/W Word 0.5mV/Bit 2 Read highest output voltage observed since last restart
Write will restart peak monitor routine
0xDE MFR_VIN_PEAK R/W Word 4mV/Bit 2 Read highest input voltage observed since last restart
Write will restart peak monitor routine
0xDF MFR_TEMPERATURE1_
PEAK
R/W Word 1°C/Bit 2 Read highest temperature observed since last restart
Write will restart peak monitor routine
0xE1 MFR_IIN_PEAK R/W Word 10mA/Bit 2 Read highest input current observed since last restart
Write will restart peak monitor routine
0xE3 MFR_CLEAR_PEAKS W Byte 0, 1 or 2 Clear all peak values, write data is ignored
0xE5 MFR_VOUT_MARGIN_HIGH R/W Word 0.1%/Bit 2 Same format as MFR_VOUT_COMMAND
0xE7 MFR_SPECIAL_ID R Word 2 Read 16-bit value (0x8000) that GUI will recognize as
LTC3815
0xE8 MFR_VOUT_COMMAND R/W Word 0.1%/Bit 2 VOUT Margining Command ±25% range at 0.1%/bit in
2's compliment. Defaults to 0% at power-up
0xED MFR_VOUT_MARGIN_LOW R/W Word 0.1%/Bit 2 Same format as MFR_VOUT_COMMAND
0xFA MFR_RAIL_ADDRESS R/W Byte 1 or 2 Set Common PMBus Address (B6-B0), Clear B7 to
enable. Set B7 to disable. Valid addresses are 0x00 to
0x7F.
0xFD MFR_RESET W Byte 0, 1 or 2 Reset PMBus Interface and ADC to Power-On State
Write data is ignored
LTC3815
14
3815fa
For more information www.linear.com/LTC3815
OPERATION
Main Control Loop
The LTC3815 is a 6A current mode monolithic step-down
regulator with PMBus Interface. The accurate 100µA cur-
rent source on the REF pin allows the user to use just one
external resistor to program the output voltage. In normal
operation, the internal top power MOSFET is turned on
for a fixed interval determined by a one-shot timer, OST.
When the top power MOSFET turns off, the bottom power
MOSFET turns on until the current comparator, ICMP, trips,
restarting the one-shot timer and initiating the next cycle.
Inductor current is determined by sensing the voltage drop
across the bottom power MOSFET’s VDS. The voltage on
the ITH pin sets the comparator threshold corresponding
to the inductor valley current. The error amplifier, EA,
adjusts this ITH voltage by comparing the feedback signal,
VFB, from the output voltage with that of voltage on the
REF pin. If the load current increases, it causes a drop in
the feedback voltage relative to the internal reference. The
ITH voltage then rises until the average inductor current
matches that of the load current.
At low load current, the inductor current can drop to zero
and become negative. This is detected by current reversal
comparator, IREV, which then shuts off the bottom power
MOSFET, resulting in discontinuous operation. Both power
MOSFETs will remain off with the output capacitor sup-
plying the load current until the ITH voltage rises above
the zero current level (~0.6V) to initiate another cycle.
Discontinuous mode operation is disabled by tying the
MODE pin to VIN, which forces continuous synchronous
operation regardless of output load.
The operating frequency is determined by the value of the
RT resistor, which programs the current for the internal
oscillator. The internal phase-lock loop servos the switching
regulator on-time to track the internal oscillator to force
constant switching frequency. If an external clock signal is
detected on the MODE/SYNC pin, the phase-lock loop will
servo the on-time to track the external clock signal instead.
VOUT Margining
The LTC3815 has an internal 9-bit DAC that provides up
to ±25% adjustment at 0.1%/bit resolution around the
reference voltage set at the REF pin. The digital offset value
is changed with the MFR_VOUT_COMMAND command
through the PMBus interface. When a change in the
reference is detected, the reference is ramped (0.1%/step)
from its current value to the new value at a rate set by the
capacitor value connected to the CSLEW pin, thus providing
programmable slew rate of the VOUT transition. To eliminate
the latency of the PMBus transaction when faster changes
are required, the LTC3815 can be pre-loaded with two
additional offsets with the MFR_VOUT_MARGIN_HIGH
and MFR_VOUT_MARGIN_LOW commands. The refer-
ence offset can then be switched between any of these
three register values with the 3-state MARGIN pin. When
using the MARGIN pin, the latency of the VOUT transition
is limited only by the chosen CSLEW capacitor and the loop
bandwidth of the power supply. Changes to these registers
are prevented by pulling the write protect (WP) pin high.
Telemetry Readback
The LTC3815 has an integrated 13-bit ADC that monitors
and performs conversions on the input and output voltage,
input and output current, and die temperature. The values
are refreshed at a 25Hz rate and are readable through the
PMBus interface.
A peak monitor is also available for each of these telemetry
measurements to provide that highest value measured
since the start of the monitor. The monitor is reset by the
MFR_CLEAR_PEAKS command, writing to the individual
peak register, or de-asserting RUN_MSTR.
Output Voltage Tracking and Soft-Start
The LTC3815 allows the user to program its output volt-
age ramp rate by means of the TRACK/SS pin. An internal
5µA pulls up the TRACK/SS pin to VIN. Putting an external
capacitor on TRACK/SS enables soft starting the output to
prevent current surge on the input supply. If no capacitor
is connected or TRACK/SS pin is connected to VIN, the
ramp rate defaults to 1.1 volts/ms. For output tracking ap-
plications, TRACK/SS can be externally driven by another
voltage source. For TRACK/SS less than the output voltage
reference (set by the IREF resistor and margin register), the
TRACK/SS voltage will override the reference input to the
error amplifier, thus regulating the feedback voltage to that
of TRACK/SS pin. During this start-up time, the LTC3815
will operate in discontinuous mode. When TRACK/SS is
LTC3815
15
3815fa
For more information www.linear.com/LTC3815
above the reference voltage, tracking is disabled and the
feedback voltage will regulate to the reference voltage. Ei-
ther concurrent or ratiometric tracking can be implemented
by connecting the track voltage to either the IREF pin or the
TRACK/SS pin as described in the applications section.
Output Power Good
When the LTC3815’s output voltage is within the its power
good window of the regulation point, the output voltage is
good and the PGOOD pin is pulled high with an external
resistor. Otherwise, an internal open-drain pull-down
device (40Ω) will pull the PGOOD pin low. This window
is programmed by the PGLIM pin by connecting it to a
resistive divider to the REF pin. This allows the the PGOOD
window to be programmed as a percentage of the output
voltage reference. If PGLIM is tied to VIN, the PGOOD
window defaults to ±10%.
The PGOOD Filter Delay pin provides a user program-
mable delay from output voltage good to the rising edge
of PGOOD. A wide range of delays from 200μs to 25ms
can be user programmed by a configuration resistor
connected to the PGFD pin. To prevent unwanted PGOOD
glitches during transients or dynamic VOUT changes, the
LTC3815’s PGOOD falling edge includes a blanking delay
of approximately 16 switching cycles.
Continuous operation is forced during OV and UV condition
except during start-up when the TRACK/SS pin is ramping
up to the internal reference voltage.
Master Shutdown and Standby Modes
There are three different ways to shut down the LTC3815:
RUN_MSTR pin, RUN_STBY pin, and the ON bit of the
OPERATION command.
Pulling the RUN_MSTR pin low forces the LTC3815 into a
master shutdown state, turning off both power MOSFETs,
the internal control circuitry, the ADC converter, and the
PMBus interface. Also, all data written to the internal
registers, such as the margin register, will be reset to the
power-on state. Supply current in this mode is typically
less than 1μA.
OPERATION
Pulling RUN_STBY pin low or clearing the ON bit in the
OPERATION register puts the LTC3815 in a standby mode
where the regulator is off but the ADC and PMBus are still
active. In standby mode the LTC3815 will still respond to
the PMBus host but will only refresh the telemetry data
at 1Hz rate instead of 25Hz. In standby mode the supply
current is 120μA. Exiting standy mode with the rising
edge of the ON bit resets all faults and the ALERT pin. All
data written to the internal registers, such as the margin
registers, is not affected by this shutdown mode, so when
RUN_STBY is re-asserted, the VOUT will power back up
to the last value written prior to shutdown (as long as no
change to the margin registers or MARGIN pin was made
during shutdown).
For the switcher to run and provide output regulation all
three must be asserted, i.e. RUN_MSTR and RUN_STBY
pins high and OPERATION ON bit set. At power on or
master shutdown, the ON bit is automatically set in the
OPERATION register. Pulling RUN_MSTR low overrides
the standby controls and puts the LTC3815 in master
shutdown.
Table 2. Shutdown Modes
INPUT CONDITIONS ON/OFF STATES
IQ
RUN_MSTR RUN_STBY ON BIT VOUT PMBus ADC
High X 0 OFF ON 1Hz Refresh
(see Note)
120μA
Low X X OFF OFF OFF <1μA
High High 1 ON ON 25Hz
Refresh
5mA
High Low X OFF ON 1Hz Refresh
(see Note)
120μA
Note: Only VIN, VOUT and temperature telemetry are refreshed.
Short Circuit Protection
The LTC3815 has a precision cycle-by-cycle current limit
to prevent inductor saturation in a short circuit condition.
The valley of the inductor current is guaranteed to not
exceed 6A ±10%. The maximum cycle-by-cycle inductor
current is therefore limited to 6A + 10% + ΔIL, where ΔIL
depends on the inductor valley and operating frequency but
is typically ~2A. Internal control circuitry also guarantees
smooth recovery with no output voltage overshoot once
the short is removed.
LTC3815
16
3815fa
For more information www.linear.com/LTC3815
OPERATION
25MHz Error Amplifier and Remote Sense Differential
Amplifier
The LTC3815 utilizes a 25MHz error amplifier and dif-
ferential amplifier for fast and accurate output voltage
regulation. The operational amplifier style error amplifier
allows precision tuning of the system poles and zeros for
optimal transient response. The remote sense differential
amplifier allows output voltage sensing at the point-of-load
and thus provides very accurate regulation of the output
voltage and telemetry readback regardless of load current.
The sensed output voltage is available at the DAOUT pin
(referenced to SGND). This pin is typically connected to
the FB pin which is the error amplifier “-“ input.
Using Separate VIN/PVIN Supplies
The LTC3815 has two supply pins: VIN that supplies the IC
control circuitry and PVIN that supplies the driver and power
switches. VIN requires a minimum of 2.25V to guarantee
proper operation, while PVIN may be able to supply power
to the load at lower voltages if the load demands do not
exceed the weaker capability of the power switches at the
lower voltage. To maximize the lower operating range of
the supply voltage, two separate supplies can be used – a
VIN supply that is > 2.25V and rated at 10mA or higher
and a PVIN supply, rated for the load, that can be run all
the way into dropout. Each supply pin has an individual
undervoltage-lockout comparator to shut off the supply
when its respective voltage is too low to guarantee proper
operation.
Thermal Warning and Thermal Shutdown
The LTC3815 has two levels of thermal thresholds
and two levels of responses. When the internal die
temperature exceeds 150°C, the overtemperature bit in
the STATUS_WORD is set and the ALERT pin pulls low
to alert the PMBus master. If the temperature continues
to rise and exceeds 170°C, the LTC3815 shuts down all
circuitry, including output regulation, and will no longer
respond to the PMBus host. Both temperature monitors
have about 20°C of hysteresis before the overtemperature
condition is cleared. The temperature warning bit in the
STATUS_WORD is latched and remains set until the host
clears it.
2-Phase Operation
For output loads that demand more than 6A of current, two
LTC3815’s can be paralleled to run out-of-phase to provide
up to 12A output current. To configure a 2-phase system,
one LTC3815 will act as a master and the other a slave
(see the schematic in the Typical Applications section).
Connecting the VSS_SENSE pin to VIN puts the LTC3815 in
slave mode by tri-stating its error amplifier and remote
sense amplifier. The ITH pins of both IC’s are connected
together so that both are regulating the inductor current
based on the master’s ITH voltage. The master’s CLKOUT
pin is a clock waveform that is 180° out-of-phase to its
internal clock. This CLKOUT can be connected to the
MODE/SYNC pin of the slave to force the slave’s PLL to
lock onto this clock input and run out-of-phase with the
master. The RUN_STBY pins are also connected together
as a handshaking signal between the two so that both will
shutoff together in case of a fault in only one of the phases,
such as overtemperature condition.
See the Applications Information section for further details
regarding 2-phase operation.
Discontinuous/Forced Continuous Operation
The LTC3815 can operate in one of two modes selectable
with the MODE/SYNC pin: discontinuous mode or forced
continuous mode. Connecting the MODE/SYNC pin to
VIN selects discontinuous mode. Discontinuous mode is
selected when high efficiency at very light loads is desired.
In this mode, when the inductor current reverses, the bot-
tom MOSFET turns off to minimize the efficiency loss due
to reverse current flow. This reduces the conduction loss
and slightly improves the efficiency. As the load reduces,
the driver switching frequency drops in proportion to the
load, which further improves efficiency by minimizing
gate charge losses.
Forcing the MODE/SYNC pin low enables forced continuous
mode operation. In forced continuous mode, the bottom
MOSFET is always on when the top MOSFET is off, allowing
the inductor current to reverse at low currents. This mode
is less efficient due to conduction and switching losses,
but has the advantage of better transient response at low
currents, constant frequency operation, and the ability to
maintain regulation when sinking current.
LTC3815
17
3815fa
For more information www.linear.com/LTC3815
OPERATION
During soft-start, the LTC3815 forces the controller to
operate in discontinuous mode until the soft-start volt-
age reaches the internal reference to guarantee smooth
startup into a precharged output capacitor. During margin-
ing transitions and overvoltage conditions, however, the
LTC3815 always operates in forced continuous mode to
allow the switcher to sink current.
SERIAL INTERFACE
The LTC3815 serial interface is a PMBus compliant slave
device and can operate at any frequency between 10kHz
and 400kHz. The address is configurable using an external
resistor. In addition the LTC3815 always responds to the
global broadcast address of 0x5A or 0x5B (7 bit). The
serial interface supports the following protocols defined
in the PMBus specifications: 1) send command, 2) write
byte, 3) write word, 4) group, 5) read byte and 6) read
word. The PMBus write operations are not acted upon
until a complete valid message is received by the LTC3815
including the STOP bit.
Communication Failure
Attempts to access unsupported commands or writing
invalid data to supported commands will result in a CML
fault. The CML bit is set in the STATUS_WORD command
and the ALERT pin is pulled low.
Device Addressing
The LTC3815 offers four different types of addressing over
the PMBus interface, specifically: 1) global, 2) device, 3)
rail addressing and 4) alert response address (ARA).
Global addressing provides a means of the PMBus master
to address all LTC3815 devices on the bus. The LTC3815
global address is fixed 0x5A or 0x5B (7 bit) or 0xB4 or
0xB6 (8 bit) and cannot be disabled.
Device addressing provides the standard means of the
PMBus master communicating with a single instance of an
LTC3815. The value of the device address is set by the ASEL
configuration pin. Rail addressing provides a means of the
PMBus master addressing a set of channels connected
to the same output rail, simultaneously. This is similar to
global addressing, however, the PMBus address can be
dynamically assigned by using the MFR_RAIL_ADDRESS
command. It is recommended that rail addressing should
be limited to command write operations.
All four means of PMBus addressing require the user to
employ disciplined planning to avoid addressing conflicts.
Fault Status
The STATUS_WORD and ALERT pin provide fault status
information of the LTC3815 to the host.
Bus Timeout Failure
The LTC3815 implements a timeout feature to avoid hang-
ing the serial interface. The data packet timer begins at the
first START event before the device address write byte.
Data packet information must be completed within 25ms
or the LTC3815 will tri-state the bus and ignore the given
data packet. Data packet information includes the device
address byte write, command byte, repeat start event
(if a read operation), device address byte read (if a read
operation), and all data bytes.
The user is encouraged to use as high a clock rate as
possible to maintain efficient data packet transfer between
all devices sharing the serial bus interface. The LTC3815
supports the full PMBus frequency range from 10kHz to
400kHz.
Similarity Between PMBus, SMBus and I2C 2-Wire
Interface
The PMBus 2-wire interface is an incremental extension
of the SMBus. SMBus is built upon I2C with some minor
differences in timing, DC parameters and protocol. The
PMBus/SMBus protocols are more robust than simple I2C
byte commands because PMBus/SMBus provide time-outs
to prevent bus hangs and optional packet error checking
(PEC) to ensure data integrity. In general, a master device
that can be configured for I2C communication can be
used for PMBus communication with little or no change
to hardware or firmware. Repeat start (restart) is not sup-
ported by all I2C controllers but is required for SMBus/
PMBus reads. If a general purpose I2C controller is used,
check that repeat start is supported.
LTC3815
18
3815fa
For more information www.linear.com/LTC3815
OPERATION
For a description of the minor extensions and exceptions
PMBus makes to SMBus, refer to PMBus Specification
Part 1 Revision 1.1: Paragraph 5: Transport.
For a description of the differences between SMBus and
I2C, refer to System Management Bus (SMBus) Speci-
fication Version 2.0: Appendix B—Differences Between
SMBus and I2C.
PMBus Serial Interface
The LTC3815 communicates with a host (master) using the
standard PMBus serial bus interface. The Timing Diagram,
Figure 1, shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines.
The LTC3815 is a slave device. The master can com-
municate with the LTC3815 using the following formats:
n Master transmitter, slave receiver
n Master receiver, slave transmitter
The following PMBus protocols are supported:
n Write Byte, Write Word, Send Byte
n Read Byte, Read Word
n Alert Response Address
Figures 3 through 6 illustrate the aforementioned PMBus
protocols. All transactions support GCP (group command
protocol).
Figure 2 is a key to the protocol diagrams in this section.
SDA
SCL
tHD(STA) tHD(DAT)
tSU(STA) tSU(STO)
tSU(DAT)
tLOW
tHD(SDA) tSP tBUF
START
CONDITION
STOP
CONDITION
REPEATED START
CONDITION
START
CONDITION
tr
tftr
tf
tHIGH 3815 F01
SLAVE ADDRESS DATA BYTEWr A A P
3815 F02
S
7
S START CONDITION
Sr REPEATED START CONDITION
Rd READ (BIT VALUE OF 1)
Wr WRITE (BIT VALUE OF 0)
x SHOWN UNDER A FIELD INDICATES THAT THAT
FIELD IS REQUIRED TO HAVE THE VALUE OF x
A ACKNOWLEDGE (THIS BIT POSITION MAY BE 0
FOR AN ACK OR 1 FOR A NACK)
P STOP CONDITION
PEC PACKET ERROR CODE
MASTER TO SLAVE
SLAVE TO MASTER
CONTINUATION OF PROTOCOL
81 1 1
x x
11
...
Figure 1. Timing Diagram
Figure 2. PMBus Packet Protocol Diagram Element Key
LTC3815
19
3815fa
For more information www.linear.com/LTC3815
OPERATION
A value shown below a field in the following figures is a
mandatory value for that field.
The data formats implemented by PMBus are:
n Master transmitter transmits to slave receiver. The
transfer direction in this case is not changed.
n Master reads slave immediately after the first byte. At
the moment of the first acknowledgment (provided by
the slave receiver) the master transmitter becomes a
master receiver and the slave receiver becomes a slave
transmitter.
n Combined format. During a change of direction within
a transfer, the master repeats both a start condition
and the slave address but with the R/W bit reversed.
In this case, the master receiver terminates the transfer
by generating a NACK on the last byte of the transfer
and a STOP condition.
Examples of these formats are shown in Figures 3 through 7.
SLAVE ADDRESS COMMAND CODE DATA BYTEWr A A A P
3815 F03
S
7 8 81 1 1 1 11
SLAVE ADDRESS COMMAND CODE DATA BYTE LOWWr A A A P
3815 F04
S
7 8 8 1
DATA BYTE HIGH
81 1 1 1 11
A
Figure 3. Write Byte Protocol
Figure 4. Write Word Protocol
Figure 5. Send Byte Protocol
SLAVE ADDRESS Wr A A P
3815 F05
S
7 81 1 1 11
COMMAND CODE
SLAVE ADDRESS COMMAND CODE SLAVE ADDRESSWr A A A P
3815 F06
S
7 8 7 1
DATA BYTE LOW
8
DATA BYTE HIGH
811 1 1
Sr
1 1
1
11
A
1
Rd A
SLAVE ADDRESS COMMAND CODE SLAVE ADDRESSWr A A Sr P
3815 F07
S
7 8 8 11
DATA BYTE
8 1
1
1 1 1 11 1
ARd A
Figure 6. Read Word Protocol
Figure 7. Read Byte Protocol
LTC3815
20
3815fa
For more information www.linear.com/LTC3815
APPLICATIONS INFORMATION
The basic LTC3815 application circuit is shown in Figure 8.
Operating Frequency
Selection of the operating frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low out-
put ripple voltage. The operating frequency of the LTC3815
is determined by an external resistor that is connected
between the RT pin and ground. The value of the resistor
sets the ramp current that is used to charge and discharge
an internal timing capacitor within the oscillator and can
be calculated by using the following equation:
RT=1.15 • 10
11
fOSC
( )
1.11 Ω
Frequencies as high as 3MHz are possible, as long as the
minimum on-time requirement is met (see next section).
Tying the RT pin to VIN sets the default internal operating
frequency to 1MHz ±15%.
The LTC3815’s internal oscillator can be synchronized to an
external frequency by applying a square wave clock signal
to the MODE/SYNC pin. During synchronization, the top
switch turn-on is locked to the rising edge of the external
frequency source. The synchronization frequency range is
300kHz to 3MHz. During synchronization, discontinuous
operation is disabled.
The internal PLL has a synchronization range of ±30%
around its programmed frequency. Therefore, during
external clock synchronization be sure that the external
clock frequency is within this ±30% range of the RT pro-
grammed frequency.
When using the RT pin to program the
oscillator frequency,
a square wave clock that is running 180° out-of-phase with
the internal oscillator is available at the CLKOUT pin for
connection to a second LTC3815 for 2-phase operation
(see the 2-Phase section).
Figure 8. 1.8V, 6A Step-Down Regulator
VIN
2.25V TO 5.5V
VOUT
1.8V
6A
PGOOD
WP
SW
LTC3815
MODE/SYNC
RUN_MSTR
RUN_STBY
CLKOUT
PGLIM
RT
MARGIN
VCC_SENSE
VSS_SENSE
REF
ASEL PGFD
DAOUT
VFB
ITH
SCL, SDA, ALERT
PVIN VIN
PMBUS
CSS
15nF
CSLEW
1nF
RT
11.8k, 1%
RASEL RPGFD
3815 F08
L
300nH
RC2
10k
RC1
1k
CC2
1nF
COUT
100µF
×2
CC1
47pF
CIN
22µF
×4
SS/TRACK
CSLEW
RREF1
14.3k
0.5%
RREF2
3.7k
0.5%
LTC3815
21
3815fa
For more information www.linear.com/LTC3815
APPLICATIONS INFORMATION
Minimum Off-Time and Minimum On-Time
Considerations
The minimum off-time, tOFF(MIN), is the smallest amount
of time that the LTC3815 is capable of turning on the bot-
tom power MOSFET, tripping the current comparator and
turning the power MOSFET back off. This time is generally
about 100ns. The minimum off-time limit imposes a maxi-
mum duty cycle of tON/(tON + tOFF(MIN)). If the maximum
duty cycle is reached, due to a dropping input voltage for
example, then the output will drop out of regulation. The
minimum input voltage to avoid dropout is:
V
IN(MIN) =VOUT •
t
ON
+t
OFF(MIN)
tON
Conversely, the minimum on-time is the smallest dura-
tion of time in which the top power MOSFET can be in
its “on” state. This time is typically 75ns. In continuous
mode operation, the minimum on-time limit imposes a
minimum duty cycle of:
DCMIN = f • tON(MIN)
where tON(MIN) is the minimum on-time. As the equation
shows, reducing the operating frequency will alleviate the
minimum duty cycle constraint.
In the cases where the minimum duty cycle is surpassed,
the output voltage will still remain in regulation, but the
switching frequency will decrease from its programmed
value. This is an acceptable result in many applications, so
this constraint may not be of critical importance in most
cases. High switching frequencies may be used in the
design without any fear of severe consequences. As the
sections on inductor and capacitor selection show, high
switching frequencies allow the use of smaller board com-
ponents, thus reducing the size of the application circuit.
Inductor Selection
Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple current:
∆IL=VOUT
f •L • 1−VOUT
V
IN
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a trade-off between
component size, efficiency and operating frequency.
A reasonable starting point is to choose a ripple current that
is about 30-40% of IOUT(MAX). This is especially important
at low VOUT operation where VOUT is 1.8V or below. Care
must be given to choose an inductance value that will gen-
erate a big enough current ripple so that the chip’s valley
current comparator has enough signal-to-noise ratio to
force constant switching frequency. Meanwhile, also note
that the largest ripple current occurs at the highest VIN. To
guarantee that ripple current does not exceed a specified
maximum, the inductance should be chosen according to:
L=VOUT
f • ∆IL(MAX)
• 1−VOUT
VIN(MAX)
Once the value for L is known, the type of inductor must
be selected. Actual core loss is independent of core size
for a fixed inductor value, but is very dependent on the
inductance selected. As the inductance or frequency in-
creases, core losses decrease. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.
Ferrite designs have very low core losses and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard”, which means that LTC3815
inductance collapses abruptly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
LTC3815
22
3815fa
For more information www.linear.com/LTC3815
mainly depends on the price versus size requirements
and any radiated field/EMI requirements. New designs for
surface mount inductors are available from Toko, Vishay,
NEC/Tokin, Cooper, TDK, Würth Elektronik and Coilcraft.
Refer to Table 3 for more details.
Table 3. Representative Surface Mount Inductors
INDUCTANCE
(μH)
DCR
(mΩ)
MAX
CURRENT (A)
DIMENSIONS
(mm)
HEIGHT
(mm)
Coilcraft XAL6030 Series
0.18 1.59 39 6.56 × 3.36 3.1
0.33 2.30 30 6.56 × 3.36 3.1
0.56 3.01 29 6.56 × 3.36 3.1
Würth 744316 Series
0.18 1.25 25 5.5 × 5.2 4
0.33 1.75 20 5.5 × 5.2 4
0.47 2.75 16 5.5 × 5.2 4
0.68 4.00 13.5 5.5 × 5.2 4
CIN and COUT Selection
The input capacitance, CIN, is needed to filter the trapezoi-
dal wave current at the drain of the top power MOSFET.
To prevent large voltage transients from occurring, a low
ESR input capacitor sized for the maximum RMS current
should be used. The maximum RMS current is given by:
IRMS ≅IOUT(MAX)
VOUT
V
IN
V
IN
VOUT
−1
This formula has a maximum at VIN = 2VOUT, where
IRMS ≅ IOUT/2.
This simple worst-case condition is commonly used for
design because even significant deviations do not offer
much relief. Note that ripple current ratings from capacitor
manufacturers are often based on only 2000 hours of life
which makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. For low input voltage
applications, sufficient bulk input capacitance is needed
to minimize transient effects during output load changes.
APPLICATIONS INFORMATION
The selection of COUT is determined by the effective series
resistance (ESR) that is required to minimize voltage ripple
and load step transients as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient response. The output ripple, ΔVOUT, is
determined by:
∆VOUT < ∆IL
1
8 • f • COUT
+ESR
The output ripple is highest at maximum input voltage
since ΔIL increases with input voltage. Multiple capaci-
tors placed in parallel may be needed to meet the ESR
and RMS current handling requirements. Dry tantalum,
special polymer, aluminum electrolytic, and ceramic
capacitors are all available in surface mount packages.
Special polymer capacitors are very low ESR but have
lower capacitance density than other types. Tantalum
capacitors have the highest capacitance density but it is
important to only use types that have been surge tested
for use in switching power supplies. Aluminum electrolytic
capacitors have significantly higher ESR, but can be used
in cost-sensitive applications provided that consideration
is given to ripple current ratings and long-term reliability.
Ceramic capacitors have excellent low ESR characteristics
and small footprints. Their relatively low value of bulk
capacitance may require multiples in parallel.
Using Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now be-
coming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
VIN input. At best, this ringing can couple to the output and
be mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause
a voltage spike at VIN large enough to damage the part.
LTC3815
23
3815fa
For more information www.linear.com/LTC3815
When choosing the input and output ceramic capacitors,
choose the X5R and X7R dielectric formulations. These
dielectrics have the best temperature and voltage char-
acteristics of all the ceramics for a given value and size.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor
must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation and the
output capacitor size. Typically, 3 to 4 cycles are required
to respond to a load step, but only in the first cycle does
the output drop linearly. The output droop, VDROOP, is
usually about 2 to 3 times the linear drop of the first cycle.
Thus, a good place to start with the output capacitor value
is approximately:
COUT ≈2.5
∆I
OUT
fO• V
DROOP
More capacitance may be required depending on the duty
cycle and load step requirements.
In most applications, the input capacitor is merely required
to supply high frequency bypassing, since the impedance to
the supply is very low. A 22µF ceramic capacitor is usually
enough for these conditions. Place this input capacitor as
close to the PVIN pins as possible.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in load current.
When a load step occurs, VOUT immediately shifts by an
amount equal to ΔILOAD • ESR, where ESR is the effective
series resistance of COUT. ΔILOAD also begins to charge or
discharge COUT generating a feedback error signal used by
the regulator to return VOUT to its LTC3815 steady-state
value. During this recovery time, VOUT can be monitored
for overshoot or ringing that would indicate a stability
problem.
APPLICATIONS INFORMATION
The OPTI-LOOP compensation allows the transient
response to be optimized for a wide range of output
capacitors. The availability of the ITH pin not only allows
optimization of the control loop behavior but also provides
a DC-coupled and AC-filtered closed-loop response test
point. The DC step, rise time and settling at this test point
truly reflects the closed-loop response. Assuming a pre-
dominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin.
The ITH external components (RC1, CC1, CC2) shown in
the Figure 8 circuit provides an adequate starting point
for most applications. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because their various types and values determine the
loop feedback factor gain and phase. An output current
pulse of 20% to 100% of full load current having a rise
time of 1µs to 10µs will produce output voltage and ITH
pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop.
In some applications, a more severe transient can be caused
by switching in loads with large (>10µF) input capacitors.
The discharged input capacitors are effectively put in paral-
lel with COUT, causing a rapid drop in VOUT. No regulator
can deliver enough current to prevent this problem, if
the switch connecting the load has low resistance and is
driven quickly. The solution is to limit the turn-on speed of
the load switch driver. A Hot Swap controller is designed
specifically for this purpose and usually incorporates
current limiting, short-circuit protection and soft-starting.
Calculating Compensation Values
If the “trial and error” approach described in the previous
section doesn’t result in adequate transient performance,
the procedure described in this section can be used to
calculate more precise compensation component values
to achieve a desired bandwidth and phase margin. This
procedure is also helpful if the output capacitor type is
LTC3815
24
3815fa
For more information www.linear.com/LTC3815
APPLICATIONS INFORMATION
very different than the one specified in the application
circuits or if a Type 3 compensation network is required.
A Type 3 compensation network includes the additional
components RC3 and CC3 shown in Figure 9.
1) Choose the crossover frequency. For best performance,
the crossover frequency should be as high as possible
but not greater than about 20% of the switching fre-
quency.
2) Plot Gain and Phase of the modulator and output filter.
The modulator and output filter is the portion of the
loop from the error amp output (ITH) to the regulator
output (VOUT). To do this, insert a 10Ω to 50Ω resistor
between the output capacitor and the VCCSEN pin (this
is R7 on the DC2065 demo board). Then use a network
analyzer to inject an AC signal across this resistor and
plot the Gain and Phase. If a network analyzer is not
available, a close approximation can obtained with a
PSPICE simulator using the LTC3815 power supply
model shown in Figure 9. The error amplifier EA can
be modeled as an ideal op amp (for crossover frequen-
cies < 200kHz) and the inductor as a voltage controlled
current source. The gain/phase plot should look similar
to Figure 10.
3) Calculate the component values. Once the gain and
phase are known, note the gain (GAIN, in dB) and phase
(PHASE, in degrees) at the crossover frequency. The
compensation components can then be calculated to
make the loop gain (VCCSEN to VOUT) equal to 0dB and
the phase margin equal to 60° at this frequency. Use
the equations below to calculate the component values.
Normally the Type 2 network will provide the required
phase margin. If not, use the Type 3 equations.
4) Add the calculated components to the LTC3815 circuit
and check the load step response. If not adequate, the
components values may need to be tweaked further or
recalculated with a lower crossover frequency until the
desired response is obtained.
3815 F09
+
–
EA
VCCSEN
VREF
ITH
RESR
gm = 12 • VITH
*TYPE 3 ONLY
RC2
CC2
CC1
RC3*CC3*
RC1
+
RLOAD
Figure 9. PSPICE Model of a LTC3815 Current Mode Regulator
FREQUENCY (Hz)
GAIN (dB)
PHASE (DEG)
3815 F10
0 0
–90
–180
GAIN
PHASE
Figure 10. Transfer Function of Buck Modulator
LTC3815
25
3815fa
For more information www.linear.com/LTC3815
APPLICATIONS INFORMATION
RC1 = A convenient resistor value ~1kΩ.
f = chosen crossover frequency
G = 10(GAIN/20) (this converts GAIN in dB to G in absolute
gain)
Type 2 Loop:
k=tan BOOST
2+45°
CC1 =1
2π• f • G • K • RC1
CC2 =CC1 K2−1
( )
RC2 =K
2π• f • CC2
RB=V
REF(RC1)
V
OUT
−V
REF
Type 3 Loop:
k=tan BOOST
4+45°
CC1 =1
2π• f • G • RC1
CC2 =CC1 K−1
( )
RC2 =K
2π• f • CC2
RC3 =RC1
K−1
C3 =1
2πf K • RC3
RB=V
REF(RC1)
VOUT −V
REF
Output Voltage Programming
The output voltage is set by an external resistor according
to the following equation:
VOUT = 100µA • RREF,
where RREF is the total resistance between REF pin and
SGND.
Programming PGOOD Threshold and Filter Delay
The upper and lower Power Good threshold default to
±10% when the PGLIM pin is tied to VIN (see Figure 11a).
However, if a narrower or wider window is desired, these
windows can be programmed to any desired value in the
range of 5% to 40%.
The PGOOD upper/lower threshold is programmed by
replacing the single resistor on the REF pin with a resistor
divider as follows (see Figure 11b):
Reference Voltage = 100µA • (R1+R2)
PGOOD Window = ±40% • R2/(R1+R2)
The PGOOD window is always centered on the DAC adjusted
reference voltage, thus the center will move to the new
reference voltage when margined up or down.
The falling PGOOD (power good to power bad) is filtered
and delayed by 16 clock cycles, thus giving the loop 16
switching cycles to recover from the power bad condition
before pulling the PGOOD pin low.
The
rising PGOOD (power bad to power good) filter delay is
user programmable by a configuration resistor at the PGFD
pin and is programmable to one of 7 possible delays from
Figure 11a. PGOOD Window Set to ±10% Default
LTC3815
SVIN
RREF = R1 + R2
REF
3815 F11a
PGLIM
LTC3815
SVIN
R1
REF
3815 F11b
R2
PGLIM
Figure 11b. PGOOD Window Set By R1/R2
Figure 11. PGOOD Window
LTC3815
26
3815fa
For more information www.linear.com/LTC3815
APPLICATIONS INFORMATION
200μs to 25.6ms as shown in Table 4. Minimum delay of
200μs can be set by grounding the PGLIM pin and maxi-
mum delay of 25.6ms can be set by tying PGLIM to SVIN.
The PGFD pin is sampled only at power on and at initialization
after the rising edge of RUN_MSTR, RUN_STBY or the
OPERATION register ON bit. Changes to PGFD will not
take effect until one of these events occur.
Table 4. PGFD Resistor Selection
PGFD RESISTOR PGOOD DELAY
0Ω 200μs
28kΩ 400μs
46.4kΩ 800μs
64.9kΩ 1.6ms
84.5kΩ 3.2ms
113kΩ 6.4ms
Open or short to VIN 25.6ms
Address Selection (ASEL pin)
The LTC3815 slave address is selected by the ASEL pin.
The upper four bits of the address are hardwired internally
to 0100 and the lower three bits are programmed by a
resistor connected between the ASEL and SGND (see
Table 5). This allows up to 7 different LTC3815’s on
a single board. The LTC3815 will also respond to the
Global Address 0x5A and the 7-bit address stored in the
MFR_RAIL_ADDRESS register.
The ASEL pin is sampled only at power on and at initialization
after the rising edge of RUN_MSTR, RUN_STBY or OP-
ERATION register ON bit. Changes to ASEL will not take
affect until one of these events occur.
Table 5. ASEL Resistor Selection
ASEL RESISTOR SLAVE ADDRESS
0Ω 0100000
28kΩ 0100001
46.4kΩ 0100010
64.9kΩ 0100011
84.5kΩ 0100100
102kΩ 0100101
Open or short to VIN 0100111
Margining/CSLEW Selection/Margin Pin
Writing to the MFR_VOUT_COMMAND register via the
PMBus allows the adjustment of the VOUT reference up to
±25% around the voltage at the REF pin. This voltage can
be adjusted in 0.1% increments by writing the appropriate
9-bit two’s complement value to the register. The MFR_
VOUT_MARGIN_HIGH and MFR_VOUT_MARGIN_LOW
register can also be used to adjust the VOUT reference
value by selecting the desired register with the MARGIN
pin or the OPERATION command as specified in Table 6.
Table 6. VOUT Margining with the MARGIN Pin and OPERATION
Command
MARGIN
PIN
OPERATION
BITS [5:4]
VOUT REFERENCEBIT 5 BIT 4
<0.4V X X = [1 + MFR_VOUT_MARGIN_LOW(%) ] • VREF
>1.2V X X = [1 + MFR_VOUT_MARGIN_HIGH(%) ] • VREF
Hi-Z 0 0 = [1 + MFR_VOUT_COMMAND(%) ] • VREF
Hi-Z 0 1 = [1 + MFR_VOUT_MARGIN_LOW(%) ] • VREF
Hi-Z 1 0 = [1 + MFR_VOUT_MARGIN_HIGH(%) ] • VREF
Hi-Z 1* 1* = [1 + MFR_VOUT_COMMAND(%) ] • VREF
* Setting both bits 4 and 5 high at the same time is illegal and will be
ignored.
Pre-loading the registers and using the MARGIN pin
provides fast margining by eliminating the latency inher-
ent to serial bus communication. Once the registers are
loaded the output voltage change is limited only by the
loop bandwidth and the slew rate capacitor (CSLEW).
The CSLEW pin provides slew rate limiting during reference
voltage changes. When the reference is changed by either
the MARGIN pin, OPERATION command, or writing new
values to the register, the LTC3815 counts up or down from
the current value in the register to the new value at 0.1%
per step. The step duration is set by the CSLEW capacitor.
The slew rate during the transition is thus:
SR =
0.1
C
SLEW
(nF)+0.0043 % / ms
If the CSLEW pin is left open, SR defaults to 23%/ms. The
slew rate limit can be disabled if desired by tying the CSLEW
pin to VIN. When disabled, the reference is immediately
stepped from old value to new value in <100ns.
LTC3815
27
3815fa
For more information www.linear.com/LTC3815
APPLICATIONS INFORMATION
Soft-Start
After the LTC3815 is turned on or power applied and
finishes its ~500µs initialization sequence, the chip enters
a soft start-up state. The type of soft startup behavior is
set by the TRACK/SS pin:
1. Tying TRACK/SS to VIN selects the internal soft-start
circuit. This circuit ramps the output voltage to the final
value within 1ms.
2. If a longer soft-start period is desired, it can be set ex-
ternally with a capacitor on the TRACK/SS pin as shown
in Figure 10. The TRACK/SS pin reduces the value of
the internal reference at FB until TRACK/SS charges
above the REF pin voltage. The external soft-start dura-
tion can be calculated by using the following formula:
tSS =
V
REF
• C
SS
5µA
3. The TRACK/SS pin can be used to track the output
voltage of another supply.
Regardless of either internal or external soft-start state,
the MODE pin is ignored and soft-start will always be in
discontinuous mode until SS voltage reaches the pro-
grammed VOUT reference voltage for the first time.
TRACKING
Using the TRACK/SS or the REF pin, two types of tracking/
sequencing can be used for the LTC3815 (see Figure 12).
For ratiometric tracking, VOUT will always track a ratio of
the input tracking voltage. In coincident tracking, VOUT
will track a ratio of the input tracking voltage until VOUT ≥
VREF, then VOUT is regulated to VREF. Also, with ratiometric
tracking, the VOUT can be adjusted with the margin com-
mands and MARGIN pin relative to the tracking voltage.
With coincident tracking, VOUT can only be adjusted relative
to VREF when VMASTER ≥ VREF.
For coincident tracking, be aware that the PGOOD window
is always centered around the DAC adjusted REF pin volt-
age, not the TRACK/SS pin voltage.
Ratiometric Tracking
To implement ratiometric tracking (Figure 13a and Figure
13b) the controlling voltage, VMASTER is connected to the
REF pin. This source must be able to sink the 100µA IREF
current. Using the REF pin allows VOUT to be adjusted
with the margining commands and MARGIN pin. For
VMASTER > VSLAVE connect VMASTER to the REF pin thru a
resistive divider. The relationship of VMASTER to VSLAVE is:
V
MASTER =VSLAVE • 1+
R1
R2
−R1• 100µA
Note that the 100µA IREF current requires VMASTER > R1
• 100µA before VSLAVE starts rising above 0V. Choose a
low value for R1 to minimize this offset.
For VMASTER < VSLAVE connect VMASTER directly to REF
pin. The ratio of VMASTER to VSLAVE is now:
V
MASTER
V
SLAVE
=
R1
R1+R2
Coincident Tracking
To implement coincident tracking with VMASTER ≥ VSLAVE
(Figure 13c) connect VMASTER to the TRACK/SS pin directly
or with a resistive divider:
V
MASTER
V
SLAVE
=
R1
R1+R2
VOUT will follow VMASTER (or a ratio of it as set by R1/R2)
until VMASTER > VREF at which time VOUT is regulated to VREF.
DDR Mode
The LTC3815 can both sink and source current if the MODE/
SYNC pin is set to forced continuous mode. Current sink-
ing is limited to –6A+ΔIL/2. An external reference voltage
connected to the REF pin can be used to set the output
voltage. The output voltage can be margined by ±25% in
the same way as a resistor programmed reference.
LTC3815
28
3815fa
For more information www.linear.com/LTC3815
APPLICATIONS INFORMATION
TIME
(12b) Ratiometric Tracking
VOUT1
VOUT2
OUTPUT VOLTAGE
TIME 3815 F10
(12a) Coincident Tracking
VOUT1
VOUT2
OUTPUT VOLTAGE
3815 F11b
LTC3815
VMASTER REF DAOUT
FB
SS/TRACK
R1
R2
3815 F11b
LTC3815
R2
R1
VMASTER REF DAOUT
FB
SS/TRACK
3815 F11c
LTC3815
R2
R1
VMASTER
REF DAOUT
FB
SS/TRACK
Figure 13a. Slave IC Circuit for Ratiometric
Tracking and VMASTER ≤ VSLAVE
Figure 13b. Slave IC Circuit for Ratiometric
Tracking and VMASTER ≥ VSLAVE
Figure 13c. Slave IC Circuit for Coincident
Tracking and VMASTER ≥ VSLAVE
Figure 12. Tw o Different Modes of Output Voltage Tracking
Figure 13. Slave IC Circuits
LTC3815
29
3815fa
For more information www.linear.com/LTC3815
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses: VIN quiescent current and I2R losses. The VIN
quiescent current loss dominates the efficiency loss at
very low load currents whereas the I2R loss dominates
the efficiency loss at medium to high load currents. In a
typical efficiency plot, the efficiency curve at very low load
currents can be misleading since the actual power lost is
usually of no consequence.
1. The VIN quiescent current is due to two components: the
DC bias current as given in the Electrical Characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
low to high to low again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is the current
out of VIN due to gate charge, and it is typically larger
than the DC bias current. Both the DC bias and gate
charge losses are proportional to VIN; thus, their effects
will be more pronounced at higher supply voltages.
2. I2R losses are calculated from the resistances of the
internal switches, RSW
, and external inductor, RL. In
continuous mode the average output current flowing
through inductor L is chopped between the main switch
and the synchronous switch. Thus, the series resistance
looking into the SW pin is a function of both top and
bottom MOSFET RDS(ON) and the duty cycle (DC) as
follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Character-
istics curves. To obtain I2R losses, simply add RSW to
RL and multiply the result by the square of the average
output current.
Other losses including CIN and COUT ESR dissipative
losses and inductor core losses generally account for
less than 2% of the total loss.
Thermal Considerations
In most applications, the LTC3815 does not dissipate
much heat due to its high efficiency.
However, in applications where the LTC3815 is running
at high ambient temperature with low supply voltage and
high duty cycles, such as in dropout, the heat dissipated
may exceed the maximum junction temperature of the part.
If the junction temperature reaches approximately 160°C,
both power switches will be turned off and the SW node
will become high impedance.
To prevent the LTC3815 from exceeding the maximum
junction temperature, some thermal analysis is required.
The temperature rise is given by:
TRISE = (PD)(θJA)
where PD is the power dissipated by the regulator and
θJA is the thermal resistance from the junction of the die
to the ambient temperature. The junction temperature,
TJ, is given by:
TJ = TA + TRISE
where TA is the ambient temperature.
As an example, consider the case when the LTC3815 is in
dropout at an input voltage of 3.3V with a load current of
6A at an ambient temperature of 70°C. From the Typical
Performance Characteristics graph of Switch Resistance,
the RDS(ON) resistance of the P-channel switch is 0.035Ω.
Therefore, power dissipated by the part is:
PD = (IOUT)2 • RDS(ON) = 1.26W
For the QFN package, the θJA is 38°C/W.
APPLICATIONS INFORMATION
LTC3815
30
3815fa
For more information www.linear.com/LTC3815
Therefore, the junction temperature of the regulator op-
erating at 70°C ambient temperature is approximately:
TJ = 1.26W • 38°C/W + 70°C = 118°C
We can safely assume that the actual junction temperature
will not exceed the absolute maximum junction temperature
of 125°C. The actual die temperature can be verified with
the READ_TEMPERATURE_1 command after the power
supply is built and operating.
Note that for very low input voltage, the junction tempera-
ture will be higher due to increased switch resistance,
RDS(ON). It is not recommended to use full load current
for high ambient temperature and low input voltage.
To maximize the thermal performance of the LTC3815 the
exposed pad should be soldered to a ground plane. See
the PCB Layout Board Checklist.
2-Phase Operation
Using two LTC3815’s as a 2-phase regulator to supply
12A loads was discussed on Page 16. A few more details
need to be brought to the user’s attention to ensure cor-
rect operation:
1) PMBus connection and READ_IIN/IOUT: Although the
2-phase regulator will operate fine with the PMBus
interface connected to the master only, the READ_IOUT
and READ_IIN measured values will only be available
for the phase(s) that are connected. Since each phase’s
LTC3815 supplies half the load in a 2-phase converter,
the value read (if from the master only) needs to be
doubled to obtain the total IOUT or IIN value. Because
of slight differences in tracking between phases due
to IC and inductor tolerances, a more accurate reading
will be obtained by connecting to both phases so that
total IOUT and IIN can be computed by summing each
phase’s contribution.
2) Slave PGOOD/ALERT status and margining: When the
master and slave are monitoring the same output, it is
sufficient to monitor the master’s PGOOD and ALERT
pins only. The PGOOD/ALERT pins from both master
and slave can also be wire OR’ed if desired. However, if
the output voltage is margined with the PMBus interface,
the PGOOD/ALERT status of the slave will only be valid
if the slave knows what the new margined reference
is, i.e. the margin change needs to be sent to both the
master and the slave. This can be done easily by using
the MFR_RAIL_ADDRESS to assign the same rail ad-
dress to both the master and slave so that the margin
change can be done with a single write. Be aware that
PMBus reads from a common address need to be done
separately to avoid bus contentions.
3) Using the Master’s CLKOUT: The CLKOUT pin provides
an 180° out-of-phase clock that can be connected to
the slaves MODE/SYNC pin as a simple way to run the
phases out-of-phase with each other. However, be
aware that the master’s CLKOUT pin only provides this
out-of-phase clock when the master is using its internal
oscillator programmed from the RT pin. If the master
is externally clocked, the slave’s anti-phase clock will
need to be obtained from another source.
APPLICATIONS INFORMATION
LTC3815
31
3815fa
For more information www.linear.com/LTC3815
APPLICATIONS INFORMATION
Design Example
As a design example, consider using the LTC3815 in an
application with the following specifications:
VIN = 2.25V to 5.5V, VOUT = 1.8V, IOUT(MAX) = 6A, IOUT(MIN)
= 200mA, f = 2MHz.
Efficiency is important at both high and low load current,
so discontinuous operation will be utilized.
First, calculate the timing resistor:
RT=1.15 • 10
11
Hz
2 • 106
( )
1.11 =11.7k
Next, calculate the inductor value for about 30% ripple
current at maximum VIN:
L=
1.8V
2MHz • 2A
• 1–
1.8V
5.5V
=0.303µH
Using a standard value of 0.3µH inductor results in a
maximum ripple current of:
∆IL=1.8V
2MHz • 0.3µH
• 1– 1.8V
5.5V
=2.02A
COUT will be selected based on the ESR that is required
to satisfy the output voltage ripple requirement and the
bulk capacitance needed for loop stability. For this design,
a 150µF (or 47µF plus 100µF) ceramic capacitor is used
with a X5R or X7R dielectric.
Assuming worst-case conditions of VIN = 2VOUT, CIN should
be selected for a maximum current rating of:
IRMS =6A • 1.8V
3.6V •3.6V
1.8V – 1
=3ARMS
Decoupling PVIN with four 22µF capacitors is adequate
for most applications.
The value of RREF can now be determined by solving the
following equation.
RREF =
1.8V
100µA =18k
A value of 18k, 0.5% will be selected for RREF.
Finally, define the soft start-up time choosing the proper
value for the capacitor and the resistor connected to
TRACK/SS. If we set minimum tSS = 5ms, the following
equation can be solved:
CSS =
5µA • 5ms
1.8V
=13.9nF
The standard value of 15nF guarantees the minimum soft-
start up time of 5ms.
Figure 10 shows the schematic for this design example.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3815:
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the SGND pin at one point which is then connected
to the PGND pin close to the LTC3815.
2. Connect the (+) terminal of the input capacitor(s), CIN,
as close as possible to the PVIN pin, and the (–) terminal
as close as possible to the exposed pad, PGND. This
capacitor provides the AC current into the internal power
MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
4. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power components. Connect the copper areas to PGND
(exposed pad) for best performance
5. Connect the remote sense pins, VCC_SENSE and
VSS_SENSE, directly to the point where maximum VOUT
accuracy is desired. The two traces should be routed
as close together as possible.
LTC3815
32
3815fa
For more information www.linear.com/LTC3815
APPLICATIONS INFORMATION
VIN
SDA
* CONNECT MODE PIN TO 3.3V WHEN POWERING
THE LTC3815 FROM THE DC1613 3.3V SUPPLY.
3815 F12
10k
ISOLATED 3.3V
SDA
SCL
LT C
CONTROLLER
HEADER
TO LTC DC1613
USB TO I2C/SMBus/PMBus
CONTROLLER
SCL
WP SGND
LTC3815
2.25V TO 5.5V
VIN MODE
MODE
VIN*
VIN*
SDA
SCL
WP SGND
LTC3815
10k
Figure 14. LT C Controller Connection
CONNECTING THE USB TO THE I2C/SMBus/PMBus
CONTROLLER TO THE LTC3815 IN SYSTEM
The LT C USB to I2C/SMBus/PMBus controller can be
interfaced to the LTC3815 on the user’s board for pro-
gramming, telemetry and system debug. The controller,
when used in conjunction with LTpowerPlay, provides a
powerful way to debug an entire power system.
Figure 14 illustrates the application schematic for power-
ing, programming and communication with one or more
LTC3815s via the LT C I2C/SMBus/PMBus controller
regardless of whether or not system power is present. If
system power is not present, the LTC3815 can be pow-
ered directly from the DC1613's 3.3V supply. Since the
current sourcing ability of this 3.3V supply is limited, the
LTC3815 should be lightly loaded (<10mA) and operating
in discontinuous mode (MODE/SYNC tied to 3.3V).
In addition any device sharing the I2C bus connections
with the LTC3815 should not have body diodes between
the SDA/SCL pins and their respective VDD node because
this will interfere with bus communication in the absence
of system power.
LTC3815
33
3815fa
For more information www.linear.com/LTC3815
APPLICATIONS INFORMATION
LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL
POWER
LTpowerPlay is a powerful Windows-based development
environment that supports Linear Technology power sys-
tem management ICs including the LTC3815. The software
supports a variety of different tasks. LTpowerPlay can be
used to evaluate Linear Technology ICs by connecting to
a demo board or the user application. LTpowerPlay can
also be used in an offline mode (with no hardware pres-
ent) in order to build multiple IC configuration files that
can be saved and reloaded at a later time. LTpowerPlay
provides unprecedented diagnostic and debug features.
It becomes a valuable diagnostic tool during board bring-
up to program or tweak the power system or to diagnose
power issues when bring up rails. LTpowerPlay utilizes
Linear Technology’s USB-to-I2C/SMBus/PMBus controller
to communication with one of the many potential targets
including the DC1590B-A/DC1590B-B demo board, the
DC1709A socketed programming board, or a customer
target system. The software also provides an automatic
update feature to keep the revisions current with the latest
set of device drivers and documentation. A great deal of con-
text sensitive help is available with LTpowerPlay along with
several tutorial demos. Complete information is available at
http://www.linear.com/ltpowerplay.
Figure 15. LTpowerPlay
LTC3815
34
3815fa
For more information www.linear.com/LTC3815
PMBus
COMMAND DETAILS
MFR_RESET
This command provides a means by which the user can
perform a reset of the LTC3815. All latched faults (ALERT
and status register) and register (telemetry, margin, etc)
contents will be reset to a power-on condition by this
command. VOUT will remain in regulation but may change
due to the reset of the margin registers. ASEL and PGFD
config resistors are re-measured.
This write-only command accepts zero, one, or two data
bytes but ignores them.
MFR_RAIL_ADDRESS
The MFR_RAIL_ADDRESS command allows all devices
to share a common address, such as all devices attached
to a single power supply rail. The desired 7-bit address
value is written to the 7 bits of the data byte.
The MSB (bit B7) must be set low to enable communication
using the MFR_RAIL_ADDRESS address. Setting this bit
disables this address.
1Hz rate to minimize supply current. Either RUN_STBY pin
or ON bit can be cleared/deasserted to put the LTC3815
into this standy mode. The ON bit is automatically reset
to ON after a master shutdown (RUN_MSTR = 0V), power
cycle, or MFR_RESET command.
The MARGIN_LOW/HIGH bits command the VOUT reference
to the offset value stored in either the MFR_VOUT_
MARGIN_HIGH or MFR_VOUT_MARGIN_LOW, resp. at
the slew rate set by the CSLEW capacitor. These bits are
identical in function to margin high/low from the MARGIN
pin. However, the MARGIN pin has precedence over the
MARGIN_LOW/HIGH bits when there is a conflict. Cycling
the RUN_STBY pin has no affect on the margin bits and
thus when re-asserting RUN_STBY, VOUT will return to
the state it was in prior to the shutdown.
Margin high (ignore faults) and margin low (ignore faults)
operations are not supported by the LTC3815.
This command has one data byte. It will accept one or two
but ignore the second byte.
Table 7. Supported OPERATION Command Register Values
ACTION VALUE
Turn off immediately 0x00
Turn on 0x80
Margin Low 0x98
Margin High 0xA8
VOUT_MODE
VOUT_MODE command specifies the formatting for
reading output voltage. The data byte always reads 0x3E
for VID data format and cannot be changed. Attempts to
write to VOUT_MODE will set a CML fault.
This read-only command has one data byte.
MFR_VOUT_COMMAND
The MFR_VOUT_COMMAND consists of a value (%) used
to offset the output reference voltage at the REF pin. The
CSLEW capacitor sets the slew rate limit of the output volt-
age if this command is modified while the output is active
and in a steady-state condition.
The user should only perform command writes to this
address. If a read is performed from this address and
the rail devices do not respond with EXACTLY the same
value, the LTC3815 will detect bus contention and set a
CML communications fault.
This command accepts one or two data bytes but the
second is ignored.
OPERATION
The OPERATION command is used to turn the unit on/off
and for margining the output voltage.
The ON bit has the same function as the RUN_STBY pin,
i.e. clearing it turns off the output voltage with PMBus
interface still active and telemetry data refreshed at a slower
Figure 16. MFR_RAIL_ADDRESS Data Byte
3815 F14
B7 B0
7-BIT ADDRESS
DISABLE
CLEAR B7 TO ENABLE RAIL ADDRESS
LTC3815
35
3815fa
For more information www.linear.com/LTC3815
PMBus
COMMAND DETAILS
This command has two data bytes and is formatted as a
9-bit 2’s complement number with 0.1%/bit scaling.
The range of MFR_VOUT_COMMAND value is limited to
±25%.
Do not attempt to write values outside of this range or
unpredictable behavior may result. Writes to this register
are inhibited when the WP pin is high.
MFR_ VOUT_MARGIN_LOW
The MFR_VOUT_MARGIN_LOW command loads the
LTC3815 with the value to which the output is changed, in
percent, when the OPERATION command is set to margin
low or the fast margining pin, MARGIN, is pulled below
0.4V. Slew rate limiting is same as MFR_VOUT_COMMAND.
This command has two data bytes and is formatted as a
9-bit 2’s complement number with 0.1%/bit scaling.
The range of MFR_VOUT_MARGIN_LOW value is limited
to ±25%. There is no restriction on the value relative to
VOUT_COMMAND and MFR_VOUT_MARGIN_HIGH, i.e.
the value is not required to be lower.
Do not attempt to write values outside of this range or
unpredictable behavior may result. Writes to this register
are inhibited when the WP pin is high.
MFR_VOUT_MARGIN_HIGH
The MFR_VOUT_MARGIN_LOW command loads the
LTC3815 with the value to which the output is changed, in
percent, when the OPERATION command is set to margin
high or the fast margining pin, MARGIN, is pulled above
1.1V. Slew rate limiting is same as MFR_VOUT_COMMAND.
This command has two data bytes and is formatted as a
9-bit 2’s complement number with 0.1%/bit scaling.
The range of MFR_VOUT_MARGIN_HIGH value is limited
to ±25%. There is no restriction on the value relative to
MFR_VOUT_COMMAND and MFR_VOUT_MARGIN_LOW,
i.e. the value is not required to be higher.
Do not attempt to write values outside of this range or
unpredictable behavior may result. Writes to this register
are inhibited when the WP pin is high.
PMBus_REVISION
The PMBUS_REVISION
command indicates the revision of
the PMBus to which the device is compliant. The LTC3815
is PMBus Version 1.2 compliant in both Part I and Part II.
This read-only command has one data byte.
MFR_SPECIAL_ID
The 16-bit word representing the part name and revision.
The MSB equals 0x80 and denotes the part is an LTC3815.
The LSB is adjustable by the manufacturer.
This read-only command has 2 data bytes.
MFR_CLEAR_PEAKS
The MFR_CLEAR_PEAKS command clears the MFR_*_
PEAK data values and restarts the peak monitor routine.
This write-only command requires no data bytes, but will
accept (and ignore) up to two.
STATUS_WORD
The STATUS_WORD command returns two bytes of
information with a summary of the unit’s fault condition.
See Table 8 for a list of the status bits that are supported
and the conditions in which each bit is set. Certain bits
when set in the STATUS_WORD also cause the ALERT
pin to be asserted.
Writing a "1" to a particular bit in the status word will at-
tempt to reset that fault in the status word and the ALERT
pin. If the fault is still present the status word bit and
ALERT will remain asserted. If the ALERT has previously
been cleared by an ARA message, the ALERT will be re-
asserted. If the fault is no longer present, the ALERT pin
will be de-asserted and the fault bit in the status word
will be cleared.
All bits in the status word are also cleared by toggling the
RUN_MSTR pin or the ON bit in OPERATION. The bit will
immediately be set again if the fault remains.
This command has two data bytes.
LTC3815
36
3815fa
For more information www.linear.com/LTC3815
All of the following telemetry registers are initialized to
0x8000 when cycling power, cycling RUN_MSTR pin or
sending a MFS_RESET command. The register will remain
at this value until its first conversion is complete—typically
within 50ms of the initialization event.
READ_VIN
The READ_VIN command returns the measured input
voltage, in volts, at the VIN pin.
This read-only command has two data bytes and is for-
matted as a 16-bit 2’s complement value scaled 4mV/bit.
READ_VOUT
The READ_VOUT command returns the measured output
voltage, in volts as specified by the VOUT_MODE command.
The output voltage is sensed at the VCC_SEN and VSS_SEN
pins.
This read-only command has two data bytes and is format-
ted as a 16-bit 2’s complement value scaled 0.5mV/bit.
READ_IIN
The READ_IIN command returns the input current in
Amperes. The input current is derived from READ_IOUT
current and the measured duty cycle with an offset term
added to account for quiescent current and driver current.
For accurate values at light load currents the part must be
in continuous conduction mode.
This register is reset to 0x8000 is standby mode when
the drivers are off.
PMBus
COMMAND DETAILS
Table 8. Status Word Bit Descriptions and Conditions
BIT DESCRIPTION CONDITION SET ALERT?
CLEARABLE BY
WRITING ‘1’ TO BIT?
0 (LSB) None of the Above If b[15] set due to VOUT undervoltage Yes No
1 Communication Failure (See Note 1) Yes Yes
2 Temperature Fault Temp > 150°C Yes Yes
3 VIN Undervoltage Fault Not Implemented
4 Output Overcurrent Fault Not Implemented
5 Output Overvoltage Fault VOUT > PGOOD High Threshold Yes Yes
6 OFF No Power to the Output (Note 2) No No
7 Busy Not Implemented
8 Unknown Not Implemented
9 Other Not Implemented
10 Fans Not Implemented
11 PGOOD Inverted state of PGOOD pin No No
12 Manufacturer Specific Not Implemented
13 Input Voltage/ Current/Power Fault Not Implemented Yes Yes
14 Output Current/Power Fault Not Implemented
15 (MSB) Output Voltage Fault VOUT outside PGOOD window
(Note 3)
Yes Yes
Note 1: Communication failure is one of following faults: host sends too
few bits, host reads too few bits, host writes too few bytes, host reads too
many bytes, improper R/W bit set, unsupported command code, attempt
to write to a read-only command. See PMBus Specification v1.2, Part II,
Sections 10.8 and 10.9 for more information.
Note 2: Power may be off due to any one of the following conditions:
RUN_STBY low, OPERATION ON cleared, PVIN undervoltage or
overtemperature warning. When the power is off due to RUN_MSTR
low or due to a more serious fault conditions such as VIN low or
overtemperature fault, the PMBus interface is turned off instead of
asserting the OFF bit.
Note 3: This bit is disabled when drivers are off for any reason, soft-start
not complete, or the VOUT has not reached the PGOOD window for the first
time.
LTC3815
37
3815fa
For more information www.linear.com/LTC3815
This read-only command has two data bytes and is format-
ted as a 16-bit 2’s complement value scaled 10mA/bit.
READ_IOUT
The READ_IOUT command returns the average output
current in amperes. The LTC3815 senses and measures
the currents through its top and bottom power switches
to derive IOUT current. For accurate values at light load
currents the part must be in continuous conduction mode.
This register is reset to 0x8000 is standby mode when
the drivers are off.
This read-only command has two data bytes and is format-
ted as a 16-bit 2’s complement value scaled 10mA/bit.
READ_TEMPERATURE_1
The READ_TEMPERATURE_1 command returns the inter-
nal die temperature, in degrees Celsius, of the LTC3815.
This read-only command has two data bytes and is for-
matted as a 16-bit 2’s complement value scaled 1°C/bit.
MFR_VOUT_PEAK
The MFR_VOUT_PEAK command reports the highest
voltage, in volts, reported by the READ_VOUT measure-
ment.
To clear the peak value and restart the peak monitor,
use the MFS_CLEAR_PEAKS command or write to the
MFR_VOUT_PEAK. When writing to MFR_VOUT_PEAK,
zero, one or two data bytes are accepted but the data is
ignored.
This read-only command has two data bytes and is format-
ted as a 16-bit 2’s complement value scaled 0.5mV/bit.
MFR_VIN_PEAK
The MFR_VIN_PEAK command reports the highest voltage,
in volts, reported by the READ_VIN measurement.
To clear the peak value and restart the peak monitor,
use the MFS_CLEAR_PEAKS command or write to the
MFR_VIN_PEAK. When writing to MFR_VIN_PEAK zero,
one or two data bytes are accepted but the data is ignored.
PMBus
COMMAND DETAILS
This read-only command has two data bytes and is for-
matted as a 16-bit 2’s complement value scaled 4mV/bit.
MFR_TEMPERATURE_1_PEAK
The MFR_TEMPERATURE_1_PEAK command reports the
highest temperature, in degrees Celsius, reported by the
READ_TEMPERATURE_1 measurement.
To clear the peak value and restart the peak monitor,
use the MFS_CLEAR_PEAKS command or write to the
MFR_TEMPERATURE_1_PEAK. When writing to MFR_
TEMPERATURE_1__PEAK zero, one or two data bytes
are accepted but the data is ignored.
This read-only command has two data bytes and is for-
matted as a 16-bit 2’s complement value scaled 1°C/bit.
MFR_IOUT_PEAK
The MFR_IOUT_PEAK command reports the highest
current, in amperes, reported by the READ_IOUT mea-
surement.
To clear the peak value and restart the peak monitor,
use the MFS_CLEAR_PEAKS command or write to the
MFR_IOUT_PEAK. When writing to MFR_IOUT_PEAK,
zero, one or two data bytes are accepted but the data is
ignored.
This read-only command has two data bytes and is format-
ted as a 16-bit 2’s complement value scaled 10mA/bit.
MFR_IIN_PEAK
This read-only command has two data bytes and is format-
ted as a 16-bit 2’s complement value scaled 10mA/bit.
To clear the peak value and restart the peak monitor,
use the MFS_CLEAR_PEAKS command or write to the
MFR_IIN_PEAK. When writing to MFR_IIN_PEAK, zero,
one or two data bytes are accepted but the data is ignored.
This read-only command has two data bytes and is format-
ted as a 16-bit 2’s complement value scaled 10mA/bit.
LTC3815
38
3815fa
For more information www.linear.com/LTC3815
TYPICAL APPLICATIONS
1.2V/6A 1MHz Buck Regulator with Minimum External Components
VIN
2.25V TO 5.5V
PGOOD
PMBus
VOUT
1.2V
6A
LTC3815
100k
SGND
12k
0.5%
PGND WP
PGOOD
SCL
SDA
ALERT
PGFD
ASEL
TRACK/SS
CSLEW
RT
PGLIM
REF
MODE/SYNC
RUN_MSTR
RUN_STBY
CLKOUT
MARGIN
SW
VCC_SENSE
VSS_SENSE
DAOUT
VFB
ITH
PVIN VIN
3815 TA02
0.33µH
10k
1k
1nF
47pF
COUT
100µF
×2
CIN
22µF
×2
10k 10k 10k PGOOD DELAY: 190ms
PGOOD THRESHOLD ±10%
FREQUENCY: 1MHz
SOFT-START DELAY: 1ms
MARGIN SLEW RATE: 23%/ms
DCM MODE
PMBus ADDRESS: 0x20
CIN: TAIYO YUDEN LMK316BJ226ML-T
COUT: MURATA GRM32ER60J107ME20
L: COILCRAFT XAL6030-331MEB
1.2V/6A 2MHz Buck Regulator
VIN
2.25V TO 5.5V
PGOOD
PMBus
VOUT
1.2V
6A
LTC3815
100k
SGND60.4k
0.5%
100pF
PGND WP
PGOOD
SCL
SDA
ALERT
PGFD
ASEL
TRACK/SS
CSLEW
RT
PGLIM
REF
MODE/SYNC
RUN_MSTR
RUN_STBY
CLKOUT
MARGIN
SW
VCC_SENSE
VSS_SENSE
DAOUT
VFB
ITH
PVIN VIN
3815 TA03
10k
1k
0.18µH
1nF
47pF
COUT
100µF
×2
CIN
22µF
×2
59.7k
0.5%
11.8k, 1%
46.4k
1%
64.9k
1%
10k 10k 10k
22nF
PGOOD DELAY: 1.6ms
PGOOD THRESHOLD ±20%
FREQUENCY: 2MHz
SOFT-START DELAY: 5ms
MARGIN SLEW RATE: 1%/ms
DCM MODE
PMBus ADDRESS: 0x22
CIN: TAIYO YUDEN LMK316BJ226ML-T
COUT: MURATA GRM32ER60J107ME20
L: COILCRAFT XAL6030-181MEB
LTC3815
39
3815fa
For more information www.linear.com/LTC3815
TYPICAL APPLICATIONS
12V Input, 1.0V/6A Output Buck Regulator
PGOOD
PMBus
VOUT
1.0V
6A
LTC3815
100k
SGND
10k
0.5%
PGND WP
PGOOD
SCL
SDA
ALERT
PGFD
ASEL
TRACK/SS
CSLEW
RT
PGLIM
REF
MODE/SYNC
RUN_MSTR
RUN_STBY
CLKOUT
MARGIN
SW
VCC_SENSE
VSS_SENSE
DAOUT
VFB
ITH
PVIN VIN
3815 TA04
0.33µH
10k
1k
1nF
47pF
COUT
100µF
×2
10k 10k 10k PGOOD DELAY: 190ms
PGOOD THRESHOLD ±10%
FREQUENCY: 1MHz
SOFT-START DELAY: 1ms
MARGIN SLEW RATE: 23%/ms
DCM MODE
PMBus ADDRESS: 0x20
CIN: TAIYO YUDEN LMK316BJ226ML-T
COUT: MURATA GRM32ER60J107ME20
L: COILCRAFT XAL6030-331MEB
CLKIN
RT
24
1
2
3
4
5
6
23
C1
2.2µF
CIN
22µF
×20.1µF
VIN
4V TO 15V
0.1µF
COUT
47µF
×2
0.1µF10pF330pF
22 21
D1
20 19
10Ω
18
17
16
L1 0.68µH 3.3V
15
14
13
7 8
100k
16.2k
12k
22.6k
4.99k
9 10 11 12
SGNDPGND
PHMODE
MODE
FB
TRACK/SS
ITH
PVIN
PVIN
SW
SW
SW
SW
CLKOUT SGND
LTC3605
INTVCC BOOST SVIN
RUN
SVIN
PGOOD VON PGND SW SW
C1: AVX 0805ZD225MAT2A
CIN: TDK C4532X5RIC226M
COUT: TDK C3216X5ROJ476M
D1: CENTRAL SEMI CMDSH-3
L1: VISHAY IHLP-2525CZERR68-M01
LTC3815
40
3815fa
For more information www.linear.com/LTC3815
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3815#packaging for the most recent package drawings.
4.00 ±0.10 2.40 REF
6.00 ±0.10
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
3837
1
2
BOTTOM VIEW—EXPOSED PAD
4.40 REF
0.75 ±0.05
R = 0.115
TYP
R = 0.10
TYP
PIN 1 NOTCH
R = 0.30 OR
0.35 × 45°
CHAMFER
0.20 ±0.05
0.40 BSC
0.200 REF
0.00 – 0.05
(UFE38) QFN 0708 REV B
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.20 ±0.05
0.40 BSC
2.40 REF
4.40 REF
5.10 ±0.05
6.50 ±0.05
2.65 ±0.05
3.10 ±0.05
4.50 ±0.05
PACKAGE OUTLINE
2.65 ±0.10
4.65 ±0.10
4.65 ±0.05
UFE Package
38-Lead Plastic QFN (4mm × 6mm)
(Reference LTC DWG # 05-08-1750 Rev B)
LTC3815
41
3815fa
For more information www.linear.com/LTC3815
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 03/16 Changed VIN_TUE from ±1% to ±1.5% 4
LTC3815
42
3815fa
For more information www.linear.com/LTC3815
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3815
LINEAR TECHNOLOGY CORPORATION 2015
LT 0316 REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
RELATED PARTS
TYPICAL APPLICATION
1.2V/12A 2-Phase Buck Regulator
VIN
2.25V TO 5.5V
PGOOD
VOUT
1.2V, 12A
LTC3815
SGND
1nF
24.9k
PGND WP
PGLIM
PGOOD
SCL, SDA, ALERT
MARGIN
MODE/SYNC
PGFD
ASEL
CSLEW
RT
CLKOUT
RUN_MSTR
RUN_STBY
SW
VCC_SENSE
VSS_SENSE
DAOUT
VFB
ITH
REF
TRACK/SS
PVIN VIN
3815 TA04
L1, 0.5µH
1nF
COUT
100µF
×2
CIN
22µF
×2
SGND PGND WP
PGLIM
MODE/SYNC
SCL, SDA, ALERT
MARGIN
PGOOD
PGFD
ASEL
CSLEW
RT
CLKOUT
MODE/SYNC
RUN_MSTR
RUN_STBY
SW
VCC_SENSE
VSS_SENSE
DAOUT
VFB
ITH
REF
TRACK/SS
PVIN VIN
L2
0.5µH
100k
1nF
24.9k
PMBUS PMBUS
10k
1k
12k
0.5%
22nF
LTC3815
MASTER SLAVE
CIN: TAIYO YUDEN LMK316BJ226ML-T
COUT: MURATA GRM32ER60J107ME20
L1, L2: COILCRAFT XAL6030-331MEB
PART
NUMBER DESCRIPTION COMMENTS
LTM4676A Dual 13A or Single 26A Step-Down DC/DC µModule Regulator
with Digital Power System Management
4.5V ≤ VIN ≤ 17V, 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, I2C/PMBus Interface,
16mm×16mm× 5mm, BGA Package
LTM4675 Dual 9A or Single 18A μModule Regulator
with Digital Power System Management
4.5V ≤ VIN ≤1 7V; 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, I2C/PMBus Interface,
11.9mm×16mm× 5mm, BGA Package
LTM4677 Dual 18A or Single 18A μModule Regulator
with Digital Power System Management
4.5V ≤ VIN ≤ 16V; 0.5V ≤ VOUT (±0.5%) ≤ 1.8V, I2C/PMBus Interface,
16mm× 16mm× 5.01mm, BGA Package
LTC3884 Dual Output Multiphase Step-Down Controller with Sub MilliOhm DCR
Sensing Current Mode Control and Digital Power System Management
4.5V ≤ VIN ≤ 38V, 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, 70ms Start-Up, I2C/PMBus
Interface, Programmable Analog Loop Compensation, Input Current Sense
LTC3887/
LTC3887-1
Dual Output Multiphase Step-Down DC/DC Controller
with Digital Power System Management, 70ms Start-Up
4.5V ≤ VIN ≤ 24V, 0.5V ≤ VOUT0,1 (±0.5%) ≤ 5.5V, 70ms Start-Up, I2C/
PMBus Interface, –1 Version Uses DrMOS and Power Blocks
LTC3882/
LTC3882-1
Dual Output Multiphase Step-Down DC/DC Voltage Mode
Controller with Digital Power System Management
3V ≤ VIN ≤ 38V, 0.5V ≤ VOUT1,2 ≤ 5.25V, ±0.5% VOUT Accuracy
I2C/PMBus Interface, Uses DrMOS or Power Blocks
LTC3886 60V Dual Output Step-Down Controller
with Digital Power System Management
4.5V ≤ VIN ≤ 60V, 0.5V ≤ VOUT0,1 (±0.5%) ≤ 13.8V, 70ms Start-Up,
I2C/PMBus Interface, Input Current Sense
LTC3883/
LTC3883-1
Single Phase Step-Down DC/DC Controller
with Digital Power System Management
VIN Up to 24V, 0.5V ≤ VOUT ≤ 5.5V, Input Current Sense Amplifier,
I2C/PMBus Interface with EEPROM and 16-Bit ADC, ±0.5% VOUT Accuracy
LTC3870/
LTC3870-1
60V Dual Output Multiphase Step-Down Slave Controller for
Current Mode Control Applications with Digital Power System
Management
VIN Up to 60V, 0.5V ≤ VOUT ≤ 14V, Very High Output Current Applications
with Accurate Current Share Between Phases Supporting LTC3880/
LTC3880-1, LTC3883/LTC3883-1, LTC3886, LTC3887/LTC3887-1
LTC3874 Multiphase Step-Down Synchronous Slave Controller
with Sub MilliOhm DCR Sensing
4.5V ≤ VIN ≤ 38V, VOUT Up to 5.5V, Very High Output Current,
Accurate Current Sharing, Current Mode Applications
LTC3880/
LTC3880-1
Dual Output Multiphase Step-Down DC/DC Controller
with Digital Power System Management
4.5V ≤ VIN ≤ 24V, 0.5V ≤ VOUT0 (±0.5%) ≤ 5.4V, 145ms Start-Up,
I2C/PMBus Interface with EEPROM and 16-Bit ADC
