ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM 18Mb DDR SRAM 4-Word Burst MT57V1MH18E MT57V512H36E FEATURES * * * * * * * * * * * * * * * * * 165-BALL FBGA 18Mb Density (1 Meg x 18, 512K x 36) Fast cycle times: 5ns, 6ns, and 7.5ns Pipelined double data rate operation Single +2.5V 0.1V power supply (VDD) Separate isolated output buffer supply (VDDQ) JEDEC-standard HSTL I/O User-selectable trip point with VREF HSTL programmable impedance outputs synchronized to optional dual data clocks JTAG boundary scan Fully static design for reduced-power standby Clock-stop capability Common data inputs and data outputs Low control ball count Internally self-timed, registered LATE WRITE cycle Linear burst order with four-tick burst counter 13 x 15mm, 1mm pitch, 11 x 15 grid FBGA package Full data coherency, providing most current data OPTIONS MARKING* * Clock Cycle Timing 5ns (200 MHz) 6ns (167 MHz) 7.5ns (133 MHz) * Configuration 1 Meg x 18 512K x 36 * Package 165-ball, 13mm x 15mm FBGA -5 -6 -7.5 isters controlled by an input clock pair (K and K#) and are latched on the rising edge of K and K#. The synchronous inputs include all addresses, all data inputs, active LOW load (LD#) read/write (R/W#) and byte write enables (BWx). Write data is registered on the rising edges of both K and K#. Read data is driven on the rising edge of C and C# if provided, or on the rising edge of K and K# if C and C# are not provided. Asynchronous inputs include impedance match (ZQ). Synchronous data outputs (Q) are closely matched to the two echo clocks (CQ and CQ#), which can be used as data receive clocks. Output data clocks (C, C#) are also provided for maximum system clocking and data synchronization flexibility. Additional write registers are incorporated to enhance pipelined WRITE cycles and reduce READ-to-WRITE turnaround time. WRITE cycles are self-timed. The device does not utilize internal phase-locked loops and can therefore be placed into a stopped-clock state to minimize power without lengthy restart times. Four balls are used to implement JTAG test capabilities: test mode select (TMS), test data-in (TDI), test clock (TCK) and test data-out (TDO). JTAG circuitry is used to serially shift data to and from the SRAM. JTAG inputs use MT57V1MH18E MT57V512H36E F * A Part Marking Guide for the FBGA devices can be found on Micron's Web site--http://www.micron.com/numberguide. VALID PART NUMBERS PART NUMBER MT57V1MH18EF-xx MT57V512H36EF-xx DESCRIPTION 1 Meg x 18, DDRb4 FBGA 512K x 36, DDRb4 FBGA GENERAL DESCRIPTION The Micron(R) DDR Synchronous SRAM employs highspeed, low-power CMOS designs using an advanced 6T CMOS process. The DDR SRAM integrates a 18Mb SRAM core with advanced synchronous peripheral circuitry and a 4-bit burst counter. All synchronous inputs pass through reg2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 PRODUCTS 1 (c)2002, Micron Technology, Inc. AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM GENERAL DESCRIPTION (continued) JEDEC-standard 2.5V I/O levels to shift data during this testing mode of operation. The device can be used in HSTL systems by supplying an appropriate reference voltage (VREF). The device is ideally suited for applications requiring very rapid data transfer by operation in data-doubled mode. The device is also ideal in applications requiring the cost benefits of pipelined CMOS SRAMs and the reduced READ-to-WRITE turnaround times of Late Write SRAMs. The SRAM operates from a +2.5V power supply, and all inputs and outputs are HSTL-compatible. The device is ideally suited for cache, network, telecom, DSP, and other applications that benefit from a very wide, highspeed data bus. Please refer to Micron's Web site (www.micron.com/ sramds) for the latest data sheet. lining) and double data rate mode of operation. At slower frequencies, the DDR SRAM requires a single NO OPERATION (NOP) cycle when transitioning from a READ to a WRITE cycle. At higher frequencies, a second NOP cycle may be required to prevent bus contention. NOP cycles are not required when switching from a WRITE to a READ. If a READ occurs after a WRITE cycle, address and data for the WRITE are stored in registers. The write information must be stored because the SRAM cannot perform the last WORD WRITE to the array without conflicting with the READ. The data stays in this register until the next WRITE cycle occurs. On the first WRITE cycle after the READ(s), the stored data from the earlier WRITE will be written into the SRAM array. This is called a POSTED WRITE. A READ can be made immediately to an address even if that address was written in the previous cycle. During this READ cycle, the SRAM array is bypassed, and data is read instead from the data register storing the recently DDR OPERATION The DDR SRAM enables high performance operation through high clock frequencies (achieved through pipe- FUNCTIONAL BLOCK DIAGRAM 512K x 36 n n SA LD# E n-2 n ADDRESS REGISTER n READ SA1 SA1' D1 Q1 SA0 SA0' BURST D0 Q0 LOGIC CLK COMPARE (NOTE 1) (NOTE 2) WRITE# n SA0'' WRITE# WRITE E ADDRESS REGISTER K 36 SA0#' SA0' E K# E 36 CLK 36 36 C# SA' SA0''' SA0' INPUT REGISTER INPUT REGISTER OUTPUT CONTROL LOGIC C n 36 36 36 WRITE DRIVER WRITE REGISTER SA0#' SA0' 36 36 2n-1 x 72 MEMORY ARRAY 36 36 36 SENSE AMPS 36 C 36 36 OUTPUT REGISTER ZQ 0 2:1 MUX 36 36 1 CQ, CQ# 36 OUTPUT BUFFER 36 DQ E 0 36 1 SA0''' 36 R/W# BWx# R/W# E REGISTER WRITE# OE REGISTER C NOTE: 1. SA0 and SA1 are advanced in linear burst order at each K and K# rising edge. 2. The compare width is n-1 bits. The compare is performed only if a WRITE is pending and a READ cycle is requested. If the address matches, data is routed directly to the device outputs, bypassing the memory array. 3. The functional block diagram illustrates simplified device operation. See truth table, ball descriptions, and timing diagrams for detailed information. 4. n = 19 5. CQ, CQ# do not tristate, except during some JEDEC test modes. 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM DDR OPERATION (continued) written data. This is transparent to the user. This feature facilitates system data coherency. The DDR SRAM differs in some ways from its predecessor, the Claymore DDR SRAM. Single data rate operation is not supported, hence no SD/DD# ball is provided. Only bursts of four are supported. In addition to the echo clocks, two single-ended input clocks are available (C, C#). The SRAM synchronizes its output data to these data clock rising edges if provided. If not present, C and C# must be tied high and output timing is derived from K and K#. No differential clocks are used in this device. This clocking scheme provides greater system tuning capability than Claymore SRAMs and reduces the number of input clocks required by the bus master. Output impedance updates may be required because variations may occur in supply voltage and temperature over time. The device samples the value of RQ. An update of the impedance is transparent to the system. Impedance updates do not affect device operation, and all data sheet timing and current specifications are met during an update. The device will power up with an output impedance set at 50W. To guarantee optimum output driver impedance after power-up, the SRAM needs 1,024 cycles to update the impedance. The user can operate the part with fewer than 1,024 clock cycles, but optimal output impedance is not guaranteed. CLOCKING PROGRAMMABLE IMPEDANCE OUTPUT BUFFER The DDR SRAM supports flexible clocking approaches. C and C# may be supplied to the SRAM to synchronize data output across multiple devices, enabling the bus master to receive all data simultaneously. If C and C# are not provided (tied HIGH), K and K# are used as the output timing reference. The echo clocks (CQ and CQ#) provide another alternate for data synchronization. The echo clocks are controlled exactly like the DQ signals except that CQ and CQ# have an additional small delay for easier data capture by the bus master. Echo clocks must be separately received for each SRAM in the system. Use of echo clocks maximizes the available data window for each SRAM in the system. The DDR SRAM is equipped with programmable impedance output buffers. This allows a user to match the driver impedance to the system. To adjust the impedance, an external precision resistor (RQ) is connected between the ZQ ball and VSS. The value of the resistor must be five times the desired impedance. For example, a 350W resistor is required for an output impedance of 70W. To ensure that output impedance is one fifth the value of RQ (within 15 percent), the range of RQ is 175W to 350W. Alternately, the ZQ ball can be connected directly to VDDQ, which will place the device in a minimum impedance mode. APPLICATION EXAMPLE R = 250 R = 250 ZQ SRAM DQ SA LD# R/W# BWn# C C# K K# BUS MASTER (CPU or ASIC) DQ Address Cycle Start# R/W# BWn# Return CLK Source CLK Return CLK# Source CLK# SRAM ZQ DQ SA LD# R/W# BWn# C C# K K# Vterm = 0.75V Vterm = 0.75V R = 50 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM 1 MEG x 18 BALL ASSIGNMENT (TOP VIEW) 165-BALL FBGA A 1 CQ# 2 VSS 3 SA 4 R/W# 5 BW1# 6 K# 7 NC 8 LD# 9 SA 10 VSS/SA* 11 CQ B C D E F NC NC NC NC NC DQ9 NC NC NC DQ12 NC NC DQ10 DQ11 NC SA VSS VSS VDDQ VDDQ NC SA VSS VSS VDD K SA0 VSS VSS VSS BW0# SA1 VSS VSS VDD SA VSS VSS VDDQ VDDQ NC NC NC NC NC NC DQ7 NC NC NC DQ8 NC NC DQ6 DQ5 G H J K NC NC NC NC NC VREF NC NC DQ13 VDDQ NC DQ14 VDDQ VDDQ VDDQ VDDQ VDD VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ NC VDDQ NC NC NC VREF DQ4 NC NC ZQ NC DQ3 L M NC NC DQ15 NC NC NC VDDQ VSS VSS VSS VSS VSS VSS VSS VDDQ VSS NC NC NC DQ1 DQ2 NC N P R NC NC TDO NC NC TCK DQ16 DQ17 SA VSS SA SA SA SA SA SA C C# SA SA SA VSS SA SA NC NC SA NC NC TMS NC DQ0 TDI *Expansion addresses: 10A for 36Mb. 512K x 36 BALL ASSIGNMENT (TOP VIEW) 165-BALL FBGA A 1 CQ# 2 VSS 3 NC/SA* 4 R/W# 5 BW2# 6 K# 7 BW1# 8 LD# 9 SA 10 VSS 11 CQ B C D NC NC NC DQ27 NC DQ29 DQ18 DQ28 DQ19 SA VSS VSS BW3# SA VSS K SA0 VSS BW0# SA1 VSS SA VSS VSS NC NC NC NC DQ17 NC DQ8 DQ7 DQ16 E F G NC NC NC NC DQ30 DQ31 DQ20 DQ21 DQ22 VDDQ VDDQ VDDQ VSS VDD VDD VSS VSS VSS VSS VDD VDD VDDQ VDDQ VDDQ NC NC NC DQ15 NC NC DQ6 DQ5 DQ14 H J K L M NC NC NC NC NC VREF NC NC DQ33 NC VDDQ DQ32 DQ23 DQ24 DQ34 VDDQ VDDQ VDDQ VDDQ VSS VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VSS VSS VDDQ VDDQ VDDQ VDDQ VSS VDDQ NC NC NC NC VREF DQ13 DQ12 NC DQ11 ZQ DQ4 DQ3 DQ2 DQ1 N P R NC NC TDO DQ35 NC TCK DQ25 DQ26 SA VSS SA SA SA SA SA SA C C# SA SA SA VSS SA SA NC NC SA NC DQ9 TMS DQ10 DQ0 TDI *Expansion addresses: 3A for 36Mb. NOTE: BW0# controls writes to DQ0:DQ8. BW1# controls writes to DQ9:DQ17. BW2# controls writes to DQ18:DQ26. BW3# controls writes to DQ27:DQ35. 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM BALL DESCRIPTIONS SYMBOL TYPE DESCRIPTION SA0 Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K. Balls 3A and 9A are reserved for the next higher-order address inputs on the 36Mb device. SA0 and SA1 are used as the lowest address bits for BURST READ and BURST WRITE operations. These inputs are ignored when device is deselected or once BURST operation is in progress. LD# Input Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition includes address and read/write direction. All transactions operate on a burst of 2 data (one clock periods of bus activity). R/W# Input Synchronous Read/Write Input: When LD# is LOW, this input designates the access type (READ when R/W# is HIGH, WRITE when R/W# is LOW) for the loaded address. R/W# must meet the setup and hold times around the rising edge of K. BW_# Input Synchronous Byte Writes: When LOW, these inputs cause their respective byte to be registered and written during WRITE cycles. These signals must meet setup and hold times around the rising edges of K and K# for each of the two rising edges comprising the WRITE cycle. See ball assignment figures for signal to data relationships. K K# Input Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. C C# Input Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of C is used as the output timing reference for first and third output data. The rising edge of C# is used as the output reference for second and fourth output data. Ideally, C# is 180 degrees out of phase with C. C and C# may be tied HIGH to force the use of K and K# as the output reference clocks instead of having to provide C and C# clocks. If tied HIGH, C and C# must remain HIGH and not be toggled during device operation. ZQ Input Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to ground. Alternately, this ball can be connected directly to VDDQ, which enables the minimum impedance mode. This ball cannot be connected directly to GND or left unconnected. TMS TDI Input IEEE 1149.1 Test Inputs: JEDEC-standard 2.5V I/O levels. These balls may be left Not Connected if the JTAG function is not used in the circuit. TCK Input IEEE 1149.1 Clock Input: JEDEC-standard 2.5V I/O levels. This ball must be tied to VSS if the JTAG function is not used in the circuit. VREF Input HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers. DQ_ Input/ Output Synchronous Data IOs: Input data must meet setup and hold times around the rising edges of K and K#. Output data is synchronized to the respective C and C# data clocks or to K and K# if C and C# are tied to HIGH. See Ball Assignment figures for ball site location of individual signals. The x18 device uses DQ0-DQ17. Remaining signals are NC. The x36 device uses DQ0-DQ35. CQ CQ# Output Echo Clocks: (continued on next page) 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM BALL DESCRIPTIONS (continued) SYMBOL TYPE TDO Output IEEE 1149.1 Test Output: JEDEC-standard 2.5V I/O level. VDD Supply Power Supply: 2.5V nominal. See DC Electrical Characteristics and Operating Conditions for range. VDDQ Supply Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. See DC Electrical Characteristics and Operating Conditions for range. VSS Supply Power Supply: GND. NC - 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 DESCRIPTION No Connect: These signals are internally connected and appear in the JTAG scan chain as a logic "0." These signals may be connected to ground to improve package heat dissipation. 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM LINEAR BURST ADDRESS TABLE FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X10 X...X11 X...X00 X...X10 X...X11 X...X00 X...X01 X...X11 X...X00 X...X01 X...X10 BUS CYCLE STATE DIAGRAM L L#, Count=4 always READ DOUBLE Count=Count+2 Count=2 ADVANCE ADDRESS BY TWO1 NOP L# L, Count=4 R LOAD NEW ADDRESS Count=0 Supply voltage provided L#, Count=4 L, Count=4 W always WRITE DOUBLE Count=Count+2 Count=2 ADVANCE ADDRESS BY TWO1 POWER-UP NOTE: 1. SA0 and SA1 are internally advanced in accordance with the burst order table. Bus cycle is terminated after burst count = 4. 2. State transitions: L = (LD# = LOW); L# = (LD# = HIGH); R = (R/W# = HIGH); W = (R/W# = LOW). 3. State machine control timing sequence is controlled by K. 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM TRUTH TABLE (Notes 1-6) OPERATION WRITE Cycle: Load address, input write data on two consecutive K and K# rising edges LD# L R/W# L K L(R)H DQ DIN(A1) at K(t+1) DQ DIN(A2) at K#(t+1) DQ DIN(A3) at K(t+2) DQ DIN(A4) at K#(t+2) READ Cycle: Load address, read data on two consecutive C and C# rising edges L H L(R)H QOUT(A1) at C#(t+1) QOUT(A2) at C(t+2) QOUT(A3) at C#(t+2) QOUT(A4) at C(t+3) NOP: No operation H X L(R)H High-Z High-Z High-Z High-Z STANDBY: Clock stopped X X Stopped Previous State Previous State Previous State Previous State BYTE WRITE OPERATION (Notes 7, 8) OPERATION K WRITE D0-17 at K rising edge K# BW0# BW1# 0 0 L(R)H 0 0 0 1 L(R)H 0 1 1 0 1 0 1 1 1 1 L(R)H WRITE D0-17 at K# rising edge WRITE D0-8 at K rising edge L(R)H WRITE D0-8 at K# rising edge WRITE D9-17 at K rising edge L(R)H WRITE D9-17 at K# rising edge L(R)H WRITE nothing at K rising edge L(R)H WRITE nothing at K# rising edge L(R)H NOTE: 1. X means "Don't Care." H means logic HIGH. L means logic LOW. means rising edge; means falling edge. 2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges except if C and C# are HIGH then data outputs are delivered at K and K# rising edges. 3. R/W# and LD# must meet setup/hold times around the rising edge (LOW to HIGH) of K and are registered at the rising edge of K. 4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 5. Refer to state diagram and timing diagrams for clarification. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal burst address in accordance with the burst sequence. 6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most rapid restart by overcoming transmission line charging symmetrically. 7. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. 8. This table illustrates operation for x18 devices. the x36 device operation is similar except for the addition of BW2# (controls D18-D26) and BW3# (controls D27-D35). 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ** Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. See Micron Technical Note TN-05-14 for more information. ABSOLUTE MAXIMUM RATINGS* Voltage on VDD Supply Relative to VSS .......................................... -0.5V to 2.9V Voltage on VDDQ Supply Relative to VSS ........................................... -0.5V to VDD VIN .......................................................... -0.5V to VDD + 0.5V Storage Temperature ............................... -55C to +125C Junction Temperature** ......................................... +125C Short Circuit Output Current ................................ 70mA DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (+20C TJ +110C; +2.4V VDD +2.6V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage CONDITIONS SYMBOL VIH (DC) VIL (DC) MIN VREF + 0.1 -0.3 MAX VDDQ + 0.3 VREF - 0.1 UNITS NOTES V 3, 4 V 3, 4 -0.3 -5 VDDQ + 0.3 5 V A -5 5 A VDDQ - 0.2 VDDQ Clock Input Signal Voltage Input Leakage Current Output Leakage Current 0V VIN VDDQ Output(s) disabled, VIN ILI ILO Output High Voltage 0V VIN VDDQ (Q) |IOH| 0.1mA VOH (LOW) V 3, 5, 7 Output Low Voltage Note 1 IOL 0.1mA VOH VOL (LOW) VDDQ/2 - 0.12 VDDQ/2 + 0.12 VSS 0.2 V V 3, 5, 7 3, 5, 7 Note 2 VOL VDD VDDQ VREF VDDQ/2 - 0.12 VDDQ/2 + 0.12 2.4 2.6 1.4 1.9 V V V 3, 5, 7 3 3, 6 V 3 Supply Voltage Isolated Output Buffer Supply Reference Voltage 0.68 0.95 3, 4 AC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (+20C TJ +110C; +2.4V VDD +2.6V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage NOTE: 1. 2. 3. 4. 5. 6. 7. 8. CONDITIONS SYMBOL VIH (AC) VIL (AC) MIN VREF + 0.2 - MAX - VREF - 0.2 UNITS NOTES V 3, 4, 8 V 3, 4, 8 Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) for values of 175W RQ 350W. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175W RQ 350W. All voltages referenced to VSS (GND). Overshoot: VIH (AC) VDD + 0.7V for t tKHKH/2 Undershoot: VIL (AC) -0.5V for t tKHKH/2 Power-up: VIH VDDQ + 0.3V and VDD 2.4V and VDDQ 1.4V for t 200ms During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less than tKHKL (MIN) or operate at cycle rates less than tKHKH (MIN). AC load current is higher than the shown DC values. AC I/O curves are available upon request. For higher VDDQ voltages, contact factory for product information. HSTL outputs meet JEDEC HSTL Class I and Class II standards. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through the target AC level, VIL (AC) or VIH (AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, V IL (DC) or VIH (DC). 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM IDD OPERATING CONDITIONS AND MAXIMUM LIMITS (+20C TJ +110C; VDD = MAX unless otherwise noted) DESCRIPTION CONDITIONS SYMBOL TYP -5 -6 All inputs VIL or VIH; Cycle time tKHKH (MIN); Outputs open IDD (x18) (x36) TBD 225 300 200 260 175 225 mA = tKHKH (MIN); Device in NOP state; All addresses/data static ISB1 (x18) (x36) TBD 170 180 150 160 125 135 mA Cycle time = 0; Inputs static ISB TBD 75 75 75 mA CL = 15pF IDDQ (x18) (x36) - 41 81 34 68 28 55 mA Operating Supply Current: DDR tKHKH Standby Supply Current: NOP Stop Clock Current MAX Output Supply Current: DDR (For information only) -7.5 UNITS NOTES 1, 2, 3 2, 4 2 5 CAPACITANCE DESCRIPTION CONDITIONS Address/Control Input Capacitance Input/Output Capacitance (DQ) TA = 25C; f = 1 MHz Clock Capacitance SYM TYP MAX UNITS NOTES CI 4 5 pF 6 CO 6 7 pF 6 CCK 5 6 pF 6 THERMAL RESISTANCE DESCRIPTION CONDITIONS SYM TYP UNITS NOTES Junction to Ambient (Airflow of 1m/s) Soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board Junction to Case (Top) qJA 25 C/W 6, 7 qJC 10 C/W 6 Junction to Balls (Bottom) qJB 12 C/W 6, 8 NOTE: 1. IDD is specified with no output current and increases with faster cycle times. I DDQ increases with faster cycle times and greater output loading. Typical value is measured at 6ns cycle time. 2. Typical values are measured at VDD = 2.5V, VDDQ = 1.5V and temperature = 25C. 3. Operating supply currents and burst mode currents are calculated with 50 percent READ cycles and 50 percent WRITE cycles. 4. NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed. 5. Average I/O current and power is provided for information purposes only and is not tested. Calculation assumes that all outputs are loaded with CL (in farads), half of outputs toggle at each transition (n = 36), VDDQ = 1.5V and uses the equations: Average I/O Power as dissipated by the SRAM is: P = 0.5 x n x f x CL x VDDQ2. Average IDDQ = n x f x CL x VDDQ. 6. This parameter is sampled. 7. Average thermal resistance between the die and the case top surface per MIL SPEC 883 Method 1012.1. 8. Junction temperature is a function of total device power dissipation and device mounting environment. Measured per SEMI G38-87. 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM AC ELECTRICAL CHARACTERISTICS (Notes 4, 5) (+20C TJ 110C; +2.4V VDD +2.6V) DESCRIPTION Clock Clock cycle time (K, K#, C, C#) Clock HIGH time (K, K#, C, C#) Clock LOW time (K, K#, C, C#) Clock to clock# (K(R)K#, C(R)C#) Clock# to clock (K#(R)K, C#(R)C) Clock to data clock (K(R)C, K#(R)C#) Output Times C, C# HIGH to output valid C, C# HIGH to output hold C HIGH to output High-Z C HIGH to output Low-Z C, C# HIGH to CQ, CQ# HIGH Setup Times Address valid to K rising edge Control inputs valid to K rising edge Data-in valid to K, K# rising edge Hold Times K rising edge to address hold K rising edge to control inputs hold K, K# rising edge to data-in hold -5 SYMBOL MIN tKHKH 5.0 2.0 2.0 2.4 2.4 0.0 tKHKL tKLKH tKHK#H tK#HKH tKHCH tCHQV -6 MAX MIN 1.5 6.0 2.4 2.4 2.8 2.8 0.0 2.4 tCHQX tCHCQH tAVKH tIVKH tDVKH tKHAX tKHIX tKHDX MIN 2.0 7.5 3.0 3.0 3.4 3.4 0.0 3.0 0.8 tCHQZ tCHQX1 MAX 2.4 0.8 0.8 2.6 2.5 3.6 0.8 3.0 0.8 0.8 -7.5 MAX 3.2 3.6 0.8 0.8 3.8 UNITS NOTES ns ns ns ns ns ns ns ns ns ns ns 6, 7 6, 7 0.6 0.6 0.6 0.7 0.7 0.7 0.8 0.8 0.8 ns ns ns 2 2 2 0.6 0.6 0.6 0.7 0.7 0.7 0.8 0.8 0.8 ns ns ns 2 2 2 NOTE: 1. This parameter is sampled. 2. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. 3. Test conditions as specified with the output loading as shown in Figure 1 unless otherwise noted. 4. Control input signals may not be operated with pulse widths less than tKHKL (MIN). 5. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters. 6. Transition is measured 100mV from steady state voltage. 7. tCHQXI is greater than tCHQZ at any given voltage and temperature. 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM AC TEST CONDITIONS Figure 1 Output Load Equivalent Input pulse levels ............................... 0.25V to 1.25V Input rise and fall times .................................... 0.7ns VDDQ/2 0.75V VREF Input timing reference levels ........................... 0.75V 50 Output reference levels ................................. VDDQ/2 SRAM ZQ for 50W impedance ...................................... 250W Z O = 50 Output load ........................................... See Figure 1 250 ZQ 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM READ/WRITE TIMING NOP READ (burst of 4) 1 2 READ (burst of 4) 3 4 NOP 5 NOP (Note 3) 7 6 WRITE (burst of 4) 8 WRITE (burst of 4) 9 10 READ (burst of 4) 12 11 13 K tKHKL tKLKH tKHKH tKHK#H K# LD# tIVKH tKHIX R/W# A A0 A1 A2 A3 tKHDX tAVKH tKHAX tDVKH DQ Qx2 Q01 tKHCH tKHCH tCHQV tCHQX1 Q02 Q03 Q04 Q11 Q12 Q13 Q14 A4 tKHDX tDVKH D21 D22 D23 D24 D31 D32 D33 D34 Q41 tCHQV tCHQX tCHQZ tCHQX CQ tCHQX tCQHQZ CQ# C tKHKL tKLKH tKHKH tKHK#H C# DON'T CARE UNDEFINED NOTE: 1. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0, etc. 2. Outputs are disabled (High-Z) one clock cycle after a NOP. 3. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies it may be required to prevent bus contention. 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG) TEST ACCESS PORT (TAP) TEST CLOCK (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. The DDR SRAM incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 2.5V I/O logic levels. The SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. TEST MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. TEST DATA-IN (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see Figure 2. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Figure 3.) DISABLING THE JTAG FEATURE It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pullup resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. TEST DATA-OUT (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. (See Figure 2.) The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Figure 3.) Figure 2 TAP Controller State Diagram 1 TEST-LOGIC RESET 0 RUN-TEST/ IDLE 0 1 SELECT DR-SCAN 1 SELECT IR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 0 SHIFT-DR 0 Bypass Register SHIFT-IR 1 0 2 1 0 1 EXIT1-DR 1 EXIT1-IR 0 TDI 1 0 x . 0 TDO . 2 1 0 . . . . 2 1 0 EXIT2-IR 1 1 UPDATE-DR TCK UPDATE-IR TMS 1 . Selection Circuitry Boundary Scan Register 1 0 Instruction Register Identification Register PAUSE-IR 1 EXIT2-DR Selection Circuitry 31 30 29 . 0 PAUSE-DR 0 Figure 3 TAP Controller Block Diagram 1 0 1 TAP CONTROLLER 0 x = 106 for the x8, x18, x36 configuration. NOTE: The 0/1 next to each state represents the value of TMS at the rising edge of TCK. 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM PERFORMING A TAP RESET A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the balls on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. IDENTIFICATION (ID) REGISTER The ID register is loaded with a vendor-specific, 32bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP REGISTERS Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. INSTRUCTION REGISTER Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in Figure 3. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board-level serial test data path. TAP INSTRUCTION SET OVERVIEW Eight different instructions are possible with the threebit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. BYPASS REGISTER To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. BOUNDARY SCAN REGISTER The boundary scan register is connected to all the input and bidirectional balls on the SRAM. Several no connect (NC) balls are also included in the scan register to reserve balls. All configurations have a 107-bit-long register. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the I/O ring. 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in the TAP controller, hence this device is not IEEE 1149.1 compliant. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/ PRELOAD instruction has been loaded. EXTEST does not place the SRAM outputs in a High-Z state, CQ, CQ#. 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls. Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state, including CQ, CQ#. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1-compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. RESERVED These instruction are not implemented but are reserved for future use. Do not use these instructions. 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM TAP TIMING 1 2 Test Clock (TCK) 3 tTHTL tMVTH tTHMX tDVTH tTHDX t TLTH 4 5 6 tTHTH Test Mode Select (TMS) Test Data-In (TDI) tTLOV tTLOX Test Data-Out (TDO) DON'T CARE UNDEFINED TAP AC ELECTRICAL CHARACTERISTICS (Notes 1, 2) (+20C TJ +100C, +2.4V VDD +2.6V) DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times TCK LOW to TDO unknown TCK LOW to TDO valid TDI valid to TCK HIGH TCK HIGH to TDI invalid Setup Times TMS setup Capture setup Hold Times TMS hold Capture hold SYMBOL MIN tTHTH 100 fTF tTHTL 10 tTLTH 40 40 tTLOX 0 tTHDX tMVTH tCS tTHMX tCH UNITS ns MHz ns ns 10 10 ns ns ns ns 10 10 ns ns 10 10 ns ns tTLOV tDVTH MAX 20 NOTE: 1. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in Figure 4. 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM TAP AC TEST CONDITIONS Figure 4 TAP AC Output Load Equivalent Input pulse levels ...................................... VSS to 2.5V Input rise and fall times ....................................... 1ns VDD /2 Input timing reference levels ............................. 1.25 50 Output reference levels .................................... 1.25V Test load termination supply voltage .............. 1.25V TDO Z O= 50 20pF TAP DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (+20C TJ 110C, +2.4V VDD +2.6V unless otherwise noted) DESCRIPTION CONDITIONS Input High (Logic 1) Voltage Input Low (Logic 0) Voltage SYMBOL MIN MAX UNITS NOTES VIH VIL 1.7 -0.3 VDD + 0.3 0.7 V V 1, 2 1, 2 ILI ILO -5.0 -5.0 5.0 5.0 A A 0.2 0.7 V V 1 1 V V 1 1 Output Low Voltage Output Low Voltage 0V VIN VDD Output(s) disabled, 0V VIN VDDQ IOLC = 100A IOLT = 2mA VOL1 VOL2 Output High Voltage Output High Voltage |IOHC| = 100A |IOHT| = 2mA VOH1 VOH2 Input Leakage Current Output Leakage Current 2.1 1.7 NOTE: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH (AC) VDD + 1.5V for t tKHKH/2 Undershoot: VIL (AC) -0.5V for t tKHKH/2 Power-up: VIH +2.6 and VDD 2.4V and VDDQ 1.4V for t 200ms During normal operation, VDDQ must not exceed VDD. Control input signals (such as LD#, R/W#, etc.) may not have pulse widths less than tKHKL (MIN) or operate at frequencies exceeding fKF (MAX). 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM IDENTIFICATION REGISTER DEFINITIONS INSTRUCTION FIELD ALL DEVICES REVISION NUMBER (31:29) DEVICE ID (28:12) 000 00def0wx000q0b0s0 MICRON JEDEC ID CODE (11:1) 00000101100 ID Register Presence Indicator (0) 1 DESCRIPTION Version number. def = 001 for 18Mb density wx = 11 for x36, 10 for x18, 01 for x8 q = 1 for QDR, 0 for DDR b = 1 for 4-word burst, 0 for 2-word burst s = 1 for separate I/O, 0 for common I/O Allows unique identification of SRAM vendor. Indicates the presence of an ID register. SCAN REGISTER SIZES REGISTER NAME BIT SIZE Instruction 3 Bypass 1 ID 32 Boundary Scan 107 INSTRUCTION CODES INSTRUCTION CODE DESCRIPTION EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. This instruction is not 1149.1-compliant. This operation does not affect SRAM operations. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. This instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM BOUNDARY SCAN (EXIT) ORDER BIT# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 FBGA BALL 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E 10E BIT# 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 FBGA BALL 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A 8B 7C 6C 8A 7A 7B 6B 6A 5B 5A 4A 5C 4B 3A 2A 1A 2B 3B 1C 1B 3D 3C 1D BIT# 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 FBGA BALL 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R NOTE: For NC balls in the range of 2B-2P, 3B-3P, 4B-4P, 9B-9P, 10B-10P, and 11B-11P, a logic "0" will be read from the chain. All other NC balls will be an unknown value. 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM 165-BALL FBGA 0.85 0.075 0.12 C SEATING PLANE C BALL A11 165X O 0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS O 0.40 10.00 BALL A1 PIN A1 ID 1.00 TYP 1.20 MAX PIN A1 ID 7.50 0.05 14.00 15.00 0.10 7.00 0.05 1.00 TYP MOLD COMPOUND: EPOXY NOVOLAC 6.50 0.05 SUBSTRATE: PLASTIC LAMINATE 5.00 0.05 SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb SOLDER BALL PAD: O .33mm 13.00 0.10 NOTE: 1. All dimensions in millimeters. 2. Molding dimensions do not include protrusion; allowable mold protrusion is 0.25mm per side. 3. Dimensions apply to solder balls post reflow DATA SHEET DESIGNATION Advance: This data sheet contains initial descriptions of products still under development. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc. 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc. ADVANCE 1 MEG x 18, 512K x 36 2.5V VDD, HSTL, PIPELINED DDRb4 SRAM REVISION HISTORY Rev. 4, Pub. 5/02, ADVANCE .................................................................................................................................................. 5/02 * Fixed voltage range error in AC Electrical Characteristics and Operating Conditions table Rev. 3, Pub. 5/02, ADVANCE .................................................................................................................................................. 5/02 * Updated DC Electrical Characteristics and Operating Conditions table * Added AC Electrical Characteristics and Operating Conditions table Rev. 2, Pub. 5/02 ....................................................................................................................................................................... 5/02 * Made corrections to the 512K x 36 Ball Assignment table Original document, ADVANCE .............................................................................................................................................. 3/02 2.5V VDD, HSTL, Pipelined DDRb4 SRAM MT57V512H36E_4.p65 - Rev. 4, Pub. 5/02 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology, Inc.