MT57V1MH18EF-6 - Micron - Datasheet.Directory

MT57V512H36E_4.p65 – Rev. 4, Pub. 5/02

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, PIPELINED DDRb4 SRAM

ADVANCE‡

‡

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE

SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S

PRODUCTION DATA SHEET SPECIFICATIONS.

18Mb DDR SRAM

4-Word Burst

FEATURES

• 18Mb Density (1 Meg x 18, 512K x 36)

• Fast cycle times: 5ns, 6ns, and 7.5ns

• Pipelined double data rate operation

• Single +2.5V ±0.1V power supply (VDD)

• Separate isolated output buffer supply (VDDQ)

• JEDEC-standard HSTL I/O

• User-selectable trip point with VREF

• HSTL programmable impedance outputs synchro-

nized to optional dual data clocks

• JTAG boundary scan

• Fully static design for reduced-power standby

• Clock-stop capability

• Common data inputs and data outputs

• Low control ball count

• Internally self-timed, registered LATE WRITE cycle

• Linear burst order with four-tick burst counter

• 13 x 15mm, 1mm pitch, 11 x 15 grid FBGA package

• Full data coherency, providing most current data

OPTIONS MARKING*

• Clock Cycle Timing

5ns (200 MHz) -5

6ns (167 MHz) -6

7.5ns (133 MHz) -7.5

• Configuration

1 Meg x 18 MT57V1MH18E

512K x 36 MT57V512H36E

• Package

165-ball, 13mm x 15mm FBGA F

* A Part Marking Guide for the FBGA devices can be found on Micron’s

Web site—http://www.micron.com/numberguide.

165-BALL FBGA

MT57V1MH18E

MT57V512H36E

GENERAL DESCRIPTION

The Micron® DDR Synchronous SRAM employs high-

speed, low-power CMOS designs using an advanced 6T

CMOS process.

The DDR SRAM integrates a 18Mb SRAM core with

advanced synchronous peripheral circuitry and a 4-bit

burst counter. All synchronous inputs pass through reg-

VALID PART NUMBERS

PART NUMBER DESCRIPTION

MT57V1MH18EF-xx 1 Meg x 18, DDRb4 FBGA

MT57V512H36EF-xx 512K x 36, DDRb4 FBGA

isters controlled by an input clock pair (K and K#) and are

latched on the rising edge of K and K#. The synchronous

inputs include all addresses, all data inputs, active LOW

load (LD#) read/write (R/W#) and byte write enables

(BWx). Write data is registered on the rising edges of both

K and K#. Read data is driven on the rising edge of C and

C# if provided, or on the rising edge of K and K# if C and

C# are not provided.

Asynchronous inputs include impedance match (ZQ).

Synchronous data outputs (Q) are closely matched to the

two echo clocks (CQ and CQ#), which can be used as data

receive clocks. Output data clocks (C, C#) are also pro-

vided for maximum system clocking and data synchroni-

zation flexibility.

Additional write registers are incorporated to enhance

pipelined WRITE cycles and reduce READ-to-WRITE turn-

around time. WRITE cycles are self-timed.

The device does not utilize internal phase-locked loops

and can therefore be placed into a stopped-clock state to

minimize power without lengthy restart times.

Four balls are used to implement JTAG test capabili-

ties: test mode select (TMS), test data-in (TDI), test clock

(TCK) and test data-out (TDO). JTAG circuitry is used to

serially shift data to and from the SRAM. JTAG inputs use

2.5V VDD, HSTL, Pipelined DDRb4 SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, PIPELINED DDRb4 SRAM

NOTE: 1. SA0 and SA1 are advanced in linear burst order at each K and K# rising edge.

2. The compare width is n-1 bits. The compare is performed only if a WRITE is pending and a READ cycle is requested. If

the address matches, data is routed directly to the device outputs, bypassing the memory array.

3. The functional block diagram illustrates simplified device operation. See truth table, ball descriptions, and timing

diagrams for detailed information.

4. n = 19

5. CQ, CQ# do not tristate, except during some JEDEC test modes.

JEDEC-standard 2.5V I/O levels to shift data during this

testing mode of operation.

The device can be used in HSTL systems by supplying

an appropriate reference voltage (VREF). The device is

ideally suited for applications requiring very rapid data

transfer by operation in data-doubled mode. The device

is also ideal in applications requiring the cost benefits of

pipelined CMOS SRAMs and the reduced READ-to-WRITE

turnaround times of Late Write SRAMs.

The SRAM operates from a +2.5V power supply, and

all inputs and outputs are HSTL-compatible. The device

is ideally suited for cache, network, telecom, DSP, and

other applications that benefit from a very wide, high-

speed data bus.

Please refer to Micron’s Web site (www.micron.com/

sramds) for the latest data sheet.

DDR OPERATION

The DDR SRAM enables high performance operation

through high clock frequencies (achieved through pipe-

GENERAL DESCRIPTION (continued)

lining) and double data rate mode of operation. At slower

frequencies, the DDR SRAM requires a single NO OPERA-

TION (NOP) cycle when transitioning from a READ to a

WRITE cycle. At higher frequencies, a second NOP cycle

may be required to prevent bus contention. NOP cycles

are not required when switching from a WRITE to a

READ.

If a READ occurs after a WRITE cycle, address and

data for the WRITE are stored in registers. The write

information must be stored because the SRAM cannot

perform the last WORD WRITE to the array without con-

flicting with the READ. The data stays in this register until

the next WRITE cycle occurs. On the first WRITE cycle

after the READ(s), the stored data from the earlier WRITE

will be written into the SRAM array. This is called a

POSTED WRITE.

A READ can be made immediately to an address even

if that address was written in the previous cycle. During

this READ cycle, the SRAM array is bypassed, and data is

read instead from the data register storing the recently

FUNCTIONAL BLOCK DIAGRAM

512K x 36

LD#

ADDRESS

nn-2 n

WRITE

ADDRESS

CQ, CQ#

OUTPUT

BUFFER

BURST

LOGIC

SA0’

SA1’

SA0

SA1

(NOTE 1)

INPUT

(NOTE 2)

R/W#

BWx#

COMPARE

CLK

WRITE#

INPUT

SA0''’

WRITE#

READ

SA0''

SA0'''

SA’

SA0#’

SA0’

SA0#’

SA0’

OUTPUT

CONTROL

LOGIC

OUTPUT

WRITE

AMPS

n-1

x 72

MEMORY

ARRAY

WRITE

DRIVER C

CLK 2:1

MUX

2.5V VDD, HSTL, Pipelined DDRb4 SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, PIPELINED DDRb4 SRAM

written data. This is transparent to the user. This feature

facilitates system data coherency.

The DDR SRAM differs in some ways from its prede-

cessor, the Claymore DDR SRAM. Single data rate opera-

tion is not supported, hence no SD/DD# ball is provided.

Only bursts of four are supported. In addition to the echo

clocks, two single-ended input clocks are available (C,

C#). The SRAM synchronizes its output data to these data

clock rising edges if provided. If not present, C and C#

must be tied high and output timing is derived from K

and K#. No differential clocks are used in this device. This

clocking scheme provides greater system tuning capabil-

ity than Claymore SRAMs and reduces the number of

input clocks required by the bus master.

PROGRAMMABLE IMPEDANCE OUTPUT

BUFFER

The DDR SRAM is equipped with programmable im-

pedance output buffers. This allows a user to match the

driver impedance to the system. To adjust the imped-

ance, an external precision resistor (RQ) is connected

between the ZQ ball and VSS. The value of the resistor

must be five times the desired impedance. For example,

a 350W resistor is required for an output impedance of

70W. To ensure that output impedance is one fifth the

value of RQ (within 15 percent), the range of RQ is 175W

to 350W. Alternately, the ZQ ball can be connected di-

rectly to VDDQ, which will place the device in a minimum

impedance mode.

DDR OPERATION (continued)

Output impedance updates may be required because

variations may occur in supply voltage and temperature

over time. The device samples the value of RQ. An update

of the impedance is transparent to the system. Imped-

ance updates do not affect device operation, and all data

sheet timing and current specifications are met during

an update.

The device will power up with an output impedance

set at 50W. To guarantee optimum output driver imped-

ance after power-up, the SRAM needs 1,024 cycles to

update the impedance. The user can operate the part

with fewer than 1,024 clock cycles, but optimal output

impedance is not guaranteed.

CLOCKING

The DDR SRAM supports flexible clocking approaches.

C and C# may be supplied to the SRAM to synchronize

data output across multiple devices, enabling the bus

master to receive all data simultaneously. If C and C# are

not provided (tied HIGH), K and K# are used as the output

timing reference.

The echo clocks (CQ and CQ#) provide another alter-

nate for data synchronization. The echo clocks are con-

trolled exactly like the DQ signals except that CQ and CQ#

have an additional small delay for easier data capture by

the bus master. Echo clocks must be separately received

for each SRAM in the system. Use of echo clocks maxi-

mizes the available data window for each SRAM in the

system.

APPLICATION EXAMPLE

LD#

Vterm = 0.75V

CC#R/W#

SA K LD# CC#

R/W#

SA K

BUS

MASTER

(CPU

ASIC)

SRAM SRAM

Address

Cycle Start#

R/W#

BWn#

Return CLK

Source CLK

Return CLK#

Source CLK# R = 50Ω

R = 250Ω

BWn#BWn#

2.5V VDD, HSTL, Pipelined DDRb4 SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, PIPELINED DDRb4 SRAM

*Expansion addresses: 10A for 36Mb.

1 MEG x 18 BALL ASSIGNMENT (TOP VIEW)

165-BALL FBGA

1234567891011

ACQ# VSS SA R/W# BW1# K# NC LD# SA VSS/SA*CQ

BNC DQ9 NC SA NC K BW0# SA NC NC DQ8

CNC NC NC VSS SA SA0 SA1 VSS NC DQ7 NC

DNC NC DQ10 VSS VSS VSS VSS VSS NC NC NC

ENC NC DQ11 VDDQVSS VSS VSS VDDQNC NC DQ6

FNC DQ12 NC VDDQVDD VSS VDD VDDQNC NC DQ5

GNC NC DQ13 VDDQVDD VSS VDD VDDQNCNCNC

HNC VREF VDDQVDDQVDD VSS VDD VDDQVDDQVREF ZQ

JNC NC NC VDDQVDD VSS VDD VDDQNC DQ4 NC

KNC NC DQ14 VDDQVDD VSS VDD VDDQNC NC DQ3

LNC DQ15 NC VDDQVSS VSS VSS VDDQNC NC DQ2

MNC NC NC VSS VSS VSS VSS VSS NC DQ1 NC

NNC NC DQ16 VSS SA SA SA VSS NC NC NC

PNC NC DQ17 SA SA CSA SA NC NC DQ0

RTDO TCK SA SA SA C# SA SA SA TMS TDI

512K x 36 BALL ASSIGNMENT (TOP VIEW)

165-BALL FBGA

1234567891011

ACQ# VSS NC/SA* R/W# BW2# K# BW1# LD# SA VSS CQ

BNC DQ27 DQ18 SA BW3# K BW0# SA NC NC DQ8

CNC NC DQ28 VSS SA SA0 SA1 VSS NC DQ17 DQ7

DNC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16

ENC NC DQ20 VDDQVSS VSS VSS VDDQNCDQ15 DQ6

FNC DQ30 DQ21 VDDQVDD VSS VDD VDDQNC NC DQ5

GNC DQ31 DQ22 VDDQVDD VSS VDD VDDQNC NCDQ14

HNC VREF VDDQVDDQVDD VSS VDD VDDQVDDQVREF ZQ

JNC NC DQ32 VDDQVDD VSS VDD VDDQNCDQ13 DQ4

KNC NC DQ23 VDDQVDD VSS VDD VDDQNCDQ12 DQ3

LNC DQ33 DQ24 VDDQVSS VSS VSS VDDQNC NC DQ2

MNC NC DQ34 VSS VSS VSS VSS VSS NC DQ11 DQ1

NNC DQ35 DQ25 VSS SA SA SA VSS NC NC DQ10

PNC NC DQ26 SA SA CSA SA NC DQ9 DQ0

RTDO TCK SA SA SA C# SA SA SA TMS TDI

*Expansion addresses: 3A for 36Mb.

NOTE: BW0# controls writes to DQ0:DQ8. BW1# controls writes to DQ9:DQ17. BW2# controls writes to DQ18:DQ26. BW3#

controls writes to DQ27:DQ35.

2.5V VDD, HSTL, Pipelined DDRb4 SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, PIPELINED DDRb4 SRAM

BALL DESCRIPTIONS

SYMBOL TYPE DESCRIPTION

SA0 Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold

times around the rising edge of K. Balls 3A and 9A are reserved for the next higher-order

address inputs on the 36Mb device. SA0 and SA1 are used as the lowest address bits for

BURST READ and BURST WRITE operations. These inputs are ignored when device is

deselected or once BURST operation is in progress.

LD# Input Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined.

This definition includes address and read/write direction. All transactions operate on a burst

of 2 data (one clock periods of bus activity).

R/W# Input Synchronous Read/Write Input: When LD# is LOW, this input designates the access type

(READ when R/W# is HIGH, WRITE when R/W# is LOW) for the loaded address. R/W# must

meet the setup and hold times around the rising edge of K.

BW_# Input Synchronous Byte Writes: When LOW, these inputs cause their respective byte to be

registered and written during WRITE cycles. These signals must meet setup and hold times

around the rising edges of K and K# for each of the two rising edges comprising the WRITE

cycle. See ball assignment figures for signal to data relationships.

K Input Input Clock: This input clock pair registers address and control inputs on the rising edge of

K# K, and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180

degrees out of phase with K. All synchronous inputs must meet setup and hold times

around the clock rising edges.

C Input Output Clock: This clock pair provides a user controlled means of tuning device output

C# data. The rising edge of C is used as the output timing reference for first and third output

data. The rising edge of C# is used as the output reference for second and fourth output

data. Ideally, C# is 180 degrees out of phase with C. C and C# may be tied HIGH to force the

use of K and K# as the output reference clocks instead of having to provide C and C# clocks.

If tied HIGH, C and C# must remain HIGH and not be toggled during device operation.

ZQ Input Output Impedance Matching Input: This input is used to tune the device outputs to the

system data bus impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is

a resistor from this bump to ground. Alternately, this ball can be connected directly to

VDDQ, which enables the minimum impedance mode. This ball cannot be connected directly

to GND or left unconnected.

TMS Input IEEE 1149.1 Test Inputs: JEDEC-standard 2.5V I/O levels. These balls may be left Not

TDI Connected if the JTAG function is not used in the circuit.

TCK Input IEEE 1149.1 Clock Input: JEDEC-standard 2.5V I/O levels. This ball must be tied to VSS if the

JTAG function is not used in the circuit.

VREF Input HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the input

buffers.

DQ_ Input/ Synchronous Data IOs: Input data must meet setup and hold times around the rising edges

Output of K and K#. Output data is synchronized to the respective C and C# data clocks or to K and

K# if C and C# are tied to HIGH. See Ball Assignment figures for ball site location of

individual signals. The x18 device uses DQ0–DQ17. Remaining signals are NC. The x36

device uses DQ0–DQ35.

CQ Output Echo Clocks:

CQ#

(continued on next page)

2.5V VDD, HSTL, Pipelined DDRb4 SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, PIPELINED DDRb4 SRAM

BALL DESCRIPTIONS (continued)

SYMBOL TYPE DESCRIPTION

TDO Output IEEE 1149.1 Test Output: JEDEC-standard 2.5V I/O level.

VDD Supply Power Supply: 2.5V nominal. See DC Electrical Characteristics and Operating Conditions for

range.

VDDQ Supply Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. See DC Electrical Characteris-

tics and Operating Conditions for range.

VSS Supply Power Supply: GND.

NC – No Connect: These signals are internally connected and appear in the JTAG scan chain as a

logic “0.” These signals may be connected to ground to improve package heat dissipation.

2.5V VDD, HSTL, Pipelined DDRb4 SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, PIPELINED DDRb4 SRAM

LINEAR BURST ADDRESS TABLE

FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)

X...X00 X...X01 X...X10 X...X11

X...X01 X...X10 X...X11 X...X00

X...X10 X...X11 X...X00 X...X01

X...X11 X...X00 X...X01 X...X10

BUS CYCLE STATE DIAGRAM

NOTE: 1. SA0 and SA1 are internally advanced in accordance with the burst order table. Bus cycle is terminated after burst

count = 4.

2. State transitions: L = (LD# = LOW); L# = (LD# = HIGH); R = (R/W# = HIGH); W = (R/W# = LOW).

3. State machine control timing sequence is controlled by K.

LOAD NEW ADDRESS

Count=0

READ DOUBLE

Count=Count+2

ADVANCE ADDRESS

BY TWO1

WRITE DOUBLE

Count=Count+2

ADVANCE ADDRESS

BY TWO1POWER-UP

Supply

voltage

provided

NOP

L, Count=4

Count=2

always

Count=2

always

L#, Count=4

2.5V VDD, HSTL, Pipelined DDRb4 SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, PIPELINED DDRb4 SRAM

BYTE WRITE OPERATION

(Notes 7, 8)

OPERATION K K# BW0# BW1#

WRITE D0–17 at K rising edge L®H00

WRITE D0–17 at K# rising edge L®H0 0

WRITE D0–8 at K rising edge L®H01

WRITE D0–8 at K# rising edge L®H0 1

WRITE D9–17 at K rising edge L®H10

WRITE D9–17 at K# rising edge L®H1 0

WRITE nothing at K rising edge L®H11

WRITE nothing at K# rising edge L®H1 1

NOTE: 1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.  means rising edge; ¯ means falling edge.

2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges except if C

and C# are HIGH then data outputs are delivered at K and K# rising edges.

3. R/W# and LD# must meet setup/hold times around the rising edge (LOW to HIGH) of K and are registered at the rising

edge of K.

4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

5. Refer to state diagram and timing diagrams for clarification. A1 refers to the address input during a WRITE or READ

cycle. A2 refers to the next internal burst address in accordance with the burst sequence.

6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most rapid restart by

overcoming transmission line charging symmetrically.

7. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST WRITE operation

provided that the setup and hold requirements are satisfied.

8. This table illustrates operation for x18 devices. the x36 device operation is similar except for the addition of BW2#

(controls D18–D26) and BW3# (controls D27–D35).

TRUTH TABLE

(Notes 1–6)

OPERATION LD# R/W# K DQ DQ DQ DQ

WRITE Cycle: Load address, L L L®HDIN(A1) DIN(A2) DIN(A3) DIN(A4)

input write data on two at at at at

consecutive K and K# rising edges K(t+1)K#(t+1)K(t+2)K#(t+2)

READ Cycle: Load address, L H L®HQOUT(A1) QOUT(A2) QOUT(A3) QOUT(A4)

read data on two consecutive at at at at

C and C# rising edges C#(t+1)C(t+2)C#(t+2)C(t+3)

NOP: No operation H X L®H High-Z High-Z High-Z High-Z

STANDBY: Clock stopped X X Stopped Previous Previous Previous Previous

State State State State

2.5V VDD, HSTL, Pipelined DDRb4 SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, PIPELINED DDRb4 SRAM

ABSOLUTE MAXIMUM RATINGS*

Voltage on VDD Supply

Relative to VSS .......................................... -0.5V to 2.9V

Voltage on VDDQ Supply

Relative to VSS ........................................... -0.5V to VDD

VIN .......................................................... -0.5V to VDD + 0.5V

Storage Temperature ............................... -55°C to +125°C

Junction Temperature** ......................................... +125°C

Short Circuit Output Current ................................ ±70mA

*Stresses greater than those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the de-

vice. This is a stress rating only, and functional operation

of the device at these or any other conditions above those

indicated in the operational sections of this specification

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

** Junction temperature depends upon package type, cycle

time, loading, ambient temperature and airflow. See Mi-

cron Technical Note TN-05-14 for more information.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(+20°C £ TJ £ +110°C; +2.4V £ VDD £ +2.6V unless otherwise noted)

DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES

Input High (Logic 1) Voltage VIH (DC)VREF + 0.1 VDDQ + 0.3 V 3, 4

Input Low (Logic 0) Voltage VIL (DC) -0.3 VREF - 0.1 V 3, 4

Clock Input Signal Voltage VIN -0.3 VDDQ + 0.3 V 3, 4

Input Leakage Current 0V £ VIN £ VDDQILI-5 5 µA

Output Leakage Current Output(s) disabled, ILO-5 5 µA

0V £ VIN £ VDDQ (Q)

Output High Voltage |IOH| £ 0.1mA VOH (LOW)VDDQ - 0.2 VDDQ V 3, 5, 7

Note 1 VOH VDDQ/2 - 0.12 VDDQ/2 + 0.12 V 3, 5, 7

Output Low Voltage IOL £ 0.1mA VOL (LOW)VSS 0.2 V 3, 5, 7

Note 2 VOL VDDQ/2 - 0.12 VDDQ/2 + 0.12 V 3, 5, 7

Supply Voltage VDD 2.4 2.6 V 3

Isolated Output Buffer Supply VDDQ 1.4 1.9 V 3, 6

Reference Voltage VREF 0.68 0.95 V 3

NOTE: 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) for values of 175W £ RQ £ 350W.

2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175W £ RQ £ 350W.

3. All voltages referenced to VSS (GND).

4. Overshoot: VIH (AC) £ VDD + 0.7V for t £ tKHKH/2

Undershoot: VIL (AC) ³ -0.5V for t £ tKHKH/2

Power-up: VIH £ VDDQ + 0.3V and VDD £ 2.4V and VDDQ £ 1.4V for t £ 200ms

During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less than tKHKL

(MIN) or operate at cycle rates less than tKHKH (MIN).

5. AC load current is higher than the shown DC values. AC I/O curves are available upon request.

6. For higher VDDQ voltages, contact factory for product information.

7. HSTL outputs meet JEDEC HSTL Class I and Class II standards.

8. To maintain a valid level, the transitioning edge of the input must:

a. Sustain a constant slew rate from the current AC level through the target AC level, VIL (AC) or VIH (AC).

b. Reach at least the target AC level.

c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC).

AC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(+20°C £ TJ £ +110°C; +2.4V £ VDD £ +2.6V unless otherwise noted)

DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES

Input High (Logic 1) Voltage VIH (AC)VREF + 0.2 – V 3, 4, 8

Input Low (Logic 0) Voltage VIL (AC)– VREF - 0.2 V 3, 4, 8

2.5V VDD, HSTL, Pipelined DDRb4 SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

1 MEG x 18, 512K x 36

2.5V VDD, HSTL, PIPELINED DDRb4 SRAM

NOTE: 1. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and

greater output loading. Typical value is measured at 6ns cycle time.

2. Typical values are measured at VDD = 2.5V, VDDQ = 1.5V and temperature = 25°C.

3. Operating supply currents and burst mode currents are calculated with 50 percent READ cycles and 50 percent WRITE

cycles.

4. NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed.

5. Average I/O current and power is provided for information purposes only and is not tested. Calculation assumes that

all outputs are loaded with CL (in farads), half of outputs toggle at each transition (n = 36), VDDQ = 1.5V and uses the

equations: Average I/O Power as dissipated by the SRAM is:

P = 0.5 × n × f × CL × VDDQ2. Average IDDQ = n × f × CL × VDDQ.

6. This parameter is sampled.

7. Average thermal resistance between the die and the case top surface per MIL SPEC 883 Method 1012.1.

8. Junction temperature is a function of total device power dissipation and device mounting environment. Measured per

SEMI G38-87.

MAX

IDD OPERATING CONDITIONS AND MAXIMUM LIMITS

(+20°C £ TJ £ +110°C; VDD = MAX unless otherwise noted)

DESCRIPTION CONDITIONS SYMBOL TYP -5 -6 -7.5 UNITS NOTES

Operating Supply All inputs £ VIL or ³ VIH;IDD 1, 2,

Current: DDR Cycle time ³ tKHKH (MIN); (x18) TBD 225 200 175 mA 3

Outputs open (x36) 300 260 225

Standby Supply tKHKH = tKHKH (MIN); ISB12, 4

Current: NOP Device in NOP state; (x18) TBD 170 150 125 mA

All addresses/data static (x36) 180 160 135

Stop Clock Current Cycle time = 0; Inputs static ISB TBD 75 75 75 mA 2

Output Supply Current: CL = 15pF IDDQ5

DDR (For information (x18) – 41 34 28 mA

only) (x36) 81 68 55

THERMAL RESISTANCE

DESCRIPTION CONDITIONS SYM TYP UNITS NOTES

Junction to Ambient (Airflow of 1m/s) Soldered on a 4.25 x 1.125 inch, qJA 25 °C/W 6, 7

Junction to Case (Top) 4-layer printed circuit board qJC 10 °C/W 6

Junction to Balls (Bottom) qJB 12 °C/W 6, 8

CAPACITANCE

DESCRIPTION CONDITIONS SYM TYP MAX UNITS NOTES

Address/Control Input Capacitance CI45pF6

Input/Output Capacitance (DQ) TA = 25°C; f = 1 MHz CO67pF6

Clock Capacitance CCK 56pF6

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NOTE: 1. This parameter is sampled.

2. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold times for all

latching clock edges.

3. Test conditions as specified with the output loading as shown in Figure 1 unless otherwise noted.

4. Control input signals may not be operated with pulse widths less than tKHKL (MIN).

5. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.

6. Transition is measured ±100mV from steady state voltage.

7. tCHQXI is greater than tCHQZ at any given voltage and temperature.

DESCRIPTION

AC ELECTRICAL CHARACTERISTICS

(Notes 4, 5) (+20°C £ TJ £ 110°C; +2.4V £ VDD £ +2.6V)

-5 -6 -7.5

SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES

Clock

Clock cycle time (K, K#, C, C#) tKHKH 5.0 6.0 7.5 ns

Clock HIGH time (K, K#, C, C#) tKHKL 2.0 2.4 3.0 ns

Clock LOW time (K, K#, C, C#) tKLKH 2.0 2.4 3.0 ns

Clock to clock# (K®K#, C®C#)tKHK#H 2.4 2.8 3.4 ns

Clock# to clock (K#®K, C#®C)tK#HKH 2.4 2.8 3.4 ns

Clock to data clock (K®C, K#®C#)tKHCH 0.0 1.5 0.0 2.0 0.0 2.5 ns

Output Times

C, C# HIGH to output valid tCHQV 2.4 3.0 3.6 ns

C, C# HIGH to output hold tCHQX 0.8 0.8 ns

C HIGH to output High-Z tCHQZ 2.4 3.0 3.6 ns 6, 7

C HIGH to output Low-Z tCHQX1 0.8 0.8 0.8 ns 6, 7

C, C# HIGH to CQ, CQ# HIGH tCHCQH 0.8 2.6 0.8 3.2 0.8 3.8 ns

Setup Times

Address valid to K rising edge tAVKH 0.6 0.7 0.8 ns 2

Control inputs valid to K rising edge tIVKH 0.6 0.7 0.8 ns 2

Data-in valid to K, K# rising edge tDVKH 0.6 0.7 0.8 ns 2

Hold Times

K rising edge to address hold tKHAX 0.6 0.7 0.8 ns 2

K rising edge to control inputs hold tKHIX 0.6 0.7 0.8 ns 2

K, K# rising edge to data-in hold tKHDX 0.6 0.7 0.8 ns 2

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AC TEST CONDITIONS

Input pulse levels ............................... 0.25V to 1.25V

Input rise and fall times .................................... 0.7ns

Input timing reference levels ........................... 0.75V

Output reference levels ................................. VDDQ/2

ZQ for 50W impedance ...................................... 250W

Output load ........................................... See Figure 1

50Ω

Q/2

250Ω

Z = 50Ω

SRAM

0.75V

REF

Figure 1

Output Load Equivalent

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READ/WRITE TIMING

NOTE: 1. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0, etc.

2. Outputs are disabled (High-Z) one clock cycle after a NOP.

3. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies it may be

required to prevent bus contention.

12345678910

11 12 13

LD#

R/W#

READ

(burst of 4)

READ

(burst of 4)

READ

(burst of 4)

NOP NOP

(Note 3)

WRITE

(burst of 4)

WRITE

(burst of 4)

tKHKL tKHK#H

tKHCH tCHQV

tKLKH tKHKH

t tKHIX

tAVKH tKHAX

tDVKH

tKHDX

tKHCH

NOP

tDVKH

tKHDX

DON’T CARE UNDEFINED

tCHQX1 tCHQX tCHQZ

IVKH

tKHKL

tCHQX

tKHK#H

tKLKH tKHKH

A4A3

A2A0 A1

D31 D32 D33 D34D21 D22 D23 D24

Q01 Q04

Q02 Q03 Q14

Q13

Q11 Q12

Qx2

tCHQV

tCHQX

CQ#

tCQHQZ

Q41

2.5V VDD, HSTL, Pipelined DDRb4 SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

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IEEE 1149.1 SERIAL BOUNDARY SCAN

(JTAG)

The DDR SRAM incorporates a serial boundary scan

test access port (TAP). This port operates in accordance

with IEEE Standard 1149.1-1990 but does not have the set

of functions required for full 1149.1 compliance. These

functions from the IEEE specification are excluded be-

cause their inclusion places an added delay in the critical

speed path of the SRAM. Note that the TAP controller

functions in a manner that does not conflict with the

operation of other devices using 1149.1 fully compliant

TAPs. The TAP operates using JEDEC-standard 2.5V I/O

logic levels.

The SRAM contains a TAP controller, instruction reg-

ister, boundary scan register, bypass register, and ID

DISABLING THE JTAG FEATURE

It is possible to operate the SRAM without using the

JTAG feature. To disable the TAP controller, TCK must be

tied LOW (VSS) to prevent clocking of the device. TDI and

TMS are internally pulled up and may be unconnected.

They may alternately be connected to VDD through a pull-

up resistor. TDO should be left unconnected. Upon

power-up, the device will come up in a reset state which

will not interfere with the operation of the device.

TEST ACCESS PORT (TAP)

TEST CLOCK (TCK)

The test clock is used only with the TAP controller. All

inputs are captured on the rising edge of TCK. All outputs

are driven from the falling edge of TCK.

TEST MODE SELECT (TMS)

The TMS input is used to give commands to the TAP

controller and is sampled on the rising edge of TCK. It is

allowable to leave this ball unconnected if the TAP is not

used. The ball is pulled up internally, resulting in a logic

HIGH level.

TEST DATA-IN (TDI)

The TDI ball is used to serially input information into

the registers and can be connected to the input of any of

the registers. The register between TDI and TDO is cho-

sen by the instruction that is loaded into the TAP instruc-

tion register. For information on loading the instruction

be unconnected if the TAP is unused in an application.

TDI is connected to the most significant bit (MSB) of any

TEST DATA-OUT (TDO)

The TDO output ball is used to serially clock data-out

from the registers. The output is active depending upon

the current state of the TAP state machine. (See Figure 2.)

The output changes on the falling edge of TCK. TDO is

connected to the least significant bit (LSB) of any regis-

ter. (See Figure 3.)

Figure 2

TAP Controller State Diagram

NOTE: The 0/1 next to each state represents the value of

TMS at the rising edge of TCK.

TEST-LOGIC

RESET

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-DR

CAPTURE-IR

SHIFT-IR

EXIT1-DR

PAUSE-DR

EXIT1-IR

PAUSE-IR

EXIT2-DR

UPDATE-DR

EXIT2-IR

UPDATE-IR

1 1

0 0

1 1

0 0

1 0

Bypass Register

Instruction Register

012

Identification Register

012293031 ...

Boundary Scan Register

012..x ...

Selection

Circuitry

Selection

Circuitry

TCK

TMS

TAP CONTROLLER

TDI TDO

x = 106 for the x8, x18, x36 configuration.

Figure 3

TAP Controller Block Diagram

2.5V VDD, HSTL, Pipelined DDRb4 SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

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PERFORMING A TAP RESET

A RESET is performed by forcing TMS HIGH (VDD) for

five rising edges of TCK. This RESET does not affect the

operation of the SRAM and may be performed while the

SRAM is operating.

At power-up, the TAP is reset internally to ensure that

TDO comes up in a High-Z state.

TAP REGISTERS

Registers are connected between the TDI and TDO

balls and allow data to be scanned into and out of the

SRAM test circuitry. Only one register can be selected at

a time through the instruction register. Data is serially

loaded into the TDI ball on the rising edge of TCK. Data is

output on the TDO ball on the falling edge of TCK.

INSTRUCTION REGISTER

Three-bit instructions can be serially loaded into the

instruction register. This register is loaded when it is

placed between the TDI and TDO balls as shown in Figure

3. Upon power-up, the instruction register is loaded with

the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in the previous section.

When the TAP controller is in the Capture-IR state, the

two least significant bits are loaded with a binary “01”

pattern to allow for fault isolation of the board-level serial

test data path.

BYPASS REGISTER

To save time when serially shifting data through reg-

isters, it is sometimes advantageous to skip certain chips.

The bypass register is a single-bit register that can be

placed between the TDI and TDO balls. This allows data

to be shifted through the SRAM with minimal delay. The

bypass register is set LOW (VSS) when the BYPASS instruc-

tion is executed.

BOUNDARY SCAN REGISTER

The boundary scan register is connected to all the

input and bidirectional balls on the SRAM. Several no

connect (NC) balls are also included in the scan register

to reserve balls. All configurations have a 107-bit-long

The boundary scan register is loaded with the con-

tents of the RAM I/O ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and

TDO balls when the controller is moved to the Shift-DR

state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z

instructions can be used to capture the contents of the

I/O ring.

The Boundary Scan Order tables show the order in

which the bits are connected. Each bit corresponds to

one of the balls on the SRAM package. The MSB of the

TDO.

IDENTIFICATION (ID) REGISTER

The ID register is loaded with a vendor-specific, 32-

bit code during the Capture-DR state when the IDCODE

command is loaded in the instruction register. The

IDCODE is hardwired into the SRAM and can be shifted

out when the TAP controller is in the Shift-DR state. The

ID register has a vendor code and other information

described in the Identification Register Definitions table.

TAP INSTRUCTION SET

OVERVIEW

Eight different instructions are possible with the three-

bit instruction register. All combinations are listed in the

Instruction Codes table. Three of these instructions are

listed as RESERVED and should not be used. The other

five instructions are described in detail below.

The TAP controller used in this SRAM is not fully

compliant to the 1149.1 convention because some of the

mandatory 1149.1 instructions are not fully implemented.

The TAP controller cannot be used to load address, data

or control signals into the SRAM and cannot preload the

I/O buffers. The SRAM does not implement the 1149.1

commands EXTEST or INTEST or the PRELOAD portion

of SAMPLE/PRELOAD; rather, it performs a capture of

the I/O ring when these instructions are executed.

Instructions are loaded into the TAP controller during

the Shift-IR state when the instruction register is placed

between TDI and TDO. During this state, instructions

are shifted through the instruction register through the

TDI and TDO balls. To execute the instruction once it is

shifted in, the TAP controller needs to be moved into the

Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to

be executed whenever the instruction register is loaded

with all 0s. EXTEST is not implemented in the TAP

controller, hence this device is not IEEE 1149.1 compli-

ant.

The TAP controller does recognize an all-0 instruc-

tion. When an EXTEST instruction is loaded into the

instruction register, the SRAM responds as if a SAMPLE/

PRELOAD instruction has been loaded. EXTEST does not

place the SRAM outputs in a High-Z state, CQ, CQ#.

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(metastable state). This will not harm the device, but

there is no guarantee as to the value that will be captured.

Repeatable results may not be possible.

To guarantee that the boundary scan register will

capture the correct value of a signal, the SRAM signal

must be stabilized long enough to meet the TAP

controller’s capture setup plus hold time (tCS plus tCH).

The SRAM clock input might not be captured correctly if

there is no way in a design to stop (or slow) the clock

during a SAMPLE/PRELOAD instruction. If this is an

issue, it is still possible to capture all other signals and

simply ignore the value of the CK and CK# captured in the

boundary scan register.

Once the data is captured, it is possible to shift out the

data by putting the TAP into the Shift-DR state. This places

the boundary scan register between the TDI and TDO

balls.

Note that since the PRELOAD part of the command is

not implemented, putting the TAP to the Update-DR

state while performing a SAMPLE/PRELOAD instruction

will have the same effect as the Pause-DR command.

BYPASS

When the BYPASS instruction is loaded in the instruc-

tion register and the TAP is placed in a Shift-DR state, the

bypass register is placed between TDI and TDO. The

advantage of the BYPASS instruction is that it shortens

the boundary scan path when multiple devices are con-

nected together on a board.

RESERVED

These instruction are not implemented but are re-

served for future use. Do not use these instructions.

IDCODE

The IDCODE instruction causes a vendor-specific,

32-bit code to be loaded into the instruction register. It

also places the instruction register between the TDI and

TDO balls and allows the IDCODE to be shifted out of the

device when the TAP controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction

is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan

when the TAP controller is in a Shift-DR state. It also

places all SRAM outputs into a High-Z state, including

CQ, CQ#.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruc-

tion. The PRELOAD portion of this instruction is not

implemented, so the device TAP controller is not fully

1149.1-compliant.

When the SAMPLE/PRELOAD instruction is loaded

into the instruction register and the TAP controller is in

the Capture-DR state, a snapshot of data on the inputs

and bidirectional balls is captured in the boundary scan

The user must be aware that the TAP controller clock

can only operate at a frequency up to 10 MHz, while the

SRAM clock operates more than an order of magnitude

faster. Because there is a large difference in the clock

frequencies, it is possible that during the Capture-DR

state, an input or output will undergo a transition. The

TAP may then try to capture a signal while in transition

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tTLTH

Test Clock

(TCK)

123456

Test Mode Select

(TMS)

tTHTL

Test Data-Out

(TDO)

tTHTH

Test Data-In

(TDI)

tTHMX

tMVTH

tTHDX

tDVTH

tTLOX

tTLOV

DON’T CARE UNDEFINED

TAP TIMING

TAP AC ELECTRICAL CHARACTERISTICS

(Notes 1, 2) (+20°C £ TJ £ +100°C, +2.4V £ VDD £ +2.6V)

DESCRIPTION SYMBOL MIN MAX UNITS

Clock

Clock cycle time tTHTH 100 ns

Clock frequency fTF 10 MHz

Clock HIGH time tTHTL 40 ns

Clock LOW time tTLTH 40 ns

Output Times

TCK LOW to TDO unknown tTLOX 0 ns

TCK LOW to TDO valid tTLOV 20 ns

TDI valid to TCK HIGH tDVTH 10 ns

TCK HIGH to TDI invalid tTHDX 10 ns

Setup Times

TMS setup tMVTH 10 ns

Capture setup tCS 10 ns

Hold Times

TMS hold tTHMX 10 ns

Capture hold tCH 10 ns

NOTE: 1. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

2. Test conditions are specified using the load in Figure 4.

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TAP AC TEST CONDITIONS

Input pulse levels ...................................... VSS to 2.5V

Input rise and fall times ....................................... 1ns

Input timing reference levels ............................. 1.25

Output reference levels ....................................1.25V

Test load termination supply voltage ..............1.25V

TDO

20pF

Z = 50Ω

50Ω

Figure 4

TAP AC Output Load Equivalent

TAP DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(+20°C £ TJ £ 110°C, +2.4V £ VDD £ +2.6V unless otherwise noted)

DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES

Input High (Logic 1) Voltage VIH 1.7 VDD + 0.3 V 1, 2

Input Low (Logic 0) Voltage VIL -0.3 0.7 V 1, 2

Input Leakage Current 0V £ VIN £ VDD ILI-5.0 5.0 µA

Output Leakage Current Output(s) disabled, ILO-5.0 5.0 µA

0V £ VIN £ VDDQ

Output Low Voltage IOLC = 100µA VOL10.2 V 1

Output Low Voltage IOLT = 2mA VOL20.7 V 1

Output High Voltage |IOHC| = 100µA VOH12.1 V 1

Output High Voltage |IOHT| = 2mA VOH21.7 V 1

NOTE: 1. All voltages referenced to VSS (GND).

2. Overshoot: VIH (AC) £ VDD + 1.5V for t £ tKHKH/2

Undershoot: VIL (AC) ³ -0.5V for t £ tKHKH/2

Power-up: VIH £ +2.6 and VDD £ 2.4V and VDDQ £ 1.4V for t £ 200ms

During normal operation, VDDQ must not exceed VDD. Control input signals (such as LD#, R/W#, etc.) may not have

pulse widths less than tKHKL (MIN) or operate at frequencies exceeding fKF (MAX).

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INSTRUCTION CODES

INSTRUCTION CODE DESCRIPTION

EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and

TDO. This instruction is not 1149.1-compliant. This operation does not affect

SRAM operations.

IDCODE 001 Loads the ID register with the vendor ID code and places the register between

TDI and TDO. This operation does not affect SRAM operations.

SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and

TDO. Forces all SRAM output drivers to a High-Z state.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and

TDO. This instruction does not implement 1149.1 preload function and is

therefore not 1149.1-compliant.

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect

SRAM operations.

IDENTIFICATION REGISTER DEFINITIONS

INSTRUCTION FIELD ALL DEVICES DESCRIPTION

REVISION NUMBER 000 Version number.

(31:29)

DEVICE ID 00def0wx000q0b0s0 def = 001 for 18Mb density

(28:12) wx = 11 for x36, 10 for x18, 01 for x8

q = 1 for QDR, 0 for DDR

b = 1 for 4-word burst, 0 for 2-word burst

s = 1 for separate I/O, 0 for common I/O

MICRON JEDEC ID 00000101100 Allows unique identification of SRAM vendor.

CODE (11:1)

ID Register Presence 1 Indicates the presence of an ID register.

Indicator (0)

SCAN REGISTER SIZES

Instruction 3

Bypass 1

ID 32

Boundary Scan 107

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BOUNDARY SCAN (EXIT) ORDER

NOTE: For NC balls in the range of 2B–2P, 3B–3P, 4B–4P, 9B–9P, 10B–10P, and 11B–11P, a logic “0” will be read from the chain.

All other NC balls will be an unknown value.

37 10D

38 9E

39 10C

40 11D

41 9C

42 9D

43 11B

44 11C

45 9B

46 10B

47 11A

48 10A

49 9A

50 8B

51 7C

52 6C

53 8A

54 7A

55 7B

56 6B

57 6A

58 5B

59 5A

60 4A

61 5C

62 4B

63 3A

64 2A

65 1A

66 2B

67 3B

68 1C

69 1B

70 3D

71 3C

72 1D

BIT# FBGA BALL BIT# FBGA BALL

73 2C

74 3E

75 2D

76 2E

77 1E

78 2F

79 3F

80 1G

81 1F

82 3G

83 2G

84 1J

85 2J

86 3K

87 3J

88 2K

89 1K

90 2L

91 3L

92 1M

93 1L

94 3N

95 3M

96 1N

97 2M

98 3P

99 2N

100 2P

101 1P

102 3R

103 4R

104 4P

105 5P

106 5N

107 5R

BIT# FBGA BALL

16R

26P

36N

47P

57N

67R

78R

88P

99R

10 11P

11 10P

12 10N

13 9P

14 10M

15 11N

16 9M

17 9N

18 11L

19 11M

20 9L

21 10L

22 11K

23 10K

24 9J

25 9K

26 10J

27 11J

28 11H

29 10G

30 9G

31 11F

32 11G

33 9F

34 10F

35 11E

36 10E

2.5V VDD, HSTL, Pipelined DDRb4 SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.

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2.5V VDD, HSTL, PIPELINED DDRb4 SRAM

165-BALL FBGA

NOTE: 1. All dimensions in millimeters.

2. Molding dimensions do not include protrusion; allowable mold protrusion is 0.25mm per side.

3. Dimensions apply to solder balls post reflow

10.00

14.00

15.00 ±0.10

1.00

TYP

1.00

TYP

5.00 ±0.05

13.00 ±0.10

PIN A1 ID

BALL A1

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

6.50 ±0.05

7.00 ±0.05

7.50 ±0.05

1.20 MAX

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb

SOLDER BALL PAD: Ø .33mm

SOLDER BALL DIAMETER REFERS

TO POST REFLOW CONDITION. THE

PRE-REFLOW DIAMETER IS Ø 0.40

SEATING PLANE

0.85 ±0.075

0.12 C

165X Ø 0.45

BALL A11

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.

Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc.

DATA SHEET DESIGNATION

Advance: This data sheet contains initial descriptions of products still under development.

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ADVANCE

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2.5V VDD, HSTL, PIPELINED DDRb4 SRAM

REVISION HISTORY

Rev. 4, Pub. 5/02, ADVANCE .................................................................................................................................................. 5/02

• Fixed voltage range error in AC Electrical Characteristics and Operating Conditions table

Rev. 3, Pub. 5/02, ADVANCE .................................................................................................................................................. 5/02

• Updated DC Electrical Characteristics and Operating Conditions table

• Added AC Electrical Characteristics and Operating Conditions table

Rev. 2, Pub. 5/02 ....................................................................................................................................................................... 5/02

• Made corrections to the 512K x 36 Ball Assignment table

Original document, ADVANCE .............................................................................................................................................. 3/02