ADVANCED INFORMATION MX69F162/164C3BT/B 16M-BIT [X16] FLASH AND 2M-BIT/4M-BIT [X16] SRAM MIXED MULTI CHIP PACKAGE MEMORY FEATURES * Supply voltage range: 2.7V to 3.6V * Fast access time: Flash memory:70/90ns SRAM memory:70/85ns * Operation temperature range: -40 ~ 85 C * Fully compatible with MX69F1602/1604C3T/B device * * * FLASH * Word mode only * VCCf=VCCQ=2.7V~3.6V for read, erase and program operation * VPP=12V for fast production programming * Low power consumption - 9mA typical active read current, f=5MHz - 18mA typical program current (VPP=1.65~3.6V) - 21mA typical erase current (VPP=1.65~3.6V) - 7uA typical standby current under power saving mode * Sector architecture - Sector structure : 4Kword x 2 (boot sectors), 4Kword x 6 (parameter sectors), 32Kword x 31 (main sectors) - Top/Bottom Boot * Auto Erase and Auto Program - Automatically program and verify data at specified address - Auto sector erase at specified sector * Automatic Suspend Enhance * * * * * - Word write suspend to read - Sector erase suspend to word write - Sector erase suspend to read register report Automatic sector erase, word write and sector lock/ unlock configuration 100,000 minimum erase/program cycles Boot Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector Status Register feature for detection of program or erase cycle completion Data protection performance - Sectors to be locked/unlocked Common Flash Interface (CFI) 128-bit Protection Register - 64-bit Unique Device Identifier - 64-bit User-Programmable Latch-up protected to 100mA from -1V to VCC+1V SRAM * * * * * * P/N:PM1083 MX69F162C3BT/B: 128K wordx16 Bit MX69F164C3BT/B: 256K wordx16 Bit 70mA maximum active current 1uA typical standby current Data retention supply voltage: 2.0V~3.6V Byte data control : LBs#(Q0 to Q7) and UBs#(Q8 to Q15) REV. 0.2, MAY 20, 2004 1 MX69F162/164C3BT/B erases one of the device's 32K-word sectors typically within 1.0s, 4K-word sectors typically within 0.5s independent of other sectors. Each sector can be independently erased minimum 100,000 times. Sector erase suspend mode allows system software to suspend sector erase to read or write data from any other sector. GENERAL DESCRIPTION The MXIC's mixed multi chip memory combines Flash and SRAM into a single package. The mixed multi chip memory operates 2.7 to 3.6V power supply to allow for simple in-system operation. Flash program automation allows program operation to be executed using an industry-standard two-write command sequence to the CUI. Writing memory data is performed in word increments of the device's 32K-word sectors typically within 0.8s and 4K-word sectors typically within 0.1s. Word program suspend mode enables the system to read data or execute code from any other memory array location. The Flash memory of mixed multi chip memory manufactured with MXIC's advanced nonvolatile memory technology, the flash memory of mixed multi chip memory is designed to be re-programmed and erased in system or in standard EPROM programmers. The device offers access times of 70ns/90ns, and 7uA typical standby current. Flash memories augment EPROM functionality with incircuit electrical erasure and programming and use a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. The Flash features with individual sectors locking by using a combination of thirty-nine sector lock-bits and WP#, to lock and unlock sectors. The Flash status register indicates the status of the WSM when the sector erase, word program or lock configuration operation is done. Flash memory reliably stores memory contents even after 100,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cycling. The Flash power saving mode feature substantially reduces active current when the device is in static mode (addresses not switching). In this mode, the typical ICCS current is 7uA (CMOS) at 3.0V VCC. As CEf# and RESET# are at VCC, ICC CMOS standby mode is enabled. When RESET# is at GND, the reset mode is enabled which minimize power consumption and provide data write protection. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamperes on address and data pin from -1V to VCC + 1V. The Flash require a reset time (tPHQV) from RESET# switching high until outputs are valid. Similarly, the flash has a wake time (tPHEL) from RESET#-high until writes to the CUI are recognized. With RESET# at GND, the WSM is reset and the status register is cleared. The dedicated VPP pin gives complete data protection when VPP< VPPLK. The Flash contains both a Command User Interface (CUI) and a Write State Machine (WSM). A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for erase, word write and sector lock/unlock configuration operations. The 2M-bit SRAM of MX69F162C3BT/B is organized as 128K-word by 16-bit. The 4M-bit SRAM of MX69F164C3BT/B is organized 256K-word by 16-bit. The advanced CMOS technology and circuit techniques provide both high speed and low power features of with a typical CMOS standby current of 1uA and maximum access time of 70ns/85ns in 3V operation. The mixed multi chip memory is available in 11mm x 8mm FBGA Package to suit a variety of design applications. Flash erase automation allows sector erase operation to be executed using an industry-standard two-write command sequence to the CUI. A sector erase operation REV. 0.2, MAY 20, 2004 P/N:PM1083 2 MX69F162/164C3BT/B Feature Summary Feature MX69F162/164C3BT/B Vcc Operating Voltage 2.7~3.6V Configuration Flash 16M:1M Word x16bit SRAM MX69F162C3BT/B:128K Word x16bit MX69F164C3BT/B:256K Word x16bit Fast Access Time Block Architecture - 70 : Flash/70ns, SRAM/70ns - 90 : Flash/90ns, SRAM/85ns Flash 2 x 4K Word Boot 6 x 4K Word Parameter 31 x 32K Word Main Address Pin Flash A0~A19 SRAM MX69F162C3BT/B:A0~A16 MX69F164C3BT/B:A0~A17 Manufacture Code Flash 00C2H Device ID Code Flash MX69F162/164C3BT=88C2H MX69F162/164C3BB=88C3H REV. 0.2, MAY 20, 2004 P/N:PM1083 3 MX69F162/164C3BT/B PIN ASSIGNMENT 66-ball CSP for MX69F162/164C3BT/B (Top View Balls Down, 11 x 8 x 1.4mm, Ball Pitch=0.8mm) A NC A11 A15 A14 A13 A12 GNDf VCCQ B A16 A8 A10 A9 Q15 WEs# Q14 Q7 C WEf# NC Q13 Q6 Q4 Q5 D GNDs RESET# Q12 CE2s VCCs VCCf E WP# VPP A19 Q10 Q2 Q3 F LBs# UBs# OEs# Q9 Q8 Q0 Q1 G A18 A17 A7 A6 A3 A2 A1 CE1 s# CEf# GNDf OEf# NC H NC NC Q11 NC NC NC A5 A4 A0 1 2 3 4 5 6 7 8 9 10 NC NC 8.0 mm NC NC 11 12 11.0 mm Notes: 1.To maintain compatibility with all JEDEC Variation B options for this ball location C6, this C6 land pad should be connected directly to the land pad for ball G4 (A17). PIN DESCRIPTION SYMBOL A0 to A16 A0 to A17 A17 to A19 A18 to A19 Q0 to Q15 CEf# CE1s# CE2s OEf# OEs# PIN NAME Address Inputs (Common) for MX69F162C3BT/B Address Inputs (Common) for MX69F164C3BT/B Address Input (Flash) for MX69F162C3BT/B Address Input (Flash) for MX69F164C3BT/B Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable (SRAM) Chip Enable (SRAM) Output Enable (Flash) Output Enable (SRAM) SYMBOL WEf# WEs# UBs# LBs# RESET# WP# N.C. GND VCCf VCCs VPP VCCQ PIN NAME Write Enable (Flash) Write Enable (SRAM) Upper Byte Control (SRAM) Lower Byte Control (SRAM) Hardware Reset Pin/Deep Power Down (Flash) Write Protect No Connection Ground Pin (Common) Power Supply (Flash, 2.7V~3.6V) Power Supply (SRAM, 2.7V~3.6V) Program/Erase Power Supply (1.65V~3.6V or 11.4V~12.6V) I/O Power Supply (Flash) tied to VCCf REV. 0.2, MAY 20, 2004 P/N:PM1083 4 MX69F162/164C3BT/B BLOCK DIAGRAM for MX69F162/164C3BT/B VCCf VPP GND VCCQ A0~A19 A0~A19 CEf# OEf# 1MWx16bit (16M) WEf# Q0 to Q15 Flash Memory RESET# WP# Q0 to Q15 Vccs GND A0~A16/A0~A17 CE1s# CE2s OEs# 2M/4M bit WEs# Static RAM Q0 to Q15 UBs# LBs# REV. 0.2, MAY 20, 2004 P/N:PM1083 5 MX69F162/164C3BT/B DEVICE BUS OPERATIONS for MX69F162/164C3BT/B Notes CEf# OEf# WEf# CE1s# CE2s OEs#WEs# LBs# (1) Full Standby 3,4 Flash Output Disable 3,4 Array H L L Read Query L X H L L X H H H from Flash Configuration L Status L L L H H Register Write to Flash Reset SRAM Output 5,7 3,4,6 3,4 L X H H X X L X X (1) (1) H X X L H X X L H X X L H X X L H X X L H X X L H X X L H X X L L H Disable Read from SRAM Write to SRAM H H X X X X L L H H UBs# Q0~ Q8~ Q7 RE- Q15 SET# X X X X High Z High Z H X X X X High Z High Z H X X X X Dout Dout H X X X X Dout Dout H X X X X ID(2) ID(2) H X X X X Dout Dout H X X X X Din Din H X X X X High Z High Z L H H X X High Z High Z H X X H H L H L L Dout Dout H H L High Z Dout H L H Dout High Z H L L Din Din H H L X Din H L H Din X H H L Legend: L=VIL, H=VIH, X at control pins=VIL or VIH. See "ELECTRIAL CHARACTERISTICS 1.DC Characteristics" for voltage levels. Notes: 1. Do not apply CEf#=VIL, CE1s#=VIL and CE2s=VIH at a time. 2. ID=Device Identifier Code. See "Table 3. Configuration Code" 3. Outputs are dependent on a seperate device controlling bus output. 4. Modes of the flash and SRAM can be interleaved so that while one is disabled the other controls outputs. 5. To program or erase the lockable sectors hold WP# at VIH. 6. RESET# at GND 0.2V to ensure the lowest power consumption. 7. Refer to Table 2 for valid Din during a write operation. REV. 0.2, MAY 20, 2004 P/N:PM1083 6 MX69F162/164C3BT/B These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operation Conditions" may affect device reliability. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Operating Temperature During Read, Sector Erase, Word Write . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC Storage Temperature . . . . . . . . . . . . . .-65oC to +125oC Voltage on Any Ball (except VCCf, VCCs, VCCQ and VPP) with respect to GND . . . . . . . . .-0.5 V to VCC+0.5(1) VPP Supply Voltage (for Sector Erase and Word Write) with respect to GND . . . . . . . . . .-0.5V to +13.5V(1,2,4) VCCf, VCCs and VCCQ Supply Voltage with respect to GND. . . . . . . . . . . . . . . . .-0.2V to +4.0V(1) Output Short Circuit Voltage . . . . . . . . . . . . .100mA(3) 1. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output balls to VCCf/VCCs/VCCQ+0.5V which during transition; may overshoot to VCCf/VCCs/VCCQ+2.0V for periods <20ns. 2. Maximum DC voltage on VPP may overshoot to +14.0V for periods <20ns. 3. Output shorted for no more than one second. No more than one output shorted at a time. 4. VPP voltage is normally 1.65V~3.6V. Connection to supply of 11.4V~12.6V can only be done for 1000 cycles on the main sectors and 2500 cycles on the parameter sectors during program/erase. VPP may be connected to 12V for a total of 80 hours maximum. WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. Operating Conditions (Temperature and VCC Operating Conditions) Symbol Parameter Min. Max. Unit Notes TA Operating Temperature -40 +85 o VCCf Flash VCC Supply Voltage 2.7 3.6 V VCCs SRAM VCC Supply Voltage 2.7 3.6 V VCCQ Flash I/O Supply Voltage 2.7 3.6 V 1 VPP1 Supply Voltage 1.65 3.6 V 1 VPP2 Supply Voltage 11.4 12.6 V 1,2 Cycling Sector Erase Cycling C 100,000 1 2 NOTE: 1.VCCf and VCCQ must share the same supply. 2.Applying VPP=11.4~12.6V during a program/erase can only be done for a maximum of 1000 cycles on the main sectors and 2500 cycles on the parameter sectors. VPP may be connected to 12V for a total of 80 hours maximum. Capacitance (1) (TA=+25oC, f=1MHz) Symbol Parameter Typ. Max. Unit CIN COUT Test Condition Input Capacitance 16 18 pF VIN=0.0V Output Capacitance 20 22 pF VOUT=0.0V NOTE: 1.Sampled, not 100% tested. REV. 0.2, MAY 20, 2004 P/N:PM1083 7 MX69F162/164C3BT/B FLASH SECTOR STRUCTURE (MX69F162/164C3BT) Sector Boot Sector 0 Boot Sector 1 Parameter Sector 0 Parameter Sector 1 Parameter Sector 2 Parameter Sector 3 Parameter Sector 4 Parameter Sector 5 Main Sector 0 Main Sector 1 Main Sector 2 Main Sector 3 Main Sector 4 Main Sector 5 Main Sector 6 Main Sector 7 Main Sector 8 Main Sector 9 Main Sector 10 Main Sector 11 Main Sector 12 Main Sector 13 Main Sector 14 Main Sector 15 Main Sector 16 Main Sector 17 Main Sector 18 Main Sector 19 Main Sector 20 Main Sector 21 Main Sector 22 Main Sector 23 Main Sector 24 Main Sector 25 Main Sector 26 Main Sector 27 Main Sector 28 Main Sector 29 Main Sector 30 Sector Size 4K Word 4K Word 4K Word 4K Word 4K Word 4K Word 4K Word 4K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word Address Range (h) FF000 ~ FFFFF FE000 ~ FEFFF FD000 ~ FDFFF FC000 ~ FCFFF FB000 ~ FBFFF FA000 ~ FAFFF F9000 ~ F9FFF F8000 ~ F8FFF F0000 ~ F7FFF E8000 ~ EFFFF E0000 ~ E7FFF D8000 ~ DFFFF D0000 ~ D7FFF C8000 ~ CFFFF C0000 ~ C7FFF B8000 ~ BFFFF B0000 ~ B7FFF A8000 ~ AFFFF A0000 ~ A7FFF 98000 ~ 9FFFF 90000 ~ 97FFF 88000 ~ 8FFFF 80000 ~ 87FFF 78000 ~ 7FFFF 70000 ~ 77FFF 68000 ~ 6FFFF 60000 ~ 67FFF 58000 ~ 5FFFF 50000 ~ 57FFF 48000 ~ 4FFFF 40000 ~ 47FFF 38000 ~ 3FFFF 30000 ~ 37FFF 28000 ~ 2FFFF 20000 ~ 27FFF 18000 ~ 1FFFF 10000 ~ 17FFF 08000 ~ 0FFFF 00000 ~ 07FFF REV. 0.2, MAY 20, 2004 P/N:PM1083 8 MX69F162/164C3BT/B FLASH SECTOR STRUCTURE (MX69F162/164C3BB) Sector Boot Sector 0 Boot Sector 1 Parameter Sector 0 Parameter Sector 1 Parameter Sector 2 Parameter Sector 3 Parameter Sector 4 Parameter Sector 5 Main Sector 0 Main Sector 1 Main Sector 2 Main Sector 3 Main Sector 4 Main Sector 5 Main Sector 6 Main Sector 7 Main Sector 8 Main Sector 9 Main Sector 10 Main Sector 11 Main Sector 12 Main Sector 13 Main Sector 14 Main Sector 15 Main Sector 16 Main Sector 17 Main Sector 18 Main Sector 19 Main Sector 20 Main Sector 21 Main Sector 22 Main Sector 23 Main Sector 24 Main Sector 25 Main Sector 26 Main Sector 27 Main Sector 28 Main Sector 29 Main Sector 30 Sector Size 4K Word 4K Word 4K Word 4K Word 4K Word 4K Word 4K Word 4K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word 32K Word Address Range (h) 00000 ~ 00FFF 01000 ~ 01FFF 02000 ~ 02FFF 03000 ~ 03FFF 04000 ~ 04FFF 05000 ~ 05FFF 06000 ~ 06FFF 07000 ~ 07FFF 08000 ~ 0FFFF 10000 ~ 17FFF 18000 ~ 1FFFF 20000 ~ 27FFF 28000 ~ 2FFFF 30000 ~ 37FFF 38000 ~ 3FFFF 40000 ~ 47FFF 48000 ~ 4FFFF 50000 ~ 57FFF 58000 ~ 5FFFF 60000 ~ 67FFF 68000 ~ 6FFFF 70000 ~ 77FFF 78000 ~ 7FFFF 80000 ~ 87FFF 88000 ~ 8FFFF 90000 ~ 97FFF 98000 ~ 9FFFF A0000 ~ A7FFF A8000 ~ AFFFF B0000 ~ B7FFF B8000 ~ BFFFF C0000 ~ C7FFF C8000 ~ CFFFF D0000 ~ D7FFF D8000 ~ DFFFF E0000 ~ E7FFF E8000 ~ EFFFF F0000 ~ F7FFF F8000 ~ FFFFF REV. 0.2, MAY 20, 2004 P/N:PM1083 9 MX69F162/164C3BT/B FLASH 2.0 BUS OPERATION 1.0 PRINCIPLES OF OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. The product includes an on-chip WSM to manage sector erase, word write and lock-bit configuration functions. After initial device power-up or return from reset mode (see section on Bus Operations), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby and output disable operations. 2.1 Read Status register and identifier codes can be accessed through the CUI independent of the VPP voltage. All functions associated with altering memory contents sector erase, word write, sector lock/unlock, status and identifier codes - are accessed via the CUI and verified through the status register. The first task is to write the appropriate read mode command (Read Array, Read Configuration, Read Query or Read Status Register) to the CUI. Upon initial device power-up or after exit from reset, the device automatically resets to read array mode. In order to read data, control pins set for CEf#, OEf#, WEf#, RESET# and WP# must be driven to active. CEf# and OEf# must be active to obtain data at the outputs. CEf# is the device selection control. OEf# is the data output (Q0-Q15) control and active drives the selected memory data onto the I/O bus, WEf# must be VIH, RESET# must be VIH, WP# must be at VIL or VIH. Information can be read from any sector, configuration codes or status register independent of the VPP voltage. RESET# can be at VIH. Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the sector erase, word write and sector lock/unlock. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification and margining of data. Addresses and data are internally latched during write cycles. Address is latched at falling edge of CEf# and data latched at rising edge of WEf#. Writing the appropriate command outputs array data, accesses the identifier codes or outputs status register data. 2.2 Output Disable With OEf# at a logic-high level (VIH), the device outputs are disabled. Output pins (Q0-Q15) are placed in a highimpedance state. Interface software that initiates and polls progress of sector erase, word write and sector lock/unlock can be stored in any sector. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Sector erase suspend allows system software to suspend a sector erase to read/write data from/to sectors other than that which is suspend. Word write suspend allows system software to suspend a word write to read data from any other flash memory array location. 2.3 Standby CEf# at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. Q0~Q15 outputs are placed in a high-impedance state independent of OEf#. If deselected during sector erase, word write or sector lock/unlock, the device continues functioning, and consuming active power until the operation completes. With the mechanism of sector lock, memory contents cannot be altered due to noise or unwanted operation. When RESET#=VIH and VCCf<VLKO (lockout voltage), any data write alteration can be failure. During read operation, if write VPP voltage is below VPPLK, then hardware level data protection is achieved. With CUI's twostep command sequence sector erase, word write or sector lock/unlock, software level data protection is achieved also. 2.4 Reset As RESET#=VIL, it initiates the reset mode. The device enters reset/deep power down mode. However, the data stored in the memory has to be sustained at least 100ns in the read mode before the device becomes deselected and output high impedance state. REV. 0.2, MAY 20, 2004 P/N:PM1083 10 MX69F162/164C3BT/B In read modes, RESET#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. RESET# must be held low for a minimum of 100ns. Time tPHQV is required after return from reset mode until initial memory access outputs are valid. After this wake-up interval tPHEL or tPHWL, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H. Sector lock bit is set at lock status. The Clear Sector Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location. It is written when WEf# and CEf# are active (whichever goes high first). The address and data needed to execute a command are latched on the rising edge of WEf# or CEf#. Standard microprocessor write timings are used. During sector erase, word write or sector lock/unlock modes, RESET#-low will abort the operation. Memory contents being altered are no longer valid; the data may be partially erased or written. In addition, CUI will go into either array read mode or erase/write interrupted mode. When power is up and the device reset subsequently, it is necessary to read status register in order to assure the status of the device. Recognizing status register (SR.7~0) will assure if the device goes back to normal reset and enters array read mode. 2.5 Read Configuration Codes The read configuration codes operation outputs the manufacturer code, device code, sector lock configuration codes, and the protection register. Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. The sector lock codes identify locked and unlocked sectors. 2.6 Write Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When VCCf=2.7V3.6V and VPP within VPP1 or VPP2 range, the CUI additionally controls sector erase, word write and sector lock/unlock. The Sector Erase command requires appropriate command data and an address within the sector to be erased. The Full Chip Erase command requires appropriate command data and an address within the device. The Word Write command requires the command and address of the location to be written. Set Sector lock/unlock commands require the command and address within the device or sector within the device (Sector Lock) to be locked. REV. 0.2, MAY 20, 2004 P/N:PM1083 11 MX69F162/164C3BT/B are disable during VPP<VPPLK. Placing VPP on VPP1/ 2 enables successful sector erase, word write and sector lock/unlock. 3.0 COMMAND DEFINITIONS The flash memory has four read modes: read array, read configuration, read status, read query, and two write modes: program, erase. These read modes are accessible independent of the VPP voltage. But write modes Device operations are selected by writing specific commands into the CUI. Table 2 defines these commands. Table 2. Command Definition (1) Command Bus Notes Cycles Read Array Read Configuration First Bus Cycle Operation Address Second Bus Cycle Data Required (1) (2) (3) 1 Write X FFH Operation Address Data (1) (2) (3) >2 2,4 Write X 90H Read IA ID Read Query 2 2,7 Write X 98H Read QA QD Read Status Register 2 3 Write X 70H Read X SRD Clear Status Register 1 3 Write X 50H Sector Erase/Confirm 2 Write X 20H Write SA D0H Word Write 2 Write X 40H/10H Write WA WD Program/Erase Suspend 1 Write X B0H Program/Erase Resume 1 Write X D0H Sector Lock 2 Write X 60H Write SA 01H Sector Unlock 2 Write X 60H Write SA D0H Lock-Down Sector 2 Write X 60H Write SA 2FH Protection Program 2 Write X C0H Write PA PD Lock Protection Register 2 Write X C0H Write PA FFFD 2,5 6 Notes: 1. Bus operation are defined at page 6 and referred to AC Timing Waveform. 2. X=Any address within device. IA=ID-Code Address (refer to Table 3). ID=Data read from identifier code. SA=Sector Address within the sector being erased. WA=Address of memory location to be written. WD=Data to be written at location WA. PA=Program Address, PD=Program Data QA=Query Address, QD=Query Data. 3. Data is latched from the rising edge of WEf# or CEf# (whichever goes high first) SRD=Data read from status register, see Table 5 for description of the status register bits. 4. Following the Read Configuration codes command, read operation access manufacturer, device codes, sector lock/unlock codes, see chapter 4.2. 5. Either 40H or 10H command is recognized by the WSM as word write setup. 6. The sector unlock operation simultaneously clear all sector lock. 7. Read Query Command is read for CFI query information. REV. 0.2, MAY 20, 2004 P/N:PM1083 12 MX69F162/164C3BT/B 3.1 Read Array Command 3.3 Read Status Register Command Upon initial device power-up and after exit from reset mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a sector erase, word write or sector lock configuration the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via a Sector Erase Suspend or Word Write Suspend command. If RESET#=VIL device is in read Read Array command mode, this read operation no longer requires VPP. The Read Array command functions independently of the VPP voltage and RESET# can be VIH. CUI writes read status command (70H). The status register may be read to determine when a sector erase, word write or lock-bit configuration is complete and whether the operation completed successfully. (refer to table 5) It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of CEf# or OEf#, whichever occurs last. CEf# or OEf# must toggle to VIH before further reads to update the status register latch. The Read Status Register command functions independently of the VPP voltage. RESET# can be VIH. 3.2 Read Configuration Codes Command 3.4 Clear Status Register Command The configuration code operation is initiated by writing the Read Configuration Codes command (90H). To return to read array mode, write the Read Array Command (FFH). Following the command write, read cycles from addresses shown in Table 3 retrieve the manufacturer, device, sector lock configuration codes and the protection register(see Table 3 for configuration code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Configuration Codes command functions independently of the VPP voltage and RESET# can be VIH. Following the Read Configuration Codes command, the information is shown: Status register bits SR.5, SR.4, SR.3 or SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command (50H). These bits indicate various failure conditions (see Table 5). By allowing system software to reset these bits, several operations (such as cumulatively erasing multiple sectors or writing several words in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written on CUI. It functions independently of the applied VPP Voltage. RESET# can be VIH. This command is not functional during sector erase or word write suspend modes. Table 3. Configuration Code Code Manufacturer Code Address Data (A19-A0) (Q15-Q0) 00000H 00C2H Device Code(Top/Bottom) 00001H 88C2/88C3H Sector Lock Configuration XX002H LocK - Sector is unlocked Q0=0 - Sector is locked Q0=1 - Sector is locked-down Q1=1 Protection Register Lock 80 PR-LK Protection Register 81-88 PR REV. 0.2, MAY 20, 2004 P/N:PM1083 13 MX69F162/164C3BT/B status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it receives another command. 3.5 Sector Erase Command Erase is executed one sector at a time and initiated by a two-cycle command. A sector erase setup is first written (20H), followed by a sector erase confirm (D0H). This command sequence requires appropriate sequencing and an address within the sector to be erased. Sector preconditioning, erase, and verify are handled internally by the WSM. After the two-cycle sector erase sequence is written, the device automatically outputs status register data when read (see Figure 8). The CPU can detect sector erase completion by analyzing the output data of the status register bit SR.7. Reliable word writes can only occur when VCCf=2.7V~3.6V and VPP=VPP1/2. If VPP is not within acceptable limits, the WSM doesn't execut the program command. If word write is attempted while VPP<VPPLK, status register bits SR.3 and SR.4 will be set to "1". Successful word write requires for boot sector that WP# is VIH the corresponding sector lock-bit be cleared. In parameter and main sectors case, it must be cleared the corresponding sector lock-bit. If word write is attempted when the excepting above sector being clocked conditions, SR.1 and SR.4 will be set to "1". Word write is not functional. When the sector erase is complete, status register bit SR.5 should be checked. If a sector erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. 3.7 Sector Erase Suspend Command This two-step command sequence of set-up followed by execution ensures that sector contents are not accidentally erased. An invalid sector Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable sector erasure can only occur when 2.7V~3.6V and VPP=VPP1/2. In the absence of this high voltage, sector contents are protected against erasure. If sector erase is attempted while VPP<VPPLK SR.3 and SR.5 will be set to "1". To successfully erase the boot sector, the corresponding sector lock-bit must be clear first. In parameter and sectors case, it must be cleared the corresponding sector lock-bit. If sector erase is attempted when the excepting above sector being locked conditions, SR.1 and SR.5 will be set to "1". Sector erase is not functional. The Sector Erase Suspend command (50H) allows sector-erase interruption to read or word write data in another sector of memory. Once the sector erase process starts, writing the Sector Erase Suspend command requests that the WSM suspend the sector erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Sector Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the sector erase operation has been suspended (both will be set to "1"). Specification tWHRH2/tEHRH2 defines the sector erase suspend latency. When Sector Erase Suspend command is written to the CUI, if sector erase was finished, the device would be placed read array mode. Therefore, after Sector Erase Suspend command is written to the CUI, Read Status Register command (70H) has to be written to CUI, then status register bit SR.6 should be checked if/when the device is in suspend mode. 3.6 Word Write Command Word write is executed by a two-cycle command sequence. Word write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data. The WSM then takes over, controlling the word write and write verify algorithms internally. After the word write sequence is written, the device automatically outputs status register data when read (see Figure 6). The CPU can detect the completion of the word write event by analyzing the status register bit SR.7. At this point, a Read Array command can be written to read data from sectors other than that which is suspended. A Word Write commands sequence can also be issued during erase suspend to program data in other sectors. Using the Word Write Suspend command (see Section 4.9), a word write operation can also be suspended. During a word write operation with sector erase suspended, status register bit SR.7 will return to "0". However, SR.6 will remain "1" to indicate sector erase suspend status. When word write is complete, status register bit SR.4 should be checked. If word write error is detected, the REV. 0.2, MAY 20, 2004 P/N:PM1083 14 MX69F162/164C3BT/B The only other valid commands while sector erase is suspended are Read Status Register, Read Configuration, Read Query, Program Setup, Program Resume, Sector Lock, Sector Unlock, Sector Lock-Down and sector erase Resume. After a Sector Erase Resume command is written to the flash memory, the WSM will continue the sector erase process. Status register bits SR.6 and SR.7 will automatically be cleared. After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 9). VPP must remain at VPP1/2 while sector erase is suspended. RESET# must also remain at VIH (the same RESET# level used for sector erase). Sector cannot resume until word write operations initiated during sector erase suspend has completed. register bits SR.2 and SR.7 will automatically be cleared. After the Word Write Resume command is written, the device automatically outputs status register data when read (see Figure 7). VPP must remain at VPP1/2 while in word write suspend mode. RESET# must also remain at VIH (the same RESET# level used for word write). If the time between writing the Word Write Resume command and writing the Word Write Suspend command is short and both commands are written repeatedly, a longer time is required than standard word write until the completion of the operation. If the time between writing the Sector Erase Resume command and writing the Sector Erase Suspend command is shorter than 15ms and both commands are written repeatedly, a longer time is required than standard sector erase until the completion of the operation. 3.8 Word Write Suspend Command The Word Write Suspend command allows word write interruption to read data in other flash memory locations. Once the word write process starts, writing the Word Write Suspend command requests that the WSM suspend the Word write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Word Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the word write operation has been suspended (both will be set to "1"). Specification tWHRH1/tEHRH1 defines the word write suspend latency. When Word Write Suspend command write to the CUI, if word write was finished, the device places read array mode. Therefore, after Word Write Suspend command write to the CUI, Read Status Register command (70H) has to be written to CUI, then status register bit SR.2 should be checked for if/when the device is in suspend mode. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while word write is suspended are Read Status Register Read Configuration, Read Query and Word Write Resume. After Word Write Resume command is written to the flash memory, the WSM will continue the Word write process. Status REV. 0.2, MAY 20, 2004 P/N:PM1083 15 MX69F162/164C3BT/B 3.9 Sector Lock/Unlock /Lockdown Command 3.9.4 Read Sector Lock Status 3.9.1 Sector Locked State The lock status of every sector can be read through Read Configuration mode. To enter this mode, first command write 90H to the device. The subsequent reads at sector address +00002 will output the lock status of this sector. The lock status can be read from the lowest two output pins Q0 and Q1. Q0 indicates the sector lock/ unlock status and set by the lock command and cleared by the unlock command. When entering lock-down, the lock status is automatically set. Q1 indicates lock-down status and is set by the lock-down command. It cannot be further cleared by software, only by device reset or power-down. The default status of all sectors upon power-up or reset is locked. Any attempt on program or erase operations will result in an error on bit SR.1 of a locked sector. The status of a locked sector can be changed to unlocked or lock-down using software commands. An unlocked sector can be locked by writing the sector lock command sequence, 60H followed by 01H. 3.9.2 Sector Unlocked State An unlocked sector can be programmed or erased. All unlocked sector return to the locked state when the device is either reset or powered down. The status of an unlocked sector can be changed to locked or lockeddown using software commands. A locked sector can be unlocked by writing unlock command sequence, 60H followed by D0H. Sector Lock Configuration Table Lock Status Sector is unlocked Sector is locked Sector is locked-down Data Q0=0 Q0=1 Q1=1 3.9.3 Sector Locked-Down State Sectors which are locked-down are protected from program and erase operation; however, the protection status of these sectors cannot be changed using software commands alone. Any sector locked or unlocked can be locked-down by writing the lock-down command sequence, 60H followed by 2FH. When the device is reset or powered down, the locked-down sectors will revert to the locked state. The status of WP# will determine the function of sector lock-down and is summarized is followed: WP# WP#=0 WP#=1 Sector Lock-down Description - sectors are protected from program, erase, and lock status changes - the sector lock-down function is disabled - an individual lock-down sector can be unlocked and relocked via software command. Once WP# goes low, sectors that previously locked-down returns to lock-down state regardless of any changes when WP# was high. In addition, sector lock-down is cleared only when the device is reset or powered down. REV. 0.2, MAY 20, 2004 P/N:PM1083 16 MX69F162/164C3BT/B If a sector is locked or locked-down during the same sector is being placed in erase suspend, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. 3.9.5 Sector Locking while Erase Suspend The sector lock status can be performed during an erase suspend by using standard locking command sequences to unlock, lock, or lock-down a sector. Locking operation cannot be performed during a program suspend. In order to change sector locking during an erase operation, the write erase suspend command (B0H) is placed first; then check the status register until it is shown that the actual erase operation has been suspended. Subsequent writing the desired lock command sequence to a sector and the lock status will be changed. When completing any desired lock, read or program operation, resume the erase operation with the Erase Resume Command (D0H). 3.9.6 Status Register Error Checking The operation of locking system for this device can be used the term "state (X,Y,Z)" to specify locking status, where X=value of WP#, Y=bit Q1 of the sector lock status register, and Z=bit Q0 of the sector lock status register. Q0 indicates if a sector is locked (1) or unlocked (0). Q1 indicates if a sector has been locked-down(1) or not (0). Table 4. Sector Locking State Transitions WP# Current State Erase/Prog. (X, Y, Z)= Operation if Lock Command Input Result (Next State) (X, Y, Z)= Q1 Q0 Name Enable ? Lock Unlock Lock-Down 0 0 0 Unlocked Yes (001) Unchanged (011) 0 0 1 Locked (default) No Unchanged (000) (011) 0 1 1 Locked-Down No Unchanged Unchanged Unchanged 1 0 0 Unlocked Yes (101) Unchanged (111) 1 0 1 Locked No Unchanged (100) (111) 1 1 0 Lock-Down Disabled Yes (111) Unchanged (111) 1 1 1 Lock-Down Disabled No Unchanged (110) Unchanged Note: At power-up or device reset, all sectors default to locked state (001) (if WP#=0). Holding WP#=0 is the recommended default. REV. 0.2, MAY 20, 2004 P/N:PM1083 17 MX69F162/164C3BT/B Table 5. Status Register Definition WSMS SESS ES PS VPPS PSS SLS R 7 6 5 4 3 2 1 0 NOTES: Check WSM bit first to determine word program or sector Erase completion, before checking Program or Erase Status bits. SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy When Sector Erase Suspend is issued, WSM halts execution and sets both WSMS and SESS bits to "1". SESS bit remains set to "1" until an Sector Erase Resume command is issued. SR.6 = SECTOR ERASE SUSPEND STATUS (SESS) 1 = Sector ERASE Suspended 0 = Sector Erase in Progress/Completed SR.5 = ERASE STATUS (ES) 1 = Error in Programming 0 = Successful Sector Erase or Clear Sector LockBits When this bit (SR.5) is set to "1", it means WSM is unable to verify successful sector erasure. SR.4 = PROGRAM STATUS (PS) 1 = Error in Programming 0 = Successful Programming When this bit is set to "1", WSM has attempted but failed to program a word. SR.3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK The WSM interrogates VPP level only after the Program or Erase command sequences have been entered and informs the system if VPP has not been switched on. SR.3 bit is not guaranteed to report accurate feedback between VPPLK and VPP1 min. SR.2 = PROGRAM SUSPEND STATUS (PSS) 1 = Program Suspended 0 = Program in Progress/Completed When program suspend is issued, WSM halts the execution and sets both WSMS and PSS bits to "1". SR.2 remains set to "1" until a Program Resume command is issued. SR.1 = SECTOR LOCK STATUS (SLS) 1 =Program/Erase attempted an a locked sector; operation aborted 0 = No operation to locked sectors If a program or erase operation is attempted to one of the locked sectors, this bit is set by the WSM. The operation specified is aborted and the device is returned to read status mode. SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR. 0 is reserved for future use and should be masked out when polling the status register. REV. 0.2, MAY 20, 2004 P/N:PM1083 18 MX69F162/164C3BT/B read cycles from addresses shown in Table 6 will retrieve the specified information. To return to read array mode, write the Read Array Command (FFH). 4.0 128-Bit Protection Register The 128 bits of protection register are divided into two 64-bit segments. One of the segments is programmed at MXIC side with unique 64-bit number; where changes are forbidden. The other segment is left empty for customer to program. Once the customer segment is programmed, it can be locked to prevent further reprogramming. Two-cycle Protection Program Command is used to program protection register bits. The 64-bit number is programmed 16 bits at a time. First, write C0H Protection Program Setup command. The next write to the device will latch in address and data and program the specified location. The allowable address are also shown in Table 6. Refer to Figure 11 for the Protection Register Programming Flowchart. 4.1 Protection Register Read & Programming Any attempt to address Protection Program command onto undefined protection register address space will result in a Status Register error (SR.4 set to "1"). In addition, attempting to program to a previously locked protection register segment will result in a status register error (SR.4=1, SR.1=1). The protection register is read in the configuration read mode, which follows the stated Command Bus Definitions. The device is switched to this read mode by writing the Read Configuration command (90H). Once in this mode, Table 6. Word-Wide Protection Register Addressing Word Lock 0 1 2 3 4 5 6 7 User Both Factory Factory Factory Factory Customer Customer Customer Customer A7 1 1 1 1 1 1 1 1 1 A6 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 1 A2 0 0 0 0 1 1 1 1 0 A1 0 0 1 1 0 0 1 1 0 A0 0 1 0 1 0 1 0 1 0 Notes: 1. Set address bit A19-A15=1 for TOP Boot device. 2. Set address bit A19-A15=0 for Bottom Boot device. 3. The address not specified in above are don't care. Table 7. Protection Register Memory Map 4.2 Protection Register Locking The user-programmable segment of the protection register is lockable by programming Bit 1 of the PR-Lock location to 0. Bit 0 of this location is programmed to 0 at MXIC to protect the unique device number. This bit is set using the protection program command to program "FFFD" to PR-LOCK location. After these bits have been programmed, no further changes can be made to the value stored in the protection register. Protection Program command to a locked section will result in a status register error (Program Error bit SR.4 and Lock Error bit SR.1 will be set to 1). Protection register lockout state is not reversible. Protection Register Bit Address 88H~85H 84H~81H 80H(Bit0 & Bit1) Purpose 4 words User Program Register 4 words Factory Program Register Protection Register Lock REV. 0.2, MAY 20, 2004 P/N:PM1083 19 MX69F162/164C3BT/B AC Input/Output Test Conditions VCCQ TEST POINTS Input VCCQ/2 VCCQ/2 Output 0.0 Note:AC test inputs are driven at VCCQ/2 for a Logic "1" and 0.0V for a Logic "0". Figure 1. Transient Input/Output Reference Waveform Figure 2. SWITCHING TEST CIRCUITS TEST SPECIFICATIONS Test Condition 70 90 Output Load 1 TTL gate Output Load Capacitance, CL 30 100 (including jig capacitance) Input Rise and Fall Times 5 Input Pulse Levels 0.0-3.0 Input timing measurement 1.5 reference levels Output timing measurement 1.5 reference levels 2.7K ohm DEVICE UNDER TEST 3.3V CL 6.2K ohm DIODES=IN3064 OR EQUIVALENT Unit pF ns V V V REV. 0.2, MAY 20, 2004 P/N:PM1083 20 MX69F162/164C3BT/B AC Characteristic -- Read Only Operation (1) -70 Notes Min. -90 Sym. Parameter Max. tAVAV Read Cycle Time tAVQV Address to Output Delay tELQV CEf# to Output Delay tGLQV OEf# to Output Delay tPHQV RESET# to Output Delay tELQX CEf# to Output in Low Z 3 0 0 ns tGLQX OEf# to Output in Low Z 3 0 0 ns tEHQZ CEf# to Output in High Z 3 20 20 ns tGHQZ OEf# to Output in High Z 3 20 20 ns tOH Output Hold from Address, 3 70 Min. Max. 90 Unit ns 70 90 ns 2 70 90 ns 2 20 30 ns 150 150 ns 0 0 ns CEf#, or OEf# Change, Whichever Occurs First Notes: 1. See AC Waveform: Read Operations at Figure 3. 2. OEf# may be delayed up to tELQV-tGLQV after the falling edge of CEf# without impact on tELQV. 3. Sampled, but not 100% tested. 4. See test Configuration. REV. 0.2, MAY 20, 2004 P/N:PM1083 21 MX69F162/164C3BT/B Figure 3. READ-ONLY OPERATION AC WAVEFORM Addresses(A) Device and Address Selection VIH Data Valid Standby Address Stable VIL tAVAV CEf# (E) VIH VIL tEHQZ OEf# (G) VIH VIL tGHQZ WEf# (W) VIH tGLQV VIL tOH tGLQX tELQV DATA VOH (D/Q) VOL tELQX High Z Valid Output High Z tAVQV RESET# (P) VIH tPHQV VIL REV. 0.2, MAY 20, 2004 P/N:PM1083 22 MX69F162/164C3BT/B AC Characteristic -- Write Operation Note -70 -90 Min. Min. Unit 150 150 ns 0 0 ns Sym. Parameter tPHWL/tPHEL RESET# High Recovery to WEf#(CEf#) Going Low tELWL/tWLEL CEf#(WEf#) Setup to WEf#(CEf#) Going Low tWLWH/tELEH WEf#(CEf#) Pulse Width 4 45 60 ns tDVWH/tDVEH Data Setup to WEf#(CEf#) Going High 2 40 50 ns tAVWH/tAVEH Address Setup to WEf#(CEf#) Going High 2 50 60 ns 0 0 ns tWHEH/tEHWH CEf#(WEf#) Hold Time from WEf#(CEf#) High tWHDX/tEHDX Data Hold Time from WEf#(CEf#) High 2 0 0 ns tWHAX/tEHAX Address Hold Time from WEf#(CEf#) High 2 0 0 ns tWHWL/tEHEL WEf#(CEf#) Pulse Width High 4 25 30 ns tVPWH/tVPEH VPP Setup to WEf#(CEf#) Going High 3 200 200 ns tQVVL VPP Hold from Valid SRD 3 0 0 ns tBHWH/tBHEH WP# Setup to WEf#(CEf#)Going High 3 0 0 ns tQVBL WP# Hold from Valid SRD 3 0 0 ns tWHGL WEf# High to OEf# Going Low 3 30 30 ns Notes: 1. Write timing characteristics during erase suspend are the same as during write-only operations. 2. Refer to Table 4 for valid AIN or DIN. 3. Sampled, not 100% tested. 4. Write pulse width (tWP) is defined from CEf# or WEf# going low (whichever goes low last) to CEf# or WEf# going high (whichever goes high first). Hence, tWP=tWLWH=tELEH=tWLEH=tELWH. Similarly, Write pulse width high (tWPH) is defined from CEf# or WEf# going high (whichever goes high first) to CEf# or WEf# going low (whichever goes low first). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL. 5. See Test Configuration. REV. 0.2, MAY 20, 2004 P/N:PM1083 23 MX69F162/164C3BT/B Figure 4. WRITE AND ERASE OPERATION AC WAVEFORM A Address (A) B C D AIN AIN E F VIH VIL tAVWH (tAVEH) tWHAX (tEHAX) (Note 1) VIH CEf#(WEf#)[E(W)] VIL tELWL (tWLEL) tWHEH (tEHWH) VIH OEf#(G) tWHWL (tEHEL) VIL tWHGL (Note 1) Disable VIH WEf#,(CEf#)[W(E)] Enable VIL tELEH (tWLWH) VIH High Z DATA[D/Q] tDVWH (tEVEH) tWHDX (tEHDX) DIN DIN VIL Valid SRD DIN tPHWL (tPHEL) VOH RESET#[P] VOL tQVBL tBHWH (tBHEH) VIH WP# VIL tVPWH (tVPEH) tQVVL VPPH2 VPPH1 VPP[V] VPPLK VIL Notes: 1. CEf# must be toggled low when reading Status Register Data. WEf# must be inactive (high) when reading Status Register Data. A.VCCf Power-Up and Standby. B.Write Program or Erase Setup Command. C.Write Valid Address and Data (for Program) or Erase Confirm Command. D.Automated Program or Erase Delay. E.Read Status Register Data (SRD): reflects completed program/erase operation. F.Write Read Array Command. REV. 0.2, MAY 20, 2004 P/N:PM1083 24 MX69F162/164C3BT/B Erase and Program Timing (1) Vpp Symbol Parameter tBWPB 4-KW Parameter Sector 1.65V-3.6V 11.4V-12.6V Note Typ(1) Max Typ(1) Max Unit 2,3 0.10 0.30 0.03 0.12 s 2,3 0.8 2.4 0.24 1 s Word Program Time 2,3 12 200 8 185 us tWHQV2/ 4-KW Parameter Sector 2,3 0.5 4 0.4 4.0 s tEHQV2 Erase Time tWHQV3/ 32-KW Main Sector 2,3 1 5 0.6 5 s tEHQV3 Erase Time tWHRH1/ Program Suspend Latency 3 15 20 15 20 us Erase Suspend Latency 3 15 20 15 20 us Word Program Time tBWMB 32-KW Main Sector Word Program Time tWHQV1/ tEHQV1 tEHRH1 tWHRH2/ tEHRH2 Notes: 1. Typical values measured at TA=+25 C and nominal voltage. 2. Excludes external system-level overhead. 3. Sampled, but not 100% tested. REV. 0.2, MAY 20, 2004 P/N:PM1083 25 MX69F162/164C3BT/B Figure 5. RESET WAVEFORM VIH RESET# (P) tPHQV tPHWL tPHEL VIL tPLPH (A) Reset during Read Mode tPLRH RESET# (P) Abort Complete tPHQV tPHWL tPHEL VIH VIL tPLPH (B) Reset during Program or Sector Erase, tPLPH < tPLRH Abort Complete tPLRH Deep PowerDown tPHQV tPHWL tPHEL VIH RESET# (P) VIL tPLPH (C) Reset Program or Sector Erase, tPLPH > tPLRH AC Characteristic -- Under Reset Operation Sym. Parameter VCCf=2.7V~3.6V Min. tPLPH RESET# Low to Reset during Read Unit Notes ns 1,3 Max. 100 (If RESET# is tied to VCCf, this specification is not applicable) tPLRH1 RESET# Low to Reset during Sector Erase 22 us 1,4 tPLRH2 RESET# Low to Reset during Program 12 us 1,4 Notes: 1. See Section 3.4 for a full description of these conditions. 2. If tPLPH is < 100ns the device may still reset but this is not guaranteed. 3. If RESET# is asserted while a sector erase or word program operation is not executing, the reset will complete within 100ns. 4. Sampled, but not 100% tested. REV. 0.2, MAY 20, 2004 P/N:PM1083 26 MX69F162/164C3BT/B DC Characteristics VCCf 2.7V-3.6V VCCQ 2.7V-3.6V Note Typ. Max. 1,2 1 Sym. Parameter ILI Input Load Current ILO Output Leakage Current VCC Standby Current 1,2 0.2 10 uA 1 7 15 uA ICCD VCC Power-Down Current 1,2 7 15 uA ICCR VCC Read Current 1,2,3 9 18 mA IPPD 1 0.2 5 uA IPPR VPP Deep PowerDown Current VPP Read Current 1,4 ICCW+ IPPW ICCE+ IPPE ICCES or ICCWS VIL VIH VOL VCC+VPP Program Current VCC+VPP Erase Current VCC Program or Erase Suspend Current Input Low Voltage Input High Voltage Output Low Voltage 2 50 18 10 21 16 7 15 200 55 30 45 45 15 uA uA mA mA mA mA uA -0.4 2.0 -0.1 VCCf*0.22V VCCQ+0.3V 0.1 V V V VOH Output High Voltage VPPLK VPP1 VPP2 VLKO VPP Lock-Out Voltage VPP during Program/ Erase Operations VCC Prog/Erase Lock Voltage VCCQ Prog/Erase Lock Voltage ICCS VLKO2 1,4 1,4 1,4 VCCQ -0.1V 6 6 6 1.65 11.4 1.5 Unit uA V 1.0 3.6 12.6 1.2 V V V V Test Conditions VCCf=VCCf Max. ; VCCQ=VCCQ Max. VIN=VCCQ or GND VCCf=VCCf Max. ; VCCQ=VCCQ Max. VIN=VCCQ or GND VCCf=VCCf Max. ; CEf#=RESET#= VCCQ or during Program/Erase Suspend WP#=VCCQ or GND VCCf=VCCf Max. ; VCCQ=VCCQ Max VIN=VCCQ or GND RESET#=GND0.2V VCCf=VCCf Max. ; VCCQ=VCCQ Max OEf#=VIH, CEf#=VIL, f=5MHz, IOUT=0mA, Inputs=VIL or VIH RESET#=GND0.2V VPP < VCCf VPP < VCCf VPP > VCCf VPP=VPP1, Program in Progress VPP=VPP2(12V), Program in Progress VPP=VPP1, Erase in Progress VPP=VPP2(12V), Erase in Progress CEf#=VCCf, Program or Erase Suspend in Progress VCCf=VCCf Min, VCCQ=VCCQ Min IOL=100uA VCCf=VCCf Min, VCCQ=VCCQ Min IOH=-100uA Complete Write Protection V REV. 0.2, MAY 20, 2004 P/N:PM1083 27 MX69F162/164C3BT/B Notes: 1. All currents are in RMS unless otherwise noted. Typical values at nominal VCCf, TA=+25 C. 2. The test conditions VCCf Max, VCCQ Max, VCCf Min, and VCCQ Min refer to the maximum or minimum VCCf or VCCQ voltage listed at the top of each column. 3. Power Savings (Mode) reduces ICCR to approximately standby levels in static operation (CMOS inputs). 4. Sampled, but not 100% tested. 5. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is sum of ICCES and ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS and ICCR. 6. Erase and Program are inhibited when VPP<VPPLK. REV. 0.2, MAY 20, 2004 P/N:PM1083 28 MX69F162/164C3BT/B Figure 6. Automated Word Programming Flowchart Bus Command Operation Write Program Setup Write Program Start Write 40H Data=40H Data=Data to Program Addr=Location to Program Read Status Register Data Toggle CEf# or OEf# to Update Status Register Data Standby Check SR.7 1=WSM Ready 0=WSM Busy Repeat for subsequent programming operations. SR full status check can be done after each program or after a sequence of program operations. Write FFH after the last program operation to reset device to read array mode. Program Address/Data Read Status Register SR.7=1 ? Comments No Yes Full Status Check if Desired Program Ccomplete Bus Command Operation Standby FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) SR.3= 1 Check SR.3 1=VPP Low Detect Standby Check SR.4 1=VPP Program Error Standby Check SR.1 1=Attempted Program to Locked Sector-Program Aborted SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine. SR.4, SR.3, and SR.1 are only cleared by the Clear Status Register Command, in cases where multiple bytes are programmed before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. VPP Range Error 0 SR.4= 1 Programming Error 0 SR.1= 1 Comments Attempted Program to Locked Sector- Aborted 0 Program Successful REV. 0.2, MAY 20, 2004 P/N:PM1083 29 MX69F162/164C3BT/B Figure 7. Program Suspend/Resume Flowchart Bus Command Operation Write Program Suspend Write Read Status Start Write B0H Write 70H Read Read Status Register SR.7= Standby 0 1 Stanby SR.2= 0 Program Completed Write 1 Write FFH Read Array Read Read Array Data Write Done Reading Program Resume Comments Data=B0H Addr=X Data=70H Addr=X Status Register Data Toggle CEf# or OEf# to Update Status Register Data Addr=X Check SR.7 1=WSM Ready 0=WSM Busy Check SR.2 1=Program Suspended 0=Program Completed Data=FFH Addr=X Read array data from sector other than the one being programmed. Data=D0H Addr=X No Yes Write D0H Write FFH Program Write Resumed Read Array Data REV. 0.2, MAY 20, 2004 P/N:PM1083 30 MX69F162/164C3BT/B Figure 8. Automated Sector Erase Flowchart Bus Command Comments Operation Write Erase Setup Data=20H Addr=Within Sector to Be Erased Write Erase Data=D0H Confirm Addr=Within Sector to Be Erased Read Status Register Data Toggle CEf# or OEf# to Update Status Register Data Standby Check SR.7 1=WSM Ready 0=WSM Busy Repeat for subsequent sector erasures. Full status check can be done after each sector erase or after a sequence of sector erasures. Write FFH after the last write operation to reset device to read array mode. Start Write 20H Write D0H and Sector Address Read Status Register Suspend Erase Loop No SR.7= Yes 0 Suspend Erase 1 Full Status Check if Desired Sector Erase Complete FULL STATUS CHECK PROCEDURE Bus Command Operation Standby Read Status Register Data(See Above) SR.3= 1 Check SR.3 1=VPP Low Detect Standby Check SR.4, 5 Both 1=Command Sequence Error Standby Check SR.5 1=Sector Erase Error Standby Check SR.1 1=Attempted Erase of Locked Sector- Erase Aborted SR.1 and SR.3 MUST be cleared, if set during an erase attempt, before further attempts are allowed by the Write State Machine. SR.1,3,4,5 are only cleared by the Clear Status Register Command, in cases where multiple bytes are erased before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. VPP Range Error 0 SR.4,5= 1 Command Sequence Error 0 SR.5= 1 Sector Erase Error 0 SR.1= 1 Comments Attempted Erase of Locked Sector - Aborted 0 Sector Erase Successful REV. 0.2, MAY 20, 2004 P/N:PM1083 31 MX69F162/164C3BT/B Figure 9. Erase Suspend/Resume Flowchart Bus Command Operation Write Erase Suspend Write Read Status Start Write B0H Write 70H Read Read Status Register SR.7= Standby 0 1 Stanby SR.6= 0 Erase Completed Write 1 Read Array Write FFH Read Read Array Data Write Done Reading Erase Resume Comments Data=B0H Addr=X Data=70H Addr=X Status Register Data Toggle CEf# or OEf# to Update Status Register Data Addr=X Check SR.7 1=WSM Ready 0=WSM Busy Check SR.6 1=Erase Suspended 0=Erase Completed Data=FFH Addr=X Read array data from sector other than the one being erased. Data=D0H Addr=X No Yes Write D0H Write FFH Erase Write Resumed Read Array Data REV. 0.2, MAY 20, 2004 P/N:PM1083 32 MX69F162/164C3BT/B Figure 10. Locking Operations Flowchart Bus Command Comments Operation Write Config. Setup Data=60H Addr=X Write Lock, unlock Data=01H (Sector Lock) or Lockdown D0H(Sector Unlock) 2FH(Sector Lockdown) Addr=Within sector to lock Write Read Status Data=70H (Optional) Register Addr=X Read Status Register Register (Optional) Addr=X Stanby Check Status Register (Optional) 80H=no error 30H=Lock Command Sequence Error Write Read Data=90H (Optional) Configuration Addr=X Read Sector Lock Sector Lock Status Data (Optional) Status Addr=Second addr of sector Stanby Confirm Locking Change on Q1, Q0 (See Sector Locking State Table for valid combinations.) Start Write 60H (Configuration Setup) Write 01H, D0H, or 2FH Write 70H (Read Status Register) Lock Command Sequence Error Read Status Register SR.4, SR.5= 1,1 0,0 Write 90H (Read Configuration) Read Sector Lock Status Locking Change Confirmed ? No Yes Locking Change Complete REV. 0.2, MAY 20, 2004 P/N:PM1083 33 MX69F162/164C3BT/B Figure 11. Protection Register Programming Flowchart Bus Command Operation Write Protection Program Setup Write Protection Program Read Start Write C0H (Protection Reg. Program Setup) Data=C0H Data=Data to Program Addr=Location to Program Status Register Data Toggle CEf# or OEf# to Update Status Register Data Standby Check SR.7 1=WSM Ready 0=WSM Busy Protection Program operations can only be addressed within the protection register address space. Addresses outside the defined space will return an error. Repeat for subsequent programming operations. SR Full Status Check can be done after each program or after a sequence of program operations. Write FFH after the last operation to reset device to read array mode. Write Protect. Register Address/Data Read Status Register SR.7=1 ? Comments No Yes Full Status Check if Desired Program Ccomplete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) SR.3, SR.4= SR.1, SR.4= SR.1, SR.4= Bus Command Operation Standby 1,1 SR.1, SR.3, SR.4 0 1 1 VPP Low Standby 0 0 1 Prot. Reg. Prog. Error Stanby 1 0 1 Register Locked: Aborted SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine. SR.1,3,4 are only cleared by the Clear Status Register Command, in cases of multiple protection register program operations before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. VPP Range Error 0,1 Protection Register programming Error 1,1 Attempted Program to Locked Register Aborted Comments Program Successful REV. 0.2, MAY 20, 2004 P/N:PM1083 34 MX69F162/164C3BT/B 5.0 VPP Program and Erase Voltage MX69F162/164C3BT/B product provides in-system programming and erase in the 1.65V~3.6V of VPP range. In addition, VPP pin on 12V provides fast production programming. 5.1 VPP Fast manufacturing Programming When VPP is between 1.65V and 3.6V, all program and erase current is drawn through the VCCf pin. If VPP is driven by a logic signal, VIH=1.65V. That is, VPP must remain above 1.65V to perform in-system flash update/ modifications. When VPP is connected to a 12V power supply, the device draws program and erase current directly from the VPP pin. 5.2 Protection Under VPP<VPPLK VPP can off additional hardware write protection. The VPP programming voltage can be kept low for the absolute hardware protection of all sector in the flash device. As VPP is below VPPLK, any program or erase operation will result in a error, prompting the corresponding status register bit (SR.3) to be set. REV. 0.2, MAY 20, 2004 P/N:PM1083 35 MX69F162/164C3BT/B The single cycle Query command is valid only when the device is in the Read mode, including Erase Suspend, Program Suspend, Standby mode, and Read ID mode; however, it is ignored otherwise. 6.0 QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE MX69F162/164C3BT/B is capable of operating in the CFI mode. This mode allows the host system to determine the manufacturer of the device such as operating parameters and configuration. Two commands are required in CFI mode. Query command of CFI mode is placed first, then the Reset command exits CFI mode. These are described in Table 2. The Reset command exits from the CFI mode to the Read mode, or Erase Suspend mode, Program Suspend or read ID mode. The command is valid only when the device is in the CFI mode. Table 8-1. CFI mode: Identification Data Values (All values in these tables are in hexadecimal) Description Address h Data h 10 0051 11 0052 12 0059 13 0003 14 0000 15 0035 16 0000 17 0000 18 0000 19 0000 1A 0000 Address h Data h VCC supply, minimum (2.7V) 1B 0027 VCC supply, maximum (3.6V) 1C 0036 VPP supply, minimum (11.4V) 1D 00B4 1E 00C6 1F 0005 20 0000 21 000A 22 0000 23 0004 24 0000 Maximum timeout for individual sector erase times (2 X Typ) 25 0003 Maximum timeout for full chip erase times (not supported) 26 0000 Query-unique ASCII string "QRY" Primary vendor command set and control interface ID code Address for primary algorithm extended query table Alternate vendor command set and control interface ID code (none) Address for secondary algorithm extended query table (none) Table 8-2. CFI Mode: System Interface Data Values Description VPP supply, maximum (12.6V) N Typical timeout for single word write (2 us) N Typical timeout for maximum size buffer write (2 us) N Typical timeout for individual sector erase (2 ms) N Typical timeout for full chip erase (2 ms) (not supported) N Maximum timeout for single word write times (2 X Typ) N Maximum timeout for maximum size buffer write times (2 X Typ) N REV. 0.2, MAY 20, 2004 P/N:PM1083 36 MX69F162/164C3BT/B Table 8-3. CFI Mode: Device Geometry Data Values Description Device size (2n bytes) Flash device interface code (asynchronous x16) Maximum number of bytes in write buffer=2n (not supported) Number of erase sector regions within device (one or more continuous same-size erase sectors at one sector region) Address h 27 28 29 2A 2B 2C Erase Sector Region 1 information [2E,2D] = number of same-size sectors in region 1-1 [30, 2F] = region erase sector size in multiples of 256-bytes 2D 2E 2F 30 Erase Sector Region 2 information [32,31] = number of same-size sectors in region 2-1 [34,33] = region erase sector size in multiples of 256-bytes 31 32 33 34 Data h 0015 0001 0000 0000 0000 0002 T B 1E 07 00 00 00 20 01 00 T B 07 1E 00 00 20 00 00 01 REV. 0.2, MAY 20, 2004 P/N:PM1083 37 MX69F162/164C3BT/B Table 8-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional Feature & Command Support bit 0 Chip Erase Supported (1=yes, 0=no) bit 1 Suspend Erase Supported (1=yes, 0=no) bit 2 Suspend Program Supported (1=yes, 0=no) bit 3 Lock/Unlock Supported (1=yes, 0=no) bit 4 Queued Erase Supported (1=yes, 0=no) bit 5 Instant individual sector locking supported (1=yes, 0=no) bit 6 Protection bits supported (1=yes, 0=no) bit 7 Page mode read supported (1=yes, 0=no) bit 8 Synchronous read support (1=yes, 0=no) bits 9-31 revered for future use; undefined bits are "0" Supported functions after suspend bit 0 Program supported after erase suspend (1=yes, 0=no) bit 1-7 Reserved for other supported options; undefined bits are "0" Sector Lock Status Define which bits in the sector status Register section of the Query are implemented. bit 0 sector Lock Status Register Lock/Unlock bit (bit 0) active; (1=yes, 0=no) bit 1 sector Lock Status Register Lock-Down bit (bit 1) active; (1=yes, 0=no) Bits 2-15 reserved for future use. Undefined bits are "0". VCC Logic Supply Optimum Program/Erase Voltage (highest performance) bits 7-4 BCD value in volts bits 3-0 BCD value in 100mV VPP Supply Optimum Program/Erase Voltage bits 7-4 HEX value in volts bits 3-0 BCD value in 100mV Number of protection register in JEDEC ID space "00" indicates that 256 protection bytes are available Protection Description bit 0-7 = Lock/bytes JEDEC-plane physical low address bit 8-15 = Lock/bytes JEDEC-plane physical high address bit 16-23 = "n" such that 2n=factory pre-programmed bytes bit 24-31 = "n" such that 2n=user programmed bytes Address h 35 36 37 38 39 3A 3B 3C 3D Data h 0050 0052 0049 0031 0030 66 00 00 00 3E 01 3F 40 03 00 41 33 42 C0 43 01 44 45 46 47 80 00 03 03 REV. 0.2, MAY 20, 2004 P/N:PM1083 38 MX69F162/164C3BT/B vide both high speed and low power features with a typical CMOS standby current of 1uA and maximum access time of 70ns in 3V operation. 2. SRAM--DESCRIPTION The SRAM of mixed multi chip memory is a high performance, very low power CMOS Static Random Access Memory. Easy memory expansion is provided by an active HIGH chip enable 2(CE2s) active LOW chip enable (CE1s#) and active LOW output enable (OEs#) and three-state output drivers. The SRAM of MX69F162/164C3BT/B is organized as 131,072 words by 16 bits / 262,144 words by 16 bits and operates from a very low range of 2.7V to 3.6V supply voltage. The SRAM of MX69F162/164C3BT/B has an autmatic power down feature, reducing the power consumption significantly when chip is deselected. Advanced CMOS technology and circuit techniques pro- DC ELECTRICAL CHARACTERISTICS Parameter Parameter Test Conditions Name VIL Guaranteed Input Low Voltage (2) VIH Guaranteed Input High Voltage (2) IIL Input Leakage Current Vccs=Max, VIN=0V to Vcc IOL Output Leakage Current Vccs=Max, CE1s#=VIH or CE2s=VIL VI/O=0V to Vcc or LB#=UB#=VIH or OEs#=VIH, VI/O=0V to Vcc VOL Output Low Voltage Vccs=Max, IOL=2mA VOH Output High Voltage Vccs=Min, IOH=-0.5mA ICC1 Active supply current LBs# and UBs#<0.2V, CE1s#<0.2V f=10MHz (AC, MOS level) CE2s>(Vccs)-0.2V other inputs<0.2V or >(Vccs)-0.2V f=1MHz Output-open (duty 100%) ICC2 Active supply current LBs# and UBs#=VIL, CE1s#=VIL f=10MHz (AC, TTL level) CE2s=VIH other inputs=VIH or VIL Output-open (duty 100%) f=1MHz ICC3 Standby Power Suppply Vcc=max, CE1s#=VIH or CE2s=VIL Current (AC, CMOS) IDQ=0mA ICC4 Standby supply current 1)CE2s=VIL, Other inputs=0 - Vccs (AC, TTL) 2)CE1s#=VIH, CE2s=VIH or VIL, Other inputs=0 - Vccs 3) LBs# and UBs#=VIH, CE1s#=VIH or VIL CE2s=VIH or VIL, Other inputs=0 Vccs MIN. -0.3 TYP. (1) - 2.2 MAX. Units 0.6 V - Vcc+0.3 V - - 1 1 uA uA 2.4 - 50 0.4 70 V V mA - 7 15 mA - 50 70 mA - 7 1 15 40 mA uA - - 1.0 mA 1.Typical characteristics are at TA=25 C and Vcc=3.0V 2.These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3.Fmax=1/tRC. REV. 0.2, MAY 20, 2004 P/N:PM1083 39 MX69F162/164C3BT/B POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Limits Symbol Parameter Test Conditions MIN. TYP. MAX. Units S-Vcc(PD) Power down supply voltage 2.0 V VI(S-BC) 2.0 V 2.0 V Byte control input LBs#, UBs# VI(CE1s#) Chip select input CE1s# VI(CE2s) ICC(PD) Chip select input CE2s Power Down supply current 0.2 V +70 ~ +85 C - - 30 uA VCCs=3.0V +40 ~ +70 C - - 15 uA CE2s<0.2V +25 ~ +40 C - 1 3 uA other inputs=0~3V -40 ~ +25 C - 0.3 1 uA (2) TIMING REQUIREMENTS Limits Symbol Parameter Test Conditions MIN. TYP. MAX. Units tsu(PD) Power down set up time 0 ns trec(PD) Power down recovery time 5 ms (3) TIMING DIAGRAM LBs#, UBs# control mode S-Vcc 2.7V 2.7V tsu(PD) LBs# UBs# trec(PD) 2.2V 2.2V LBs#, UBs# > (VCCs)-0.2V CE1s# control mode VCCs 2.7V 2.7V tsu(PD) trec(PD) 2.2V 2.2V CE1s# CE1s# > (VCCs)-0.2V CE2s control mode VCCs 2.7V 2.7V CE2s 0.2V 0.2V tsu(PD) trec(PD) CE2s < 0.2V REV. 0.2, MAY 20, 2004 P/N:PM1083 40 MX69F162/164C3BT/B AC TEST LOADS AND WAVEFORMS AC TEST LOADS AND WAVEFORMS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Supply Voltage DQ CL Output loads: Including scope and jig capacitance 3.0/0V 5ns 1.5V 2.7V~3.6V CL=30pF CL=5pF (for ten. tdis) FIGURE 1. Output load REV. 0.2, MAY 20, 2004 P/N:PM1083 41 MX69F162/164C3BT/B AC ELECTRICAL CHARACTERISTICS READ CYCLE Limits Symbol Parameter SRAM 70 MIN. 85 MAX. 70 MIN. Units MAX. tCR Read cycle time 85 ns ta(A) Address access time 70 85 ns ta(CE1) Chip select 1 access time 70 85 ns ta(CE2) Chip select 2 access time 70 85 ns ta(LB) Lower Byte control access time 70 85 ns ta(UB) Upper Byte control access time 70 85 ns ta(OE) Output enable access time 45 45 ns tdis(CE1) Output disable time after CE1s# high 30 30 ns tdis(CE2) Output disable time after CE2s low 30 30 ns tdis(LB) Output disable time after LBs# high 30 30 ns tdis(UB) Output disable time after UBs# high 30 30 ns tdis(OE) Output disable time after OEs# high 30 30 ns ten(CE1) Output enable time after CE1s# low 10 10 ns ten(CE2) Output enable time after CE2s low 10 10 ns ten(LB) Output enable time after LBs# low 10 10 ns ten(UB) Output enable time after UBs# low 10 10 ns ten(OE) Output enable time after OEs# low 5 5 ns tv(A) Data valid time after address 10 10 ns REV. 0.2, MAY 20, 2004 P/N:PM1083 42 MX69F162/164C3BT/B READ CYCLE TIMING DIAGRAMS tCR A0~A16/A0~A17 ta(A) LBs# tv(A) ta(LB) or ta(UB) UBs# (Note3) (Note3) tdis(LB) or tdis(UB) ta(CE1) CE1s# (Note3) tdis(CE1) (Note3) ta(CE2) CE2s (Note3) tdis(CE2) (Note3) ta(OE) OEs# (Note3) ten(OE) tdis(OE) (Note3) WEs#="H" level Q0~15 ten(LB) ten(UB) ten(CE1) ten(CE2) VALID DATA REV. 0.2, MAY 20, 2004 P/N:PM1083 43 MX69F162/164C3BT/B AC ELECTRICAL CHARACTERISTICS WRITE CYCLE Limits Symbol Parameter SRAM 70 MIN. 85 MAX. MIN. Units MAX. tCW Write cycle time 70 85 ns tw(W) Write pulse width 50 50 ns tsu(A) Address setup time 0 0 ns tsu(A-WH) Address setup time with respect to WEs# 70 70 ns tsu(LB) Lower Byte control setup time 70 70 ns tsu(UB) Upper Byte control setup time 70 70 ns tsu(CE1) Chip select 1 setup time 70 70 ns tsu(CE2) Chip select 2 setup time 70 70 ns tsu(D) Data setup time 35 35 ns th(D) Data hold time 0 0 ns trec(W) Write recovery time 0 0 ns tdis(W) Output disable time WEs# low 30 30 ns tdis(OE) Output disable time OEs# high 30 30 ns ten(W) Output enable time WEs# high 5 5 ns ten(OE) Output enable time from OEs# low 5 5 ns REV. 0.2, MAY 20, 2004 P/N:PM1083 44 MX69F162/164C3BT/B WRITE CYCLE (WEs# control mode) tCW A0~A16/A0~A17 tsu(LB) or tsu(UB) LBs# UBs# (Note3) (Note3) tsu(CE1) CE1s# (Note3) (Note3) tsu(CE2) CE2s (Note3) (Note3) OEs# tsu(A-WH) tsu(A) tw(W) trec(W) tdis(W) WEs# ten(OE) tdis(OE) ten(W) DATA IN STABLE Q0~15 tsu(D) th(D) REV. 0.2, MAY 20, 2004 P/N:PM1083 45 MX69F162/164C3BT/B WRITE CYCLE (LBs#, UBs# control mode) tCW A0~A16/A0~A17 tsu(A) tsu(LB) or trec(W) tsu(UB) LBs# UBs# CE1s# (Note3) (Note3) CE2s (Note3) (Note3) (Note5) WEs# (Note4) (Note3) (Note3) tsu(D) th(D) DATA IN STABLE Q0~15 Note 3: Hatching indicates the state is "don't care". Note 4: A Write occurs during CE1s# low, CE2s high overlaps LBs# and/or UBs# low and WEs# low. Note 5: When the falling edge of WEs# is simultaneously or prior to the falling edge of LBs# and/or UBs# or the falling edge of CE1s# or rising edge of CE2s the outputs are maintained in the high impedance state. Note 6: Don't apply inverted phase signal externally when I/O pin is in output mode. REV. 0.2, MAY 20, 2004 P/N:PM1083 46 MX69F162/164C3BT/B WRITE CYCLE (CE1s# control mode) tCW A0~A16/A0~A17 LBs# UBs# (Note3) tsu(A) tsu(CE1) trec(W) (Note3) CE1s# CE2s (Note3) (Note3) (Note5) WEs# (Note4) (Note3) (Note3) tsu(D) th(D) DATA IN STABLE Q0~15 WRITE CYCLE (CE2s control mode) tCW A0~A16/A0~A17 LBs# UBs# (Note3) tsu(A) tsu(CE1) trec(W) (Note3) CE1s# (Note3) CE2s (Note3) (Note5) WEs# (Note4) (Note3) (Note3) tsu(D) th(D) DATA IN STABLE Q0~15 REV. 0.2, MAY 20, 2004 P/N:PM1083 47 MX69F162/164C3BT/B ORDERING INFORMATION PLASTIC PACKAGE PART NO. Access Time Temperature (ns) Range Type Package Type MX69F162C3BTXBI-70 70 -40~85 C 66 Ball FBGA FBGA 0.8mm MX69F162C3BBXBI-70 70 -40~85 C 66 Ball FBGA FBGA 0.8mm MX69F162C3BTXBI-90 90 -40~85 C 66 Ball FBGA FBGA 0.8mm MX69F162C3BBXBI-90 90 -40~85 C 66 Ball FBGA FBGA 0.8mm MX69F164C3BTXBI-70 70 -40~85 C 66 Ball FBGA FBGA 0.8mm MX69F164C3BBXBI-70 70 -40~85 C 66 Ball FBGA FBGA 0.8mm MX69F164C3BTXBI-90 90 -40~85 C 66 Ball FBGA FBGA 0.8mm MX69F164C3BBXBI-90 90 -40~85 C 66 Ball FBGA FBGA 0.8mm Ball Pitch REV. 0.2, MAY 20, 2004 P/N:PM1083 48 MX69F162/164C3BT/B PACKAGE INFORMATION REV. 0.2, MAY 20, 2004 P/N:PM1083 49 MX69F162/164C3BT/B REVISION HISTORY Revision No. Description 0.1 1. Removed "-" from ordering information 0.2 1. Change part no from MX69F1602/1604C3BT/B to MX69F162/164C3BT/B 2. Add "-" before speed option Page P21,23,48 All Date MAY/14/2004 MAY/20/2004 P21,23,48 REV. 0.2, MAY 20, 2004 P/N:PM1083 50 MX69F162/164C3BT/B MACRONIX INTERNATIONAL CO., LTD. Headquarters: TEL:+886-3-578-6688 FAX:+886-3-563-2888 Europe Office : TEL:+32-2-456-8020 FAX:+32-2-456-8021 Hong Kong Office : TEL:+86-755-834-335-79 FAX:+86-755-834-380-78 Japan Office : Kawasaki Office : TEL:+81-44-246-9100 FAX:+81-44-246-9105 Osaka Office : TEL:+81-6-4807-5460 FAX:+81-6-4807-5461 Singapore Office : TEL:+65-6346-5505 FAX:+65-6348-8096 Taipei Office : TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. TEL:+1-408-262-8887 FAX:+1-408-262-8810 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.