SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D – DECEMBER 1982 – REVISED JULY 2003
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D
Wide Operating Voltage Range of 2 V to 6 V
D
Outputs Can Drive Up To 10 LSTTL Loads
D
Low Power Consumption, 40-µA Max ICC
D
Typical tpd = 15 ns
D
±4-mA Output Drive at 5 V
D
Low Input Current of 1 µA Max
description/ordering information
The ’HC74 devices contain two independent
D-type positive-edge-triggered flip-flops. A low
level at the preset (PRE) or clear (CLR) inputs sets
or resets the outputs, regardless of the levels of
the other inputs. When PRE and CLR are inactive
(high), data at the data (D) input meeting the setup
time requirements are transferred to the outputs
on the positive-going edge of the clock (CLK)
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of CLK.
Following the hold-time interval, data at the
D input can be changed without affecting the
levels at the outputs.
ORDERING INFORMATION
TAPACKAGEORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP – N T ube of 25 SN74HC74N SN74HC74N
T ube of 50 SN74HC74D
SOIC – D Reel of 2500 SN74HC74DR HC74
Reel of 250 SN74HC74DT
–40°C to 85°CSOP – NS Reel of 2000 SN74HC74NSR HC74
SSOP – DB Reel of 2000 SN74HC74DBR HC74
T ube of 90 SN74HC74PW
TSSOP – PW Reel of 2000 SN74HC74PWR HC74
Reel of 250 SN74HC74PWT
CDIP – J T ube of 25 SNJ54HC74J SNJ54HC74J
–55°C to 125°CCFP – W T ube of 150 SNJ54HC74W SNJ54HC74W
LCCC – FK T ube of 55 SNJ54HC74FK SNJ54HC74FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
SN54HC74 ...J OR W PACKAGE
SN74HC74 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
2D
NC
2CLK
NC
2PRE
1CLK
NC
1PRE
NC
1Q
1D
1CLR
NC
2Q
2Q V
2CLR
1Q
GND
NC
SN54HC74 . . . FK PACKAGE
(TOP VIEW)
CC
NC – No internal connection
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D DECEMBER 1982 REVISED JULY 2003
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
HLXXLH
LLXXH
H
H H HHL
H H LLH
H H L X Q0Q0
This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
logic diagram (positive logic)
PRE
CLK
D
CLR
Q
Q
C
C
C
C
C
C
C
C
C
C
TG
TG TG TG
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC 0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D DECEMBER 1982 REVISED JULY 2003
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54HC74 SN74HC74
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0.5 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VCC = 6 V 1.8 1.8
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
VCC = 2 V 1000 1000
t/vInput transition rise/fall time VCC = 4.5 V 500 500 ns
VCC = 6 V 400 400
TAOperating free-air temperature 55 125 40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C SN54HC74 SN74HC74
UNIT
PARAMETER
TEST
CONDITIONS
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 1.998 1.9 1.9
IOH = 20 µA4.5 V 4.4 4.499 4.4 4.4
VOH VI = VIH or VIL 6 V 5.9 5.999 5.9 5.9 V
IOH = 4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = 5.2 mA 6 V 5.48 5.8 5.2 5.34
2 V 0.002 0.1 0.1 0.1
IOL = 20 µA4.5 V 0.001 0.1 0.1 0.1
VOL VI = VIH or VIL 6 V 0.001 0.1 0.1 0.1 V
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
IIVI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
ICC VI = VCC or 0, IO = 0 6 V 4 80 40 µA
Ci2 V to 6 V 3 10 10 10 pF
SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D DECEMBER 1982 REVISED JULY 2003
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25°C SN54HC74 SN74HC74
UNIT
V
CC MIN MAX MIN MAX MIN MAX
UNIT
2 V 6 4.2 5
fclock Clock frequency 4.5 V 31 21 25 MHz
6 V 0 36 0 25 0 29
2 V 100 150 125
PRE or CLR low 4.5 V 20 30 25
t
Pulse duration
6 V 17 25 21
ns
t
w
Pulse
duration
2 V 80 120 100
ns
CLK high or low 4.5 V 16 24 20
6 V 14 20 17
2 V 100 150 125
Data 4.5 V 20 30 25
t
Setu
p
time before CLK
6 V 17 25 21
ns
t
su
Setup
time
before
CLK
2 V 25 40 30
ns
PRE or CLR inactive 4.5 V 5 8 6
6 V 4 7 5
2 V 0 0 0
thHold time, data after CLK
4.5 V 0 0 0 ns
6 V 0 0 0
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO
VCC
TA = 25°C SN54HC74 SN74HC74
UNIT
PARAMETER
(INPUT) (OUTPUT)
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 6 10 4.2 5
fmax 4.5 V 31 50 21 25 MHz
6 V 36 60 25 29
2 V 70 230 345 290
PRE or CLR Q or Q 4.5 V 20 46 69 58
td
6 V 15 39 59 49
ns
t
pd 2 V 70 175 250 220
ns
CLK Q or Q 4.5 V 20 35 50 44
6 V 15 30 42 37
2 V 28 75 110 95
ttQ or Q 4.5 V 8 15 22 19 ns
6 V 6 13 19 16
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per flip-flop No load 35 pF
SN54HC74, SN74HC74
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS094D DECEMBER 1982 REVISED JULY 2003
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
50%
50%50% 10%10% 90% 90%
VCC
VCC
0 V
0 V
trtf
Reference
Input
Data
Input
50%
High-Level
Pulse 50% VCC
0 V
50% 50%
VCC
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%50% 10%10% 90% 90%
VCC
VOH
VOL
0 V
trtf
Input
In-Phase
Output
50%
tPLH tPHL
50% 50%
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-Phase
Output
Test
Point
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily . All input pulses are supplied by generators having the following
characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current andcomplete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’sstandard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support thiswarranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarilyperformed.
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2007, Texas Instruments Incorporated
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
5962-8405601VCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
5962-8405601VDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
84056012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
8405601CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
8405601DA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
JM38510/65302B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
JM38510/65302BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
JM38510/65302BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
SN54HC74J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
SN74HC74ADBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI
SN74HC74D ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74DBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI
SN74HC74DBR ACTIVE SSOP DB 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74DBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74DE4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74DG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74DR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74DRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74DRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74DT ACTIVE SOIC D 14 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74DTE4 ACTIVE SOIC D 14 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74DTG4 ACTIVE SOIC D 14 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74N ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74HC74N3 OBSOLETE PDIP N 14 TBD Call TI Call TI
SN74HC74NE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74HC74NSR ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74NSRE4 ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74NSRG4 ACTIVE SO NS 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74PW ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
no Sb/Br)
SN74HC74PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI
SN74HC74PWR ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74PWT ACTIVE TSSOP PW 14 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74PWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC74PWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SNJ54HC74FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54HC74J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
SNJ54HC74W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC74, SN54HC74-SP, SN74HC74 :
Automotive: SN74HC74-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 2
Enhanced Product: SN74HC74-EP
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Enhanced Product - Supports Defense, Aerospace and Medical Applications
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 3
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HC74DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74HC74DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC74DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC74NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74HC74PWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jul-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC74DBR SSOP DB 14 2000 346.0 346.0 33.0
SN74HC74DR SOIC D 14 2500 346.0 346.0 33.0
SN74HC74DR SOIC D 14 2500 333.2 345.9 28.6
SN74HC74NSR SO NS 14 2000 346.0 346.0 33.0
SN74HC74PWR TSSOP PW 14 2000 346.0 346.0 29.0
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jul-2009
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
MECHANICAL DATA
MLCC006B – OCTOBER 1996
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153