DATASHEET
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER IDT5V41068A
IDT®
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 1
IDT5V41068A REV F 040616
Description
The IDT5V41068A is a 2:1 differential clock mux for PCI
Express applications. It has very low additive jitter making it
suitable for use in PCIe Gen2 and Gen3 systems. The
IDT5V41068A selects between 1 of 2 differential HCSL
inputs to drive a single differential HCSL output pair. The
output can also be terminated to LVDS.
Recommended Applications
•Clock muxing in PCIe Gen2 and Gen3 applications
Output Features
•1 – 0.7V current mode differential HCSL output pair
Features/Benefits
•Low additive jitter; suitable for use in PCIe Gen2 and
Gen3 systems
•16-pin TSSOP package; small board footprint
•Outputs can be terminated to LVDS; can drive a wider
variety of devices
•OE control pin; greater system power management
•Industrial temperature range available; supports
demanding embedded applications
Key Specifications
•Additive cycle-to-cycle jitter <5 ps
•Additive phase jitter (PCIe Gen3) <0.2ps
•Operating frequency up to 200MHz
Block Diagram
VDD
Rr (IREF)
CLK
CLK
SEL GND
IN1
IN1
IN2
IN2
MUX
2 to 1
OE
3
3
PD
IDT5V41068A
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER
IDT®
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 2
IDT5V41068A REV F 040616
Pin Assignment Select Table
Pin Descriptions
VDDIN 1 16 ^SEL
DIF_IN1 2 15 DIF_0
DIF_IN1# 3 14 DIF_0#
^PD# 4 13 GND
DIF_IN2 5 12 GND
DIF_IN2# 6 11 VDD
^OE 7 10 VDD
GND
89
IREF
16-pin TSSOP
5V41068
Note : Pins preceeded by '*^ have internal
120K ohm pull up resistors
SEL Outputs
0DIF_IN2
1DIF_IN1
PIN # PIN NAME PIN TYPE DESCRIPTION
1 VDDIN PWR Power
p
in for the In
p
uts, nominal 3.3V
2 DIF_IN1 IN 0.7 V Differential TRUE in
p
ut
3 DIF_IN1# IN 0.7 V Differential Com
p
lementar
y
In
p
ut
4^PD# IN Asynchronous active low input pin used to power down the device. The internal
clocks are disabled and the VCO and the crystal osc. (if any) are stopped.
5 DIF_IN2 IN 0.7 V Differential TRUE input
6 DIF_IN2# IN 0.7 V Differential Com
p
lementar
y
In
p
ut
7^OE IN Active high input for enabling outputs. This pin has an internal pull up resistor.
0 = disable outputs, 1= enable outputs
8 GND PWR Ground pin.
9IREF OUT
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the standard value for
100ohm differential impedance. Other impedances require different values. See
data sheet.
10 VDD PWR Power su
pp
l
y
, nominal 3.3V
11 VDD PWR Power su
pp
l
y
, nominal 3.3V
12 GND PWR Ground pin.
13 GND PWR Ground pin.
14 DIF_0# OUT 0.7V differential Complementary clock output
15 DIF_0 OUT 0.7V differential true clock out
p
ut
16 ^SEL IN Selects between one of two inputs. This pin has internal pull up resistor.
IDT5V41068A
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER
IDT®
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 3
IDT5V41068A REV F 040616
Application Information
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
IDT5V41068A must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the IDT5V41068A.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
External Components
A minimum number of external components are required for
proper operation. Decoupling capacitors of 0.01F should
be connected between VDD and GND pairs (2,9 and 15,16)
as close to the device as possible.
Current Reference Source Rr (Iref)
If board target trace impedance (Z) is 50, then Rr = 475
(1%), providing IREF of 2.32 mA, output current (IOH) is
equal to 6*IREF.
Load Resistors RL
Since the clock outputs are open source outputs, 50 ohm
external resistors to ground are to be connected at each
clock output.
Output Termination
The PCI-Express differential clock outputs of the
IDT5V41068A are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown in
detail in the Layout Guidelines section.
The IDT5V41068A can also be terminated to LVDS
compatible voltage levels. See the Layout Guidelines
section.
IDT5V41068A
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER
IDT®
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 4
IDT5V41068A REV F 040616
Output Structures
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the IDT5V41068A.This includes signal
traces just underneath the device, or on layers adjacent to
the ground plane layer used by the device.
IDT5V41068A
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER
IDT®
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 5
IDT5V41068A REV F 040616
Layout Guidelines
Common R ecommendations for Differential Routing Dimension or Value Unit Figure
L1 length, route as non-coupled 50ohm trace 0.5 max inch 1
L2 length, route as non-coupled 50ohm trace 0.2 max inch 1
L3 length, route as non-coupled 50ohm trace 0.2 max inch 1
Rs 33 ohm 1
Rt 49.9 ohm 1
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1
L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2
L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2
PCIe (S RC) Re ference Cloc k
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt PCI Express
Down Device
REF_CLK Input
Figure 1: Down Device Routing
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt PCI Express
Add-in Board
REF_CLK Input
Figure 2: PCI Express Connector Routing
IDT5V41068A
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER
IDT®
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 6
IDT5V41068A REV F 040616
Vdiff Vp-p Vcm R1 R2 R3 R4 Note
0.45v 0.22v 1.08 33 150 100 100
0.58 0.28 0.6 33 78.7 137 100
0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible
0.60 0.3 1.2 33 174 140 100 Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Alterna tive Termination for LVDS and other Common Differential Signals (fi gure 3)
HCSL Output Buffer
L1
L1'
R1b
L2
L2'
R1a
L4'
L4
L3
R2a R2b Down Device
REF_CLK Input
Figure 3
L3'
R3 R4
Component Value Note
R5a, R5b 8.2K 5%
R6a, R6b 1K 5%
Cc 0.1 µF
Vcm 0.350 volts
Cable Connected AC Coupled Applicati on (figure 4)
PCIe Device
REF_CLK Input
Figure 4
R5a
L4'
L4
3.3 Volts
R5b
R6a R6b
Cc
Cc
IDT5V41068A
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER
IDT®
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 7
IDT5V41068A REV F 040616
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT5V41068A. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only
over the recommended operating temperature range.
Electrical Characteristics–Input/Supply/Common Parameters
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
3.3V Logic Supply Voltage VDD 4.6 V 1,2
Input Low Voltage V
IL
GND-0.5 V 1
Input High Voltage V
IH
V
DD
+0.5V V 1
Storage Temperature Ts -65 150
°
C1
Junction Temperature Tj 125 °C
1
Input ESD protection ESD prot Human Body Model 2000 V
1
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
TA = TCOM or T
I ND; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
T
COM
Commmercial range 0 70 °C 1
TIND Industrial range -40 85 °C 1
Input High Voltage VIH
Single-ended inputs, excep
t
SMBus, low threshold
and tri-level in
p
uts, if
p
re se nt
2.2 VDD
+ 0.3 V1
Input Low Voltage VIL
Single-ended inputs, excep
t
SMBus, low threshold
and tri-level in
p
uts, if
p
re se nt
GND - 0.3 0.8 V 1
IIN Single-ended inputs, VIN = GND, VIN = VDD -5 5 uA 1
IIN P
Sin gle -ended inp uts
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
-200 200 uA 1
Input Frequency Fibyp VDD = 3.3 V, Bypass mode 200 MHz 2
Pin Inductance L
p
in
7nH1
CIN Logic Inputs, except DIF_IN 1.5 5 pF 1
C
IN DIF _IN
Differential clock inputs 1.5 2.7 pF 1,4
COUT Output pin capacitance 6 pF 1
OE Latency tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion 13clocks1,3,5
PD# Latency t
STABPD#
DIF driven to 200mV after PDE# assertion 300 usec 1,3,5
Tfall tFFall time of control inputs 5 ns 1,2
Trise tRRise time of control inputs 5 ns 1,2
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
5The differential input clock must be running for the OE pin to work
Ambient Operating
Temperature
Input Current
3Time from deassertion until outputs are >200 mV
4 INA/B inputs
Capacitance
IDT5V41068A
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER
IDT®
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 8
IDT5V41068A REV F 040616
Electrical Characteristics–Clock Input Parameters
Electrical Characteristics–DIF 0.7V Current Mode Differential Outputs
Electrical Characteristics–Current Consumption
TA = TCOM or T
IND;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARA ME TER SYM BOL CONDITIONS M IN TY P MAX UNITS N OTE S
Input High Voltage - DIF_IN VIHD IF
Differential inputs
(
sin
g
le-ended measurement
)
600 800 1150 mV 1
Input Low Voltage - DIF_IN VIL DIF
Differential inputs
(
sin
g
le-ended measurement
)
VSS - 300 0300mV1
Input Common Mode Voltage
- DIF_IN
VCOM Common Mode Input Voltage 300 1000 mV 1
Input Amplitude - DIF_IN VSWING Peak to Peak value 300 1450 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 1 8 V/ns 1,2
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
=
GND -5 5 uA 1
Input Duty Cycle dtin Measurement from differential wavefrom 45 55 % 1
Input Jitter - Cycle to Cycle JDIF In Differential Measurement 0 1 25 ps 1
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero.
TA = TCOM or TIND; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Slew rate Trf Scope averaging on 1.5 2.9 4 V/ns 1, 2, 3
Slew rate matching ∆Trf Slew rate matching, Scope averaging on 14 20 %1, 2, 4
Voltage High VHigh 660 761 850 1
Voltage Low VLow -150 0.6 150 1
Max Voltage Vmax 860 1150 1
Min Voltage Vmin -300 -78 1
Vswing Vswing Scope averaging off 300 1531 mV 1, 2
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 354 550 mV 1, 5
Crossing Voltage (var) ∆-Vcross Scope averaging off -29 140 mV 1, 6
2 Measured from differential waveform
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross
absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
mV
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Measurement on single ended signal using
absolute value. (Scope averaging off) mV
1Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA.
I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50Ω (100Ω differential impedance).
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the average
cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope
uses for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
TA = TCOM or T
IND;
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Operating Supply Current IDD3.3OP All outputs active @100MHz, CL = 2 pF; 40 mA 1
Power Down Current
I
DD3 .3PD PD# pin low, input clock stopped 5 mA 1
1Guaranteed by design and characterization, not 100% test ed in production.
IDT5V41068A
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER
IDT®
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 9
IDT5V41068A REV F 040616
Electrical Characteristics–Output Duty Cycle, Jitter, and Skew Characteristics
Electrical Characteristics–PCIe Phase Jitter Parameter
TA = TCOM or TIND; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Duty Cycle t
D
C
When driven by 932SQ420 or equivalent 45 49 55 % 1
Duty Cycle Distortion t
DCD
Measured differentially, @100MHz -2 1 2 % 1,4
Skew, Input to Output t
p
dBYP
V
T
= 50% 2500 3299 4500 ps 1
Additive Jitter tjcyc-cyc Cycle to cycle Additive Jitter 1 5 ps 1,3
1Guaranteed by design and characterization, not 100% tested in production.
2 IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
3 Measured from differential waveform
4 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
TA = TCOM or TIND; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
tjphPCIeG1 PCIe Gen 1 1 2 ps (p-p) 1,2,3,6
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.1 0.2 ps
(rms)
1,2,5,6
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz) 0.1 0.2 ps
(rms) 1,2,5,6
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz) 0.1 0.2 ps
(rms)
1,2,4,5,
6
1 Applies to all outputs.
5
For RMS fi
g
ures, additive jitter is calculated by solvin
g
the followin
g
equation: Additive jitter = SQRT[(total jittter)^2 - (input jitter)^2]
6 Applies to 100MHz spread off and 0.5% down spread sources only.
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 Subject to final radification by PCI SIG.
2 See http://www.pcisig.com for complete specs
tjphPCIeG2
Additive Phase Jitter
33
HCSL Output
33 5050
HCSL Differential Output Test Load
2pF 2pF
Zo=100ohm differential
IDT5V41068A
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER
IDT®
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 10
IDT5V41068A REV F 040616
Thermal Characteristics
Marking Diagram Marking Diagram (Industrial)
Notes:
1. “$” is the mark code.
2. “YYWW” is the last two digits of the year and week that the part was assembled.
3. “G” after the two-letter package code denotes RoHS compliant package.
4. “I” denotes industrial grade.
5. “LOT” denotes the lot number
6. “x” denotes year molded; “y” denotes WW molded
7. Bottom marking: country of origin if not USA.
Parameter Symbol Conditions Min. Typ. Max. Units
Thermal Resistance Junction to
Ambient
JA Still air 93 C/W
JA 1 m/s air flow 78 C/W
JA 3 m/s air flow 65 C/W
Thermal Resistance Junction to Case JC 20 C/W
1 8
916
IDT5V410
68APGG
YYWW$
LOT xy
1 8
916
IDT5V410
68APGGI
YYWW$
LOT xy
IDT5V41068A
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER
IDT®
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 11
IDT5V41068A REV F 040616
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
“G" after the two-letter package code are the Pb-Free configuration, RoHS 6 compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
INDEX
AREA
1 2
16
D
E1 E
SEATING
PLANE
A1
A
A2
e
- C -
b
aaa C
c
L
*For reference only. Controlling dimensions in mm.
Millimeters Inches*
Symbol Min Max Min Max
A -- 1.20 -- 0.047
A1 0.05 0.15 0.002 0.006
A2 0.80 1.05 0.032 0.041
b 0.19 0.30 0.007 0.012
C 0.09 0.20 0.0035 0.008
D 4.90 5.1 0.193 0.201
E 6.40 BASIC 0.252 BASIC
E1 4.30 4.50 0.169 0.177
e 0.65 Basic 0.0256 Basic
L 0.45 0.75 0.018 0.030
a0808
aaa -- 0.10 -- 0.004
P art / Orde r Num be r Ma rking S hipping Pa cka ging Pa cka ge Te m pe ra ture
5V41068APGG See pg 10 Tubes 16-pin TSSOP 0 to +70°C
5V41068APGG8 See pg 10 Tape and Reel 16-pin TSSOP 0 to +70°C
5V41068APGGI See pg 10 Tubes 16-pin TSSOP -40 to +85°C
5V41068APGGI8 See pg 10 Tape and Reel 16-pin TSSOP -40 to +85°C
IDT5V41068A
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER
IDT®
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IDT5V41068A REV F 040616
Revision History
Rev. Originator Issue Date Description Page #
A RDW 1/26/2011 Initial Release
B RDW 6/9/2011
1. Updated ordering info
2. Updated electrical Tables
3. Added mark spec Various
C RDW 7/14/2011 1. Updated Vih min to 2.2V 7
D RDW 10/6/2011 Released to final
E RDW 11/22/2011
1. Changed title to "2:4 PCIe Gen1/2/3 Clock Multiplexer"
2. Updated PCIe Phase Jitter table Various
F RDW 4/6/2016 Corrected error in marking diagram; added lot designator and notes 10
© 2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
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trademarks used to identify products or services of their respective owners.
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IDT5V41068A
2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER