DATASHEET IDT5V41068A 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER Description Features/Benefits The IDT5V41068A is a 2:1 differential clock mux for PCI Express applications. It has very low additive jitter making it suitable for use in PCIe Gen2 and Gen3 systems. The IDT5V41068A selects between 1 of 2 differential HCSL inputs to drive a single differential HCSL output pair. The output can also be terminated to LVDS. * Low additive jitter; suitable for use in PCIe Gen2 and * * * * Recommended Applications * Clock muxing in PCIe Gen2 and Gen3 applications Gen3 systems 16-pin TSSOP package; small board footprint Outputs can be terminated to LVDS; can drive a wider variety of devices OE control pin; greater system power management Industrial temperature range available; supports demanding embedded applications Output Features Key Specifications * 1 - 0.7V current mode differential HCSL output pair * Additive cycle-to-cycle jitter <5 ps * Additive phase jitter (PCIe Gen3) <0.2ps * Operating frequency up to 200MHz Block Diagram OE VDD 3 IN1 IN1 IN2 CLK MUX 2 to 1 CLK IN2 3 SEL IDT(R) 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER Rr (IREF) GND PD 1 IDT5V41068A REV F 040616 IDT5V41068A 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER Pin Assignment 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 5V41068 VDDIN DIF_IN1 DIF_IN1# ^PD# DIF_IN2 DIF_IN2# ^OE GND Select Table ^SEL DIF_0 DIF_0# GND GND VDD VDD IREF SEL Outputs 0 1 DIF_IN2 DIF_IN1 Note: Pins preceeded by '*^ have internal 120K ohm pull up resistors 16-pin TSSOP Pin Descriptions PIN # PIN NAME 1 VDDIN 2 DIF_IN1 3 DIF_IN1# PIN TYPE DESCRIPTION PWR Power pin for the Inputs, nominal 3.3V IN 0.7 V Differential TRUE input IN 0.7 V Differential Complementary Input 4 ^PD# IN Asynchronous active low input pin used to power down the device. The internal c locks are dis abled and the VCO and the crystal os c. (if any) are stopped. 5 6 DIF_IN2 DIF_IN2# IN IN 0.7 V Differential TRUE input 0.7 V Differential Complementary Input 7 ^OE IN Activ e high input for enabling outputs. This pin has an internal pull up resistor. 0 = disable outputs, 1= enable outputs 8 GND PWR 9 IREF OUT VDD VDD GND GND DIF_0# DIF_0 ^SEL PWR PWR PWR PWR OUT OUT IN 10 11 12 13 14 15 16 Ground pin. This pin establishes the reference for the differential current-mode output pairs. It requires a fixed precision resistor to ground. 475ohm is the s tandard value for 100ohm differential impedance. Other impedances require different values. See data sheet. Power supply, nominal 3.3V Power supply, nominal 3.3V Ground pin. Ground pin. 0.7V differential Complementary clock output 0.7V differential true clock output Selects between one of two inputs . This pin has internal pull up resis tor. IDT(R) 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 2 IDT5V41068A REV F 040616 IDT5V41068A 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER Application Information Decoupling Capacitors External Components As with any high-performance mixed-signal IC, the IDT5V41068A must be isolated from system power supply noise to perform optimally. A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01F should be connected between VDD and GND pairs (2,9 and 15,16) as close to the device as possible. Decoupling capacitors of 0.01F must be connected between each VDD and the PCB ground plane. Current Reference Source Rr (Iref) If board target trace impedance (Z) is 50, then Rr = 475 (1%), providing IREF of 2.32 mA, output current (IOH) is equal to 6*IREF. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Load Resistors RL Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. Since the clock outputs are open source outputs, 50 ohm external resistors to ground are to be connected at each clock output. Output Termination The PCI-Express differential clock outputs of the IDT5V41068A are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the Layout Guidelines section. 2) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the IDT5V41068A. The IDT5V41068A can also be terminated to LVDS compatible voltage levels. See the Layout Guidelines section. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. IDT(R) 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 3 IDT5V41068A REV F 040616 IDT5V41068A 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER Output Structures IREF =2.3 mA R R 475 6*IREF See Layout Guidelines Sections - Pages 5, 6 General PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the IDT5V41068A.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. IDT(R) 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 4 IDT5V41068A REV F 040616 IDT5V41068A 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER Layout Guidelines PCIe (SRC) R eference Clock Common Recommendations for Differential Routing D imension or Value L1 length, route as non-coupled 50ohm trace 0.5 max L2 length, route as non-coupled 50ohm trace 0.2 max L3 length, route as non-coupled 50ohm trace 0.2 max Rs 33 Rt 49.9 Unit inch inch inch ohm ohm Figure 1 1 1 1 1 Down Device Differential Routing L4 length, route as coupled microstrip 100ohm differential trace L4 length, route as coupled stripline 100ohm differential trace 2 min to 16 max 1.8 min to 14.4 max inch inch 1 1 Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 100ohm differential trace L4 length, route as coupled stripline 100ohm differential trace 0.25 to 14 max 0.225 min to 12.6 max inch inch 2 2 Figure 1: Down Device Routing L2 L1 Rs L4 L4' L2' L1' Rs HCSL Output Buffer Rt Rt L3' PCI Express Down Device REF_CLK Input L3 Figure 2: PCI Express Connector Routing L2 L1 Rs L4 L4' L2' L1' HCSL Output Buffer Rs Rt Rt L3' IDT(R) 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 5 PCI Express Add-in Board REF_CLK Input L3 IDT5V41068A REV F 040616 IDT5V41068A 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Figure 3 L2 L1 R3 R1a L4 R4 L4' L2' L1' R1b HCSL Output Buffer R2a R2b L3' Down Device REF_CLK Input L3 Cable Connected AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 F Vcm 0.350 volts Figure 4 3.3 Volts R5a R5b R6a R6b Cc L4 L4' Cc IDT(R) 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 6 PCIe Device REF_CLK Input IDT5V41068A REV F 040616 IDT5V41068A 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the IDT5V41068A. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. 1 PARAMETER SYMBOL 3.3V Logic Supply Voltage Input Low Voltage Input High Voltage Storage Temperature Junction Temperature Input ESD protection VDD V IL VIH Ts Tj ESD prot CONDITIONS MIN TYP MAX 4.6 UNITS NOTES V V V C C V GND-0.5 VD D+0.5V 150 125 -65 Human Body Model 2000 1,2 1 1 1 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 Operation under these conditions is neither implied nor guaranteed. Electrical Characteristics-Input/Supply/Common Parameters TA = TCOM or TI ND; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions Ambient Operating Temperature PARAMETER SYMBOL TCOM TIND Input High Voltage V IH Input Low Voltage V IL IIN Input Current IIN P Input Frequency Pin Inductance Fibyp Lpin CIN Capacitance CIN DIF _IN CONDITIONS MIN Commmercial range 0 Industrial range -40 Single-ended inputs, except SMBus, low threshold 2.2 and tri-level inputs, if present Single-ended inputs, except SMBus, low threshold GND - 0.3 and tri-level inputs, if present Single-ended inputs, VIN = GND, VIN = VDD -5 Single-ended inputs VIN = 0 V; Inputs with internal pull-up resistors VIN = VDD; Inputs with internal pull-down resistors COUT OE Latency tLAT OE# PD# Latency Tfall Trise tST ABPD# tF tR 1 Guaranteed by design and characterization, not 100% tested in production. 2 Control input must be monotonic from 20% to 80% of input swing. Time from deassertion until outputs are >200 mV 3 4 INA/B inputs 5 The differential input clock must be running for the OE pin to work IDT(R) 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 7 UNITS NOTES C 1 C 1 V 1 0.8 V 1 5 uA 1 -200 200 uA 1 1.5 1.5 200 7 5 2.7 MHz nH pF pF 2 1 1 1,4 6 pF 1 3 clocks 1,3,5 300 5 5 usec ns ns 1,3,5 1,2 1,2 Output pin capacitance DIF start after OE# assertion D IF stop after OE# deassertion DIF driven to 200mV after PDE# assertion Fall time of control inputs Rise time of control inputs MAX 70 85 VD D + 0.3 V DD = 3.3 V, Bypass mode Logic Inputs, except DIF_IN Differential clock inputs TYP 1 IDT5V41068A REV F 040616 IDT5V41068A 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER Electrical Characteristics-Clock Input Parameters TA = TCOM or TI ND; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions PARAMETER SYMBOL Input High Voltage - DIF_IN V IHD IF Input Low Voltage - DIF_IN VIL DIF Input Common Mode Voltage - DIF_IN Input Amplitude - DIF_IN Input Slew Rate - DIF_IN Input Leakage Current Input Duty Cycle Input Jitter - Cycle to Cycle CONDITIONS Differential inputs (single-ended measurement) Differential inputs (single-ended measurement) MIN TYP MAX UNITS NOTES 600 800 1150 mV 1 VSS - 300 0 300 mV 1 V COM Common Mode Input Voltage 300 1000 mV 1 V SWING dv/dt IIN dtin J DIF In Peak to Peak value Measured differentially VIN = V DD , VIN = GND Measurement from differential wavefrom Differential Measurement 300 1 -5 45 0 1450 8 5 55 125 mV V/ns uA % ps 1 1,2 1 1 1 1 Guaranteed by design and characterization, not 100% tested in production. 2 Slew rate measured through +/-75mV window centered around differential zero. Electrical Characteristics-DIF 0.7V Current Mode Differential Outputs TA = TCOM or TIND; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP Slew rate Slew rate matching Trf Trf Scope averaging on Slew rate matching, Scope averaging on 1.5 2.9 14 4 20 Voltage High VHigh 660 761 850 Voltage Low VLow Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) Max Voltage Min Voltage Vswing Crossing Voltage (abs) Crossing Voltage (var) Vmax Vmin Vswing Vcross_abs -Vcross Measurement on single ended signal using absolute value. (Scope averaging off) Scope averaging off Scope averaging off Scope averaging off MAX UNITS NOTES V/ns % 1, 2, 3 1, 2, 4 1 mV -150 0.6 150 1150 -300 300 250 860 -78 1531 354 -29 1 mV mV mV mV 550 140 1 1 1, 2 1, 5 1, 6 1 Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR ). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50 (100 differential impedance). 2 Measured from differential waveform 3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4 Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope uses for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute. Electrical Characteristics-Current Consumption TA = TCOM or TI ND; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS Operating Supply Current ID D3.3 OP IDD3 .3PD All outputs active @100MHz, CL = 2pF; PD# pin low, input clock stopped Power Down Current 1 MIN TYP MAX 40 5 UNITS NOTES mA mA 1 1 Guaranteed by design and characterization, not 100% tested in production. IDT(R) 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 8 IDT5V41068A REV F 040616 IDT5V41068A 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER Electrical Characteristics-Output Duty Cycle, Jitter, and Skew Characteristics TA = TCOM or TIND; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions PARAMETER SYMBOL CONDITIONS MIN TYP MAX Duty Cycle Duty Cycle Distortion Skew, Input to Output Additive Jitter tDC tDCD When driven by 932SQ420 or equivalent Measured differentially, @100MHz VT = 50% Cycle to cycle Additive Jitter 45 -2 2500 49 1 3299 1 55 2 4500 5 tpdBYP tjcyc-cyc UNITS NOTES % % ps ps 1 1,4 1 1,3 1 Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. I OH = 6 x IREF and VOH = 0.7V @ ZO=50. 2 3 Measured from differential waveform 4 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. Electrical Characteristics-PCIe Phase Jitter Parameter TA = TCOM or TIND; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions PARAMETER Additive Phase Jitter SYMBOL CONDITIONS t jphPCIeG1 PCIe Gen 1 t jphPCIeG2 t jphPCIeG3 MIN PCIe Gen 2 Lo Band 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) TYP MAX 1 2 0.1 0.2 0.1 0.2 0.1 0.2 UNITS Notes ps (p-p) 1,2,3,6 ps (rms) ps (rms) ps (rms) 1,2,5,6 1,2,5,6 1,2,4,5, 6 1 Applies to all outputs. 2 See http://www.pcisig.com for complete specs 3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 4 Subject to final radification by PCI SIG. 5 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jittter)^2 - (input jitter)^2] 6 Applies to 100MHz spread off and 0.5% down spread sources only. HCSL Differential Output Test Load Zo=100ohm differential 33 33 HCSL Output IDT(R) 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 2pF 50 2pF 50 9 IDT5V41068A REV F 040616 IDT5V41068A 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER Thermal Characteristics Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Conditions Max. Units Still air 93 C/W JA 1 m/s air flow 78 C/W JA 3 m/s air flow 65 C/W 20 C/W JC Marking Diagram (Industrial) 16 9 9 IDT5V410 68APGGI YYWW$ IDT5V410 68APGG YYWW$ LOT xy LOT xy 1 Typ. JA Marking Diagram 16 Min. 1 8 8 Notes: 1. "$" is the mark code. 2. "YYWW" is the last two digits of the year and week that the part was assembled. 3. "G" after the two-letter package code denotes RoHS compliant package. 4. "I" denotes industrial grade. 5. "LOT" denotes the lot number 6. "x" denotes year molded; "y" denotes WW molded 7. Bottom marking: country of origin if not USA. IDT(R) 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 10 IDT5V41068A REV F 040616 IDT5V41068A 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 16 Symbol E1 A A1 A2 b C D E E1 e L a aaa E INDEX AREA 1 2 D A A2 Min Max -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10 Inches* Min Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004 *For reference only. Controlling dimensions in mm. A1 c -Ce b SEATING PLANE L aaa C Ordering Information Pa rt / Orde r Num be r 5V41068APGG 5V41068APGG8 5V41068APGGI 5V41068APGGI8 Ma rking See pg 10 See pg 10 See pg 10 See pg 10 Shipping Pa cka ging Tubes Tape and Reel Tubes Tape and Reel Pa cka ge 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP Te m pe ra ture 0 to +70C 0 to +70C -40 to +85C -40 to +85C "G" after the two-letter package code are the Pb-Free configuration, RoHS 6 compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT(R) 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 11 IDT5V41068A REV F 040616 IDT5V41068A 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER Revision History Rev. A B C D E F Originator Issue Date Description RDW 1/26/2011 Initial Release 1. Updated ordering info 2. Updated electrical Tables RDW 6/9/2011 3. Added mark spec RDW 7/14/2011 1. Updated Vih min to 2.2V RDW 10/6/2011 Released to final 1. Changed title to "2:4 PCIe Gen1/2/3 Clock Multiplexer" RDW 11/22/2011 2. Updated PCIe Phase Jitter table RDW 4/6/2016 Corrected error in marking diagram; added lot designator and notes IDT(R) 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER 12 Page # Various 7 Various 10 IDT5V41068A REV F 040616 IDT5V41068A 2:1 PCIE GEN1/2/3 CLOCK MULTIPLEXER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com Sales Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/support Corporate Headquarters Integrated Device Technology, Inc. www.idt.com (c) 2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA