Low Noise, Precision, Rail-to-Rail Output,
JFET Single/Dual/Quad Op Amps
Data Sheet
ADA4610-1/ADA4610-2/ADA4610-4
Rev. H Document Feedback
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FEATURES
Low offset voltage
B grade: 0.4 mV maximum (ADA4610-1/ADA4610-2 only)
A grade: 1 mV maximum
Low offset voltage drift
B grade: 4 µV/°C maximum (ADA4610-1/ADA4610-2 only)
A grade: 8 µV/°C maximum (SOIC, MSOP, LFCSP packages)
Low input bias current: 5 pA typical
Dual-supply operation: ±5 V to ±15 V
Low voltage noise: 0.45 µV p-p at 0.1 Hz to 10 Hz
Voltage noise density: 7.30 nV/√Hz at f = 1 kHz
Low THD + N: 0.00025%
No phase reversal
Rail-to-rail output
Unity-gain stable
Long-term offset voltage drift (10,000 hours): 5 µV typical
Temperature hysteresis: 8 µV typical
APPLICATIONS
Instrumentation
Medical instruments
Multipole filters
Precision current measurement
Photodiode amplifiers
Sensors
Audio
PIN CONFIGURATION
09646-002
OUT A 1
–IN A 2
+IN A 3
V– 4
V+
8
OUT B
7
–IN B
6
+I N B
5
ADA4610-2
TOP VIEW
(No t t o Scale)
Figure 1. ADA4610-2 8-Lead SOIC (R Suffix); for Additional Packages and
Models, See the Pin Configurations and Function Descriptions Section
GENERAL DESCRIPTION
The ADA4610-1/ADA4610-2/ADA4610-4 are precision junction
field effect transistor (JFET) amplifiers that feature low input noise
voltage, current noise, offset voltage, input bias current, and rail-to-
rail output. The ADA4610-1 is a single amplifier, the ADA4610-2 is
a dual amplifier, and the ADA4610-4 is a quad amplifier.
The combination of low offset, noise, and very low input bias
current makes these amplifiers especially suitable for high
impedance sensor amplification and precise current measurements
using shunts. With excellent dc precision, low noise, and fast
settling time, the ADA4610-1/ADA4610-2/ADA4610-4 provide
superior accuracy in medical instruments, electronic measurement,
and automated test equipment. Unlike many competitive
amplifiers, the ADA4610-1/ADA4610-2/ADA4610-4 maintain
fast settling performance with substantial capacitive loads. Unlike
many older JFET amplifiers, the ADA4610-1/ADA4610-2/
ADA4610-4 do not suffer from output phase reversal when input
voltages exceed the maximum common-mode voltage range.
The fast slew rate and great stability with capacitive loads make
the ADA4610-1/ADA4610-2/ADA4610-4 ideal for high
performance filters. Low input bias currents, low offset, and low
noise result in a wide dynamic range for photodiode amplifier
circuits. Low noise and distortion, high output current, and
excellent speed make the ADA4610-1/ADA4610-2/ADA4610-4
great choices for audio applications.
The ADA4610-1/ADA4610-2/ADA4610-4 are specified over
the −40°C to +125°C extended industrial temperature range.
The ADA4610-1 is available in an 8-lead SOIC package and in a
5-lead SOT-23 package. The ADA4610-2 is available in 8-lead
SOIC, 8-lea d M S O P, a n d 8 -lead LFCSP packages. The ADA4610-4
is available in a 14-lead SOIC package and in a 16-lead LFCSP.
Table 1. Related Precision JFET Operational Amplifiers
Single Dual Quad
AD8510 AD8512 AD8513
AD8610 AD8620 Not applicable
AD820 AD822 AD824
ADA4627-1/ADA4637-1
Not applicable
Not applicable
Not applicable
ADA4001-2
Not applicable
ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet
Rev. H | Page 2 of 27
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Configuration ............................................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Electrical Characteristics ............................................................. 5
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 11
Comparative Voltage and Variable Voltage Graphs ............... 17
Theory of Operation ...................................................................... 20
Applications Information .............................................................. 21
Input Overvoltage Protection ................................................... 21
Peak Detector .............................................................................. 21
Current to Voltage (I to V) Conversion Applications ........... 21
Comparator Operation .............................................................. 22
Long-Term Drift ......................................................................... 23
Temperature Hysteresis ............................................................. 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 27
Data Sheet ADA4610-1/ADA4610-2/ADA4610-4
Rev. H | Page 3 of 27
REVISION HISTORY
5/2017—Rev. G to Rev. H
Changed CP-8-21 to CP-8-11 ...................................... Throughout
Changes to Features Section ............................................................ 1
Changes to Figure 15 Caption, Figure 16 Caption, Figure 18
Caption, and Figure 19 Caption .................................................... 12
Changed Functional Description Section to Theory of
Operation Section ........................................................................... 20
Added Long-Term Drift Section, Temperature Hysteresis Section,
Figure 61, Figure 62, and Figure 63; Renumbered Sequentially ..... 23
Updated Outline Dimensions ........................................................ 24
Changes to Ordering Guide ........................................................... 27
5/2016—Rev. F to Rev. G
Changed CP-8-20 to CP-8-21 ...................................... Throughout
Changes to Figure 23 Caption and Figure 26 Caption ............... 13
Updated Outline Dimensions ........................................................ 24
Changes to Ordering Guide ........................................................... 25
1/2016—Rev. E to Rev. F
Added 5-Lead SOT-23 ....................................................... Universal
Changed CP-8-9 to CP-8-20 ........................................ Throughout
Change to Features Section .............................................................. 1
Added Figure 3 and Table 7; Renumbered Sequentially .............. 8
Updated Outline Dimensions ........................................................ 23
Changes to Ordering Guide ........................................................... 25
4/2015—Rev. D to Rev. E
Added ADA4610-1 ............................................................ Universal
Added 16-Lead LFCSP_WQ ............................................. Universal
Deleted Figure 1 and Figure 3; Renumbered Sequentially .......... 1
Changes to Features Section ............................................................ 1
Changes to Table 2 ............................................................................ 4
Changes to Table 3 ............................................................................. 5
Added Figure 2 and Table 6; Renumbered Sequentially .............. 7
Added Figure 4 .................................................................................. 8
Added Figure 7 .................................................................................. 9
Changes to Table 8 ............................................................................ 9
Changes to Figure 10 Caption and Figure 13 Caption ............... 10
Changes to Figure 14 Caption, Figure 15, Figure 17 Caption,
and Figure 18 ................................................................................... 11
Changes to Figure 22 and Figure 25 ............................................. 12
Changes to Figure 26 to Figure 31 ................................................ 13
Changes to Figure 32 and Figure 35 ............................................. 14
Changes to Figure 38 and Figure 40 ............................................. 15
Changes to Figure 42 to Figure 46 ................................................ 16
Changes to Figure 48, Figure 50, and Figure 53 .......................... 17
Changes to Figure 54 and Figure 55 ............................................. 18
Changes to Figure 57 and Figure 58 ............................................. 20
Updated Outline Dimensions ........................................................ 22
Added Figure 64 .............................................................................. 23
Changes to Ordering Guide ........................................................... 24
11/2014—Rev. C to Rev. D
Change to Figure 56 ........................................................................ 19
5/2014—Rev. B to Rev. C
Added ADA4610-4 and 14-Lead SOIC ........................... Universal
Added Voltage Noise Density to Features Section, Figure 3, and
Table 1; Renumbered Sequentially .................................................. 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 4
Changes to Table 4 ............................................................................ 6
Added Pin Configurations and Function Descriptions
Section, Figure 4 to Figure 6, Table 6, and Table 7 ....................... 7
Changes to Typical Performance Characteristics Section ........... 8
Added Functional Description Section ........................................ 17
Added Input Overvoltage Protection Section, Peak Detector
Section, I to V Conversion Applications Section, and
Photodiode Circuits Section .......................................................... 18
Change to Figure 56 ........................................................................ 18
Added Figure 62, Outline Dimensions ........................................ 20
Changes to Ordering Guide ........................................................... 20
8/2012—Rev. A to Rev. B
Changes to Figure 9 .......................................................................... 8
5/2012—Rev. 0 to Rev. A
Changes to Data Sheet Title and General Description Section .. 1
Changed Input Impedance Parameter, Differential to Input
Capacitance Parameter, and Differential Parameter, Table 1 ...... 3
Added Input Resistance in Table 1.................................................. 3
Changed Input Impedance, Differential Parameter to Input
Capacitance, Differential Parameter, Table 2 ................................ 4
Added Input Resistance Parameter, Table 2 .................................. 4
Added Figure 9, Figure 10, and Figure 14; Renumbered
Sequentially ........................................................................................ 8
Added Figure 15 ................................................................................ 9
Updated Outline Dimensions........................................................ 16
Changes to Ordering Guide ........................................................... 17
12/2011—Revision 0: Initial Version
ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet
Rev. H | Page 4 of 27
SPECIFICATIONS
VSY = ±5 V, VCM = 0 V, T A = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS
B Grade (ADA4610-1/ADA4610-2) 0.2 0.4 mV
−40°C < TA < +125°C 0.8 mV
A Grade 0.4 1 mV
−40°C < TA < +125°C 1.8 mV
Offset Voltage Drift
OS
B Grade (ADA4610-1/ADA4610-2)1 0.5 4 µV/°C
A Grade1 (SOIC, MSOP, LFCSP) 1 8 µV/°C
A Grade1 (SOT-23) 1 12 µV/°C
Input Bias Current IB 5 25 pA
−40°C < TA < +125°C 1.5 nA
Input Offset Current IOS 2 20 pA
−40°C < TA < +125°C 0.25 nA
Input Voltage Range −2.5 +2.5 V
Common-Mode Rejection Ratio CMRR VCM = −2.5 V to +2.5 V 94 110 dB
−40°C < TA < +125°C 86 dB
Large Signal Voltage Gain AVO RL = 2 kΩ, VOUT = −3.5 V to +3.5 V
ADA4610-2 98 100 dB
−40°C < TA < +125°C 86 dB
ADA4610-1/ADA4610-4 96 98 dB
−40°C < TA < +125°C 84 dB
Input Capacitance VCM = 0 V
Differential
3.1
pF
Common-Mode 4.8 pF
Input Resistance VCM = 0 V >1013 Ω
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 2 kΩ 4.85 4.90 V
−40°C < TA < +125°C 4.60 V
RL = 600 Ω 4.60 4.89 V
−40°C < TA < +125°C 4.05 V
Output Voltage Low
OL
R
L
= 2 kΩ
−4.95
−4.90
V
−40°C < TA < +125°C −4.75 V
RL = 600 Ω −4.90 −4.80 V
−40°C < TA < +125°C −4.40 V
Short-Circuit Current ISC ±63 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = ±4.5 V to ±18 V
ADA4610-2 106 125 dB
−40°C < TA < +125°C 103 dB
ADA4610-1/ADA4610-4 104 117 dB
−40°C < TA < +125°C 100 dB
Supply Current per Amplifier ISY IOUT = 0 mA 1.50 1.70 mA
−40°C < TA < +125°C 1.85 mA
Data Sheet ADA4610-1/ADA4610-2/ADA4610-4
Rev. H | Page 5 of 27
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
Slew Rate ±SR RL = 2 kΩ, AV = 1
Rising 151 21 V/µs
Falling 151 46 V/µs
Gain Bandwidth Product
V
IN
= 5 mV p-p, R
L
= 2 kΩ, A
V
= 100
15.4
MHz
Unity-Gain Crossover UGC VIN = 5 mV p-p, RL = 2 kΩ, AV = 1 9.3 MHz
Phase Margin φM 61 Degrees
−3 dB Closed-Loop Bandwidth −3 dB AV = 1, VIN = 5 mV p-p 10.6 MHz
Total Harmonic Distortion + Noise THD + N 1 kHz, AV = 1, RL = 2 kΩ, VIN = 1 V rms 0.00025 %
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.45 µV p-p
Voltage Noise Density en f = 10 Hz 14 nV/√Hz
f = 100 Hz 8.20 nV/√Hz
f = 1 kHz
7.30
nV/√Hz
f = 10 kHz 7.30 nV/√Hz
1 Guaranteed by design and characterization.
ELECTRICAL CHARACTERISTICS
VSY = ±15 V, VCM = 0 V, T A = 25°C, unless otherwise noted.
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS
B Grade (ADA4610-1/ADA4610-2) 0.2 0.4 mV
−40°C < TA < +125°C 0.8 mV
A Grade
0.4
1
mV
−40°C < TA < +125°C 1.8 mV
Offset Voltage Drift ΔVOS/ΔT
B Grade (ADA4610-1/ADA4610-2)1 0.5 4 µV/°C
A Grade1 (SOIC, MSOP, LFCSP) 1 8 µV/°C
A Grade1 (SOT-23) 1 12 µV/°C
Input Bias Current IB 5 25 pA
−40°C < TA < +125°C 1.50 nA
Input Offset Current IOS 2 20 pA
−40°C < TA < +125°C 0.25 nA
Input Voltage Range −12.5 +12.5 V
Common-Mode Rejection Ratio CMRR VCM = −12.5 V to +12.5 V 100 115 dB
−40°C < TA < +125°C 96 dB
Large Signal Voltage Gain AVO RL = 2 kΩ, VOUT = ±13.5 V
ADA4610-2 104 107 dB
−40°C < TA < +125°C 91 dB
ADA4610-1/ADA4610-4 102 104 dB
−40°C < T
A
< +125°C
86
dB
Input Capacitance VCM = 0 V
Differential 3.1 pF
Common-Mode 4.8 pF
Input Resistance VCM = 0 V >1013 Ω
ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet
Rev. H | Page 6 of 27
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 2 kΩ 14.80 14.90 V
−40°C < TA < +125°C 14.65 V
RL = 600 Ω 14.25 14.47 V
−40°C < T
A
< +125°C
13.35
V
Output Voltage Low VOL RL = 2 kΩ −14.90 −14.85 V
−40°C < TA < +125°C −14.75 V
RL = 600 Ω −14.68 −14.60 V
−40°C < TA < +125°C −14.30 V
Short-Circuit Current ISC ±79 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = ±4.5 V to ±18 V
ADA4610-2 106 125 dB
−40°C < T
A
< +125°C
103
dB
ADA4610-1/ADA4610-4 104 117 dB
−40°C < TA < +125°C 100 dB
Supply Current per Amplifier ISY IOUT = 0 mA 1.60 1.85 mA
−40°C < TA < +125°C 2.0 mA
DYNAMIC PERFORMANCE
Slew Rate ±SR RL = 2 kΩ, AV = +1
Rising 171 25 V/µs
Falling 171 61 V/µs
Gain Bandwidth Product GBP VIN = 5 mV p-p, RL = 2 kΩ, AV = 100 16.3 MHz
Unity-Gain Crossover UGC VIN = 5 mV p-p, RL = 2 kΩ, AV = 1 9.3 MHz
Phase Margin φM 66 Degrees
−3 dB Closed-Loop Bandwidth −3 dB AV = 1, VIN = 5 mV p-p 9.5 MHz
Total Harmonic Distortion + Noise THD + N 1 kHz, AV = 1, RL = 2 kΩ, VIN = 5 V rms 0.00025 %
NOISE PERFORMANCE
Peak-to-Peak Voltage Noise en p-p 0.1 Hz to 10 Hz bandwidth 0.45 µV p-p
Voltage Noise Density
e
n
f = 10 Hz
14
nV/√Hz
f = 100 Hz 8.50 nV/√Hz
f = 1 kHz 7.30 nV/√Hz
f = 10 kHz 7.30 nV/√Hz
1 Guaranteed by design and characterization.
Data Sheet ADA4610-1/ADA4610-2/ADA4610-4
Rev. H | Page 7 of 27
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage ±18 V
Input Voltage
±V
S
Input Current1 ±10 mA
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Electrostatic Discharge (ESD)
Human Body Model (HBM)2 2500 V
Field Induced Charge Device Model (FICDM)3 1250 V
1 The input pins have clamp diodes connected to the power supply pins. Limit
the input current to 10 mA or less whenever input signals exceed the power
supply rail by 0.3 V.
2 ESDA/JEDEC JS-001-2011 applicable standard.
3 JESD22-C101 (ESD FICDM standard of JEDEC) applicable standard.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Table 5. Thermal Resistance
Package Type θJA1 θJC Unit
5-Lead SOT-23 219.4 155.6 °C/W
8-Lead SOIC 120 43 °C/W
8-Lead LFCSP 57 12 °C/W
8-Lead MSOP 142 45 °C/W
14-Lead SOIC 115 36 °C/W
16-Lead LFCSP 65 3.2 °C/W
1 θJA is specified for worst-case conditions, that is, θJA is specified for a device
soldered in a circuit board for surface-mount packages.
ESD CAUTION
ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet
Rev. H | Page 8 of 27
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NIC 1
–IN 2
+IN 3
V– 4
NIC
8
V+
7
OUT
6
NIC
5
NOTES
1. NI C = NOT INT E RNALL Y CONNECTED.
ADA4610-1
TOP VIEW
(No t t o Scale)
09646-101
Figure 2. ADA4610-1 Pin Configuration, 8-Lead SOIC (R Suffix)
Table 6. ADA4610-1 Pin Function Descriptions, 8-Lead SOIC
Pin No. Mnemonic Description
1, 5, 8 NIC Not Internally Connected.
2
−IN
Inverting Input.
3 +IN Noninverting Input.
4 V− Negative Supply Voltage.
6 OUT Output.
7 V+ Positive Supply Voltage.
09646-100
OUT 1
+IN 3
V– 2
V+
5
–IN
4
ADA4610-1
TOP VI EW
(No t t o Scale)
Figure 3. ADA4610-1 Pin Configuration, 5-Lead SOT-23 (RJ Suffix)
Table 7. ADA4610-1 Pin Function Descriptions, 5-Lead SOT-23
Pin No. Mnemonic Description
1 OUT Output.
2 V− Negative Supply Voltage.
3 +IN Noninverting Input.
4 −IN Inverting Input.
5 V+ Positive Supply Voltage.
Data Sheet ADA4610-1/ADA4610-2/ADA4610-4
Rev. H | Page 9 of 27
09646-104
OUT A 1
–IN A
2
+IN A
3
V–
4
V+
8
OUT B
7
–IN B
6
+IN B
5
ADA4610-2
TOP VIEW
(No t t o Scal e)
Figure 4. ADA4610-2 Pin Configuration, 8-Lead SOIC (R Suffix)
OUT A
–IN A
+IN A
V–
V+
OUT B
–IN B
+IN B
1
2
3
4
8
7
6
5
ADA4610-2
TOP VIEW
(No t t o Scal e)
09646-102
Figure 5. ADA4610-2 Pin Configuration, 8-Lead MSOP (RM Suffix)
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO V–.
OUT A
–IN A
+IN A
V–
OUT B
V+
–IN B
+IN B
09646-105
3
4
1
2
6
5
8
7
ADA4610-2
TOP VIEW
(No t t o Scal e)
Figure 6. ADA4610-2 Pin Configuration, 8-Lead LFCSP (CP Suffix)
Table 8. ADA4610-2 Pin Function Descriptions, 8-Lead SOIC, 8-Lead MSOP, and 8-Lead LFCSP
Pin No. Mnemonic Description
1 OUT A Output Channel A.
2 −IN A Inverting Input Channel A.
3 +IN A Noninverting Input Channel A.
4 V− Negative Supply Voltage.
5 +IN B Noninverting Input Channel B.
6
−IN B
Inverting Input Channel B.
7 OUT B Output Channel B.
8 V+ Positive Supply Voltage.
EPAD Exposed Pad for the 8-Lead LFCSP (CP Suffix). The exposed pad must be connected to V−.
ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet
Rev. H | Page 10 of 27
OUT A
1
–IN A
2
+IN A
3
V+
4
OUT D
14
–IN D
13
+IN D
12
V–
11
+IN B
5
+IN C
10
–IN B
6
–IN C
9
OUT B
7
OUT C
8
ADA4610-4
TOP VIEW
(No t t o Scal e)
09646-106
Figure 7. ADA4610-4 Pin Configuration, 14-Lead SOIC (R Suffix)
12
11
10
1
3
4
–IN D
+IN D
V–
9+IN C
–IN A
V+
2
+IN A
+IN B
6OUT B
5–IN B
7OUT C
8
–IN C
16 NIC
15 OUT A
14 OUT D
13 NIC
TOP
VIEW
ADA4610-4
NOTES
1. NIC = NOT INT E RNALL Y CONNECTED.
2.T HE EXPOSED PAD MUST BE CONNECTED TO V–.
09646-107
Figure 8. ADA4610-4 Pin Configuration, 16-Lead LFCSP (CP Suffix)
Table 9. ADA4610-4 Pin Function Descriptions, 14-Lead SOIC and 16-Lead LFCSP
Pin No.
14-Lead SOIC 16-Lead LFCSP Mnemonic Description
1 15 OUT A Output Channel A.
2 1 −IN A Inverting Input Channel A.
3 2 +IN A Noninverting Input Channel A.
4 3 V+ Positive Supply Voltage.
5 4 +IN B Noninverting Input Channel B.
6 5 −IN B Inverting Input Channel B.
7 6 OUT B Output Channel B.
8 7 OUT C Output Channel C.
9 8 −IN C Inverting Input Channel C.
10 9 +IN C Noninverting Input Channel C.
11
10
V−
Negative Supply Voltage.
12 11 +IN D Noninverting Input Channel D.
13 12 −IN D Inverting Input Channel D.
14 14 OUT D Output Channel D.
Not applicable 13, 16 NIC Not Internally Connected.
Not applicable EPAD Exposed Pad. The exposed pad must be connected to V−.
Data Sheet ADA4610-1/ADA4610-2/ADA4610-4
Rev. H | Page 11 of 27
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
400
350
300
250
200
150
100
50
0
–1000 –800 –600 –400 –200 0200 400 600 800 1000 1200
OFFSET VOLTAGE (µV)
NUMBER O F CHANNELS
09646-003
SOIC
Figure 9. Input Offset Voltage Distribution, VSY = ±5 V
350
300
250
200
150
100
50
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
TCV
OS
(µV/°C)
NUMBER OF CHANNE LS
09646-004
SOIC
Figure 10. Input Offset Voltage Drift (TCVOS) Distribution, VSY = ±5 V
09646-005
–1500
–1000
–500
0
500
1000
1500
–5 –4 –3 –2 –1 012345
V
CM
(V)
INPUT OFFSET VOLTAGE (µV)
MEAN
MEAN + 3σ
MEAN – 3σ
Figure 11. Input Offset Voltage vs. Common-Mode Input Voltage (VCM),
VSY = ±5 V, RL = ∞
400
350
300
250
200
150
100
50
0
–1000 –800 –600 –400 –200 0200 400 600 800 1000 1200
OFFSET VOLTAGE (µV)
NUMBER O F CHANNELS
09646-006
SOIC
Figure 12. Input Offset Voltage Distribution, VSY = ±15 V
350
300
250
200
150
100
50
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
TCV
OS
(µV/°C)
NUMBER OF CHANNE LS
09646-007
SOIC
Figure 13. TCVOS Distribution, VSY = ±15 V
09646-008
–1500
–1000
–500
0
500
1000
1500
–15 –10 –5 0
V
CM
(V)
510 15
INPUT OFFSET VOLTAGE (uV)
MEAN
MEAN + 3σ
MEAN – 3σ
Figure 14. Input Offset Voltage vs. Input Common-Mode Voltage (VCM),
VSY = ±15 V, RL = ∞
ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet
Rev. H | Page 12 of 27
09646-055
–50
–40
–30
–20
–10
0
10
20
30
40
50
–5 –4 –3 –2 –1 0
VCM (V) 12345
INPUT BI AS CURRE NT (pA)
MEAN
MEAN + 3σ
MEAN – 3σ
Figure 15. Input Bias Current vs. Common-Mode Input Voltage (VCM),
Mean and Three Standard Deviations, VSY = ±5 V, RL = ∞
10
1
100
1k
10k
100k
0.01
0.1
–5
INPUT BI AS CURRE NT (pA)
V
CM
(V)
09646-056
+125°C
+25°C
–4 –3 –2 –1 0 1 2 3 4 5
–40°C
SOIC
Figure 16. Input Bias Current vs. Common-Mode Input Voltage (VCM),
Three Temperatures, VSY = ±5 V, RL = ∞
100
10
1
0.1
–50 –25 025 50 75 100 125
TEMPERATURE (°C)
INPUT BI AS CURRE NT (pA)
09646-009
Figure 17. Input Bias Current vs. Temperature, VSY = ±5 V
–15 –10 10–5 50 15
INPUT BI AS CURRE NT (pA)
V
CM
(V)
09646-057
–50
–40
–30
–20
–10
0
10
20
30
40
50
MEAN
MEAN + 3σ
MEAN – 3σ
Figure 18. Input Bias Current vs. Common-Mode Input Voltage (VCM),
Mean and Three Standard Deviations, VSY = ±15 V, RL = ∞
–15 –10 10–5 50 15
INPUT BI AS CURRE NT (pA)
V
CM
(V)
09646-058
10
1
100
1k
10k
100k
0.1
+125°C
+25°C
–40°C
SOIC
Figure 19. Input Bias Current vs. Common-Mode Input Voltage (VCM),
Three Temperatures, VSY = ±15 V, RL = ∞
100
10
1
0.1
–50 –25 025 50 75 100 125
TEMPERATURE (°C)
INPUT BI AS CURRE NT (pA)
09646-012
Figure 20. Input Bias Current vs. Temperature, VSY = ±15 V
Data Sheet ADA4610-1/ADA4610-2/ADA4610-4
Rev. H | Page 13 of 27
1
0.1
0.01
0.1 110 100
I
OUT
SOURCE ( mA)
(V+ – V
OUT
) (V)
09646-011
Figure 21. Dropout Voltage (V+ − VOUT) vs. IOUT Source, VSY = ±5 V
0.1 110 100
IOUT SI NK ( mA)
09646-015
10
1
0.1
0.01
(VOUT – V–) (V)
Figure 22. Dropout Voltage (VOUT − V−) vs. IOUT Sink, VSY = ±5 V
120 270
225
180
135
90
45
0
–45
–90
100
80
60
40
20
0
–20
–4010 100 1k 10k 100k 1M 10M 100M
FRE Q UE NCY ( Hz )
GAI N ( dB)
PHASE ( Degrees)
09646-016
GAIN
PHASE
Figure 23. Open-Loop Gain and Phase Margin vs. Frequency,
VSY = ±5 V, RL = 2 kΩ, VIN = 5 mV
0.01
0.1 110 100
I
OUT
SOURCE ( mA)
09646-014
1
0.1
0.01
(V+ – V
OUT
) (V)
Figure 24. Dropout Voltage (V+ − VOUT) vs. IOUT Source, VSY = ±15 V
10
1
0.1
0.01 10.10.01 10 100
IOUT SI NK ( mA)
(VOUT – V–) (V)
09646-018
Figure 25. Dropout Voltage (VOUT − V−) vs. IOUT Sink, VSY = ±15 V
120 270
225
180
135
90
45
0
–45
–90
100
80
60
40
20
0
–20
–4010 100 1k 10k 100k 1M 10M 100M
FRE Q UE NCY ( Hz )
GAI N ( dB)
PHASE ( Degrees)
09646-019
GAIN
PHASE
Figure 26. Open-Loop Gain and Phase Margin vs. Frequency,
VSY = ±15 V, RL = 2 kΩ, VIN = 5 mV
ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet
Rev. H | Page 14 of 27
60
40
20
0
–20
–401k 10k 100k 1M 10M 100M
FRE Q UE NCY ( Hz )
GAI N ( dB)
09646-017
AV = +100
AV = +10
AV = +1
Figure 27. Closed-Loop Gain vs. Frequency, VSY = ±5 V
1k
100
10
1
0.1
0.01 1k100 10k 100k 1M 10M 100M
FRE Q UE NCY ( Hz )
Z
OUT
(Ω)
09646-021
A
V
= +100
AV = +10
A
V
= +1
Figure 28. Closed-Loop Output Impedance (ZOUT) vs. Frequency, VSY = ±5 V
120
100
80
60
40
20
0
–20 1k100 10k 100k 1M 10M
FRE Q UE NCY ( Hz )
PSRR (dB)
09646-022
PSRR–
PSRR+
Figure 29. PSRR vs. Frequency, VSY = ±5 V
60
40
20
0
–20
–401k 10k 100k 1M 10M 100M
FREQUENCY ( Hz )
GAI N ( dB)
09646-020
AV = +100
AV = +10
AV = +1
Figure 30. Closed-Loop Gain vs. Frequency, VSY = ±15 V
1k
100
10
1
0.1
0.01 1k100 10k 100k 1M 10M 100M
FRE Q UE NCY ( Hz )
Z
OUT
(Ω)
09646-024
A
V
= +100
A
V
= +10
A
V
= +1
Figure 31. Closed-Loop Output Impedance (ZOUT) vs. Frequency, VSY = ±15 V
120
100
80
60
40
20
0
–20 1k100 10k 100k 1M 10M
FREQUENCY ( Hz )
PSRR (dB)
09646-025
PSRR–
PSRR+
Figure 32. PSRR vs. Frequency, VSY = ±15 V
Data Sheet ADA4610-1/ADA4610-2/ADA4610-4
Rev. H | Page 15 of 27
120
140
100
80
60
40
20
01k100 10k 100k 1M 10M
FRE Q UE NCY ( Hz )
CMRR (dB)
09646-023
Figure 33. CMRR vs. Frequency, VSY = ±5 V
3
2
1
0
–1
–2
–30 1 2 3 4 5 6 7 8 9 10
TIME (µs)
OUTPUT VOLTAGE (V)
09646-027
Figure 34. Large Signal Transient Response, VSY = ±5 V, AV = 1,
RL = 2 kΩ, CL = 100 pF
75
50
25
0
–25
–50
–75012345678910
TIME (µs)
OUTPUT VOLTAGE (mV)
09646-028
Figure 35. Small Signal Transient Response, VSY = ±5 V, AV = 1,
RL = 2 kΩ, CL = 100 pF
120
140
100
80
60
40
20
01k100 10k 100k 1M 10M
FRE Q UE NCY ( Hz )
CMRR (dB)
09646-026
Figure 36. CMRR vs. Frequency, VSY = ±15 V
12
8
4
0
–4
–8
–120 1 2 3 4 5 6 7 8 9 10
TIME (µs)
OUTPUT VOLTAGE (V)
09646-030
Figure 37. Large Signal Transient Response, VSY = ±15 V, AV = 1,
RL = 2 kΩ, CL = 100 pF
75
50
25
0
–25
–50
–750 1 2 3 4 5 6 7 8 9 10
TIME (µs)
OUTPUT VOLTAGE (mV)
09646-031
Figure 38. Small Signal Transient Response, VSY = ±15 V, AV = 1,
RL = 2 kΩ, CL = 100 pF
ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet
Rev. H | Page 16 of 27
100
10
1110 100 1k 10k 100k
FRE Q UE NCY ( Hz )
VOLT AGE NOISE DENSIT Y (n V/ Hz)
09646-033
Figure 39. Voltage Noise Density vs. Frequency, VSY = ±5 V
50
40
30
20
0
10
0.01 0.1 1
LOAD CAPACI TANCE ( nF )
OVERSHOOT (%)
09646-034
OS–
OS+
Figure 40. Overshoot vs. Load Capacitance, VSY = ±5 V, AV = 1,
RL = 2 kΩ, VIN = 100 mV p-p
100
10
1110 100 1k 10k
FRE Q UE NCY ( Hz )
VOLT AGE NOISE DENSIT Y (n V/ Hz)
09646-036
Figure 41. Voltage Noise Density vs. Frequency, VSY = ±15 V
50
40
30
0
20
10
0.01 0.1 1
LOAD CAPACI TANCE ( nF )
OVERSHOOT (%)
09646-037
OS–
OS+
Figure 42. Overshoot vs. Load Capacitance, VSY = ±15 V, AV = 1,
RL = 2 kΩ, VIN = 100 mV p-p
Data Sheet ADA4610-1/ADA4610-2/ADA4610-4
Rev. H | Page 17 of 27
COMPARATIVE VOLTAGE AND VARIABLE VOLTAGE GRAPHS
09646-205
0.00001
0.0001
0.001
0.01
0.1
1
10
0.01 0.1 1
THD + N ( %)
AMPLITUDE ( V rms)
V
SY
= ±5V
R
L
= 2kΩ
f
IN
= 1kHz
80kHz F ILTER
Figure 43. THD + N vs. Amplitude, VSY = ±5 V
09646-204
0.00001
0.0001
0.001
0.01
0.1
1
10 100 1k 10k 100k
THD + N (%)
FREQUENCY (Hz)
80kHz BAND-P ASS FI LT E R
500kHz BAND-P AS S FI LT E R
VSY = ± 5V
VIN = 1.5V rms
Figure 44. THD + N vs. Frequency, VSY = ±5 V
–60
–80
–120
–140
–160
–100
–40
100 1k 10k 100k
FRE Q UE NCY ( Hz )
CHANNEL SE P ARATI ON (dB)
09646-039
Figure 45. Channel Separation vs. Frequency
0.10.010.001 110
AMPLITUDE ( V rms)
THD + N (%)
0.00001
0.0001
0.001
0.01
0.1
1
10
09646-040
VSY = ± 15V
RL = 2kΩ
fIN = 1kHz
80kHz F ILTER
Figure 46. THD + N vs. Amplitude, VSY = ±15 V
09646-141
0.00001
0.0001
0.001
0.01
0.1
1
10 100 1k 10k 100k
THD + N (%)
FREQUENCY (Hz)
V
SY
= ±15V
V
IN
= 5V rms
80kHz BAND-P ASS FI LT E R
500kHz BAND-P AS S FI LT E R
Figure 47. THD + N vs. Frequency, VSY = ±15 V
16
12
8
4
0
–4
–8
–12
–1600.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
TIME (ms)
VOLTAGE (V)
09646-042
OUTPUT
INPUT
Figure 48. No Phase Reversal, VSY = ±15 V, AV = +1, RL = 2 kΩ, CL = 100 pF
ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet
Rev. H | Page 18 of 27
400
300
200
100
0
–100
–200
–300
–4000 1 2 3 4 5 6 7 8 9 10
TIME (Seconds)
VOLTAGE (nV)
09646-043
Figure 49. Voltage Noise, 0.1 Hz to 10 Hz
12
10
8
6
4
2
000.2 0.4 0.6 0.8 1.0
0.1%
0.01%
1.2 1.4
SETTLING TIME (µs)
STEP SIZ E (V)
09646-044
Figure 50. Positive Step Settling Time
–4
–2
0
2
4
6
8
10
12
14
16
18
–0.5 00.5 1.0 1.5 2.0 2.5 3.0
V
OUT
(V)
V
IN
TIME (µs)
V
OUT
09646-200
V
OUT
= 7.3 × V
IN
Figure 51. Positive Overload Recovery
V
SY
(V)
09646-047
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
0 5 10 15 20 25 30 35
I
SY
PER AMP LIFI E R ( mA)
–40°C
+25°C
+85°C
+125°C
Figure 52. Supply Current (ISY) per Amplifier vs. Supply Voltage (VSY) at
Various Temperatures
12
10
8
6
4
2
000.2 0.4 0.6 0.8 1.0
0.1%
0.01%
1.2 1.4
SETTLING TIME (µs)
STEP SIZ E (V)
09646-045
Figure 53. Negative Step Settling Time
–0.5 00.5 1.0 1.5 2.0 2.5 3.0
V
OUT
(V)
V
IN
TIME (µs)
V
OUT
09646-201
–18
–16
–14
–12
–10
–8
–6
–4
–2
0
2
4
V
OUT
= 7.3 × V
IN
Figure 54. Negative Overload Recovery
Data Sheet ADA4610-1/ADA4610-2/ADA4610-4
Rev. H | Page 19 of 27
–3
–2
–1
0
1
2
3
–0.2 00.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
TIME (µs)
09646-203
VOLTAGE (V)
V
SY
= ±5V
V
IN
= ±2V
A
V
= +1
R
L
= 2kΩ
C
L
= 100pF
OUTPUT
INPUT
Figure 55. Positive and Negative Slew Rate (VSY = ±5 V, AV = 1, RL = 2 kΩ)
–15
–10
–5
0
5
10
15
–2.0 –1.5 –1.0 –0.5 00.5 1.0
VOLTAGE (V)
TIME (µs)
VIN
VOUT
09646-202
VSY = ± 15V
VIN = ±10V
AV = +1
RL = 2kΩ
CL = 100 pF
Figure 56. Positive and Negative Slew Rate (VSY = ±15 V, AV = 1, RL = 2 kΩ)
ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet
Rev. H | Page 20 of 27
THEORY OF OPERATION
The ADA4610-1/ADA4610-2/ADA4610-4 are manufactured
using the Analog Devices, Inc., iPolar® process, a 36 V dielectrically
isolated (DI) process with P-channel JFET technology. The
unique architecture of the ADA4610-1/ADA4610-2/ADA4610-4
makes it possible to combine high precision and high speed
characteristics into a high voltage, low power op amp. A simplified
schematic for the ADA4610-1/ADA4610-2/ADA4610-4 is
shown in Figure 57. The JFET input stage architecture offers
advantages of low input bias current, high bandwidth, high
gain, low noise, and no phase reversal when the applied input
signal exceeds the common-mode voltage range. The output
stage is rail-to-rail with high drive characteristics and low
dropout voltage for both sinking and sourcing currents.
The ADA4610-1/ADA4610-2/ADA4610-4 are unconditionally
stable for all gain configurations, even with capacitive loads well
in excess of 1 nF. The devices have internal protective circuitry
that allows voltages as high as 0.3 V beyond the supplies to be
applied at the input of either terminal without causing damage (for
higher input voltages, refer to the Input Overvoltage Protection
section).
The ADA4610-1/ADA4610-2 B grades achieve less than 0.4 mV
of offset and 4 µV/°C of offset drift; these characteristics are
usually associated with very high precision bipolar input amplifiers.
The gate current of a typical JFET doubles every 10°C, resulting
in a similar increase in input bias current over temperature. The
low power consumption characteristic of the ADA4610-1/
ADA4610-2/ADA4610-4 minimizes the die temperature, which
warrants low input bias currents even at elevated ambient tem-
peratures, making the amplifiers ideal for applications that require
low leakage specifications without active cooling. Ensure proper
printed circuit board (PCB) layout to minimize leakage currents
between PCB traces. Improper layout and board handling can
generate leakage currents exceeding the bias currents of the
operational amplifier.
The ADA4610-1/ADA4610-2/ADA4610-4 are fully specified with
supply voltages from ±5 V to ±15 V over the extended industrial
temperature range of −40°C to +125°C. The ADA4610-1 is
available in an 8-lead SOIC. The ADA4610-2 is available in an
8-lead MSOP, an 8-lead SOIC, and an 8-lead LFCSP. The
ADA4610-4 is available in a 14-lead SOIC and a 16-lead LFCSP.
All these packages are surface-mount type.
1++ –
D31
Q28
Q27
VOUT
09646-054
V–
Q15Q14
Q13 Q17Q16Q23
Q29Q30
J1 J2
Q9
Q5
Q4
Q8
Q1
Q6
Q7
Q25
Q24
Q18
Q12
I2I3I4
C2
C1
C3
DE1
VIN+
VIN–
C4
A2A1
R16
R7R6
R3
R5
R2
R10 R11
RC4
D26
R15
V+
DE5
DE6
DE3
DE2
DE4
Figure 57. Simplified Schematic
Data Sheet ADA4610-1/ADA4610-2/ADA4610-4
Rev. H | Page 21 of 27
APPLICATIONS INFORMATION
INPUT OVERVOLTAGE PROTECTION
The ADA4610-1/ADA4610-2/ADA4610-4 have internal protective
circuitry that allows voltages as high as 0.3 V beyond the supplies
to be applied at the input of either terminal without causing
damage. For higher input voltages, a series resistor is necessary
to limit the input current. Determine the resistor value by
mA10≤
−
S
S
IN
R
VV
where:
VIN is the input voltage.
VS is the voltage of either V+ or V−.
RS is the series resistor.
With a very low bias current of <1.5 nA up to 125°C, higher
resistor values can be used in series with the inputs. A 5 kΩ
resistor protects the inputs from voltages as high as 25 V
beyond the supplies and adds less than 10 µV to the offset.
PEAK DETECTOR
The function of a peak detector is to capture the peak value of a
signal and produce an output equal to it. By taking advantage of
the dc precision and super low input bias current of the JFET input
amplifiers, such as the ADA4610-1/ADA4610-2/ADA4610-4, a
highly accurate peak detector can be built, as shown in Figure 58.
V
CC
V
IN
+
–
ADA4610-1/
ADA4610-2
ADA4610-4 ADA4610-1/
ADA4610-2
ADA4610-4
V
EE
U2A
3
24
8
15
64
8
7
C4
50pF C3
1µF
R6
1kΩ
R7
10kΩ
D2
1N448
D3
1N4148
+PEAK
D4
1N4148 U2B
09646-149
Figure 58. Positive Peak Detector
In this application, Diode D3 and Diode D4 act as unidirectional
current switches that open up when the output is kept constant (in
hold mode). To detect a positive peak, U2A drives C3 through D3
and D4 until C3 is charged to a voltage equal to the input peak
value. Feedback from the output of the U2B + peak through R6
limits the output voltage of U2A. After detecting the peak, the
output of U2A swings low but is clamped by D2. Diode D3
reverses bias and the common node of D3, D4, and R7 is held to a
voltage equal to + peak by R7. The voltage across D4 is 0 V;
therefore, its leakage is small. The bias current of U2B is also small.
With almost no leakage, C3 has a long hold time.
The ADA4610-1/ADA4610-2/ADA4610-4, shown in Figure 58,
are ideal for building a peak detector because U2A requires dc
precision and high output current during fast peaks, and U2B
requires low input bias current (IB) to minimize capacitance
discharge between peaks. A low leakage and low dielectric
absorption capacitor, such as polystyrene or polypropylene, is
required for C3. Reversing the diode directions causes the
circuit to detect negative peaks.
CURRENT TO VOLTAGE (I TO V) CONVERSION
APPLICATIONS
Photodiode Circuits
Common applications for I to V conversion include photodiode
circuits where the amplifier converts a current emitted by a diode
placed at the negative input terminal into an output voltage.
The low input bias current, wide bandwidth, and low noise of
the ADA4610-1/ADA4610-2/ADA4610-4 make them excellent
choices for various photodiode applications, including fax
machines, fiber optic controls, motion sensors, and barcode
readers.
The circuit shown in Figure 59 uses a silicon diode with zero
bias voltage. This setup is a photovoltaic mode, which uses
many large photodiodes. This configuration limits the overall
noise and is suitable for instrumentation applications.
4
8
3
1
2
1/2
C
F
R
F
R
D
C
T
V
EE
V
CC
09646-154
ADA4610-1/
ADA4610-2
ADA4610-4
Figure 59. Equivalent Preamplifier Photodiode Circuit
A larger signal bandwidth can be attained at the expense of
additional output noise. The total input capacitance (CT) consists of
the sum of the diode capacitance (typically 30 pF to 40 pF) and
the amplifier input capacitance (<10 pF), which includes external
parasitic capacitance. CT creates a zero in the frequency response
that can lead to an unstable system. To ensure stability and
optimize the bandwidth of the signal, place a capacitor in the
feedback loop of the circuit shown in Figure 59. The capacitor
creates a pole and yields a bandwidth with a corner frequency of
1/(2π(RFCF))
where:
RF is the feedback resistor.
CF is the feedback capacitor.
ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet
Rev. H | Page 22 of 27
Determine the RF value by the following ratio:
V/ID
where:
V is the desired output voltage of the op amp.
ID is the diode current.
For example, if ID is 100 µA and a 10 V output voltage is needed,
RF must be 100 kΩ. The resistance of the photodiode (RD) is a
junction resistance (see Figure 59).
A typical value for RD is 1000 MΩ. Because RD >> RF, the circuit
behavior is not impacted by the effect of the junction resistance.
The maximum signal bandwidth (fMAX) is
T
F
MAX CR
ft
fπ
=
2
where ft is the unity-gain frequency of the op amp.
Calculate CF by
ftR
C
C
F
T
F
π
=
2
where ft is the unity-gain frequency of the op amp, and achieves a
phase margin, φM, of approximately 45°.
Increase the CF value to obtain a higher phase margin. Setting
CF to twice the previous value yields approximately φM = 65° and a
maximal flat frequency response, but it reduces the maximum
signal bandwidth by 50%.
Using the previous parameters with a CF ≈ 7 pF, the signal
bandwidth is approximately 250 kHz.
COMPARATOR OPERATION
Although op amps are quite different from comparators,
occasionally an unused section of a dual or a quad op amp can
be used as a comparator; however, this is not recommended for
rail-to-rail output op amps. For rail-to-rail output op amps, the
output stage is generally a ratioed current mirror with bipolar or
MOSFET transistors. With the device operating in open-loop
mode, the second stage increases the current drive to the ratioed
mirror to close the loop. However, the second stage cannot close
the loop, which results in an increase in supply current. With
the ADA4610-1/ADA4610-2/ADA4610-4 op amps configured
as comparators, the supply current can be significantly higher
(see Figure 60 for the supply current vs. the supply voltage for the
ADA4610-4). Configuring an unused section as a voltage follower
with the noninverting input connected to a voltage within the
input voltage range is recommended. The ADA4610-1/ADA4610-2/
ADA4610-4 have a unique output stage design that reduces the
excess supply current but does not entirely eliminate this effect
when the op amp is operating in open-loop mode.
09646-053
0
1
2
3
4
5
6
7
8
9
0 5 10 15 20 25 30 35 40
ISY FOR ALL CHANNEL S ( mA)
VSY (V)
COM P ARATOR, VOUT = HIGH
COM P ARATOR, VOUT = LOW
FOLLOWER
Figure 60. Supply Current (ISY) vs. Supply Voltage (VSY) for the ADA4610-4 Only
Data Sheet ADA4610-1/ADA4610-2/ADA4610-4
Rev. H | Page 23 of 27
LONG-TERM DRIFT
The stability of a precision signal path over its lifetime or
between calibration procedures is dependent on the long-term
stability of the analog components in the path, such as op amps,
references, and data converters. To help system designers
predict the long-term drift of circuits that use the ADA4610-1/
ADA4610-2/ADA4610-4, Analog Devices measured the offset
voltage of multiple units for 10,000 hours (more than 13 months)
using a high precision measurement system, including an
ultrastable oil bath. To replicate real-world system performance,
the devices under test (DUTs ) were soldered onto an FR4 PCB
using a standard reflow profile (as defined in the JEDEC J-STD-
020D standard), as opposed to testing them in sockets. This
manner of testing is important because expansion and
contraction of the PCB can apply stress to the integrated circuit
(IC) package and contribute to shifts in the offset voltage.
The ADA4610-1/ADA4610-2/ADA4610-4 have extremely low
long-term drift, as shown in Figure 61. The red, blue, and green
traces show sample units. Note that the ADA4610-1/
ADA4610-2/ADA4610-4 (B-grade) have a mean drift over
10,000 hours of approximately 5 µV, or less than 2% of their
maximum specified offset voltage of 400 µV at room
temperature.
TIME (Hours)
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10,000
CHANGE IN OFFSET VOLTAGE (µV)
–60
–40
–20
0
20
40
60
V
SY
= 10V
27 UNITS
T
A
= 25° C
MEAN
MEAN P L US ONE S TANDARD DEV IAT IO N
MEAN M INUS O NE S TANDARD DEV IAT IO N
SAMPLE 1
SAMPLE 2
SAMPLE 3
09646-061
Figure 61. Measured Long-Term Drift of the ADA4610-1/ADA4610-2/
ADA4610-4 Offset Voltage over 10,000 Hours
TEMPERATURE HYSTERESIS
In addition to stability over time as described in the Long-Term
Drift section, it is useful to know the temperature hysteresis,
that is, the stability vs. cycling of temperature. Hysteresis is an
important parameter because it tells the system designer how
closely the signal returns to its starting amplitude after the
ambient temperature changes and subsequent return to room
temperature. Figure 62 shows the change in input offset voltage
as the temperature cycles three times from room temperature to
125°C to −40°C and back to room temperature. The dotted line
is an initial preconditioning cycle to eliminate the original
temperature-induced offset shift from exposure to production
solder reflow temperatures. In the three full cycles, the offset
hysteresis is typically only 8 µ V, or 1% of its 800 µV maximum
offset voltage over the full operating temperature range. The
histogram in Figure 63 shows that the hysteresis is larger when
the device is cycled through only a half cycle, from room
temperature to 125°C and back to room temperature.
TEMPERATURE (°C)
–40 –20 020 40 60 80 100 120
CHANGE IN OFFSET VOLTAGE (µV)
–150
–100
–50
0
50
100
150 VSY = 10V PRECONDITION
CYCL E 1
CYCL E 2
CYCL E 3
09646-062
Figure 62. Change in Offset Voltage over Three Full Temperature Cycles
0
40
30
50
35
45
25
20
15
10
5
0
40
30
50
35
45
25
20
15
10
5
OFFSET VOLTAGE HYSTERESIS (µV)
NUMBER O F DEV ICES
09646-063
–80 –64 –48 –32 –16 016 32 48 64 80
HALF CYCLE
FULL CYCLE
V
SY
= 10V
27 UNITS × 3 CYCL ES
HALF CYCLE = + 26°C, + 1 25°C, +26°C
FULL CYCLE = +2 6° C, +125°C, +26°C, –40°C, + 26°C
Figure 63. Histogram Showing the Temperature Hysteresis of the Offset
Voltage over Three Full Cycles and over Three Half Cycles
ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet
Rev. H | Page 24 of 27
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 64. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
COM P LIANT T O JEDE C S TANDARDS M O-187- AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 M AX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° M AX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 65. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Data Sheet ADA4610-1/ADA4610-2/ADA4610-4
Rev. H | Page 25 of 27
COMPLIANT TO JEDEC STANDARDS MO-178-AA
10°
5°
0°
SEATING
PLANE
1.90
BSC
0.95 BSC
0.60
BSC
5
1 2 3
4
3.00
2.90
2.80
3.00
2.80
2.60
1.70
1.60
1.50
1.30
1.15
0.90
0.15 MAX
0.05 MIN
1.45 MAX
0.95 MIN
0.20 MAX
0.08 MIN
0.50 MAX
0.35 MIN
0.55
0.45
0.35
11-01-2010-A
Figure 66. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
2.44
2.34
2.24
0.30
0.25
0.20
PIN 1 INDEX
AREA
0.80
0.75
0.70
1.70
1.60
1.50
0.203 REF
0.05 M AX
0.02 NO M
0.50 BSC
3.10
3.00 SQ
2.90
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS M O-229- W3030D-4
0.20 M IN
8
1
5
4
PKG-005136
02-10-2017-C
SEATING
PLANE
TOP VIEW
SIDE VIEW
EXPOSED
PAD
BOTTOM VIEW
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET
PIN 1
INDIC ATOR AREA O P TI ONS
(SEE DETAIL A)
1
DETAIL A
(JEDEC 95)
Figure 67. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-11)
Dimensions shown in millimeters
ADA4610-1/ADA4610-2/ADA4610-4 Data Sheet
Rev. H | Page 26 of 27
CONTROLLING DIMENSIONSARE IN MIL LI M E TERS ; INCH DIM E NS IO NS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFE RE NCE ON LY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JE DE C S TANDARDS MS-012-AB
060606-A
14 8
7
1
6.20 ( 0. 2441)
5.80 ( 0. 2283)
4.00 ( 0. 1575)
3.80 ( 0. 1496)
8.75 ( 0. 3445)
8.55 ( 0. 3366)
1.27 ( 0. 0500)
BSC
SEATING
PLANE
0.25 ( 0. 0098)
0.10 ( 0. 0039)
0.51 ( 0. 0201)
0.31 ( 0. 0122)
1.75 ( 0. 0689)
1.35 ( 0. 0531)
0.50 ( 0. 0197)
0.25 ( 0. 0098)
1.27 ( 0. 0500)
0.40 ( 0. 0157)
0.25 ( 0. 0098)
0.17 ( 0. 0067)
COPLANARITY
0.10
8°
0°
45°
Figure 68. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
4.10
4.00 SQ
3.90
0.35
0.30
0.25
2.25
2.10 SQ
1.95
1
0.65
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12
13
4
0.70
0.60
0.50
SEATING
PLANE
0.05 M AX
0.02 NO M
0.203 REF
0.25 M IN
COPLANARITY
0.08
PIN 1
INDICATOR
0.80
0.75
0.70
COMPLIANT
TO
JEDEC STANDARDS M O-220- WG GC.
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
04-15-2016-A
PKG-004025/5112
PIN 1
INDIC ATOR AREA O P TI ONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
EXPOSED
PAD
Figure 69. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-23)
Dimensions shown in millimeters
Data Sheet ADA4610-1/ADA4610-2/ADA4610-4
Rev. H | Page 27 of 27
ORDERING GUIDE
Model
1
Temperature Range
Package Description
Package Option
Branding
ADA4610-1ARZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4610-1ARZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4610-1ARZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4610-1BRZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4610-1BRZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4610-1BRZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4610-1ARJZ-R2 −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A37
ADA4610-1ARJZ-R7 −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A37
ADA4610-1ARJZ-RL −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A37
ADA4610-2ACPZ-R7
−40°C to +125°C
8-Lead Lead Frame Chip Scale Package [LFCSP]
CP-8-11
A2U
ADA4610-2ACPZ-RL −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-11 A2U
ADA4610-2ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2U
ADA4610-2ARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2U
ADA4610-2ARMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2U
ADA4610-2ARZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4610-2ARZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4610-2ARZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4610-2BRZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4610-2BRZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4610-2BRZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4610-4ARZ −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
ADA4610-4ARZ-R7 −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
ADA4610-4ARZ-RL −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
ADA4610-4ACPZ-R7
−40°C to +125°C
16-Lead Lead Frame Chip Scale Package [LFCSP]
CP-16-23
ADA4610-4ACPZ-RL −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-23
1 Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
D09646-0-5/17(H)