intel. MCS 51 8-BIT CONTROL-ORIENTED MICROCONTROLLERS Commercial/Express 8031AH/8051AH/8051AHP 8032AH/8052AH 8751H/8751H-8 8751BH/8752BH High Performance HMOS Process a Boolean Processor Internal Timers/Event Counters m Bit-Addressable RAM 2-Level Interrupt Priority Structure gw Programmable Full Duplex Serial 32 I/O Lines (Four 8-Bit Ports) Channel 64K External Program Memory Space @ 111 Instructions (64 Single-Cycie) Security Feature Protects EPROM Parts 64K External Data Memory Space Against Software Piracy m Extended Temperature Range (40C to + 85C) The MCS 51 controllers are optimizd for control applications. Byte-processing and numerical operations on small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The instruction set provides a convenient nenu of 8-bit arithmetic instructions, including multiply and divide instruc- tions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit manipulation and testing in control and logic systems that require Boolean processing. The 8751H is an EPROM version of the 8051AH. It has 4 Kbytes of electrically programmable ROM which can be erased with ultraviolet light. It is fully compatible with the 8051AH but incorporates one additional feature: a Program Memory Security bit that can be used to protect the EPROM against unauthorized readout. The 8751H-8 is identical to the 8751H but only operates up to 8 MHz. The 8051AHP is identical to the 80!,1AH with the exception of the Protection Feature. To incorporate this Protection Feature, program verificaton has been disabled and external memory accesses have been limited to 4K. The 8052AH is an enhanced versio. of the 8051AH. It is backwards compatible with the 8051AH and is fabricated with HMOS II technology. 1 he 8052AH erihancements are listed in the table below. Also refer to this table for the ROM, ROMiess and EPOM versions of each product October 1994 Order Number: 272318-002 . Inte: nal Memory Timers/ Device [on Bent Counters Interrupts Program Data _ 8031AH none } 128x8RAM 2x 16-Bit 5 8051AH 4K x 8 ROM | 128x8RAM 2x 16-Bit 5 8051 AHP 4K x 8 ROM | 128 8 RAM 2x 16-Bit 5 8751H 4Kx8EPROM = 128x8RAM 2x 16-Bit 5 8751H-8 4KxB EPROM | 128xBRAM 2x 16-Bit 5 8751BH 4KxBEPROM i 128x8RAM 2x 16-Bit 5 8032AH none | 256x8RAM 3x 16-Bit 6 8052AH 8K x 8 ROM 256 x 8 RAM 3x 16-Bit 6 8752BH 8K x 8 EPROM 256 x 8 RAM 3x 16-Bit 6 2-21MCS 51 CONTROLLER Po 0-907 P2.0-P27 tee ror ror | ORIVERS DAIVERS | Ves iy ! ra | 33 | 23 nau EPROM 33 PORT 2 | LATCH Rom | \ | | ! | | 2 | Sa PROGRAM | ACK ADDR. POINTER AEGISTEA | | | - | . , BUFFER | | necisrer | | | PCON [SCON|TMOD] TCON | Tacon: | THo | TLo | THI ne | , , - INCREMENTER | Tur | TH2* | TL2* | RCAP2H | IRCAP2L-| seuF| te 1p INTERRUPT, SERIAL PROGRAM | | PORT AND TIMER BLOCKS COUNTER | maar <4 ae | HY rams ae wanes | E DPTA | ma comrnor [Fg | rst + 2 ! [ j | | | | | osc | | } Cl] bes ) xTaut Cc TAL 2 1 Pr O-Pi? P10-P37 272318-1 Figure 1. MCS 51 Controller Block Diagram PROCESS INFORMATION The 8031AH/8051AH and 8032AH/8052AH devic- es are manufactured on P414.1, an 4MOS Il pro- cess. The 8751H/8751H-8 devices are manufac- tured on P421.X, an HMOS-E process The 8751BH and 8752BH devices are manufactured on P422. Additional process and reliability information is avaii- able in Intels Components Quality and Feliability Handbook, Order No. 210997. 2-22a intel MCS 51 CONTROLLER PACKAGES a ~ 7 Part Prefix Package Type Oja ec 8051AH P 40-Pin Plastic DIP 45C/W 16C/W 8031AH D 40-Pin CERDIP 45C/W 15C/W 8052AH N 44-Pin PLCC 46C/W 16C/W 8032AH 8752BH* 8751H D 40-Pin CERDIP 45C/W 15C/W 8751H-8 8051AHP P 40-Pin Plastic DIP 45C/W 16C/W D 40-Pin CERDIP 45C/W 15C/W 8751BH P 40-Pin Plastic DIP 36C/W 12C/W N 44-Pin PLCC 47C/W 16C/w NOTE: 2 *8752BH is 36/10 for D, and 38/22 for N. All thermal impedance data is apprcximate for static air conditions at 1W of power dissipation. Values will change depending on operating cond:tions and application. See the Intel Packaging Handbook (Order Number 240800) for a description of Intels thermal impedance test methodology. 8052/8032 ONLY y y ose \e ~_~ moe tz Prod 7 4071 Veg a ok 8988 T2EX PTI CI2 39/3 P0.0 ADO INDEX ce efe<ee P1243 38) Po. ADI CORNER e22228 8esg3 praca 3701 Po.2 AD2 aiaaeESEREE p14 ds 36-1 P0.3 ADa Sh ostth trp gp Be P1516 35 [7] Po.4 AD4 PIs [> Ci] P0.4 (ADA) P1617 3410) PO.5 ADS PLE Te. 134] PO.5 (ADS) P17 Cle 33 [73 PO.6 ADE Pu7 pe OF] Poe (AD6) RST C9 32[) Po.?7 AD? RST fis 36] PO.7 (AD7) RXD P3.0 C] 10 310) EA Vpp* (RXD) P3.0 [5 134] EA/Vpp* - cas PP Txo P31 C14 BX5X 2 "2 ALE/PROG' Reeserved** |i 37| Reserved** NTO P3.2 Cy 12 29) BSEN (TxD) P3.1 |i 33 ] ALE/PROG* NTT P33 C113 26 [01 92.7 A15S (NTO) P3.2 [33 37] BEEN 4 on ~ i To P34 Ci} 14 a7 2.6A14 {INT) P3.3 [5 [31] P2.7 (a15) T1Pa.s Chis 260) 2.5 a3 (ro) p3.4 {5 oa] poe cata WR P36 C16 25173 P24 At2 12) pas ti, 24] P28 (A14) AD P37 C117 2a) P23 an (TAPS TS ney cuca en ey en ne egeted PERSIANS) XTAL2 Cl 18 23f. 1 P2.2 a10 Veg RL IR, IRI IRE IR, ae) vet IAL ogy xTaL1 CJ 19 22[1 p21 a9 Sryy gr enuxrae ai Vss C] 20 2107 P20 48 gk<e> sigag Po eo x easora = fig & < 272318-2 DIP PLCC *EPROM only **Do not connect reserved pins. Figure 2. MCS 51 Controller Connections | 2-23MCS 51 CONTROLLER PIN DESCRIPTIONS Vcc: Supply voitage. Vsg: Circuit ground. Port 0: Port 0 is an 8-bit open drain bidirectional 1/0 port. As an output port each pin can sink 8 LS TTL inputs. Port 0 pins that have 1s written to the n float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application it uses strong inter- nal pullups when emitting 1s and can source and sink 8 LS TTL inputs. Port 0 also receives the code bytes during program- ming of the EPROM parts, and outputs the code bytes during program verification of the ROM and EPROM parts. External pullups are required during program verification. Port 1: Port 1 is an 8-bit bidirectional |/O port with internal pullups. The Port 1 output buffers can sink/ source 4 LS TTL inputs. Port t pins that have 1's written to them are pulled high by the internal pull- ups, and in that state can be used is inputs. As inputs, Port 1 pins that are externally pulled low will source current (lj, on the data sheet) b3cause of ihe internal pullups Port 1 also receives the low-order address bytes during programming of the EPROM parts and during program verification of the ROM and EPROM parts. In the 8032AH, 8052AH and 8752BK Port 1 pins P1.0 and P1.1 also serve the T2 an. T2EX func- tions, respectively. os intel Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullups when emitting 1s. Dur- ing accesses to external Data Memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits dur- ing programming of the EPROM parts and during program verification of the ROM and EPROM parts. The protection feature of the 8051AHP causes bits P2.4 through P2.7 ta be forced to 0, effectively limit- ing external Data and Code space to 4K each during external accesses. Port 3: Port 3 is an 8-bit bidirectional |/O port with internal pullups. The Port 3 output buffers can sink/ source 4 LS TTL inputs. Port 3 pins that have 1's written to them are pulled high by the internal pull- ups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current (||, on the data sheet) because of the pullups. Port 3 also serves the functions of various specia! features of the MCS 51 Family, as listed below: Port Pin ; P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 | INTO (external interrupt 0) P3.3 | INT (external interrupt 1) P3.4 TO (Timer 0 external input) P3.5 T1 (Timer 1 external input) P3.6 | WR (externa! data memory write strobe} | P3.7 it RD (external data memory read strobe) Alternative Function Port Alternative Function Pin P1.0 T2 (Timer/Counter 2 Externai nput) P1.4 T2EX (Timer/Counter 2 Capture/Reload Trigge j Port 2: Port 2 is an 8-bit bidirectional O port with internal pullups. The Port 2 output buffers can sink/ source 4 LS TTL inputs. Port 2 pins tiat have 1's written to them are pulled high by the internal pull- ups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally p illed tow will source current (I1_ on the data sheet) because of the internal pullups. 2-24 RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the de- vice. ALE/PROG: Address Latch Enable output pulse for latching the low byte of the address during accesses to external rnemory. This pin is also the program pulse input (PROG) during programming of the EPROM parts In normal operation ALE is emitted at a constant rate of the oscillator frequency, and may be used for external timing or clocking purposes. Note, how- ever, that one ALE pulse is skipped during each ac- cess to external Data Memory.intel. PSEN: Program Store Enable is the read strobe to external Program Memory. When the device is executing code from external Program Memory, PSEN is activated twice each ma- chine cycle, except that two PSEN activations are skipped during each access to external Data Memo- ry. EA/Vpp: External Access enable EA must be strapped to Vsg in order to enable any MCS 51 de- vice to fetch code from external Program memory locations starting at OOOOH up to FFFFH. EA must be strapped to Vcc for internal program execution. Note, however, that if the Security Bit in the EPROM devices is programmed, the device will not fetch code from any location in external Program Memory. This pin also receives the programming supply volt- age (VPP) during programming of the EPROM parts. C2 pT xa CI | 4 I I... ci a SS a 272318-3 C1, C2 = 30 pF +10 pF for Crystals For Ceramic Resonators contact resonator manufacturer. Figure 3. Oscillator Connections XTAL1: Input to the inverting oscillator amplifier. XTAL2: Output from the inverting oscillator amplifi- er. OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respec- tively, of an inverting amplifier which can be config- ured for use as an on-chip oscillator, as shown in Figure 3. Either a quartz crystal or ceramic resonator may be used. More detailed information concerning the use of the on-chip oscillator is available in Appli- cation Note AP-155, Oscillators for Microcontrol- fers, Order No. 230659. MCS 51 CONTROLLER To drive the device from an external clock source, XTAL1 should be grounded, while XTAL2 is driven, as shown in Figure 4. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. EXTERNAL OSCILLATOR XTAL2 SIGNAL. XTALI vss 272318-4 Figure 4. External Drive Configuration EXPRESS Version The Intel EXPRESS system offers enhancements to the operational specifications of the MCS 51 family of microcontroliers. These EXPRESS products are designed to meet the needs of those applications whose operating requirements exceed commercial standards. The EXPRESS program includes the commercial standard temperature range with burn-in, and an ex- tended temperature range with or without burn-in. With the commercial standard temperature range, operational characteristics are guaranteed over the temperature range of 0C to + 70C. With the ex- tended temperature range option, operational char- acteristics are guaranteed over a range of 40C to + 85C. The optional burn-in is dynamic, for a minimum time of 160 hours at 125C with Vcc = 5.5V +0.25V, following guidelines in MIL-STD-883, Method 1015. Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The prefixes are listed in Table 1. For the extended temperature range option, this data sheet specifies the parameters which deviate from their commercial temperature range limits. 2-25MCS 51 CONTROLLER intel Table 1. EXPRESS Prefix Identification Prefix Package Type Temperature Range Burn-in P Plastic Commercial No D Cerdip Commercial No N PLCC Commercial No TD Cerdip Extended No TP Plastic Extended No TN PLCC Extended No LD Cerdip Extended Yes LP Plastic Extended Yes NOTE: Contact distributor or local sales office to match EXPRESS prefix with proper device. * The 8051AHP cannot access external Program DESIGN CONSIDERATIONS If an 8751BH or 8752BH is replacing an 8751H in a future design, the user should carefully com- pare both data sheets for DC or AC Characteris- tic differences. Note that the Vj} and ||, specifi- cations for the EA pin differ significantly between the devices. e Exposure to light when the EPROM device is in operation may cause logic errors. For this reason, it is suggested that an opaque label be placed over the window when the die is exposed to am- bient light. 2-26 or Data memory above 4K. This means that the following instructions that use the Data Pointer only read/write data at address locations below OFFFH: MOVX A,@DPTR MOVX @DPTIR, A When the Data Pointer contains an address above the 4K limit, those locations will not be ac: cessed. To access Data Memory above 4K, the MOVX @Ri,A or MOVX A,@Ri instructions must be used.intel. ABSOLUTE MAXIMUM RATINGS* Ambient Temperature Under Bias . 40C to + 85C Storage Temperature .......... 65C to + 150C Voltage on EA/Vpp Pin to Vsg B751H.. 0. ee eee 0.5V to +21.5V 8751BH/8752BH ........... ~O.5V to +13.0V Voltage on Any Other Pin to Vsg ....- 0.5Vto +7V Power Dissipation.............0022. 0.0 eee 1.5W OPERATING CONDITIONS MCS 51 CONTROLLER NOTICE: This is a production data sheet. It is valid for the devices indicated in the revision history. The specifications are subject to change without notice. *WAARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and ex- tended exposure beyond the Operating Conditions may affect device reliability. Symbol Description Min Max Units Ta Ambient Temperature Under Bias Commercial 0 +70 C Express _. - 40 +85 C Voc Supply Voltage 45 5.5 Vv Fosc Oscillator Frequency 3.5 12 MHz DC CHARACTERISTICS (Over Operating Conditions) All parameter values apply to all devices unless otherwise indicated Symbol Parameter Min Max Units | Test Conditions Vit Input Low Voltage (Except &A Pin of 0.5 0.8 Vv 8751H and 875tH-8) Vins Input Low Voltage to EA Pin of 0 0.7 V 8751H and 8751H-8 _ Vin Input High Voltage (Except XTAL2, RST) 2.0 |} Voc + 0.5 Vv Vint Input High Voltage to XTAL2, RST 2.5 | Veco + 0.5 v XTAL1 = Vss Vino Input High Voltage to EA pin 4.5 5.5V of 8751BH and 8752BH VoL Output Low Voltage (Ports t, 2, 3)" 0.45 Vv lo. = 1.6mA Vout Output Low Voltage (Port C. ALE, PSEN)* 8751H, 8751H-8 0.60 Vv lo. = 3.2 mA 0.45 V lo, = 2.4mA All Others 0.45 Vv lol = 3.2mMA VoH Output High Voltage (Ports 1, 2. 3, ALE, PSEN) 2.4 _ Vv lon = 80 pA VoH1 Output High Voltage (Port }) in 2.4 Vv lon = ~400 pA External Bus Mode) _ Ne Logical 0 Input Current (Ports 1. 2, 3, and RST) ~ 500 pA | Vin = 0.45V hea Logical 0 Input Current (EA) 8751H and 8751H-8 -15 mA } Vin = 0.45V 8751BH ~10 mA | Vin = Vss 8752BH -10 mA | Vin = Vss __ _ 0.5 mA 2-27MCS 51 CONTROLLER intel e DC CHARACTERISTICS (Over Operating Conditions) All parameter values apply to all devices unless otherwise indicated (Continued) Symbol Parameter Min | Max | Units; Test Conditions Ine Logical 0 Input Current (XTAL2) ~3.2 | mA | Vin = 0.45V lu Input Leakage Current (Port 0) 8751H and 8751H-8 100 | pA | 0.45 < Vin s Voc All Others +10 pA | 0.45 < Vin < Voc [tia Logical 1 Input Current (FA) 8751H and 8751H-8 500 pA | Vin = 2.4V 8751BH/8752BH _ 1 mA | 4.5V < Vin < 5.5V lie Input Current to RST to Activate Reset 500 vA | Vin < (Voc 1.5V) loc Power Supply Current: 8031 AH/8051AH/805 1 AHP 125 mA | All Outputs 8032AH/8052AH/875 1 BH/8752BH 175 mA | Disconnected; 8751H/8751H-8 _ 250 mA | EA = Voc Cio Pin Capacitance __ 10 pF | Test freq = 1 MHz NOTES: 1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vos of ALE/PROG and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE/PROG pin may exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 2. ALE/PAOG refers to a pin on the 87513H. ALE refers to a timing signal that is output on the ALE/PROG pin. 3. Under steady state (non-transient) conditions, lo, must be externally limited as follows: Maximum Io, per port pin: 1OmMA Maximum Io, per 8-bit part - Pori a: 26mA Ports 1, 2, and 3: 15 mA Maximum total lo, for all output pins: 7imA If lo, exceeds the test condition, Vo, may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2-28 |intel MCS 51 CONTROLLER EXPLANATION OF THE AC SYMBOLS Be vet LOW, or ALE EN Each timing symbol has 5 characters. The first char- Q: Output data acter is always a T (stands for time). The other R: RD signal characters, depending on their positions, stand for T: Time the name of a signal or the logical status of that V: Valid signal. The following is a list of all the characters and W: WR signal what they stand for. X: No longer a valid logic level Z: Float A: Address C: Clock For example, D: Input Data ; H: Logic level HIGH TAVLL = Time from Address Valid to ALE Low. |: Instruction (program memory contents) TLLPL = Time from ALE Low to PSEN Low. AC CHARACTERISTICS (Under Operating Conditions; Load Capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF) EXTERNAL PROGRAM MEMORY CHARACTERISTICS Symbol Parameter 12 MHz Oscillator Variable Oscillator Units Min Max Min Max 1/TCLCL | Oscillator Frequency a 3.5 12.0 MHz TLHLL ALE Pulse Width 127 2TCLCL- 40 ns TAVLL Address Valid to ALE Low _t 43 TCLCL 40 ns TLLAX Address Hold after ALE Low | 48 TCLCL - 35 ns TLLIV ALE Low to Valid Instr In 8751H 183 4TCLCL - 150 ns Ail Others _ 233 4TCLCL 100 ns TLLPL ALE Low to PSEN Low _ 58 TCLCL 25 ns TPLPH PSEN Pulse Width 8751H 190 3TCLCL-60 ns Ail Others _. 215 3TCLCL-35 ns TPLIV PSEN Low to Valid Instr Ir 8751H 100 3TCLCL 150 ns All Others | 125 3TCLCL125 | ns TPXIX Input Instr Hold after PSEN 0 0 ns TPXIZ Input Instr Float after PSEN 63 TCLCL20 ns TPXAV PSEN to Address Valid _. 75 TCLCL --8 ns TAVIV Address to Valid Insir In 8751H 267 STCLCL ~ 150 ns All Others __ 302 5TCLCL115 ns TPLAZ __| PSEN Low to Address Ficat | 20 20 ns TRLRH RD Pulse Width 400 6TCLCL- 100 ns TWLWH_ | WR Pulse Width __ 400 ! 6TCLCL- 100 ns TRLDV RD Low to Valid Data in 252 5TCLCL 165 ns TRHDX Data Hold after RD 0 0 ns TRHDZ Data Float after RD 97 2TCLCL 70 ns TLLDV | ALE Lowto Valid Data In 517 BTCLCL-150 | ns TAVDV Address to Valid Data In | 585 Q9TCLCL 165 ns | 2.29MCS 51 CONTROLLER in EXTERNAL PROGRAM MEMORY CHARACTERISTICS (Continued) tel. Symbol Parameter 12 MHz Oscillator Variable Oscillator Units Min Max Min Max TLLWL | ALE Low to RD or WR Low 200 300 3TCLCL-50 | 3TCLCL+50 ns TAVWL | Address to RD or WR Low 203 4TCLCL- 130 ns TAVWX | Data Valid to WR Transition 8751H 13 TCLCL70 ns All Others 23 TCLCL 60 ns TQVWH | Data Valid to WR High 433 7TCLCL 150 ns TWHQX | Data Hold after WR 33 TCLCL50 ns TRLAZ | RD Low to Address Float 20 20 ns TWHLH | RD or WR High to ALE High 8751H 33 133 TCLCL-- 50 TCLCL+ 50 ns All Others 43 123 TCLCL 40 TCLCL+ 40 ns NOTE: *The 8751H-8 is identical to the 8751H but only operates up to 8 MHz. When calculating the AC Characteristics for the 8751H-8, use the 8751H formula for variable oscillators. 2-30intel MCS 51 CONTROLLER EXTERNAL PROGRAM MEMORY READ CYCLE TLHLL ALE TLEPL TAVLL TPLPH TLLIV PSEN TPLIV TPXAY TPLAZ TPXIZ TPXIX PORT 0 INSTR IN PORT 2 272318-5 EXTERNAL DATA MEMORY READ CYCLE ALE PSEN TLLOV TLLWL TRHDZ TLLAX TRHDX PORT 0 AO-A7 FROM Ri OR DPL DATA IN AO-A7 FROM PCL INSTR. 1N TAVWL TAVOV PORT 2 P2.C0-P2.7 OR A8-A15 FROM DPH AB-A1S FROM PCH 272318-6 EXTERNAL DATA MEMORY WRITE CYCLE ALE PSEN TWHOX TQVWH PORT 0 DATA OUT AO~A7 FROM PCL INSTR. IN TAVWL - PORT 2 P2.3-P2.7 OR A8-A15 FROM DPH A8B-A15 FROM PCH 272318-7 | 2-31a MCS 51 CONTROLLER intel e SERIAL PORT TIMINGSHIFT REGISTER MODE Test Conditions: Over Operating Conditions; Load Capacitance = 80 pF Symbol Parameter 12 MHz Oscillator Variable Oscillator Units Min Max Min Max TXLXL | Seriai Port Clock Cycle Time 1.0 12TCLCL ps TQVXH | Output Data Setup to Clock Fising 700 1OTCLCL -- 133 ns Edge TXHQX | Output Data Hold after Clock 50 2TCLCL- 117 ns Rising Edge TXHDX | input Data Hold after Clock Rising 0 0 ns Edge TXHDV | Clock Rising Edge to Input Data 700 10TCLCL133] ns Valid SHIFT REGISTER MODE TIMING WAVEFORMS INSTRUCTION | 9 [| ft | & | 38 | 4 | 5S Gf 6 JFoF | 8B 4 ae TLILI i fl MIS L_I__IL_iL_iu_SJLLL_LL__JL_S_] proTXLxLy cLack LJ TLS UP USD LS WS LS peeved Pr TXHCX | OUTPUT DATA Xo 1K UiK 2 KS CK KS CK OK OF aed ie TX WRITE TO SBUF .| TXHDV = tr "Ox set Tl (NPUT DATA CD ED ID GD CI GD CE DP CD GD CD ED CD ED ID CLEAR at SET RI 272318-8 2-32 iintel MCS 51 CONTROLLER EXTERNAL CLOCK DRIVE Symbol Parameter Min Max Units 1/TCLCL Oscillator Frequency (except 8751 H-8) 3.5 12 MHz 8751H-8 3.5 8 MHz TCHCX High Time 20 ns TCLCOX Low Time 20 ns TCLCH Rise Time 20 ns TCHCL Fall Time 20 ns EXTERNAL CLOCK DRIVE WAVEFORM p TCHCX TCLCH e FCHCL ja TCLCX t TCLCL 272318-9 AC TESTING INPUT, OUTPUT WAVEFORM 0.45 / a wef : \ 272318-10 AC Testing: Inputs are driven at 2.4V for a Logic 1 and 0.45V tor a Logic 0". Timing measurements are made at 2.0V for a Logic 1 and 0.8V for a Logic 0. | 2-33MCS 51 CONTROLLER EPROM CHARACTERISTICS Table 3. EPROM Programming Modes Mode RST PSEN ALE EA P2.7 P2.6 P2.5 P2.4 Program 1 0 o* VPP 1 0 X xX Verity 1 0 1 1 0) 0 X X Security Set 1 0 o* VPP 1 1 X x NOTE: 1 = logic high for that pin VPP" = +21V +0.5V 0 = logic low for that pin *ALE is pulsed low for 50 ms. X" = dont care PROGRAMMING THE 8751H Note that the EA/VPP pin must not be allowed to go To be programmed, the part must be -unning with a 4 to 6 MHz oscillator. (The reason the oscillator needs to be running is that the internal bus is being used to transfer address and program data to appro- priate internal registers.) The address of an EPROM location to be programmed is applied to Port 1 and pins P2.0-P2.3 of Port 2, while the cede byte to be programmed into that location is applied to Port 0. The other Port 2 pins, and RST, PSEN, and EA/Vpp should be held at the Program leveis indicated in Table 3. ALE/PROG is pulsed low for 50 ms to pro- gram the code byte into the addressed EPROM lo- cation. The setup is shown in Figure 5 Normally EA/Vpp is held at a logic high until just before ALE/PROG is to be pulsed. Then EA/Vpp is raised to +21V, ALE/PROG is pulsed, and then EA/Vpp is returned to a logic high. Waveforms and detailed timing specifications are shown in later sec- tions of this data sheet. +5V vee J Po Krom DATA P2.0- P23 87S1H Xm] 72.4 X ed p25 ALE o aLePROG 50 ma PULSE TO GND X = DON'T CARE VIL ~} p26 Vint ol P27 XTAL2 EA p caver XTALI RST bo UT pe_=h 4-6MHz s T#l A 272318-11 Figure 5. Programming Configuration 2-34 above the maximum specified VPP level of 21.5V for any amount of time. Even a narrow glitch above that voltage level can cause permanent damage to the device. The VPP source should be well regulated and free of glitches. Program Verification If the Security Bit has not been programmed, the on- chip Program Memory can be read out for verifica- tion purposes, if desired, either during or after the programming operation. The address of the Program Memory location to be read is applied to Port 1 and pins P2.0-P2.3. The other pins should be held at the Verify leveis indicated in Table 3. The contents of the addressed location will come out on Port 0. Ex- ternal pullups are required on Port 0 for this opera- tion. The setup, which is shown in Figure 6, is the same as for programming the EPROM except that pin P2.7 is held at a logic low, or may be used as an active- low read strobe. Sv vec J aopR a0-a7 Pd Ln pom Po ATA OOOOH -OFFEH aa P20- L/ (use 10K MB-AM! A p23 PULLUPS) Xl p24 8751H X= OONT CARE X wT P25 ALE Vi od P26 T+ vIH ENABLE wy P27 EA aa XTAL2 4-6mHs CD x] RST [oe viet T xTALI f vss PSEN r] 272318-12 Figure 6. Program Verificationintel. EPROM Security The security feature consists of a locking bit which when programmed denies electrical access by any external means to the on-chip Program Memory. The bit is programmed as shown in Figure 7. The setup and procedure are the same as for normal EPROM programming, except that P2.6 is held at a logic high. Port 0, Port 1 and pins P2.0-P2.3 may be in any state. The other pins should be held at the Security levels indicated in Table 3. Once the Security Bit has been programmed, it can be cleared only by full erasure of the Program Mem- ory. While it is programmed, the internal Program Memory can not be read out, the device can not be further programmed, and it can not execute out of external program memory. Erasing the EPROM, thus clearing the Security Bit, restores the devices full functionality. It can then be reprogrammed. Erasure Characteristics Erasure of the EPROM begins to occur when the device is exposed to light with wavelengths shorter than approximately 4,000 Angstroms. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an ex- tended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause inadver- tent erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window. MCS 51 CONTROLLER +5V X = DON'T CARE vec J yr 7 PO x P2.0- P23 P25 50 ms PULSE TO GND P26 x > 6751H _ i P24 ALE [-* ALE/PROG _} mo P27 Ea -* EAvppP XTAL2 > RST P* VIH1 > oh XTALI t vss PSEN ry 272318~13 Figure 7. Programming the Securlty Bit The recommended erasure procedure is exposure to ultraviolet light (at 2537 Angstroms) to an integrat- ed dose of at least 15 W-sec/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000 ~W/cm2 rating for 20 to 30 minutes, at a distance of about 1 inch, should be sufficient. Erasure leaves the array in an all 1s state. EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS Ta = 21C to 27C; VCC = 5V +10%; VSS = OV Symbol Parameter Min Max Units VPP Programming Supply Voltage 20.5 21.5 Vv IPP Programming Supply Current __ 30 mA 1/TCLOL Oscillator Frequency 4 6 MHz TAVGL Address Setup to PROG Low 48TCLCL TGHAX Address Hold atter PROG 48TCLCL TDVGL Data Setup to PROG Low 48TCLC. TGHDX Data Hold after PROG 48TCLCL TEHSH P2.7 (ENABLE) High to VPP 48TCLCt. TSHGL VPP Setup to PROG Low 10. us TGHSL VPP Hold after PROG 10 us TGLGH PROG Width 45 55 ms TAVQV Address to Data Valid ~ | 48TCLCL TELQV ENABLE Low to Data Valid _ 48TCLCL TEHQZ Data Float after ENABLE oO 48TCLCL 2-35MCS 51 CONTROLLER EPROM PROGRAMMING AND VERIFICATION WAVEFORMS PROGRAMMING VERIFICATION P1.0-P1. pa0P23 ADDRESS )- ADORESS - TAVQV PORT 0 DATA IN , DATA OUT }____ TDVGL TGHDX TAVGL | TGHAX ALE/ PROG 7 TSHG! TGHSL t TGLGH 21V 2 SV HIGH / \ zi/ver TT TTL HIGH TTL HIGH TTL HIGH TEHSH TELQV TEHOZ P27 ______ (ENABLE) 272318-14 For programming conditions 369 Figure 5. For verification conditions see Figure 6. 2-36intel. Programming the 8751BH/8752BH To be programmed, the 875XBH must be running with a 4 to 6 MHz oscillator. (The reason the oscilla- tor needs to be running is that the internal bus is being used to transfer address and program data to appropriate internal registers.) The address of an EPROM location to be programmed is applied to Port 1 and pins P2.0 - P2.4 of Port 2, while the code byte to be programmed into that location is applied to Port 0. The other Port 2 and 3 pins, and RST, PSEN, and EA/Vpp should be held at the Program levels indicated in Table 1. ALE/PROG is pulsed low to program the code byte into the addressed EPROM location. The setup is shown in Figure 8. MCS 51 CONTROLLER Normally EA/Vpp is held at a togic high until just before ALE/PR is to be pulsed. Then EA/Vpp is raised to Vpp, ALE/PROG is pulsed low, and then EA/Vpp is returned to a valid high voltage. The volt- age on the EA/Vpp pin must be at the valid EA/Vpp high level before a verify is attempted. Waveforms and detailed timing specifications are shown in later sections of this data sheet. Note that the EA/Vpp pin must not be allowed to go above the maximum specified Vpp level for any amount of time. Even a narrow glitch above that volt- age level can cause permanent damage to the de- vice. The Vpp source should be well regulated and free of glitches. +5V Voc Po K PGM DATA 1 mend RST EA/Vpp f4 +12 75 ALE/PROG f- 25 100 ws PULSES TO GND 1]Ps.6 a oe B7sxnn PSEN F 0 1>] 3.7 Tro a-ounz [_] te Teh xTAL 1 P20 aa: 27231B-15 Figure 8. Programming the EPROM Table 4. EPROM Programming Modes for 875X8H seen | ALE/ | EA/ > MODE RST PSEN PROG Vpp P27 P2.6 P3.6 P3.7 Program Code Data 1 0 0* Vpp 1 OQ 1 1 Verify Code Data 1 1 1 0 0 1 1 Program Encryption Table 1 Q* Vpp 1 0 0 1 Use Addresses 0-1FH Program Lock x=1 1 0 0" Vpp 1 1 1 1 Bits (LBx) x=2 1 0 o* Vpp 1 1 0 Read Signature 1 1 1 0 0 NOTES: 4 = Valid high for that pin O = Valid low for that pin Vpp = +12.75V +0.25V *ALE/PROG is pulsed low for 100 uS for programming. (Quick-Pulse Programming) | 2-37MCS 51 CONTROLLER QUICK-PULSE PROGRAMMING ALGORITHM The 875XBH can be programmed using the Quick- Pulse Programming Algorithm for microcontrollers. The features of the new programming method are a lower Vpp (12.75 volts as compared to 21 volts) and a shorter programming pulse. For example, it is pos- sible to program the entire 8 Kbytes of 875XBH EPROM memory in less than 25 seconds with this algorithm! To program the part using the new algorithm, Vpp must be 12.75 +0.25 Volts. ALE/PROG is pulsed low for 100 ywseconds, 25 times as shown in Figure 9. Then, the byte just programmed may be verified. After programming, the entire array should be verified. The Program Lock features are pro- grammed using the same method, bu: with the setup as shown in Table 4. The only difference in program- ming Lock features is that the Lock features cannot be directly verified. Instead, verification of program- ming is by observing that their features are enabled. intel. PROGRAM VERIFICATION If the Lock Bits have not been programmed, the on- chip Program Memory can be read out for verifica- tion purposes, if desired, either during or after the programming operation. The address of the Program Memory location to be read is applied to Port 1 and pins P2.0 - P2.4. The other pins should be held at the Verify levels indicated in Table 1. The con- tents of the addressed location will come out on Port 0. External pullups are required on Port 0 for this operation. (If the Encryption Array in the EPROM has been programmed, the data present at Port 0 will be Code Data XNOR Encryption Data. The user must know the Encryption Array contents to manual- ly unencrypt the data during verify.) The setup, which is shown in Figure 10, is the same as for programming the EPROM except that pin P2.7 is held at a logic low, or may be used as an active low read strobe. 1 ALE/PROG : 0 ALE/PROG : | IL WU | l|:--- o 10 ws MIN ' ous *| STC us j 25 PULSES 106 ys ' | | | 272318-16 Figure 9. PROG Waveforms Oka Yee x8 005 Po tata EA/Vpp ' 1 ALE/PROG 1 a7sxay PSEN 9 1 P2.7 0 (ENABLE) LC P2.6 o 4-6 MHz CL} L AV2 272918-17 Figure 10. Verifying the EPROM 2-38intel. PROGRAM MEMORY LOCK The two-level Program Lock system consists of 2 Lock bits and a 32-byte Encryption Array which are used to protect the program memory against soft- ware piracy. ENCRYPTION ARRAY Within the EPROM array are 32 bytes of Encryption Array that are initially unprogrammed (all 1s). Every time that a byte is addressed during a verify, 5 ad- dress lines are used to select a byte of the Encryp- tion Array. This byte is then exclusive-NORed (XNOR) with the code byte, creating an Encrypted Verify byte. The algorithm, with the array in the un- programmed state (all 1s), will return the code in its original, unmodified form. It is recommended that whenever the Encryption Ar- ray is used, at least one of the Lock Bits be pro- grammed as well. LOCK BITS Also included in the EPROM Program Lock scheme are two Lock Bits which function as shown in Table 5. Erasing the EPROM also erases the Encryption Ar- ray and the Lock Bits, returning the part te full un- locked functionality. To ensure proper functionality of the ct ip, the inter- nally latched value of the EA pin must agree with its external state. MCS 51 CONTROLLER Table 5. Lock Bits and their Features Lock Bits Logic Enabled LB1 LB2 U U [Minimum Program Lock features enabled. (Code Verify will still be encrypted by the Encryption Array) P U MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the EPROM is disabled P P |Same as above, but Verify is also disabled U P Reserved for Future Definition P = Programmed U = Unprogrammed READING THE SIGNATURE BYTES The signature bytes are read by the same procedure as a normal verification of locations O30H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values returned are: (030H) = 89H indicates manufactured by intel (031H) = 51H indicates 8751BH 52H indicates 8752BH 2-39MCS 51 CONTROLLER ERASURE CHARACTERISTICS Erasure of the EPROM begins to occur when the 8752BH is exposed to light with wavelengths shorter than approximately 4,000 Angstroms. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an ex- tended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause inadver- tent erasure. If an application subjects the device to a intel e this type of exposure, it is suggested that an opaque label be placed over the window. The recommended erasure procedure is exposure to ultraviolet light (at 2597 Angstroms) to an integrat- ed dose of at lease 15 W-sec/cm. Exposing the EPROM to an ultraviolet lamp of 12,000 W/cm rat- ing for 30 minutes, at a distance of about 1 inch, should be sufficient. Erasure leaves the array in an all 1s state. EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS (Ta = 21C to 27C, Voc = 5.0V +10%, Vgg = OV) Symbol Parameter Min Max Units Vpp Programming Supply Voltage 12.6 13.0 Vv Ipp Programming Supply Current 50 mA 1/TCLCOL Oscillator Frequency 4 6 MHz TAVGL Address Setup to PROG Low 48TCLCL TGHAX Address Hold After PROG 48TCLCL TDVGL Data Setup to PROG Low 48TCLCL TGHDX Data Hold After PROG 48TCLCL TEHSH P2.7 (ENABLE) High to Vpp 48TCLCL TSHGL Vpp Setup to PROG Low 10 ps TGHSL Vpp Hold After PROG 10 ps TGLGH PROG Width | 90 110 us TAVQV Address to Data Valid 48TCLCL TELQV ENABLE Low to Data Valid 48TCLCL TEHQZ Data Float After ENABLE 0 48TCLCL TGHGL PROG High to PROG Low 10 ps EPROM PROGRAMMING AND VERIFICATION WAVEFORMS "ROGRAMMING VERIFICATION i coolpha _ ADDRESS n ADDRESS _~ fe- TAVQY PORT 0 owe th = iN 1] vouoe DATA OUT | st/RROE TAVG! naar es TGHAX | TSH. ee at TGHSL | of oy EA/HIGH | .. TEHS:t TELQY >| [+- r TEHOZ | P2.7 ) \ | 272918-18 2-40intel MCS 51 CONTROLLER DATA SHEET REVISION HISTORY Datasheets are changed as new device information becomes available. Verify with your local intel sales office that you have the latest version before finalizing a design or ordering devices. The following differences exist between this datasheet (272318-002) and the previous version (272318-001): 1. Removed QP and QD (commercial with extended burn-in) from Table 1. EXPRESS Prefix identification. This datasheet (272318-001) replaces the following datasheets: MCS 51 Controllers (270048-007) 8051AHP (270279-004) 8751BH (270248-005) 8751BH EXPRESS (270708-001) 8752BH (270429-004) 8752BH EXPRESS (270650-002) a | 2-41