MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70
H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
7th.July.2000 Ver. 1.1
MITSUBISHI
ELECTRIC
NC : NO CONNECTION
DESCRIPTION
FEATURES
Type name
Access
time
(max)
Active
(max)
stand-by
(max)
Power supply current
The M5M5V108DFP,VP,KV are a 1048576-bit CMOS static RAM
organized as 131072 word by 8-bit which are fabricated using high-
performance triple-polysilicon and double metal CMOS technology.
The use of thin film transistor (TFT) load cells and CMOS periphery
result in a high density and low power static RAM.
They are low standby current and low operation current and ideal
for the battery back-up application.
The M5M5V108DVP,KV are packaged in a 32-pin thin small
outline package which is a high reliability and high density surface
mount device(SMD).
Package
APPLICATION
Small capacity memory units
Directly TTL compatible : All inputs and outputs
Easy memory expansion and power down by S1,S2
Data hold on +2V power supply
Three-state outputs : OR - tie capability
OE prevents data contention in the I/O bus
Common data I/O
M5M5V108DFP,VP,KV-70H
70ns
5mA
2.7~3.6V
12µA
(1MHz)
VCC
M5M5V108DFP ············ 32pin 525mil SOP
M5M5V108DVP,RV ············ 32pin 8 X 20 mm TSOP
M5M5V108DKV,KR ············ 32pin 8 X 13.4 mm TSOP
1
22
PIN CONFIGURATION (TOP VIEW)
A11
A9
A8
A13
W
S2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
OE
A10
S1
DQ8
DQ7
DQ6
DQ5
DQ4
GND
DQ3
DQ2
DQ1
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
M5M5V108DVP,KV
Outline 32P3H-E(VP),
32P3K-B(KV)
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
GND
VCC
A15
S2
W
A13
A8
A9
A11
OE
A10
S1
DQ8
DQ7
DQ6
DQ5
DQ4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Outline
32P2M-A
ADDRESS
INPUT
CHIP SELECT
INPUT
WRITE CONTROL
INPUT
ADDRESS
INPUTS
OUTPUT ENABLE
INPUT
ADDRESS
INPUT
CHIP SELECT
INPUT
DATA
INPUTS/
OUTPUTS
ADDRESS
INPUTS
DATA
INPUTS/
OUTPUTS
MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70
H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
7th.July.2000 Ver. 1.1
MITSUBISHI
ELECTRIC
FUNCTION
BLOCK DIAGRAM
The operation mode of the M5M5V108D series are determined by
a combination of the device control inputs S1,S2,W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps with
the low level S1and the high level S2. The address must be set up
before the write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W,S1or
S2,whichever occurs first,requiring the set-up and hold time relative
to these edge to be maintained. The output enable input OE
directly controls the output stage. Setting the OE at a high level,
the output stage is in a high-impedance state, and the data bus
contention problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and OE at a
low level while S1and S2are in an active state(S1=L,S2=H).
When setting S1at a high level or S2at a low level, the chip are in
a non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high- impedance
state, allowing OR-tie with other chips and memory expansion by
S1and S2. The power supply current is reduced as low as the
stand-by current which is specified as ICC3 or ICC4, and the memory
data can be held at +2V power supply, enabling battery back-up
operation during power failure or power-down operation in the non-
selected mode.
S1
S2
W
OE
Mode
DQ
ICC
L
L
H
H
H
H
L
H
Non selection
Write
Read
High-impedance
Din
Dout
Active
Stand-by
Non selection
High-impedance
High-impedance
Active
Active
Stand-by
FUNCTION TABLE
L
H
L
X
H
X
X
X
X
L
X
X
2
CLOCK
GENERATOR
131072 WORDS
X 8 BITS
( 512 ROWS
X128 COLUMNS
X 16BLOCKS )
21
22
23
25
26
27
28
29
13
14
15
17
18
19
20
21
5
30
6
32
8
29
22
30
24
32
16
24
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
W
S1
S2
OE
VCC
GND
(0V)
* Pin numbers inside dotted line show those of TSOP
*
*
DATA
INPUTS/
OUTPUTS
WRITE
CONTROL
INPUT
CHIP
SELECT
INPUTS
OUTPUT
ENABLE
INPUT
ADDRESS
INPUTS
A3
A2
A5
A6
A7
A12
A14
A16
A15
A13
A8
A9
A11
A1
A0
A10
A4
7
10
3
4
5
6
7
10
9
11
12
13
14
15
18
17
2
31
2
3
4
28
27
26
1
25
20
19
11
12
31
23
16
8
MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70
H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
7th.July.2000 Ver. 1.1
MITSUBISHI
ELECTRIC
ABSOLUTE MAXIMUM RATINGS
CAPACITANCE
Symbol
Parameter
Test conditions
pF
pF
Unit
Max
8
10
Typ
Min
Limits
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
Input capacitance
Output capacitance
CI
CO
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Unit
V
V
V
mW
°C
°C
Conditions
With respect to GND
Ta=25°C
700
0~70
– 65~150
Ratings
Symbol
V
cc
DC ELECTRICAL CHARACTERISTICS
(Ta=0~70°C, Vcc=2.7~3.6V, unless otherwise noted)
Symbol
Parameter
V
V
V
Max
Typ
Limits
Min
Test conditions
Unit
V
µA
– 0.3*~4.6
– 0.3*~Vcc + 0.3
(Ta=0~70°C, unless otherwise noted)
0~Vcc
* –3.0V in case of AC ( Pulse width ≤ 30ns )
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is Vcc = 3V, Ta = 25°C
mA
* –3.0V in case of AC ( Pulse width ≤ 30ns )
µA
µA
V
Vcc
+ 0.3
0.6
2.0
–0.3*
2.4
0.33
Stand-by current
0.4
±1
Active supply current
Active supply current
Vcc
– 0.5
±1
35
VIH
VIL
VOH1
VOH2
VOL
II
IO
ICC1
ICC2
ICC3
ICC4
High-level input voltage
Low-level input voltage
High-level output voltage 1
High-level output voltage 2
Low-level output voltage
Input current
Output current in off-state
Stand-by current
IOH= – 0.5mA
IOH= – 0.05mA
IOL= 2mA
VI=0~Vcc
S1=VIH or S2=VIL or OE=VIH
VI/O=0~VCC
S1=VIL,S2=VIH,
other inputs=VIH or VIL
Output-open(duty 100%)
1) S2≤ 0.2V
other inputs=0~VCC
2) S1≥ VCC–0.2V,
S2 ≥ VCC–0.2V
other inputs=0~VCC
S1=VIH or S2=VIL,
other inputs=0~VCC
~25°C
(Max 4.6)
3
~40°C
~70°C
1.2
3.6
12
5
70ns
1MHz
VI
VO
Pd
Topr
Tstg
-H
MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70
H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
7th.July.2000 Ver. 1.1
MITSUBISHI
ELECTRIC
(2) READ CYCLE
(3) WRITE CYCLE
Symbol
Parameter
tCR
Read cycle time
Address access time
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Limits
ta(S1)
ta(S2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(OE)
ten(S1)
ten(S2)
ten(OE)
tV(A)
ta(A)
Limits
AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, unless otherwise noted )
(1) MEASUREMENT CONDITIONS
Chip select 1 access time
Chip select 2 access time
Output enable access time
Output disable time after S1high
Output disable time after S2low
Output disable time after OE high
Output enable time after S1low
Output enable time after S2high
Output enable time after OE low
Data valid time after address
70
70
70
35
25
25
25
70
10
10
5
10
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to W
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
25
25
70
55
0
65
65
65
30
0
0
5
5
VCC 2.7~3.6V
Input pulse level VIH=2.2V,VIL=0.4V
Input rise and fall time 5ns
Reference level VOH=VOL=1.5V
Output loads Fig.1, CL=30pF
CL=5pF (for ten,tdis)
Transition is measured ± 500mV from steady
state voltage. (for ten,tdis)
.................................
...............
.............
.....
...................
including
scope and JIG
1TTL
CL
DQ
Fig.1 Output load
Min
Max
-70H
Max
Min
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(S1)
tsu(S2)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
-70H
4
MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70
H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
7th.July.2000 Ver. 1.1
MITSUBISHI
ELECTRIC
ten (W)
Read cycle
Write cycle (W control mode)
(4) TIMING DIAGRAMS
DATA VALID
(Note 3)
(Note 3)
ta(A)
ta (S1)
tv (A)
ta (S2)
ten (S2)
tdis (S1)
tdis (S2)
ta (OE)
ten (OE)
tdis (OE)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
tCR
th (D)
tsu (D)
DQ1~8
S1
tsu (S1)
S2
OE
tsu (S2)
tsu (A-WH)
ten(OE)
tdis (OE)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
W
tw (W)
trec (W)
tsu (A)
tdis (W)
tCW
ten (S1)
W = "H" level
A0~16
DQ1~8
S1
S2
OE
A0~16
STABLE
DATA IN
5
MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70
H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
7th.July.2000 Ver. 1.1
MITSUBISHI
ELECTRIC
Write cycle ( S1control mode)
Write cycle (S2control mode)
tsu (S1)
(Note 3)
(Note 3)
trec (W)
th (D)
tCW
(Note 5)
(Note 3)
(Note 3)
tsu (A)
(Note 4)
tsu (D)
th (D)
tCW
(Note 5)
(Note 3)
(Note 3)
tsu (S2)
trec (W)
tsu (A)
(Note 4)
(Note 3)
(Note 3)
tsu (D)
DATA IN
STABLE
DATA IN
STABLE
DQ1~8
S1
S2
W
A0~16
DQ1~8
S1
S2
W
A0~16
Note 3: Hatching indicates the state is "don't care".
4: Writing is executed while S2high overlaps S1and W low.
5: When the falling edge of W is simultaneously or prior to the falling edge of S1
or rising edge of S2, the outputs are maintained in the high impedance state.
6: Don't apply inverted phase signal externally when DQ pin is output mode.
6
MITSUBISHI LSIs
M5M5V108DFP,VP,KV -70
H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
7th.July.2000 Ver. 1.1
MITSUBISHI
ELECTRIC
VCC = 3V 1) S2 ≤ 0.2V,
other inputs = 0~3V
2) S1 ≥ VCC–0.2V,
S2 ≥ VCC–0.2V
other inputs = 0~3V
(Ta=0~70°C, unless otherwise noted)
(3) POWER DOWN CHARACTERISTICS
S1control mode
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Power down set up time
Power down recovery time
(2) TIMING REQUIREMENTS (Ta=0~70°C, unless otherwise noted )
tsu (PD)
trec (PD)
Symbol
Parameter
ns
Max
Typ
Limits
Min
Test conditions
Unit
0
5
ms
2.2V
tsu (PD)
2.7V
2.7V
2.2V
trec (PD)
S1≥ VCC - 0.2V
VCC
S1
0.2V
trec (PD)
2.7V
S2≤ 0.2V
S2control mode
2.7V
tsu (PD)
0.2V
VCC
S2
Symbol
Parameter
V
V
Max
Typ
Limits
Min
Test conditions
Unit
µA
V
2
0.2
VCC (PD)
VI (S1)
VI (S2)
ICC (PD)
Power down supply voltage
Chip select input S1
Chip select input S2
Power down supply current
2.0
7
~25°C
~40°C
~70°C
-H
1
3
10
V
0.6
Vcc(PD)
2.7V≤Vcc(PD)
Vcc(PD)<2.7V
Note 7: On the power down mode by controlling S1,the input level of S2 must be S2
≥Vcc - 0.2V or
S2 ≤ 0.2V. The other pins(Address,I/O,WE,OE) can be in high impedance state.
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MITSUBISHI ELECTRIC
8
