100325
Low Power Hex ECL-to-TTL Translator
General Description
The 100325 is a hex translator for converting F100K logic
levels to TTLlogic levels. Differential inputs allow each circuit
to be used as an inverting, non-inverting or differential re-
ceiver. An internal reference voltage generator provides V
BB
for single-ended operation, or for use in Schmitt trigger appli-
cations. All inputs have 50 kΩpull-down resistors. When the
inputs are either unconnected or at the same potential the
outputs will go low.
When used in single-ended operation the apparent input
threshold of the true inputs is 20 mV to 40 mV higher (posi-
tive) than the threshold of the complementary inputs. The
V
EE
and V
TTL
power may be applied in either order.
Features
nPin/function compatible with 100125
nMeets 100125 AC specifications
n50%power reduction of the 100125
nDifferential inputs with built in offset
nStandard FAST®outputs
n2000V ESD protection
n−4.2V to −5.7V operating range
nAvailable to Microcircuit Drawing
(SMD) 5962-9153101
Logic Diagram Pin Names Description
D
0
–D
5
Data Inputs
D
0
–D
5
Inverting Data Inputs
Q
0
–Q
5
Data Outputs
FAST®is a registered trademark of Fairchild Semiconductor.
DS100314-4
August 1998
100325 Low Power Hex ECL-to-TTL Translator
© 1998 National Semiconductor Corporation DS100314 www.national.com
Connection Diagrams Truth Table
Inputs Outputs
D
n
D
n
Q
n
LH L
HL H
LL L
HH L
Open Open L
V
EE
V
EE
L
LV
BB
L
HV
BB
H
V
BB
LH
V
BB
HL
H
=
HIGH Voltage Level
L=LOW Voltage Level
24-Pin DIP
DS100314-1
24-Pin Quad Cerpak
DS100314-2
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Above which the useful life may be impaired.
Storage Temperature (T
STG
) −65˚C to +150˚C
Maximum Junction Temperature (T
J
)
Ceramic +175˚C
V
EE
Pin Potential to Ground Pin −7.0V to +0.5V
V
TTL
Pin Potential to Ground Pin −0.5V to +6.0V
Input Voltage (DC) V
EE
to +0.5V
Voltage Applied to Output
in HIGH State (with V
CC
=0V) −0.5V to V
CC
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
ESD (Note 2) ≥2000V
Recommended Operating
Conditions
Case Temperature (T
C
)
Military −55˚C to +125˚C
Supply Voltage (V
EE
) −5.7V to −4.2V
Note 1: Absolute maximum ratings are those values beyond which the de-
vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version
DC Electrical Characteristics
V
EE
=−4.2V to −5.7V, V
CC
=V
CCA
=GND, T
C
=−55˚C to +125˚C, C
L
=50 pF, V
TTL
=+4.5V to +5.5V
Symbol Parameter Min Max Units TCConditions Notes
VBB Output Reference Voltage −1380 −1260 0˚C to +125˚C IVBB =−3 µA, VEE =−4.2V (Notes 3,
4, 5)
mV IVBB =−2.1 mA VEE =−5.7V
−1396 −1260 −55˚C IVBB =−3 mA
VIH Input HIGH Voltage −1165 −870 mV −55˚C to +125˚C Guaranteed HIGH Signal for All Inputs (Notes 3,
4, 5, 6)
(with One Input Tied to VBB)
VIL Input LOW Voltage −1830 −1475 mV −55˚C to +125˚C Guaranteed LOW Signal for All Inputs (Notes 3,
4, 5, 6)
(with One Input Tied to VBB)
VOH Output HIGH Voltage 2.5 mV 0˚C to +125˚C IOH =−2.0 mA VIN =VIH (Max) (Notes 3,
4, 5)
2.4 −55˚C or VIL (Min)
VOL Output LOW Voltage 0.5 mV −55˚C to +125˚C IOL =20 mA
VDIFF Input Voltage Differential 150 mV −55˚C to +125˚C Required for Full Output Swing (Notes 3,
4, 5)
VCM Common Mode Voltage −2000 −500 mV −55˚C to +125˚C (Notes 3,
4, 5, 6)
IIH Input HIGH Current 350 µA 0˚C to +125˚C VIN =VIH (Max),D
0
–D5=VBB ,(Notes 3,
4, 5)
500 −55˚C D0–D5=VIL (Min)
IIL Input LOW Current 0.50 µA −55˚C to +125˚C VIN =VIL (Min), D0–D5=VBB (Notes 3,
4, 5)
IOS Output Short Circuit −150 −60 mA −55˚C to +125˚C VOUT =GND (Notes 3,
4, 5)
Current Test One Output at a Time
ICEX Output HIGH 250 µA −55˚C to +125˚C VOUT =5.5V (Notes 3,
4, 5)
Leakage Current
IEE VEE Power Supply Current −35 −12 mA −55˚C to +125˚C D0–D5=VBB (Notes 3,
4, 5)
ITTL VTTL Power Supply Current 65 mA −55˚C to +125˚C D0–D5=VBB (Notes 3,
4, 5)
Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case
condition at cold temperatures.
Note 4: Screen tested 100%on each device at −55˚C, +25˚C, and +125˚C, Subgroups 1, 2, 3, 7, and 8.
Note 5: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, + 25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8.
Note 6: Guaranteed by applying specified input condition and testing VOH/VOL.
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AC Electrical Characteristics
V
EE
=−4.2V to −5.7V, V
CC
=GND, V
TTL
=+4.5V to +5.5V
Symbol Parameter T
C
=−55˚C T
C
=+25˚C T
C
=+125˚C Units Conditions Notes
Min Max Min Max Min Max
t
PLH
Propagation Delay 1.50 5.00 1.60 4.70 1.70 5.70 ns C
L
=50 pF (Notes 7,
8, 9)
t
PHL
Data to Output
Figures 1, 3
Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
after power-up. This provides “cold start” specs which can be considered a worst case condition at cold temperatures.
Note 8: Screen tested 100%on each device at +25˚C, temperature only, Subgroup A9.
Note 9: Sample tested (Method 5005, Table I) on each manufactured lot at +25˚C, Subgroup A9, and at +125˚C and −55˚C temperatures, SubgroupsA10 andA11.
Note 10: Not tested at +25˚C, +125˚C, and −55˚C temperature (design characterization data).
Switching Waveform
DS100314-6
FIGURE 1. Propagation Delay
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Test Circuits
DS100314-5
Notes:
VCC =0V, VEE =−4.5V, VTTL =+5V
L1 and L2 =equal length 50Ωimpedance lines
RT=50Ωterminator internal to scope
Decoupling 0.1 µF from GND to VCC,V
EE and VTTL
All unused outputs are loaded with 500Ωto GND
CL=Fixture and stray capacitance =15 pF
FIGURE 2. AC Test Circuit for 15 pF Loading
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Test Circuits (Continued)
DS100314-8
Notes:
VCC =0V, VEE =−4.5V, VTTL =+5V
L1 and L2 =equal length 50Ωimpedance lines
RT=50Ωterminator internal to scope
Decoupling 0.1 µF from GND to VCC,V
EE and VTTL
All unused outputs are loaded with 500Ωto GND
CL=Fixture and stray capacitance =50 pF
FIGURE 3. AC Test Circuit for 50 pF Loading
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Physical Dimensions inches (millimeters) unless otherwise noted
24 Lead Ceramic Dual-In-Line Package (0.400" Wide) (D)
NS Package Number J24E
24 Lead Quad Cerpak (F)
NS Package Number W24B
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ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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100325 Low Power Hex ECL-to-TTL Translator
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
