Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 268
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 270
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 272
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 273
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 275
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 276
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 277
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 279
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 280
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 281
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 282
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 283
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 284
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 285
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 286
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 287
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 288
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 289
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 290
SSI ................................................................................................................................................. 291
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 303
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 305
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 307
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 308
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 309
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 310
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 311
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 312
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 313
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 314
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 315
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 316
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 317
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 318
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 319
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 320
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 321
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 322
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 323
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 324
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 325
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 326
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 340
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 341
Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 345
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 346
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 347
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 348
15June 14, 2007
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LM3S1150 Microcontroller