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* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.
REV. D
DAC10–SPECIFICATIONS
–2–
ELECTRICAL CHARACTERISTICS
DAC10F DAC10G
Parameter Symbol Conditions Min Typ Max Min Typ Max Units
MONOTONICITY 10 10 Bits
NONLINEARITY NL 0.3 0.5 0.6 1 LSB
DIFFERENTIAL
NONLINEARITY DNL 0.3 1 0.7 LSB
SETTLING TIME t
S
All Bits Switched ON or OFF
Settle to 0.05% of FS (See Note) 85 135 85 150 ns
OUTPUT CAPACITANCE C
O
18 18 pF
PROPAGATION DELAY t
PLH
All Bits Switched R
L
= 5 kΩ50 50 ns
t
PHL
R
L
= 0 kΩ50 50 ns
OUTPUT VOLTAGE Full-Scale Current Change –5.5 –5.5 V
COMPLIANCE V
OC
<1 LSB +10 +10 V
GAIN TEMPCO TCI
FS
(See Note) ±10 ±25 ±10 ±50 ppm/°C
FULL-SCALE SYMMETRY I
FSS
I
FR
–I
FR
0.1 4 0.1 4 µA
ZERO-SCALE CURRENT I
ZS
0.01 0.5 0.01 0.5 µA
FULL-SCALE CURRENT I
FR
(See Note) 3.960 3.996 4.032 3.920 3.996 4.072 mA
REFERENCE INPUT
SLEW RATE DI/dt 6 6 mA/µs
REFERENCE BIAS
CURRENT I
B
–1 –3 –1 –3 µA
POWER SUPPLY PPS/
FS
+ 4.5 V ≤ V+ ≤ –18 V 0.001 0.01 0.001 0.01 %∆I
FS
/%∆V
SENSITIVITY PPS/
FS
– –18 V ≤ V– ≤ –10 V 0.0012 0.01 0.0012 0.01 %∆I
FS
/%∆V
POWER SUPPLY CURRENT I+ V
S
= ±15 V; I
REF
= 2 mA 2.3 4 2.3 4 mA
I– –9 –15 –9 –15 mA
I+ V
S
= +5 V; –7.5 V; I
REF
= 1 mA 1.8 4 1.8 4 mA
I– –5.9 –9 –5.9 –9 mA
POWER DISSIPATION P
D
V
S
= ±15 V; I
REF
= 2 mA 231 285 231 285 mW
P
D
V
S
= +5 V; –7.5 V; I
REF
= 1 mA 85 88 85 88 mW
LOGIC INPUT LEVELS V
IL
V
LC
= 0 0.8 0.8 V
V
IH
V
LC
= 0 2 2 V
LOGIC INPUT CURRENTS I
IL
V
LC
= 0; V
IN
= 0.8 V –10 –5 –10 –5 µA
I
IH
V
IN
= 2.0 V 0.001 10 0.001 10 µA
ELECTRICAL CHARACTERISTICS
DAC10F DAC10G
Parameter Symbol Conditions Min Typ Max Min Typ Max Units
MONOTONICITY 10 10 Bits
NONLINEARITY NL 0.3 0.5 0.6 1 LSB
DIFFERENTIAL
NONLINEARITY DNL 0.3 1 0.7 LSB
OUTPUT VOLTAGE
COMPLIANCE V
OC
Full-Scale Current Change, <1 LSB –5 –6/+18 +10 –5 –6/+15 +10 V
FULL-SCALE CURRENT I
FS
V
REF
= 10.000 V,
R14 = R15 = 5.000 kΩ3.978 3.996 4.014 3.956 3.996 4.036 mA
FULL-SCALE SYMMETRY I
FSS
I
FR
–I
FR
0.1 4 0.1 0.4 µA
ZERO-SCALE CURRENT I
ZS
0.01 0.5 0.01 0.5 µA
NOTE: Guaranteed by design.
(@ VS = 615 V; IREF = 2 mA; 08C ≤ TA ≤ +708C for DAC10F and G, unless otherwise noted.
Output characteristics apply to both IOUT and IOUT.)
(@ VS = 615 V; IREF = 2 mA; TA = +258C, unless otherwise noted. Output characteristics
apply to both IOUT and IOUT.)
–3–REV. D
DAC10
WAFER TEST LIMITS
DAC10N
Parameter Symbol Conditions Limit Units
RESOLUTION 10 Bits min
MONOTONICITY 10 Bits min
NONLINEARITY NL ±0.5 LSB max
OUTPUT VOLTAGE COMPLIANCE V
OC
True 1 LSB +10 V max
–5 V min
OUTPUT CURRENT RANGE I
FS
±3.996 mA ±18 µA max
ZERO-SCALE CURRENT I
ZS
All Bits OFF 0.5 µA max
LOGIC INPUT “1” V
IH
I
IN
= 100 nA 2 V min
LOGIC INPUT “0” V
IL
V
LC
@ Ground 0.8 V max
I
IN
= –100 µA
POSITIVE SUPPLY CURRENT I+ V+ = 15 V 4 mA max
NEGATIVE SUPPLY CURRENT I– V+ = –15 V –15 mA max
NOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not
guaranteed for standard produce dice.
TYPICAL ELECTRICAL CHARACTERISTICS
DAC10F
Parameter Symbol Conditions Typ Units
SETTLING TIME t
S
To ±1/2 LSB When Output Is Switched from 0 to FS 85 ns
GAIN TEMPERATURE
COEFFICIENT (TC) V
REF
Tempco Excluded ±10 ppm FS/°C
OUTPUT CAPACITANCE 18 pF
OUTPUT RESISTANCE 10 MΩ
(@ VS = 615 V, IREF = 2 mA, TA = +258C, unless otherwise noted. Output characteristics refer to both
IOUT and IOUT).
(@ VS = 615 V, IREF = 2 mA, unless otherwise noted. Output characteristics
refer to both IOUT and IOUT).
DICE CHARACTERISTICS
DIE SIZE 0.091 3 0.087 inch, 7,917 sq. mils
(2.311 3 2.210 mm, 5.107 sq. mm)
DAC10
–4– REV. D
ABSOLUTE MAXIMUM RATINGS
1
Operating Temperature
DAC10FX, GX, GS, GP . . . . . . . . . . . . . . . . 0°C to +70°C
Junction Temperature (T
J
) . . . . . . . . . . . . . –65°C to +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . +300°C
V+ Supply to V– Supply . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . V– to V– plus 36 V
V
LC
␣ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V– to V+
Analog Current Outputs . . . . . . . . . . . . . . . . +18 V to –18 V
Reference Inputs (V
16
to V
17
) . . . . . . . . . . . . . . . . . V– to V+
Reference Input Differential Voltage (V
16
to V
17
) . . . . ±18 V
Reference Input Current (I
16
) . . . . . . . . . . . . . . . . . . 2.5 mA
Package Type u
JA2
u
JC
Units
18-Lead Hermetic DIP (X) 48 15 °C/W
18-Lead SOIC (S) 89 28 °C/W
18-Lead Plastic DIP (P) 74 33 °C/W
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
θ
JA
is specified for worst case mounting conditions, i.e., θ
JA
is specified for device
in socket for Cerdip packages.
ORDERING GUIDE
INL Temperature Package Package
Model (LSB) Range Description Options
DAC10FX 0.5 0°C to +70°C Cerdip Q-18
DAC10GX 1 0°C to +70°C Cerdip Q-18
DAC10GS 1 0°C to +70°C SOIC R-18
DAC10GP 1 0°C to +70°C Plastic DIP N-18
PIN CONNECTIONS
18-Lead Hermetic DIP
18-Lead Plastic DIP
18-Lead SOIC
TOP VIEW
(Not to Scale)
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
DAC10
B5
B4
V
LC
I
O
V–
I
O
B3
B2
(MSB) B1
B6
B7
COMP
V
REF
(–)
V
REF
(+)
V+
B8
B9
B10 (LSB)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
BASIC CONNECTIONS
0mA
1.0mA
2.0mA
IOUT
IOUT
(0000000000) (11111111111)
IREF = 2mA
Figure 1. True and Complementary
Output Operations
V+, POSITIVE POWER SUPPLY – V
DC
POWER SUPPLY CURRENT – mA
10
3
002 20
4681012141618
9
4
2
1
6
5
8
7
ALL BITS "HIGH" OR "LOW"
I–
I+
Figure 4. Power Supply Current
vs. V+
0.1mF
C
C
318
V+
0.01mF
15
COMP
B
1
5 6
B
2
B
3
7 8
B
4
9
B
5
10
B
6
11
B
7
12
B
8
13
B
9
14
B
10
V
LC
1
I
FR
= +V
REF
R
REF
31023
1024 2
3
I
O
+ I
O
= I
FR
FOR ALL
LOGIC STATES
+V
REF
R
REF
(R16)
I
REF
R17
16
MSB LSB
FOR FIXED REFERENCE,
TTL OPERATION,
TYPICAL VALUES ARE:
V
REF
= +10.000V
R
REF
= 5.000kV
R15 = R
REF
C
C
= 0.01mF
V
LC
= 0V (GROUND)
I
O
I
O
4
2
17
DAC10
V–
Figure 7. Basic Positive Reference Operation
Typical Performance Characteristics–DAC10
–5–
REV. D
WARNING!
ESD SENSITIVE DEVICE
V– = –15V, V– = –10V
T
A
= T
MIN
TO T
MAX
ALL BITS ON
OUTPUT VOLTAGE – Volts
OUTPUT CURRENT – mA
8.0
0
–14 –10 18–6 –2 2 6 10 14
7.2
4.8
4.0
2.4
0.8
6.4
5.6
3.2
1.6
I
REF
= 1mA
I
REF
= 2mA
I
REF
= 0.2mA
Figure 2. Output Current vs. Output
Voltage (Output Voltage Compliance)
POWER SUPPLY CURRENT – mA
10
3
00 –20
–4 –8 –12 –16
9
4
2
1
6
5
8
7
V–, NEGATIVE POWER SUPPLY – VDC
BITS MAY BE HIGH OR LOW
I – WITH IREF = 2mA
I – WITH IREF = 1mA
I – WITH IREF = 0.2mA
I – WITH IREF = 0.2mA
Figure 5. Power Supply Current
vs. V–
TEMPERATURE – 8C
OUTPUT VOLTAGE – Volts
+28
–12 –50
FOR OTHER V– OR IREF
SEE OUTPUT CURRENT
vs. OUTPUT VOLTAGE
CURVE
SHADED AREA INDICATES
PERMISSABLE OUTPUT
VOLTAGE RANGE
FOR V– = –15V
IREF # 2.0mA
0+50 +100 +150
+24
+4
0
–4
–8
+20
+16
+8
+12
Figure 3. Output Voltage Compliance
vs. Temperature
TEMPERATURE – 8C
POWER SUPPLY CURRENT – mA
10
0–50 0 +50 +100 +150
9
4
3
2
1
8
7
5
6ALL BITS MAY BE "HIGH" OR "LOW"
V+ = +15V I+
I–
I
REF
= 2.0mA
V– = –15V
Figure 6. Power Supply Current vs.
Temperature
DAC10
DAC10
16
17
16
17
V
IN
V
IN
I
IN
R
REF
R17
(OPTIONAL)
R
IN
I
REF
+V
REF
R
REF
R
REF
R17 +V
REF
I
REF
PEAK NEGATIVE SWING OF I
IN
+V
REF
MUST BE ABOVE PEAK POSITIVE SWING OF V
IN
HIGH INPUT
IMPEDANCE
Figure 8. Accommodating Bipolar References
DAC10
–6– REV. D
Figure 13. Offset Binary Operation
Figure 12. Basic Bipolar Output Operation
Figure 11. Basic Unipolar Negative Operation
Figure 9. Basic Negative Reference Operation Figure 10. Recommended Full-Scale Adjustment Circuit
DAC10
16
17
R
REF
R17
4
2I
O
I
O
I
FS
–V
REF
R
REF
2
3
–V
REF
NOTE: R
REF
SETS I
FS
; R17 IS FOR BIAS
CURRENT CANCELLATION
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
B
9
B
10
MSB LSB
DAC10
I
REF
=
2.000mA 16
2
41.25kV
1.25kV
I
O
I
O
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
B
9
B
10
1111 111 111
1000 000 010
1000 000 000
0111 111 111
0000 000 010
0000 000 000
FULL RANGE
HALF-SCALE +LSB
HALF-SCALE
HALF-SCALE –LSB
HALF-SCALE +LSB
ZERO SCALE +LSB
I
O
mA
0.000
1.992
1.996
2.000
3.992
3.996
E
O
–0.000
–2.490
–2.495
–2.500
–4.990
–4.995
I
O
mA
3.996
2.004
2.000
1.996
0.004
0.000
E
O
–4.995
–2.505
–2.500
–2.495
–0.005
0.000
E
O
E
O
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
B
9
B
10
MSB LSB
DAC10
I
REF (+)
=
2.000mA 16
2
4
2.5kV
I
O
I
O
2.5kV
+5V
E
O
E
O
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
B
9
B
10
1111111 111
1111111 101
1000000 010
1000000 000
1111111 111
0000000 010
POSITIVE FULL RANGE
POSITIVE FULL RANGE –LSB
ZERO-SCALE +LSB
ZERO-SCALE
NEGATIVE FULL-SCALE +LSB
NEGATIVE FULL-SCALE
E
O
+5.000
+4.990
+0.020
+0.010
0.000
–4.980
E
O
–4.990
–4.980
–0.010
0.000
+0.010
+4.990
ZERO-SCALE –LSB
0000000 000 +5.000 –4.990
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
B
9
B
10
MSB LSB
DAC10
2
4
2.5kV
I
O
I
O
+15V
E
O
+15V
2
V
IN
V
O
REF01
GND
4
6
5kV
5.000
kV
5kV
V–
V+
C
C
V
LC
–15V
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
B
9
B
10
1111 111 111
1000 000 000
0000 000 010
0000 000 000
POSITIVE FULL RANGE
ZERO-SCALE
NEGATIVE FULL-SCALE +LSB
NEGATIVE FULL-SCALE
E
O
+4.990
0.00
–4.990
–5.000
I
REF
(+) 2mA DAC10
16
17
V
REF
+10V
LOW T.C.
4.5kV
39kV
10kV
POT 1V
APPROXIMATELY
5kV
DAC10
REV. D –7–
Figure 15. Positive Low Impedance Output Operation
Figure 16. Negative Low Impedance Output Operation Figure 17. Interfacing with Various Logic Families
Figure 14. Settling Time Measurement
DAC10 EOOP01
RL
0 TO +IFR 3 RL
IO
IO
4
2
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE
LOGIC DAC), CONNECT INVERTING INPUT OF OP AMP TO
IO (PIN 2); CONNECT IO (PIN 4) TO GROUND.
IFR =1023
10243 2 3 IREF
DAC10
E
O
OP15
0 TO –I
FR
3 R
L
I
O
I
O
4
2I
FR =
1023
10243 2 3 I
REF
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE
LOGIC DAC), CONNECT NOINVERTING INPUT OF OP AMP TO
I
O
PIN 2); CONNECT I
O
(PIN 4) TO GROUND.
R
L
ECL
13kV
–5.2V
V
LC
TO PIN 1
2N3904
"A"
39kV
3kV
6.2kV
2N3904
+15V
V
LC
9.1kV
V
TH
= V
LC
+1.4V
+15V CMOS
V
TH
= +7.6V
6.2kV0.1mF
DAC10
TTL
V
TH
= +1.4V
V
LC
1
51V
2.5kV
2.5kV
10kV
1MV
1/4W, 5%
CARBON
2kV
4kV
1kV499kV
1/4W, 5% CARBON
0.01mF
1mF
0.01mF
0.1mF10mF
4.7mF0.01mF
1mF
0.01mF 4.7mF
0.1mF10mF
+15V
V
L
0.500V 60.001V +15V
–15V
V
O
–15V
+15V
15 16 18 317 1 2
514
4
26
5
4
REF-01
–15V
–15V
175mV
2N918
2N918
LOW-TO-HIGH SETTLING V
L
= 16.500V 60.001V
HIGH-TO-LOW SETTLING V
L
= 0.500V 60.001V
1/2 LSB SETTLING = 7.8mV
NOTES:
1. CASE OF 2N918s MUST BE GROUNDED.
2. RESISTORS ARE 1/4W MF, 1% UNLESS OTHERWISE SPECIFIED.
3. USE FET PROBE (7A11 SCOPE PLUGIN).
D.U.T.
IN5711
DAC10
–8– REV. D
APPLICATIONS
DAC10
OPTIONAL RESISTOR
FOR OFFSET INPUTS
R
REF
R
L
R
L
2
4
17
16
R
P
R
IN
+V
REF
R
EQ
= 800V
NO CAP
0V
TYPICAL VALUES:
R
IN
= 1kV
+V
IN
= 2V
1
R
IN
1
R
P
1
R
REF
+
R
EQ
= +
1
Figure 18. Pulsed Reference Operation
Reference Amplifier Setup
The DAC10 is a multiplying D/A converter in which the output
current is the product of a digital number and the input refer-
ence current. The reference current may be fixed or may vary
from nearly zero to 2 mA. The full-scale output current is a
linear function of the reference current and is given by:
I
FR
=1023
1024 ×2×I
REF
where I
REF
equals current flowing into Pin 16.
In positive reference applications, an external positive reference
voltage forces current through R16 into the V
REF
(+) terminal
(Pin 16) of the reference amplifier. Alternatively, a negative
reference may be applied to V
REF
(–) at Pin 17; reference current
flows from ground through R16 into V(+) as in the positive
reference case. This negative reference connection has the ad-
vantage of a very high impedance presented at Pin 17. R17
(nominally equal to R16) is used to cancel bias current errors;
R17 may be eliminated with only a minor increase in error.
Bipolar references may be accommodated by offsetting V
REF
or
Pin 17. The negative common-mode range of the reference
amplifier is given by: V
CM
– = V– plus (I
REF
× 2 kΩ) plus 2 V.
The positive common-mode range is V+ less 1.8 V.
When a dc reference is used, a reference bypass capacitor is
recommended. A 5 V TTL logic supply is not recommended as
a reference. If a regulated power supply is used as a reference,
R16 should be split into two resistors with the junction bypassed
to ground with a 0.1 µF capacitor.
For most applications, the tight relationship between I
REF
and
I
FS
will eliminate the need for trimming I
REF
. If required, full-
scale trimming may be accomplished by adjusting the value of
R16, or by using a potentiometer for R16. An improved method
of full-scale trimming that eliminates potentiometer TC effect is
shown in the Recommended Full-Scale Adjustment circuit.
The reference amplifier must be compensated by using a capaci-
tor from Pin 18 to V–. For fixed reference operation, a 0.01 µF
capacitor is recommended. For variable reference applications,
see section entitled Reference Amplifier Compensation for Mul-
tiplying Applications.
Multiplying Operation
The DAC10 provides excellent multiplying performance with an
extremely linear relationship between I
FS
and I
REF
over a range
of 4 mA to 4 µA. Monotonic operation is maintained over a
typical range of I
REF
from 100 µA to 2 mA.
Reference Amplifier Compensation for Multiplying Applications
AC reference applications will require the reference amplifier to
be compensated using a capacitor from Pin 18 to V–. The value
of this capacitor depends on the impedance presented to Pin 16
for R16 values of 1.0 kΩ, 2.5 kΩ and 5.0 kΩ, minimum values
of C
C
are 15 pF, 37 pF and 75 pF. Larger values of R16 require
proportionately increased values of C
C
for proper phase margin.
For fastest response to a pulse, low values of R16 enabling small
C
C
values should be used. If Pin 16 is driven by a high imped-
ance such as a transistor current source, none of the above val-
ues will suffice and the amplifier must be heavily compensated,
which will decrease overall bandwidth and slew rate. For R16 =
1kΩ and C
C
= 15 pF, the reference amplifier slews at 4 mA/µs
enabling a transition from I
REF
= 0 to I
REF
= 2 mA in 500 ns.
Operation with pulse inputs to the reference amplifier may be
accommodated by an alternate compensation scheme. This
technique provides lowest full-scale transition times. An internal
clamp allows quick recovery of the reference amplifier from a
cutoff (I
REF
= 0) condition. Full-scale transition (0 mA to 2 mA)
occurs in 120 ns when the equivalent impedance at Pin 16 is
200 Ω and C
C
= 0. This yields a reference slew rate of 16 mA/
µs, which is relatively independent of R
IN
and V
IN
values.
LOGIC INPUTS
The DAC10 design incorporates a unique logic input circuit
that enables direct interface to all popular logic families and
provides maximum noise immunity. This feature is made pos-
sible by the large input swing capability, 2 µA logic input current
and completely adjustable logic threshold voltage. For V– = –15 V,
the logic inputs may swing between –5 and +18 V. This enables
direct interface with +15 V CMOS logic, even when the DAC10
is powered from a +5 V supply. Minimum input logic swing and
minimum logic threshold voltage are given by: V– plus (l
REF
×
2kΩ) plus 3 V. The logic threshold may be adjusted over a wide
range by placing an appropriate voltage at the logic threshold
control Pin (Pin 1, V
LC
). The appropriate graph shows the
relationship between V
LC
and V
TH
over the temperature range,
with V
TH
nominally 1.4 V above V
LC
. For TTL interface, simply
ground Pin 1. When interfacing ECL, an I
REF
= 1 mA is recom-
mended. For interfacing other logic families, see Figure 17. For
general setup of the logic control circuit, it should be noted that
Pin 1 will sink 1.1 mA typical; external circuitry should be de-
signed to accommodate this current.
Fastest settling times are obtained when Pin 1 sees a low imped-
ance. If Pin 1 is connected to a 1 kΩ divider, for example, it
should be bypassed to ground by a 0.01 µF capacitor.
DAC10
REV. D –9–
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided
where
I
O
+I
O
=I
FS
. Current appears at the “true” output
when a “1” is applied to each logic input. As the binary count
increases, the sink current at Pin 4 increases proportionally, in
the fashion of a “positive logic” D/A converter. When a “0” is
applied to any input bit, that current is turned off at Pin 4 and
turned on at Pin 2. A decreasing logic count increases
I
O
as in
a negative or inverted logic D/A converter. Both outputs may be
used simultaneously. If one of the outputs is not required, it
must still be connected to ground or to a point capable of sourc-
ing I
FS
. DO NOT LEAVE AN UNUSED OUTPUT PIN OPEN.
Both outputs have an extremely wide voltage compliance en-
abling fast direct current-to-voltage conversion through a resis-
tor tied to ground or other voltage source. Positive compliance
is 36 V above V– and is independent of the positive supply.
Negative compliance is +10 V above V–.
The dual outputs enable double the usual peak-to-peak load
swing when driving loads in quasi-differential fashion. This
feature is especially useful in cable driving, CRT deflection and
in other balanced applications such as driving center-tapped
coils and transformers.
POWER SUPPLIES
The DAC10 operates over a wide range of power supply volt-
ages from a total supply of 9 V to 36 V. When operating with V–
supplies of –10 V or less, I
REF
≤ 1 mA is recommended. Low
reference current operation decreases power consumption and
increases negative compliance, reference amplifier negative
common-mode range, negative logic input range and negative
logic threshold range; consult the various figures for guidance.
For example, operation at –9 V with I
REF
= 2 mA is not recom-
mended because negative output compliance would be reduced
to near zero. Operation from lower supplies is possible, however
at least 8 V total must be applied to ensure turn-on of the inter-
nal bias network.
Symmetrical supplies are not required, as the DAC10 is quite
insensitive to variations in supply voltage. Battery operation is
feasible as no ground connection is required; however, an artifi-
cial ground may be used to ensure that logic swings, etc., remain
within acceptable limits.
TEMPERATURE PERFORMANCE
The nonlinearity and monotonicity specifications of the DAC10
are guaranteed to apply over the entire rated operating tempera-
ture range. Full-scale output current drift is tight, typically
+10 ppm/°C, with zero-scale output current and drift essentially
negligible compared to 1/2 LSB.
The temperature coefficient of the reference resistor, R14,
should match and track that of the output resistor for minimum
overall full-scale drift. Settling times of the DAC10 decrease
approximately 10% at –55°C; an increase of about 15% is typi-
cal at +125°C.
SETTLING TIME
The DAC10 is capable of extremely fast settling times; typically
85 ns at I
REF
= 2 mA. Judicious circuit design and careful board
layout must be employed to obtain full performance potential
during testing and application. The logic switch design enables
propagation delays of only 35 ns for each of the 10 bits. Settling
time to within 1/2 LSB of the LSB is therefore 35 ns, with each
progressively larger bit taking successively longer. The MSB
settles in 85 ns, thus determining the overall settling time of
130 ns. Settling to 8-bit accuracy requires about 60 ns to 78 ns.
The output capacitance of the DAC10, including the package, is
approximately 18 pF; therefore, the output RC time constant
dominates settling time if R
L
> 500 Ω.
Settling time and propagation delay are relatively insensitive to
logic input amplitude and rise and fall times, due to the high
gain of the logic switches. Settling time also remains essentially
constant for I
REF
values down to 1 mA, with gradual increases
for lower I
REF
values. The principal advantage of higher I
REF
values lies in the ability to attain a given output level with lower
load resistors, thus reducing the output RC time constant.
Measurement of settling time requires the ability to accurately
resolve ±2µA; therefore, a 4 kΩ load is needed to provide ad-
equate drive for most oscilloscopes. The settling time fixture of
schematic titled “Settling Time Measurement” uses a cascode
design to permit driving a 4 kΩ load with less than 5 pF of para-
sitic capacitance at the measurement node. At I
REF
values of less
than 1 mA, excessive RC damping of the output is difficult to
prevent while maintaining adequate sensitivity. However, the
major carry from 0111111111 to 1000000000 provides an accu-
rate indicator of settling time. This code change does not re-
quire the normal 6.2 time constants to settle to within ±0.2% of
the final value, and thus settling times may be observed at lower
values of I
REF
.
DAC10 switching transients or “glitches” are very low and may
be further reduced by small capacitive loads at the output with a
minor sacrifice in settling time.
Fastest operation can be obtained by using short leads, minimiz-
ing output capacitance and load resistor values, and by adequate
bypassing at the supply, reference and V
LC
terminals. Supplies
do not require large electrolytic bypass capacitors as the supply
current drain is independent of input logic states; 0.1 µF capaci-
tors at the supply pins provide full transient protection.
DAC10
–10– REV. D
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
18-Lead Cerdip
(Q-18)
18
19
10
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13) MIN 0.098 (2.49) MAX
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.200 (5.08)
MAX
0.960 (24.38) MAX
0.150
(3.81)
MIN
0.070 (1.78)
0.030 (0.76)
0.200 (5.08)
0.125 (3.18) 0.100
(2.54)
BSC
0.060 (1.52)
0.015 (0.38)
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
18-Lead Plastic DIP
(N-18)
18
19
10
0.925 (23.49)
0.845 (21.47)
0.280 (7.11)
0.240 (6.10)
PIN 1
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX 0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
18-Lead Wide Body SOL
(R-18)
0.4193 (10.65)
0.3937 (10.00)
18 10
91
0.4625 (11.75)
0.4469 (11.35)
PIN 1
0.2992 (7.60)
0.2914 (7.40)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10) 0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC 0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0291 (0.74)
0.0098 (0.25) x 45°
C3134–0–5/98
PRINTED IN U.S.A.
