ICX075AK 1/2-inch Progressive Scan CCD Image Sensor with Square Pixel for Color Video Cameras Description The ICX075AK is a 1/2-inch optical interline CCD solid-state image sensor with a square pixel array which supports VGA format. Progressive scan allows all pixels signals to be output independently within approximately 1/60 second. This chip features an electronic shutter with variable chargestorage time which makes it possible to realize fullframe still image without a mechanical shutter. High resolution and high color reproductivity are achieved through the use of R, G, B primary color mosaic filters. Further, high sensitivity and low dark current are achieved through the adoption of HAD (HoleAccumulation Diode) sensors. This chip is suitable for image input and processing applications. 22 pin DIP (Cer-DIP) AAAAA AAAAA AAAAA AAAAA Pin 1 V 3 2 8 Features 38 H Pin 12 * Progressive scan allows individual readout of the image signals from all pixels. Optical black position * High vertical resolusion (580TV-lines) still picture (Top View) without a mechanical shutter. * Square pixel unit cell * VGA format-compatible * R, G, B primary color mosaic filters on chip * High resolution, high color reproductivity, high sensitivity, low dark current * Continuous variable-speed shutter * Low smear * Excellent antiblooming characteristics * Reset gate: 5V drive (bias: no adjustment) Device Structure * Optical size: * Number of effective pixels: * Total number of pixels: * Interline CCD image sensor * Chip size: * Unit cell size: * Optical black: * Number of dummy bits: * Substrate material: 1/2-inch format 782 (H) x 582 (V) 823 (H) x 592 (V) approx. 460K pixels approx. 490K pixels 8.10mm (H) x 6.33mm (V) 8.3m (H) x 8.3m (V) Horizontal (H) direction: Front 3 pixels, rear 38 pixels Vertical (V) direction: Front 8 pixels, rear 2 pixels Horizontal 19 Vertical 5 Silicon Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E95706D72-PS ICX075AK CGG2 VOUT1 CGG1 GND VHOLD V1 V2 V3 HIS HIG1 11 10 9 8 7 6 5 4 3 2 1 Vertical Register VOUT2 Block Diagram and Pin Configuration (Top View) G B G B G R G R G B G B R G R G G B G B R G R G Note) Horizontal Register 1 Note) : Photo sensor 17 RG VL SUB H1 H2 18 19 20 21 22 VOG 16 POG 15 HIG2 14 HHG2 13 HHG1 12 VDD Horizontal Register 2 Pin Description Pin No. Symbol Description 1 HIG1 2 HIS Test pin 2 Test pin 2 3 V3 4 Pin No. Symbol Description 12 VDD Supply voltage 13 RG Reset gate clock Vertical register transfer clock 14 VL Protective transistor bias V2 Vertical register transfer clock 15 SUB Substrate (overflow drain) 5 V1 Vertical register transfer clock 16 H1 Horizontal register transfer clock 6 VHOLD Vertical register final stage accumulation clock 17 H2 Horizontal register transfer clock 7 GND GND 18 HHG1 Inter-horizontal register transfer clock 8 CGG1 Output amplifier 1 gate 1 decoupling capacitor 19 HHG2 9 VOUT1 Signal output 1 20 HIG2 Inter-horizontal register transfer clock Test pin 2 10 CGG2 Output amplifier 2 gate 1 decoupling capacitor 21 POG Test pin 2 11 VOUT2 Signal output 2 22 VOG Vertical register final stage transfer clock 1 DC bias is applied within the CCD, so that this pin should be grounded externally through a capacitance of 1F or more. 2 Regarding the test pins: apply the same voltage as the supply voltage to HIS, and ground HIG1, HIG2, and POG. -2- ICX075AK Absolute Maximum Ratings Item Ratings Unit -0.3 to +55 V VDD, VOUT1, VOUT2, HIS, CGG1, CGG2 - GND -0.3 to +18 V VDD, VOUT1, VOUT2, HIS, CGG1, CGG2 - SUB -55 to +10 V V1, V2, V3, VHOLD, VOG - GND -15 to +20 V V1, V2, V3, VHOLD, VOG - SUB to +10 V Voltage difference between vertical clock input pins to +15 V Voltage difference between horizontal clock input pins to +17 V H1, H2 - VOG -17 to +17 V H1, H2 - GND -10 to +15 V H1, H2 - SUB -55 to +10 V VL - SUB -65 to +0.3 V V2, V3, VDD, VOUT1, VOUT2, HIS, HIG1, HIG2, POG - VL -0.3 to +27.5 V RG - GND -0.3 to +22.5 V V1, CGG1, CGG2, H1, H2, HHG1, HHG2, VOG, VHOLD - VL -0.3 to +17.5 V Storage temperature -30 to +80 C Operating temperature -10 to +60 C Substrate voltage SUB - GND Supply voltage Clock input voltage 1 +27V (Max.) when clock width < 10s, clock duty factor < 0.1%. -3- Remarks 1 ICX075AK Bias Conditions Item Symbol Min. Typ. Max. 15.0 15.45 V 18.5 V Indicated voltage + 0.1 V Supply voltage VDD 14.55 Substrate voltage adjustment range VSUB 9.0 Substrate voltage adjustment precision Protective transistor bias Indicated voltage - 0.1 Indicated voltage 2 VL Unit Remarks 1 DC Characteristics Item Symbol Min. Typ. Max. Unit Remarks Supply current IDD Input current IIN1 1 A 3 Input current IIN2 10 A 4 mA 10 1 Indications of substrate voltage (VSUB) setting value The setting value of the substrate voltage is indicated on the back of image sensor by a special code. Adjust the substrate voltage (VSUB) to the indicated voltage. VSUB code -- two characters indication Integer portion Decimal portion The integer portion of the code and the actual value correspond to each other as follows. Integer portion of code 9 A C d E f G h Value 9 10 11 12 13 14 15 16 17 18 J K <Example> "A5" VSUB = 10.5V. 2 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. 3 (1) Current to each pin when 18V is applied to VDD, VOUT1, VOUT2, HIS, RG, CGG1, CGG2, GND and SUB pins, while all pins that are not tested are grounded. (2) Current to each pin when 20V is applied sequentially to V1, V2 and V3 pins, while all pins that are not tested are grounded. However, 20V is applied to SUB pin. (3) Current to each pin when 15V is applied sequentially to RG, H1 and H2 pins, while all pins that are not tested are grounded. However, 15V is applied to SUB pin. (4) Current to VL pin when 25V is applied to V2, V3, POG, HIG1, HIG2, VDD, VOUT1 and VOUT2 pins or when, 15V is applied to V1, VHOLD, VOG, CGG1, CGG2, H1, H2, HHG1 and HHG2 pins, while VL pin is grounded. However, GND and SUB pins are left open. (5) Current to GND pin when 20V is applied to the RG pin and the GND pin is grounded. 4 Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded. -4- ICX075AK Clock Voltage Conditions Min. Typ. Max. Unit Waveform diagram VVT 14.55 15.0 15.45 V 1 VVH02 -0.05 0 0.05 V 2 VVH1, VVH2, VVH3 -0.2 0 0.05 V 2 VVL1, VVL2, VVL3 -8.0 -7.5 -7.0 V 2 VVL = (VVL01 + VVL03)/2 VV 6.8 7.5 8.05 V 2 VV = VVHn - VVLn (n = 1 to 3) I VVL1 - VVL3 I 0.1 V 2 VVHH 0.5 V 2 High-level coupling VVHL 0.5 V 2 High-level coupling VVLH 0.5 V 2 Low-level coupling VVLL 0.5 V 2 Low-level coupling Item Readout clock voltage Vertical transfer clock voltage Horizontal transfer clock voltage Symbol VVH = VVH02 VH 4.75 5.0 5.25 V 3 VHL -0.05 0 0.05 V 3 4.5 5.0 5.5 V 4 Input through 0.01F capacitance 0.8 V 4 Low-level coupling VRG Reset gate clock voltage Remarks VRGLH - VRGLL VDD +0.4 VDD +0.6 VDD +0.8 V 4 Substrate clock voltage VSUB 21.5 22.5 23.5 V 5 Vertical final stage accumulation clock voltage transfer clock voltage VVHOLDH, VVOGH -0.05 0 0.05 V 6 VVHOLDL, VVOGL -8.0 -7.5 -7.0 V 6 4.75 5.0 5.25 V 7 -8.0 -7.5 -7.0 V 7 -0.05 0 0.05 V 7 VRGH VHHG1H, VHHG2H Inter-horizontal register VHHG1L, VHHG2L transfer clock voltage VHHG1M, VHHG2M -5- ICX075AK Clock Equivalent Circuit Constant Symbol Item Capacitance between vertical transfer clock and GND Capacitance between vertical transfer clocks Min. Typ. Max. Unit Remarks CV1 820 pF CV2 820 pF CV3 820 pF CV12 3300 pF CV23 2200 pF CV31 2200 pF Capacitance between vertical final stage accumulation clock and GND CVHOLD 19 pF Capacitance between vertical final stage transfer clock and GND CVOG 12 pF Capacitance between inter-horizontal register transfer clock and GND CHHG1 19 pF CHHG2 19 pF Capacitance between horizontal transfer clock and GND CH1 68 pF CH2 68 pF Capacitance between horizontal transfer clocks CHH 47 pF Capacitance between reset gate clock and GND CRG 10 pF Capacitance between substrate clock and GND CSUB 400 pF Vertical transfer clock series resistor R1, R2, R3 22 Vertical transfer clock ground resistor RGND 15 RH1 24 RH2 24 Horizontal transfer clock series resistor V1 R1 CV12 CV1 R2 V2 CV2 RH1 RGND Cv31 RH2 H1 H2 CHH CV3 Cv23 CH1 CH2 R3 V3 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit -6- ICX075AK Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% II II M VVT M 2 10% 0% tr twh 0V tf (2) Vertical transfer clock waveform V1 VVH1 VVH1 VVHH VVHL VVH VVHH VVHL VVLH VVL01 VVLH VVL1 VVLL V2 VVH02 VVL VVL1 VVLL VVH2 VVHH VVH2 VVHH VVH VVHL VVHL VVLH VVLH VVL2 VVL2 VVLL V3 VVL VVLL VVH3 VVH3 VVHH VVHL VVHH VVH VVHL VVLH VVLH VVL03 VVLL VVL3 VVL VVLL VV1 = VVH1 - VVL01 VV2 = VVH02 - VVL2 VV3 = VVH3 - VVL03 VVH = VVH02 VVL = (VVL01 + VVL03)/2 -7- ICX075AK (3) Horizontal transfer clock waveform tr twh tf 90% VH twl 10% VHL (4) Reset gate clock waveform tr twh tf VRGH twl RG waveform Point A VRG VRGL + 0.5V VRGLH VRGL VRGLL H1 waveform 2.5V VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval twh, then: VRG = VRGH - VRGL (5) Substrate clock waveform 100% 90% M VSUB VSUB 10% 0% tr twh -8- M 2 tf ICX075AK (6) Vertical final stage accumulation clock waveform * Vertical final stage transfer clock waveform VHOLD, VOG tr tf VVHOLDH, VVOGH 90% 10% VVHOLDL, VVOGL (7) Inter-horizontal register transfer clock waveform HHG1, HHG2 tr tf1 VHHG1H, VHHG2H 90% 90% tf2 10% VHHG1M, VHHG2M 90% 10% 10% VHHG1L, VHHG2L -9- ICX075AK Clock Switching Characteristics Symbol twh twl tr tf, tf1, tf2 Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Readout clock VT Vertical transfer clock V1, V2, V3 Horizontal transfer clock Item H1 18 23 21 26 10 17.5 10 17.5 H2 21 26 18 23 10 10 During imaging 2.3 2.5 0.4 0.1 15 During parallel- H1 serial conversion H2 Reset gate clock RG 11 Substrate clock SUB 1.4 1.6 14 49 15 400 0.01 0.01 0.01 0.01 2 2 0.4 15 Unit Remarks s During readout ns 1 ns 2 s ns 0.4 s Vertical final stage VHOLD accumulation/ VOG transfer clock 20 20 ns 20 20 ns Inter-horizontal register transfer clock HHG1 20 20 ns HHG2 20 20 ns During drain charge 1 When vertical transfer clock driver CXD1268M is used. 2 tf tr - 2ns, and the cross-point voltage (VCR) for the H1 rising side of the H1 and H2 waveforms must be at least 2.5V. two Item Horizontal transfer clock Symbol H1, H2 Min. Typ. Max. 24 29 Unit ns Remarks 3 3 The overlap period for twh and twl of horizontal transfer clocks H1 and H2 is two. - 10 - ICX075AK Image Sensor Characteristics Item (Ta = 25C) Symbol Min. Typ. Sg 170 250 R Rr 0.3 0.45 0.6 1 B Rb 0.4 0.55 0.7 1 Saturation signal Vsat 375 Smear Sm Video signal shading SHg G sensitivity Sensitivity comparison Max. Unit Measurement method mV 1 Remarks mV 2 % 3 25 % 4 Srg 8 % 5 Sbg 8 % 5 Dark signal Vdt 2 mV 6 Ta = 60C Dark signal shading Vdt 1 mV 7 Ta = 60C Lag Lag 0.5 % 8 Uniformity between video signal channels 0.003 0.007 Ta = 60C Zone 0 Note) All the characteristic data of this image sensor was yielded when the sensor was operated in the 1/50s interlaced mode. Zone Definition of Video Signal Shading 782 (H) 6 6 2 582 (V) Zone 0 2 Ignored region Effective pixel region Measurement System CCD signal output 1 [A] [C] C.D.S AMP S/H C.D.S AMP S/H Signal output 1 CCD [B] CCD signal output 2 [D] Signal output 2 Note) Adjust the amplifier gain so that the gain between [A] and [C], and between [B] and [D] equals 1. - 11 - ICX075AK Composition of color coding and output signal The color filters of this image sensor are arranged in the layout shown in the figure below. Gb B Gb B R Gr R Gr Gr and Gb denote the G signals on the same line as the R signal and the B signal, respectively. Gb B Gb B R Gr R Gr Readout modes The output methods for the two readout modes indicated below are now described. 1/50s interlaced 1/25s non-interlaced Gb B R Gr Odd field VOUT1 VOUT2 Gb B R Gr Gb B R Gr VOUT1 VOUT2 Even field VOUT1 VOUT2 1. 1/50s interlaced In this mode, the signals are output in a 1/50s period using the two output pins (VOUT1, VOUT2). The signals from two adjacent horizontal lines are simultaneously output from the respective output pins. The lines output from the output pins are changed over with each field. The VOUT1 signal after it has passed through the CDS and other external circuits or the signal produced by adding the VOUT1 and VOUT2 signals accommodate interlaced scanning. In the Odd field, R signal and Gr signal are output from VOUT1 pin and Gb signal and B signal are output from VOUT2 pin. In the Even field, Gb signal and B signal are output from VOUT1 pin and R signal and Gr signal are output from VOUT2 pin. 2. 1/25s non-interlaced In this mode, the signals are output in a 1/25s period using only one output pin (VOUT1). Unlike the 1/50s interlaced mode described above, the external circuit can be simplified. The imaging characteristics also differ from those of the other modes. R signal and Gr signal lines and Gb signal and B signal lines are output sequentially from VOUT1 pin only. - 12 - ICX075AK Image Sensor Characteristics Measurement Method Measurement conditions 1) In the following measurements, the substrate voltage is set to the value indicated on the device, and the device drive conditions are at the typical values of the bias and clock voltage conditions. 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black (OB) level is used as the reference for the signal output, which is taken as the value of the Gr/Gb signal output or R/B signal output of signal output 1 in the measurement system. 3) In the following measurements, this image sensor is operated in 1/50s interlaced mode. Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II : Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. G sensitivity, sensitivity comparison Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/100s, measure the signal outputs (VGr, VGb, VR and VB) at the center of each Gr, Gb, R and B channel screens, and substitute the values into the following formula. VG = (VGr + VGb)/2 Sg = VG x 100 [mV] 50 Rr = VR/VG Rb = VB/VG 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 20 times the intensity with the average value of the Gr signal output, 120mV, measure the minimum values of the Gr, Gb, R and B signal outputs. 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, first adjust the average value of the Gr signal output to 120mV. Measure the average values of the Gr signal output, Gb signal output, R signal output and B signal output (Gra, Gba, Ra and Ba), and then adjust the luminous intensity to 500 times the intensity with average value of the Gr signal output, 120mV. After the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (Sm1 [mV]) of signal output 1 and the maximum value (Sm2 [mV]) of signal output 2, and substitute the values into the following formula. Sm = Sm1 + Sm2 Gra + Gba + Ra + Ba 1 1 / x x x 100 [%] (1/10V method conversion value) 2 4 10 500 - 13 - ICX075AK 4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the Gr signal output is 120mV. Then measure the maximum (Grmax [mV]) and minimum (Grmin [mV]) values of the Gr signal output and substitute the values into the following formula. SHg = (Grmax - Grmin)/120 x 100 [%] 5. Uniformity between video signal channels After measuring 4, measure the maximum (Rmax [mV]) and minimum (Rmin [mV]) values of R signal, and the maximum (Bmax [mV]) and minimum (Bmin [mV]) values of B signal. Substitute the values into the following formula. Srg = (Rmax - Rmin)/120 x 100 [%] Sbg = (Bmax - Bmin)/120 x 100 [%] 6. Dark signal Measure the average value of the signal output 1 (Vdt [mV]) with the device ambient temperature 60C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 7. Dark signal shading After measuring 6, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output 1 and substitute the values into the following formula. Vdt = Vdmax - Vdmin [mV] 8. Lag Adjust the Gr signal output value generated by strobe light to 120mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/120) x 100 [%] FLD SG Light Strobe light timing Gr signal output 120mV Output - 14 - Vlag (lag) - 15 - RG XH1 XH2 XSUB XVHOLD XHHG1-1 XHHG1-2 XHHG2-1 XHHG2-2 XVOG XV1 XV3 XV2 XSG 5V -7.5V 22/10V 22 /16V 22/16V 10 8 9 1 2 3 4 5 6 7 CXD1250 CXD1268M 22/10V 12 11 17 16 15 14 13 18 20 19 13 12 11 20 19 18 17 N.C. 16 15 14 22/16V 1/35V 10/20V 22/20V 100k 3.3/16V 1/10V 1/35V 1/35V 1 2 3 4 5 6 7 8 9 10 11 ICX075 (BOTTOM VIEW) 0.01 HC04 HC04 1/20V 100 22 21 20 19 18 17 16 15 14 13 12 HIG2 HIG1 HIS VOG POG 1 2 N.C. 3 4 5 6 7 N.C. 8 9 10 56k HHG2 HHG1 H2 H1 SUB VL RG 15V V3 V2 V1 VHOLD GND CGG1 VOUT1 CGG2 VOUT2 VDD Drive Circuit 3.3/20V 2SK523 1/10V 2SK523 27k 0.1 0.1 0.01 3.9k 100 3.9k 100 0.1 270k 39 2SC2785 x 3 1M 15k 47k 15k [B] CCD OUT2 [A] CCD OUT1 ICX075AK ICX075AK Spectral Sensitivity Characteristics (Includes lens characteristics, excludes light source characteristics) 1 0.9 R 0.8 B G Relative Response 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 500 600 700 Wave Length [nm] Sensor Readout Clock Timing Chart 1/50s interlaced mode HD V1 Odd Field V2 V3 43.25 2.58 2.58 3.25 V1 Even Field V2 V3 Unit : s - 16 - CCD OUT2 SG CCD OUT1 V3 V2 V1 HD BLK VD FLD 246 8 24 6 8 13 57 1 35 7 581 1/50s interlaced mode 625 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 582 - 17 - 581 335 1 35 7 1 3 57 2 4 6 8 2 4 6 8 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 582 Drive Timing Chart (Vertical Sync) ICX075AK 340 - 18 - SUB SHD SHP RG H2 H1 HHG2 HHG1 VHOLD VOG V3 V2 V1 CLK BLK HD Drive Timing Chart (Horizontal Sync) 1/50s interlaced mode ICX075AK ICX075AK Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them. a) Operate in clean environments (around class 1000 is appropriate). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Do not expose to strong light (sun rays) for long periods, color filters will be discolored. For continuous using under cruel condition exceeding the normal using condition, consult our company. 5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to too much mechanical shocks. - 19 - - 20 - 7.55 1 V 22 Cer-DIP TIN PLATING 42 ALLOY 2.6g PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT 0.3 M 14.6 18.0 0.4 H 9.0 0.69 (For the 1st. pin only) 1.27 PACKAGE STRUCTURE B 0.7 3 0.55 3 11.55 3 11 12 A 0.46 0.3 B' C 1 11 17.6 22 12 2-R0.7 9. The notches on the bottom must not be used for reference of fixing. 8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5. 7. The tilt of the effective image area relative to the bottom "C" is less than 60m. 6. The height from the bottom "C" to the effective image area is 1.41 0.15mm. 5. The rotation angle of the effective image area relative to H and V is 1. 4. The center of the effective image area, relative to "B" and "B'" is (H, V) = (9.0, 7.55) 0.15mm. 3. The bottom "C" of the package is the height reference. 2. The two points "B" of the package are the horizontal reference. The point "B'" of the package is the vertical reference. 1. "A" is the center of the effective image area. 22pin DIP (600mil) 15.1 0.3 0.7 Unit: mm 1.27 15.24 3.4 0.3 4.0 0.3 0 to 9 0.25 Package Outline ICX075AK