Description
The ICX075AK is a 1/2-inch optical interline CCD
solid-state image sensor with a square pixel array
which supports VGA format. Progressive scan
allows all pixels signals to be output independently
within approximately 1/60 second. This chip
features an electronic shutter with variable charge-
storage time which makes it possible to realize full-
frame still image without a mechanical shutter. High
resolution and high color reproductivity are achieved
through the use of R, G, B primary color mosaic
filters.
Further, high sensitivity and low dark current are
achieved through the adoption of HAD (Hole-
Accumulation Diode) sensors.
This chip is suitable for image input and
processing applications.
Features
•Progressive scan allows individual readout of the
image signals from all pixels.
•High vertical resolusion (580TV-lines) still picture
without a mechanical shutter.
•Square pixel unit cell
•VGA format-compatible
•R, G, B primary color mosaic filters on chip
•High resolution, high color reproductivity, high sensitivity, low dark current
•Continuous variable-speed shutter
•Low smear
•Excellent antiblooming characteristics
•Reset gate: 5V drive (bias: no adjustment)
Device Structure
•Optical size: 1/2-inch format
•Number of effective pixels: 782 (H) ×582 (V) approx. 460K pixels
•Total number of pixels: 823 (H) ×592 (V) approx. 490K pixels
•Interline CCD image sensor
•Chip size: 8.10mm (H) ×6.33mm (V)
•Unit cell size: 8.3µm (H) ×8.3µm (V)
•Optical black: Horizontal (H) direction: Front 3 pixels, rear 38 pixels
Vertical (V) direction: Front 8 pixels, rear 2 pixels
•Number of dummy bits: Horizontal 19
Vertical 5
•Substrate material: Silicon
– 1 –
ICX075AK
E95706D72-PS
1/2-inch Progressive Scan CCD Image Sensor with Square Pixel for Color Video Cameras
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
22 pin DIP (Cer-DIP)
AAAAA
A
AAA
A
A
AAA
A
AAAAA
Pin 1
V
338
2
8
Pin 12 H
Optical black position
(Top View)
– 2 –
ICX075AK
Horizontal Register 1
Horizontal Register 2
1
2
3
4
5
6
7
8
9
10
11
12 13 14
Note)
Note) : Photo sensor
V
OUT2
GND
C
GG2
C
GG1
VHOLDφ
Vφ
1
Vφ
2
HIGφ
1
V
DD
VOGφ
SUB
V
L
RG
POGφ
Hφ
1
Hφ
2
Vertical Register
15 16 17 18 19 20 21 22
HHGφ
1
HHGφ
2
HIG
2
V
OUT1
Vφ
3
HIS
G
R
G
R
G
R
B
G
B
G
B
G
G
R
G
R
G
R
B
G
B
G
B
G
Block Diagram and Pin Configuration
(Top View)
Pin
No. Symbol Description Description
Pin
No. Symbol
Pin Description
∗1DC bias is applied within the CCD, so that this pin should be grounded externally through a capacitance of
1µF or more.
∗2Regarding the test pins: apply the same voltage as the supply voltage to HIS, and ground HIGφ1, HIG2, and
POGφ.
Test pin ∗2
Test pin ∗2
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register final
stage accumulation clock
GND
Output amplifier 1 gate ∗1
decoupling capacitor
Signal output 1
Output amplifier 2 gate ∗1
decoupling capacitor
Signal output 2
1
2
3
4
5
6
7
8
9
10
11
HIGφ1
HIS
Vφ3
Vφ2
Vφ1
VHOLD
φ
GND
CGG1
VOUT1
CGG2
VOUT2
12
13
14
15
16
17
18
19
20
21
22
VDD
RG
VL
SUB
Hφ1
Hφ2
HHGφ1
HHGφ2
HIG2
POGφ
VOGφ
Supply voltage
Reset gate clock
Protective transistor bias
Substrate (overflow drain)
Horizontal register transfer clock
Horizontal register transfer clock
Inter-horizontal register
transfer clock
Inter-horizontal register
transfer clock
Test pin ∗2
Test pin ∗2
Vertical register final stage
transfer clock
– 3 –
ICX075AK
Item
–0.3 to +55
–0.3 to +18
–55 to +10
–15 to +20
to +10
to +15
to +17
–17 to +17
–10 to +15
–55 to +10
–65 to +0.3
–0.3 to +27.5
–0.3 to +22.5
–0.3 to +17.5
–30 to +80
–10 to +60
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
∗1
Ratings Unit Remarks
Absolute Maximum Ratings
∗1+27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
Substrate voltage SUB – GND
VDD, VOUT1, VOUT2, HIS, CGG1, CGG2 – GND
Supply voltage VDD, VOUT1, VOUT2, HIS, CGG1, CGG2 – SUB
Vφ1, Vφ2, Vφ3, VHOLDφ, VOGφ– GND
Clock input voltage Vφ1, Vφ2, Vφ3, VHOLDφ, VOGφ– SUB
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
Hφ1, Hφ2– VOGφ
Hφ1, Hφ2– GND
Hφ1, Hφ2– SUB
VL– SUB
Vφ2, Vφ3, VDD, VOUT1, VOUT2, HIS, HIGφ1, HIG2, POGφ– VL
RG – GND
Vφ1, CGG1, CGG2, Hφ1, Hφ2, HHGφ1, HHGφ2, VOGφ, VHOLDφ– VL
Storage temperature
Operating temperature
– 4 –
ICX075AK
∗1Indications of substrate voltage (VSUB) setting value
The setting value of the substrate voltage is indicated on the back of image sensor by a special code.
Adjust the substrate voltage (VSUB) to the indicated voltage.
VSUB code — two characters indication ↑↑
Integer portion Decimal portion
The integer portion of the code and the actual value correspond to each other as follows.
Item VDD
VSUB
VL
14.55
9.0
Indicated
voltage – 0.1
15.45
18.5
Indicated
voltage + 0.1
15.0
Indicated
voltage
∗2
V
V
V
∗1
Symbol Min. Typ. Max. Unit Remarks
Bias Conditions
DC Characteristics
Value 9 10 11 12 13 14 15 16 17 18
9ACdEfGhJK
<Example> "A5" →VSUB = 10.5V.
∗2VLsetting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.
∗3(1) Current to each pin when 18V is applied to VDD, VOUT1, VOUT2, HIS, RG, CGG1, CGG2, GND and SUB
pins, while all pins that are not tested are grounded.
(2) Current to each pin when 20V is applied sequentially to Vφ1, Vφ2and Vφ3pins, while all pins that are not
tested are grounded. However, 20V is applied to SUB pin.
(3) Current to each pin when 15V is applied sequentially to RG, Hφ1and Hφ2pins, while all pins that are not
tested are grounded. However, 15V is applied to SUB pin.
(4) Current to VLpin when 25V is applied to Vφ2, Vφ3, POGφ, HIGφ1, HIG2, VDD, VOUT1 and VOUT2 pins or
when, 15V is applied to Vφ1, VHOLDφ, VOGφ, CGG1, CGG2, Hφ1, Hφ2, HHGφ1and HHGφ2pins, while VL
pin is grounded. However, GND and SUB pins are left open.
(5) Current to GND pin when 20V is applied to the RG pin and the GND pin is grounded.
∗4Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded.
Supply voltage
Substrate voltage
adjustment range
Substrate voltage
adjustment precision
Protective transistor bias
Item
Supply current
Input current
Input current
IDD
IIN1
IIN2
10
1
10
mA
µA
µA
∗3
∗4
Symbol Min. Typ. Max. Unit Remarks
Integer portion of code
– 5 –
ICX075AK
Item
VVT
VVH02
VVH1, VVH2, VVH3
VVL1, VVL2, VVL3
VφV
I VVL1
–
VVL3 I
VVHH
VVHL
VVLH
VVLL
VφH
VHL
VφRG
V
RGLH –
V
RGLL
VRGH
VφSUB
VVHOLDH, VVOGH
VVHOLDL, VVOGL
VHHG1H, VHHG2H
VHHG1L, VHHG2L
VHHG1M, VHHG2M
14.55
–0.05
–0.2
–8.0
6.8
4.75
–0.05
4.5
VDD
+0.4
21.5
–0.05
–8.0
4.75
–8.0
–0.05
15.0
0
0
–7.5
7.5
5.0
0
5.0
VDD
+0.6
22.5
0
–7.5
5.0
–7.5
0
15.45
0.05
0.05
–7.0
8.05
0.1
0.5
0.5
0.5
0.5
5.25
0.05
5.5
0.8
VDD
+0.8
23.5
0.05
–7.0
5.25
–7.0
0.05
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
6
6
7
7
7
VVH = VVH02
VVL = (VVL01 + VVL03)/2
VφV= VVHn – VVLn (n = 1 to 3)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Input through 0.01µF
capacitance
Low-level coupling
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
Vertical final stage
accumulation clock voltage
transfer clock voltage
Inter-horizontal register
transfer clock voltage
Symbol Min. Typ. Max. Unit
Waveform
diagram
Remarks
Clock Voltage Conditions
– 6 –
ICX075AK
Clock Equivalent Circuit Constant
Item
CφV1
CφV2
CφV3
CφV12
CφV23
CφV31
CφVHOLD
CφVOG
CφHHG1
CφHHG2
CφH1
CφH2
CφHH
CφRG
CφSUB
R1, R2, R3
RGND
RφH1
RφH2
820
820
820
3300
2200
2200
19
12
19
19
68
68
47
10
400
22
15
24
24
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Ω
Ω
Ω
Ω
Capacitance between vertical transfer
clock and GND
Capacitance between vertical transfer
clocks
Capacitance between vertical final stage
accumulation clock and GND
Capacitance between vertical final stage
transfer clock and GND
Capacitance between inter-horizontal
register transfer clock and GND
Capacitance between horizontal transfer
clock and GND
Capacitance between horizontal transfer
clocks
Capacitance between reset gate clock and
GND
Capacitance between substrate clock and
GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Symbol Min. Typ. Max. Unit
Remarks
RφH1 RφH2 Hφ2
CφH1 CφH2
CφHH
Vφ1CφV12 Vφ2
Vφ3
CφV2
RGND
R3
R1R2
Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit
CφV1
Cφv31 Cφv23
Hφ1
CφV3
– 7 –
ICX075AK
Drive Clock Waveform Conditions
(1) Readout clock waveform
(2) Vertical transfer clock waveform
II II
100%
90%
10%
0%
VVT
tr twh tf
φM
0V
φM
2
Vφ1VVH1 VVH1
VVHH VVHH VVH
VVHL VVHL
VVLH VVLH
VVL1
VVL1
VVL01 VVL
VVLL VVLL
Vφ3VVH3 VVH3
VVHH VVHH VVH
VVHL VVHL
VVLH
VVLH VVL3
VVL03 VVL
VVLLVVLL
VφV1 = VVH1 – VVL01
VφV2 = VVH02 – VVL2
VφV3 = VVH3 – VVL03
VVH = VVH02
VVL = (VVL01 + VVL03)/2
Vφ2
VVLH
VVL2
VVLL
VVLH
VVL2 VVL
VVLL
VVH
VVHH
VVH02 VVHH
VVH2
VVHL
VVH2
VVHL
– 8 –
ICX075AK
(3) Horizontal transfer clock waveform
tr twh tf
90%
10%
twl
VφH
VHL
(4) Reset gate clock waveform
Point A
twl
VφRG
VRGH
VRGL + 0.5V
VRGL
VRGLH
RG waveform
VRGLL
Hφ1 waveform
2.5V
twhtr tf
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and
VRGLL.VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL
(5) Substrate clock waveform
90%
100%
10%
0%
VSUB tr twh tf
φM
φM
2
VφSUB
– 9 –
ICX075AK
(6) Vertical final stage accumulation clock waveform · Vertical final stage transfer clock waveform
(7) Inter-horizontal register transfer clock waveform
tftr
90%
10% VVHOLDL, VVOGL
VVHOLDH, VVOGH
VHOLDφ, VOGφ
tf2
tr
10%
VHHG1L, VHHG2L
VHHG1M, VHHG2M
90%
tf1
VHHG1H, VHHG2H
90%
10%
90%
10%
HHGφ1, HHGφ2
– 10 –
ICX075AK
Readout clock
Vertical transfer
clock
During imaging
During parallel-
serial conversion
Reset gate clock
Substrate clock
Vertical final stage
accumulation/
transfer clock
Inter-horizontal
register transfer
clock
VT
Vφ1,
Vφ2, Vφ3
Hφ1
Hφ2
Hφ1
Hφ2
φRG
φSUB
VHOLDφ
VOGφ
HHGφ1
HHGφ2
2.3
18
21
11
1.4
2.5
23
26
14
1.6
21
18
26
23
49
0.4
10
10
0.01
0.01
2
20
20
20
20
17.5
15
0.4
15
0.1
10
10
0.01
0.01
2
20
20
20
20
400
17.5
15
0.4
µs
ns
ns
µs
ns
µs
ns
ns
ns
ns
During
readout
∗1
∗2
During drain
charge
Horizontal transfer clock
Item Symbol twh twl tr tf, tf1, tf2
Min. Typ.
Max.
Min. Typ.
Max.
Min. Typ.
Max.
Min. Typ.
Max.
Unit Remarks
Horizontal transfer clock Hφ1, Hφ224 29 ns ∗3
Item Symbol two
Min. Typ. Max. Unit Remarks
∗1When vertical transfer clock driver CXD1268M is used.
∗2tf ≥tr – 2ns, and the cross-point voltage (VCR) for the Hφ1rising side of the Hφ1and Hφ2waveforms must be
at least 2.5V.
∗3The overlap period for twh and twl of horizontal transfer clocks Hφ1and Hφ2is two.
Clock Switching Characteristics
– 11 –
ICX075AK
Image Sensor Characteristics (Ta = 25°C)
Zone Definition of Video Signal Shading
2
2
582 (V)
66 782 (H)
Ignored region
Zone 0
Effective pixel region
Note) All the characteristic data of this image sensor was yielded when the sensor was operated in the 1/50s
interlaced mode.
Measurement System
CCD
C.D.S S/H
AMP
CCD signal output 1
Signal output 1
[∗A] [∗C]
C.D.S S/H
AMP
CCD signal output 2
Signal output 2
[∗B] [∗D]
Note) Adjust the amplifier gain so that the gain between [∗A] and [∗C], and between [∗B] and [∗D] equals 1.
Item
G sensitivity
Sensitivity comparison
Saturation signal
Smear
Video signal shading
Uniformity between video
signal channels
Dark signal
Dark signal shading
Lag
Sg
Rr
Rb
Vsat
Sm
SHg
∆Srg
∆Sbg
Vdt
∆Vdt
Lag
170
0.3
0.4
375
250
0.45
0.55
0.003
0.6
0.7
0.007
25
8
8
2
1
0.5
mV
mV
%
%
%
%
mV
mV
%
1
1
1
2
3
4
5
5
6
7
8
Ta = 60°C
Zone 0
Ta = 60°C
Ta = 60°C
Symbol Min. Typ. Max. Unit Measurement method Remarks
R
B
– 12 –
ICX075AK
Readout modes
The output methods for the two readout modes indicated below are now described.
Odd field
Even field
1/50s interlaced 1/25s non-interlaced
1. 1/50s interlaced
In this mode, the signals are output in a 1/50s period using the two output pins (VOUT1, VOUT2).
The signals from two adjacent horizontal lines are simultaneously output from the respective output pins.
The lines output from the output pins are changed over with each field. The VOUT1 signal after it has passed
through the CDS and other external circuits or the signal produced by adding the VOUT1 and VOUT2 signals
accommodate interlaced scanning. In the Odd field, R signal and Gr signal are output from VOUT1 pin and
Gb signal and B signal are output from VOUT2 pin. In the Even field, Gb signal and B signal are output from
VOUT1 pin and R signal and Gr signal are output from VOUT2 pin.
2. 1/25s non-interlaced
In this mode, the signals are output in a 1/25s period using only one output pin (VOUT1).
Unlike the 1/50s interlaced mode described above, the external circuit can be simplified. The imaging
characteristics also differ from those of the other modes. R signal and Gr signal lines and Gb signal and B
signal lines are output sequentially from VOUT1 pin only.
VOUT1
VOUT2
B
RGr
Gb
VOUT1
VOUT2
B
RGr
Gb VOUT1
VOUT2
B
RGr
Gb
Composition of color coding and output signal
The color filters of this image sensor are arranged in the layout shown in the figure below.
Gr and Gb denote the G signals on the same line as the R signal and the B signal,
respectively.
Gb BGbB
RGrRGr
Gb BGbB
RGrRGr
– 13 –
ICX075AK
Image Sensor Characteristics Measurement Method
Measurement conditions
1) In the following measurements, the substrate voltage is set to the value indicated on the device, and the
device drive conditions are at the typical values of the bias and clock voltage conditions.
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black (OB) level is used as the reference for the signal output, which is taken as the value of the Gr/Gb
signal output or R/B signal output of signal output 1 in the measurement system.
3) In the following measurements, this image sensor is operated in 1/50s interlaced mode.
Definition of standard imaging conditions
1) Standard imaging condition I:
Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern
for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter
and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the
standard sensitivity testing luminous intensity.
2) Standard imaging condition II :
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.
1. G sensitivity, sensitivity comparison
Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of
1/100s, measure the signal outputs (VGr, VGb, VRand VB) at the center of each Gr, Gb, R and B channel
screens, and substitute the values into the following formula.
VG= (VGr + VGb)/2
Sg = VG×[mV]
Rr = VR/VG
Rb = VB/VG
2. Saturation signal
Set to standard imaging condition II. After adjusting the luminous intensity to 20 times the intensity with the
average value of the Gr signal output, 120mV, measure the minimum values of the Gr, Gb, R and B signal
outputs.
3. Smear
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, first adjust the average value of
the Gr signal output to 120mV. Measure the average values of the Gr signal output, Gb signal output, R
signal output and B signal output (Gra, Gba, Ra and Ba), and then adjust the luminous intensity to 500 times
the intensity with average value of the Gr signal output, 120mV. After the readout clock is stopped and the
charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value
(Sm1 [mV]) of signal output 1 and the maximum value (Sm2 [mV]) of signal output 2, and substitute the
values into the following formula.
Sm = ÷ ×××100 [%] (1/10V method conversion value)
100
50
1
500
Gra + Gba + Ra + Ba
41
10
Sm1 + Sm2
2
– 14 –
ICX075AK
4. Video signal shading
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so
that the average value of the Gr signal output is 120mV. Then measure the maximum (Grmax [mV]) and
minimum (Grmin [mV]) values of the Gr signal output and substitute the values into the following formula.
SHg = (Grmax – Grmin)/120 ×100 [%]
5. Uniformity between video signal channels
After measuring 4, measure the maximum (Rmax [mV]) and minimum (Rmin [mV]) values of R signal, and
the maximum (Bmax [mV]) and minimum (Bmin [mV]) values of B signal. Substitute the values into the
following formula.
∆Srg = (Rmax – Rmin)/120 ×100 [%]
∆Sbg = (Bmax – Bmin)/120 ×100 [%]
6. Dark signal
Measure the average value of the signal output 1 (Vdt [mV]) with the device ambient temperature 60°C and
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
7. Dark signal shading
After measuring 6, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark
signal output 1 and substitute the values into the following formula.
∆Vdt = Vdmax – Vdmin [mV]
8. Lag
Adjust the Gr signal output value generated by strobe light to 120mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following
formula.
Lag = (Vlag/120) ×100 [%]
Vlag (lag)Gr signal output 120mV
Light
FLD
SG
Strobe light
timing
Output
– 15 –
ICX075AK
XHφ2
XHφ1
RG
15V
–7.5V
5V
XV2
XSG
XV1
XV3
XSUB
XVHOLD
XHHG1-1
XHHG1-2
XHHG2-1
XHHG2-2
XVOG
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CXD1268M
CXD1250
1
2
3
4
5
6
7
8
9
10
20
19
18
16
15
14
13
12
11
17
22/16V
22
/16V
N.C.
N.C.
N.C.
22/20V
10/20V
1/35V
22/16V
22/10V
22/10V
3.3/16V
CCD OUT1
CCD OUT2
[∗A]
1234567891011
22 21 20 191817 16 15 1413 12
ICX075
(BOTTOM VIEW)
HIGφ1
HIS
Vφ
3
Vφ
2
GND
C
GG1
V
OUT1
C
GG2
V
OUT2
VOGφ
POGφ
HIG
2
HHGφ
2
HHGφ
1
Hφ
2
Hφ
1
SUB
V
L
RG
V
DD
1/10V
1/10V
2SK523 100
3.9k
100
3.9k
2SK523
3.3/20V 0.01
1M
100
1/20V
15k
47k
15k
39
0.1
56k 0.1
1/35V
1/35V 27k
270k
2SC2785 × 3
100k
HC04
HC04
0.01
Vφ
1
VHOLDφ
0.1
[∗B]
Drive Circuit
– 16 –
ICX075AK
Spectral Sensitivity Characteristics
(Includes lens characteristics, excludes light source characteristics)
Wave Length [nm]
Relative Response
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
400 500 600 700
R
G
B
Sensor Readout Clock Timing Chart 1/50s interlaced mode
HD
V1
V3
V2
Odd Field
V1
V3
V2
Even Field
43.25 2.58 2.58 3.25
Unit : µs
– 17 –
ICX075AK
2468
1357
582 581
1357
2468
581 582
340
335
330
329
328
327
326
325
324
323
322
321
320
319
318
317
316
315
314
313
312
311
310
309
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
625
FLD
VD
BLK
HD
V1
V2
V3
CCD
OUT1
CCD
OUT2
SG
357
468
2468
1357
1
2
Drive Timing Chart (Vertical Sync) 1/50s interlaced mode
– 18 –
ICX075AK
HD
BLK
V1
V2
V3
VOG
VHOLD
HHG1
HHG2
H1
H2
RG
SHP
SHD
SUB
CLK
Drive Timing Chart (Horizontal Sync) 1/50s interlaced mode
– 19 –
ICX075AK
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Operate in clean environments (around class 1000 is appropriate).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces.
Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity
ionized air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Do not expose to strong light (sun rays) for long periods, color filters will be discolored. For continuous
using under cruel condition exceeding the normal using condition, consult our company.
5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage
in such conditions.
6) CCD image sensors are precise optical equipment that should not be subject to too much mechanical
shocks.
– 20 –
ICX075AK
Package Outline Unit: mm
PACKAGE STRUCTURE
0.7
3
11.55
3
0.55
7.55
VH
18.0 ± 0.4
15.1 ± 0.3
15.24
9.0
22 12
111
0° to 9°
12 22
2-R0.7
1
11
0.25
17.6
3.4 ± 0.3
4.0 ± 0.3
1.27
0.46
0.30.69
1.27
14.6 3
0.7
0.3
(For the 1st. pin only)
22pin DIP (600mil)
1. “A” is the center of the effective image area.
2. The two points “B” of the package are the horizontal reference.
The point “B'” of the package is the vertical reference.
3. The bottom “C” of the package is the height reference.
4. The center of the effective image area, relative to “B” and “B'” is
(H, V) = (9.0, 7.55) ± 0.15mm.
5. The rotation angle of the effective image area relative to H and V is ± 1°.
6. The height from the bottom “C” to the effective image area is 1.41 ± 0.15mm.
7. The tilt of the effective image area relative to the bottom “C” is less than 60µm.
8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5.
9. The notches on the bottom must not be used for reference of fixing.
C
A
B
B'
M
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
Cer-DIP
TIN PLATING
42 ALLOY
2.6g
