Semiconductor Components Industries, LLC, 2001
March, 2001 – Rev. 0 1Publication Order Number:
MMBT4126LT1/D
MMBT4126LT1
Preferred Device
General Purpose Transistor
PNP Silicon
•Moisture Sensitivity Level: 1
•ESD Rating – Human Body Model: >4000 V
ESD Rating – Machine Model: >400 V
MAXIMUM RATINGS
Rating Symbol Value Unit
Collector–Emitter Voltage VCEO –25 Vdc
Collector–Base Voltage VCBO –25 Vdc
Emitter–Base Voltage VEBO –4 Vdc
Collector Current–Continuous IC–200 mAdc
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation FR–5 Board
(Note 1.)
TA = 25°C
Derate above 25°C
PD225
1.8
mW
mW/°C
Thermal Resistance,
Junction to Ambient (Note 1.) RJA 556 °C/W
Total Device Dissipation
Alumina Substrate, (Note 2.)
TA = 25°C
Derate above 25°C
PD300
2.4
mW
mW/°C
Thermal Resistance,
Junction to Ambient (Note 2.) RJA 417 °C/W
Junction and Storage
Temperature Range TJ, Tstg –55 to
+150 °C
1. FR–5 = 1.0 0.75 0.062 in.
2. Alumina = 0.4 0.3 0.024 in. 99.5% alumina.
Device Package Shipping
ORDERING INFORMATION
SOT–23
CASE 318
STYLE 6
http://onsemi.com
MMBT4126LT1 SOT–23 3000/Tape & Reel
MARKING DIAGRAM
C3 M
C3 = Device Code
M = Date Code
12
3
Preferred devices are recommended choices for future use
and best overall value.
COLLECTOR
3
1
BASE
2
EMITTER
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ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Max Unit
OFF CHARACTERISTICS
Collector–Emitter Breakdown Voltage (Note 3.)
(IC = –1.0 mAdc, IB = 0) V(BR)CEO –25 – Vdc
Collector–Base Breakdown Voltage
(IC = –10 Adc, IE = 0) V(BR)CBO –25 – Vdc
Emitter–Base Breakdown Voltage
(IE = –10 Adc, IC = 0) V(BR)EBO –4 – Vdc
Collector Cutoff Current
(VCE = –30 Vdc, VEB = –3.0 Vdc) ICEX – –50 nAdc
ON CHARACTERISTICS (Note 3.)
DC Current Gain
(IC = –2.0 mAdc, VCE = –1.0 Vdc)
(IC = –50 mAdc, VCE = –1.0 Vdc)
HFE 120
60 300
–
–
Collector–Emitter Saturation Voltage
(IC = –50 mAdc, IB = –5.0 mAdc) VCE(sat) – –0.4 Vdc
Base–Emitter Saturation Voltage
(IC = –50 mAdc, IB = –5.0 mAdc) VBE(sat) – –0.95 Vdc
SMALL–SIGNAL CHARACTERISTICS
Current–Gain – Bandwidth Product
(IC = –10 mAdc, VCE = –20 Vdc, f = 100 MHz) fT250 – MHz
Output Capacitance
(VCB = –5.0 Vdc, IE = 0, f = 1.0 MHz) Cobo – 4.5 pF
Input Capacitance
(VEB = –0.5 Vdc, IC = 0, f = 1.0 MHz) Cibo – 10 pF
Small–Signal Current Gain
(IC = –2.0 mAdc, VCE = –10 Vdc, f = 1.0 kHz)
(IC = 10 mAdc, VCE = 20 Vdc, f = 100 MHz)
hfe 120
2.5 480
–
–
Noise Figure
(IC = –100 Adc, VCE = –5.0 Vdc, RS = 1.0 kΩ, f = 1.0 kHz) NF – 4.0 dB
3. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.
TYPICAL TRANSIENT CHARACTERISTICS
Figure 1. Capacitance
REVERSE BIAS (VOLTS)
2.0
3.0
5.0
7.0
10
1.0
0.1
Figure 2. Charge Data
IC, COLLECTOR CURRENT (mA)
5000
1.0
VCC = 40 V
IC/IB = 10
Q, CHARGE (pC)
3000
2000
1000
500
300
200
700
100
50
70
2.0 3.0 5.0 7.0 10 20 30 50 70 100 200
CAPACITANCE (pF)
1.0 2.0 3.0 5.0 7.0 10 20 30 40
0.2 0.3 0.5 0.7
QT
QA
Cibo
Cobo
TJ = 25°C
TJ = 125°C
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TYPICAL AUDIO SMALL–SIGNAL CHARACTERISTICS
NOISE FIGURE VARIATIONS
(VCE = –5.0 Vdc, TA = 25°C, Bandwidth = 1.0 Hz)
Figure 3.
f, FREQUENCY (kHz)
2.0
3.0
4.0
5.0
1.0
0.1
Figure 4.
Rg, SOURCE RESISTANCE (k OHMS)
0
NF, NOISE FIGURE (dB)
1.0 2.0 4.0 10 20 40
0.2 0.4
0100
4
6
8
10
12
2
0.1 1.0 2.0 4.0 10 20 40
0.2 0.4 100
NF, NOISE FIGURE (dB)
f = 1.0 kHz IC = 1.0 mA
IC = 0.5 mA
IC = 50 A
IC = 100 A
SOURCE RESISTANCE = 200
IC = 1.0 mA
SOURCE RESISTANCE = 200
IC = 0.5 mA
SOURCE RESISTANCE = 2.0 k
IC = 100 A
SOURCE RESISTANCE = 2.0 k
IC = 50 A
h PARAMETERS
(VCE = –10 Vdc, f = 1.0 kHz, TA = 25°C)
Figure 5. Current Gain
IC, COLLECTOR CURRENT (mA)
70
100
200
300
50
Figure 6. Output Admittance
IC, COLLECTOR CURRENT (mA)
h , DC CURRENT GAIN
h , OUTPUT ADMITTANCE ( mhos)
Figure 7. Input Impedance
IC, COLLECTOR CURRENT (mA)
Figure 8. Voltage Feedback Ratio
IC, COLLECTOR CURRENT (mA)
30
100
50
10
20
2.0
3.0
5.0
7.0
10
1.0
0.1 0.2 1.0 2.0 5.0
0.5 10
0.3 0.5 3.0
0.7
2.0
5.0
10
20
1.0
0.2
0.5
oe
h , VOLTAGE FEEDBACK RATIO (X 10 )
re
h , INPUT IMPEDANCE (k OHMS)
ie
0.1 0.2 1.0 2.0 5.0 10
0.3 0.5 3.0
0.1 0.2 1.0 2.0 5.0 10
0.3 0.5 3.0
7
5
0.1 0.2 1.0 2.0 5.0 10
0.3 0.5 3.0
fe
-4
70
30
0.7 7.0
0.7 7.0
7.0
3.0
0.7
0.3
0.7 7.0
0.7 7.0
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TYPICAL STATIC CHARACTERISTICS
Figure 9. DC Current Gain
IC, COLLECTOR CURRENT (mA)
0.3
0.5
0.7
1.0
2.0
0.2
0.1
h , DC CURRENT GAIN (NORMALIZED)
0.5 2.0 3.0 10 50 70
0.2 0.3
0.1 100
1.00.7 200
30205.0 7.0
FE
VCE = 1.0 V
TJ = +125°C
+25°C
-55°C
Figure 10. Collector Saturation Region
IB, BASE CURRENT (mA)
0.4
0.6
0.8
1.0
0.2
0.1
V , COLLECTOR EMITTER VOLTAGE (VOLTS)
0.5 2.0 3.0 100.2 0.3
01.00.7 5.0 7.0
CE
IC = 1.0 mA
TJ = 25°C
0.070.050.030.020.01
10 mA 30 mA 100 mA
Figure 11. “ON” Voltages
IC, COLLECTOR CURRENT (mA)
0.4
0.6
0.8
1.0
0.2
Figure 12. Temperature Coefficients
IC, COLLECTOR CURRENT (mA)
V, VOLTAGE (VOLTS)
1.0 2.0 5.0 10 20 50
0100
-0.5
0
0.5
1.0
0 60 80 120 140 160 180
20 40 100 200
-1.0
-1.5
-2.0
200
TJ = 25°C VBE(sat) @ IC/IB = 10
VCE(sat) @ IC/IB = 10
VBE @ VCE = 1.0 V
+25°C TO +125°C
-55°C TO +25°C
+25°C TO +125°C
-55°C TO +25°C
VC FOR VCE(sat)
VB FOR VBE(sat)
, TEMPERATURE COEFFICIENTS (mV/ C)°
V
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INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
SOT–23
mm
inches
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the
drain pad size. This can vary from the minimum pad size
for soldering to a pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature of the die, RθJA, the thermal resistance from
the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data
sheet for the SOT–23 package, PD can be calculated as
follows:
PD = TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 225 milliwatts.
PD = 150°C – 25°C
556°C/W = 225 milliwatts
The 556°C/W f or t he SOT–23 p ackage a ssumes t he us e of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 225 milliwatts.
There are other alternatives to achieving higher power
dissipation from the SOT–23 package. Another alternative
would be to use a ceramic substrate or an aluminum core
board such as Thermal Clad. Using a board material such
as Thermal Clad, an aluminum core board, the power
dissipation can be doubled using the same footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
•Always preheat the device.
•The delta temperature between the preheat and
soldering should be 100°C or less.*
•When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
•The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
•When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
•After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
•Mechanical stress or shock should not be applied
during cooling.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
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PACKAGE DIMENSIONS
SOT–23
TO–236AB
CASE 318–09
ISSUE AF
DIM
A
MIN MAX MIN MAX
MILLIMETERS
0.1102 0.1197 2.80 3.04
INCHES
B0.0472 0.0551 1.20 1.40
C0.0385 0.0498 0.99 1.26
D0.0140 0.0200 0.36 0.50
G0.0670 0.0826 1.70 2.10
H0.0040 0.0098 0.10 0.25
J0.0034 0.0070 0.085 0.177
K0.0180 0.0236 0.45 0.60
L0.0350 0.0401 0.89 1.02
S0.0830 0.0984 2.10 2.50
V0.0177 0.0236 0.45 0.60
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIUMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
1
3
2
AL
BS
VG
DH
C
KJ
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
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Notes
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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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MMBT4126LT1/D
Thermal Clad is a registered trademark of the Bergquist Company
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