MC10EP139DWR2 - ON Semiconductor - Datasheet.Directory

April, 2012 − Rev. 12

1Publication Order Number:

MC10EP139/D

MC10EP139, MC100EP139

3.3V / 5V ECL ÷2/4, ÷4/5/6

Clock Generation Chip

Description

The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation

chip designed explicitly for low skew clock generation applications. The

internal dividers are synchronous to each other, therefore, the common

output edges are all precisely aligned.

The common enable (EN) is synchronous so that the internal dividers

will only be enabled/disabled when the internal clock is already in the

LOW state. This avoids any chance of generating a runt clock pulse on

the internal clock when the device is enabled/disabled as can happen with

an asynchronous control. The internal enable flip−flop is clocked on the

falling edge of the input clock, therefore, all associated specification

limits are referenced to the negative edge of the clock input.

Upon start−up, the internal flip−flops will attain a random state;

therefore the master reset (MR) input may require assertion to ensure

system synchronization. Internal divider design ensures synchronization

between the ÷2/4 and the ÷4/5/6 outputs within a device. All VCC and

VEE pins must be externally connected to power supply to guarantee

proper operation.

The VBB Pin, an internally generated voltage supply, is available to

this device only. For single−ended input conditions, the unused

differential input is connected to VBB as a switching reference voltage.

VBB may also rebias AC coupled inputs. When used, decouple VBB and

VCC via a 0.01 mF capacitor and limit current sourcing or sinking to

0.5 mA. When not used, VBB should be left open.

The 100 Series contains temperature compensation.

Features

•Maximum Frequency > 1.0 GHz Typical

•50 ps Output−to−Output Skew

•PECL Mode Operating Range: VCC = 3.0 V to 5.5 V

with VEE = 0 V

•NECL Mode Operating Range: VCC = 0 V

with VEE = −3.0 V to −5.5 V

•Open Input Default State

•Safety Clamp on Inputs

•Synchronous Enable/Disable

•Master Reset for Synchronization of Multiple Chips

•VBB Output

•Pb−Free Packages are Available

MARKING

DIAGRAMS*

HEP = MC10EP

KEP = MC100EP

XXX = 10 or 100

A = Assembly Loca-

tion

L,WL = Wafer Lot

Y, YY = Year

W, WW = Work Week

G or G= Pb−Free Package

*For additional marking information, refer to

Application Note AND8002/D.

TSSOP−20

DT SUFFIX

CASE 948E

SOIC−20

DW SUFFIX

CASE 751D

http://onsemi.com

See detailed ordering and shipping information in the

package dimensions section on page 11 of this data sheet.

ORDERING INFORMATION

MCXXXEP139

AWLYYWWG

XXXX

EP139

ALYWG

QFN−20

MN SUFFIX

CASE 485E

HEP or KEP

139

ALYWG

(Note: Microdot may be in either location)

MC10EP139, MC100EP139

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CLK

Figure 1. 20−Lead Pinout (Top View)

CLK

VCC

VEE

VCC

VBB

Warning: All VCC and VEE pins must be externally connected to

a Power Supply to guarantee proper operation.

DIVSELb0

DIVSELb1

DIVSELa

VCC

MC10/100EP139

Table 1. PIN DESCRIPTION

PIN FUNCTION

CLK*, CLK*ECL Differential Clock Inputs

EN* ECL Sync Enable

MR* ECL Master Reset

VBB ECL Reference Output

Q0, Q1, Q0, Q1 ECL Differential B2/4 Outputs

Q2, Q3, Q2, Q3 ECL Differential B4/5/6 Outputs

DIVSELa* ECL Frequency Select Input B2/4

DIVSELb0* ECL Frequency Select Input B4/5/6

DIVSELb1* ECL Frequency Select Input B4/5/6

VCC ECL Positive Supply

VEE ECL Negative Supply

EP Exposed Pad

*Pins will default low when left open.

678910

20 19 18 17 16

Figure 2. QFN−20 Pinout (Top View)

VCC

VEE

CLK

DIVSELb0

VBB

VCC

DIVSELb1

DIVSELa

Exposed Pad

MC10/100EP139

Warning: All VCC and VEE pins must be externally connected to a Power Supply to

guarantee proper operation.

The Exposed Pad (EP) on package bottom must be attached to a heat−sinking

conduit. The Exposed Pad may only be electrically connected to VEE.

MC10EP139, MC100EP139

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CLK

DIVSELb1

÷2/4

÷4/5/6

Figure 3. Logic Diagram

DIVSELa

DIVSELb0

VEE

Table 2. FUNCTION TABLES

CLK EN MR Function

Divide

Hold Q0:3

Reset Q0:3

Z = Low−to−High Transition

ZZ = High−to−Low Transition

DIVSELa Q0:1 Outputs

Divide by 2

Divide by 4

DIVSELb0 DIVSELb1 Q2:3 Outputs

Divide by 4

Divide by 6

Divide by 5

CLK

Q (÷2)

Q (÷4)

Q (÷5)

Figure 4. CLK and OUTPUT Timing Diagram

Q (÷6)

Figure 5. Timing Diagram

CLK

RESET

Q (÷n)

tRR

MC10EP139, MC100EP139

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Table 3. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor 75 kW

Internal Input Pullup Resistor N/A

ESD Protection Human Body Model

Machine Model

Charged Device Model

> 2 kV

> 100 V

> 2 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg

SOIC−20

TSSOP−20

QFN−20

Level 1

N/A

Level 3

Level 1

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 758 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Table 4. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VCC PECL Mode Power Supply VEE = 0 V 6 V

VEE NECL Mode Power Supply VCC = 0 V −6 V

VIPECL Mode Input Voltage

NECL Mode Input Voltage

VEE = 0 V

VCC = 0 V

VI v VCC

VI w VEE

−6

Iout Output Current Continuous

Surge

100

IBB VBB Sink/Source ± 0.5 mA

TAOperating Temperature Range −40 to +85 °C

Tstg Storage Temperature Range −65 to +150 °C

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

TSSOP−20

140

100

°C/W

qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−20 23 to 41 °C/W

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

SOIC−20

°C/W

qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−20 33 to 35 °C/W

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

QFN−20

°C/W

qJC Thermal Resistance (Junction−to−Case) Standard Board QFN−20 18 °C/W

Tsol Wave Solder Pb

Pb−Free

<2 to 3 sec @ 248°C

<2 to 3 sec @ 260°C

265

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

MC10EP139, MC100EP139

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Table 5. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2)

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 65 82 105 65 83 105 65 84 105 mA

VOH Output HIGH Voltage (Note 3) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV

VOL Output LOW Voltage (Note 3) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV

VIH Input HIGH Voltage (Single−Ended) 2090 2415 2155 2480 2215 2540 mV

VIL Input LOW Voltage (Single−Ended) 1365 1690 1460 1755 1490 1815 mV

VBB Output Voltage Reference 1790 1890 1990 1855 1955 2055 1915 2015 2115 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 4)

2.0 3.3 2.0 3.3 2.0 3.3 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.5 0.5 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.

3. All loading with 50 W to VCC − 2.0 V (see Figure 10).

4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

Table 6. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5)

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 65 82 105 65 83 105 65 84 105 mA

VOH Output HIGH Voltage (Note 6) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV

VOL Output LOW Voltage (Note 6) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV

VIH Input HIGH Voltage (Single−Ended) 3790 4115 3855 4180 3915 4240 mV

VIL Input LOW Voltage (Single−Ended) 3065 3390 3130 3455 3190 3515 mV

VBB Output Voltage Reference 3490 3590 3690 3555 3655 3755 3615 3715 3815 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 7)

2.0 5.0 2.0 5.0 2.0 5.0 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.5 0.5 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.

6. All loading with 50 W to VCC − 2.0 V (see Figure 10).

7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

MC10EP139, MC100EP139

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Table 7. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 8)

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 65 82 105 65 83 105 65 84 105 mA

VOH Output HIGH Voltage (Note 9) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV

VOL Output LOW Voltage (Note 9) −1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV

VIH Input HIGH Voltage (Single−Ended) −1210 −885 −1145 −820 −1085 −760 mV

VIL Input LOW Voltage (Single−Ended) −1935 −1610 −1870 −1545 −1810 −1485 mV

VBB Output Voltage Reference −1510 −1410 −1310 −1445 −1345 −1245 −1385 −1285 −1185 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 10)

VEE+2.0 0.0 VEE+2.0 0.0 VEE+2.0 0.0 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.5 0.5 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

8. Input and output parameters vary 1:1 with VCC.

9. All loading with 50 W to VCC − 2.0 V (see Figure 10).

10.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 11)

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 70 83 100 70 87 105 75 90 110 mA

VOH Output HIGH Voltage (Note 12) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV

VOL Output LOW Voltage (Note 12) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV

VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV

VIL Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV

VBB Output Voltage Reference 1725 1825 1925 1725 1825 1925 1725 1825 1925 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 13)

2.0 3.3 2.0 3.3 2.0 3.3 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.5 0.5 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.

12.All loading with 50 W to VCC − 2.0 V (see Figure 10).

13.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

MC10EP139, MC100EP139

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Table 9. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 14)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 70 85 100 70 90 105 75 95 110 mA

VOH Output HIGH Voltage (Note 15) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV

VOL Output LOW Voltage (Note 15) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV

VIH Input HIGH Voltage (Single−Ended) 3775 4120 3775 4120 3775 4120 mV

VIL Input LOW Voltage (Single−Ended) 3055 3375 3055 3375 3055 3375 mV

VBB Output Voltage Reference 3425 3525 3625 3425 3525 3625 3425 3525 3625 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 16)

2.0 5.0 2.0 5.0 2.0 5.0 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.5 0.5 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

14.Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.

15.All loading with 50 W to VCC − 2.0 V (see Figure 10).

16.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

Table 10. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 17)

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

IEE Power Supply Current 70 85 100 70 90 105 75 95 110 mA

VOH Output HIGH Voltage (Note 18) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV

VOL Output LOW Voltage (Note 18) −1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695 mV

VIH Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV

VIL Input LOW Voltage (Single−Ended) −1945 −1625 −1945 −1625 −1945 −1625 mV

VBB Output Voltage Reference −1575 −1475 −1375 −1575 −1475 −1375 −1575 −1475 −1375 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 19)

VEE+2.0 0.0 VEE+2.0 0.0 VEE+2.0 0.0 V

IIH Input HIGH Current 150 150 150 mA

IIL Input LOW Current 0.5 0.5 0.5 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

17.Input and output parameters vary 1:1 with VCC.

18.All loading with 50 W to VCC − 2.0 V (see Figure 10).

19.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

MC10EP139, MC100EP139

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Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 20)

−40°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit

fmax Maximum Frequency

(See Figures 6, 7, 8 and 9 Fmax/JIT-

TER)

> 1 > 1 > 1 GHz

tPLH,

tPHL

Propagation Delay CLK, Q (Diff)

MR, Q

550

700

800

900

600

700

750

850

900

1000

675

800

825

950

975

1100

tRR Reset Recovery 200 100 200 100 200 100 ps

tsSetup Time EN, CLK

DIVSEL, CLK

200

400

120

180

200

400

120

180

200

400

120

180

thHold Time CLK, EN

CLK, DIVSEL

100

200

140

100

200

140

100

200

140

tPW Minimum Pulse Width MR 550 450 550 450 550 450 ps

tSKEW Within Device Skew Q, Q

Device−to−Device Skew (Note 21)

200

100

300

200

100

300

200

100

300

tJITTER Random Clock Jitter (RMS)

(See Figures 6, 7, 8 and 9 Fmax/JIT-

TER)

0.2 < 1.0 0.2 < 1.0 0.2 < 1.5 ps

VPP Input Voltage Swing (Differential Con-

figuration)

150 800 1200 150 800 1200 150 800 1200 mV

Output Rise/Fall Times Q, Q

(20% − 80%)

110 180 250 125 190 275 150 215 300 ps

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

20.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V (see Figure 10).

21.Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays

are measured from the cross point of the inputs to the cross point of the outputs.

MC10EP139, MC100EP139

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100

200

300

400

500

600

700

800

900

0 200 400 600 800 1000 1200 1400 1600 1800 2000

Figure 6. B2, Fmax/Jitter

FREQUENCY (MHz)

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

(JITTER)

VOUTpp (mV)

JITTEROUT ps (RMS)

ÉÉ

100

200

300

400

500

600

700

800

900

0 200 400 600 800 1000 1200 1400 1600 1800 2000

Figure 7. B5, Fmax/Jitter

FREQUENCY (MHz)

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

(JITTER)

VOUTpp (mV)

JITTEROUT ps (RMS)

ÉÉ

MC10EP139, MC100EP139

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100

200

300

400

500

600

700

800

900

0 200 400 600 800 1000 1200 1400 1600 1800 2000

Figure 8. B4, Fmax/Jitter

FREQUENCY (MHz)

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

(JITTER)

VOUTpp (mV)

JITTEROUT ps (RMS)

ÉÉ

100

200

300

400

500

600

700

800

900

0 200 400 600 800 1000 1200 1400 1600 1800 2000

Figure 9. B6, Fmax/Jitter

FREQUENCY (MHz)

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

(JITTER)

VOUTpp (mV)

JITTEROUT ps (RMS)

ÉÉ

Figure 10. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices.)

Driver

Device

Receiver

Device

Q D

Zo = 50 W

50 W50 W

VTT

VTT = VCC − 2.0 V

MC10EP139, MC100EP139

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ORDERING INFORMATION

Device Package Shipping†

MC10EP139DT TSSOP−20* 75 Units / Rail

MC10EP139DTG TSSOP−20* 75 Units / Rail

MC10EP139DTR2 TSSOP−20* 2500 / Tape & Reel

MC10EP139DTR2G TSSOP−20* 2500 / Tape & Reel

MC10EP139DW SOIC−20 38 Units / Rail

MC10EP139DWG SOIC−20

(Pb−Free

38 Units / Rail

MC10EP139DWR2 SOIC−20 1000 / Tape & Reel

MC10EP139DWR2G SOIC−20

(Pb−Free

1000 / Tape & Reel

MC10EP139MNG QFN−20

(Pb−Free)

92 Units / Rail

MC10EP139MNTXG QFN−20

(Pb−Free)

3000 / Tape & Reel

MC100EP139DT TSSOP−20* 75 Units / Rail

MC100EP139DTG TSSOP−20* 75 Units / Rail

MC100EP139DTR2 TSSOP−20* 2500 / Tape & Reel

MC100EP139DTR2G TSSOP−20* 2500 / Tape & Reel

MC100EP139DW SOIC−20 38 Units / Rail

MC100EP139DWG SOIC−20

(Pb−Free

38 Units / Rail

MC100EP139DWR2 SOIC−20 1000 / Tape & Reel

MC100EP139DWR2G SOIC−20

(Pb−Free

1000 / Tape & Reel

MC100EP139MNG QFN−20

(Pb−Free)

92 Units / Rail

MC100EP139MNTXG QFN−20

(Pb−Free)

3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

Resource Reference of Application Notes

AN1405/D −ECL Clock Distribution Techniques

AN1406/D −Designing with PECL (ECL at +5.0 V)

AN1503/D −ECLinPSt I/O SPiCE Modeling Kit

AN1504/D −Metastability and the ECLinPS Family

AN1568/D −Interfacing Between LVDS and ECL

AN1672/D −The ECL Translator Guide

AND8001/D −Odd Number Counters Design

AND8002/D −Marking and Date Codes

AND8020/D −Termination of ECL Logic Devices

AND8066/D −Interfacing with ECLinPS

AND8090/D −AC Characteristics of ECL Devices

MC10EP139, MC100EP139

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PACKAGE DIMENSIONS

TSSOP−20

CASE 948E−02

ISSUE C

DIM

MIN MAX MIN MAX

INCHES

6.60 0.260

MILLIMETERS

B4.30 4.50 0.169 0.177

C1.20 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.27 0.37 0.011 0.015

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION

SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

ÍÍÍÍ

110

1120

PIN 1

IDENT

−T−

0.100 (0.004)

DGH

SECTION N−N

JJ1

−W−

SEATING

PLANE

−V−

−U−

0.10 (0.004) V S

20X REFK

L/2

U0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E

6.40 0.252

--- ---

U0.15 (0.006) T

7.06

16X

0.36 16X

1.26

0.65

DIMENSIONS: MILLIMETERS

PITCH

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

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PACKAGE DIMENSIONS

SOIC−20 WB

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D−05

ISSUE G

B20X

H10X

18X A1

SEATING

PLANE

hX 45_

0.25 M

0.25 S

DIM MIN MAX

MILLIMETERS

A2.35 2.65

A1 0.10 0.25

B0.35 0.49

C0.23 0.32

D12.65 12.95

E7.40 7.60

e1.27 BSC

H10.05 10.55

h0.25 0.75

L0.50 0.90

q0 7

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION SHALL

BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT

MAXIMUM MATERIAL CONDITION.

MC10EP139, MC100EP139

http://onsemi.com

PACKAGE DIMENSIONS

ÉÉÉ

QFN20, 4x4, 0.5P

CASE 485E−01

ISSUE B

2.88

20X

0.35

20X

0.58

4.30

0.50

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

PITCH

PKG

OUTLINE

DIM MIN MAX

MILLIMETERS

D4.00 BSC

E4.00 BSC

A0.80 1.00

b0.20 0.30

e0.50 BSC

L1 0.00 0.15

A3 0.20 REF

A1 --- 0.05

L0.35 0.45

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL

AND IS MEASURED BETWEEN 0.15 AND 0.30 MM

FROM THE TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED PAD

AS WELL AS THE TERMINALS.

D2 2.60 2.90

E2 2.60 2.90

DETAIL A

OPTIONAL CONSTRUCTIONS

ÉÉ

ÇÇ

ÉÉ

DETAIL B

MOLD CMPDEXPOSED Cu

OPTIONAL CONSTRUCTIONS

0.15 C

PIN ONE

REFERENCE

TOP VIEW

0.15 C

(A3)

0.08 C

0.10 C

CSEATING

PLANE

SIDE VIEW

DETAIL B

BOTTOM VIEW

b20X

0.10 B

0.05

CNOTE 3

DETAIL A

K0.20 REF

0.10 BAC

L20X

0.10 BAC

4.30

2.88

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arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent

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