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AS3931
3D Low Power Wakeup Receiver
www.austriamicrosystems.com/AS3931 Revision 6.2 1 - 30
Datasheet
1 General Description
The AS3931 is an ultra low power, three channel LF ASK receiver
designed to operate in various applications such as LF identifications
systems and LF tag receivers. AS3931 detects a low frequency
ASK-modulated signal by looking for a digital wakeup pattern and
generates a WAKE signal after successful pattern detection. The
device incorporates an intelligent pattern detection algorithm that
provides reliable operation in presence of strong interference. An
RSSI signal can be generated at the RSSI pin for each receiver
channel.
The product is available in 16-pin TSSOP package.
The AS3931 contains:
Antenna rotation switch
Three independent LF receiver chains
Wakeup output combining the three receiver chains
Low power 32.768kHz crystal oscillator circuit
Serial programming interface
Voltage regulator with 2.4V output, on/off switchable
Each independent LF receiver chain contains:
Input overload protection
Input attenuator
Ultra low power LF amplifier with logarithmic envelope output
Robust data detector with adaptive slicing threshold that
translates the logarithmic envelope into a digital data signal.
Error tolerant digital pattern correlator that detects a given code
sequences in the received data signal and generates a wakeup
signal.
Sophisticated power management logic that powers down the
correlator if no data is received.
2 Key Features
Programmable Serial Data Interface
Flexible carrier frequencies
Three axis wakeup pattern detection
Three axis LF field strength measurement
Antenna rotation for easy calibration
High sensitivity and high dynamic range
Wide operating frequency range
Reliable, interference resistant wakeup decoding
Highly protected differential inputs
Ultra low power consumption
Automotive qualified
16-pin TSSOP package
3 Applications
The device is ideal for LF identification systems, LF tag receivers,
three dimensional LF field strength measurement systems, and Ultra
low power wake up systems.
Transmitting
Antenna
Receiving Antennas
VCC
CBAT RP
CREG
RSSI
DATA
CLOCK
CHIP SEL
WAKE
CB
XTAL
CA
VCC
LF1N
LF1P
LF2N
LF2P
LF3N
LF3P
GND XIN
XOUT
WAKE
CS
SCL
SDA
RSSI
VREG
AS3931
Figure 1. Typical Application Diagram
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AS3931
Datasheet - Contents
Contents
1 General Description .................................................................................................................................................................. 1
2 Key Features ............................................................................................................................................................................ 1
3 Applications .............................................................................................................................................................................. 1
4 Pin Assignments ....................................................................................................................................................................... 4
4.1 Pin Descriptions ...................................................................................................................................................................................4
5 Absolute Maximum Ratings ...................................................................................................................................................... 5
6 Electrical Characteristics .......................................................................................................................................................... 6
7 Typical Operating Characteristics ............................................................................................................................................. 9
7.1 RSSI Characteristic ..............................................................................................................................................................................9
7.2 Temperature Dependence of RSSI ....................................................................................................................................................10
7.3 Supply Voltage Dependence of RSSI ................................................................................................................................................11
7.4 Frequency Dependence of RSSI .......................................................................................................................................................12
8 Detailed Description ............................................................................................................................................................... 13
8.1 Block Diagram ....................................................................................................................................................................................13
8.2 Block Description ...............................................................................................................................................................................13
8.2.1 Antenna Rotator ......................................................................................................................................................................... 13
8.2.2 Input Attenuator ......................................................................................................................................................................... 13
8.2.3 Input Shortcutting ....................................................................................................................................................................... 13
8.2.4 Input Protection Circuit .............................................................................................................................................................. 13
8.2.5 Logarithmic Envelope Amplifiers ............................................................................................................................................... 14
8.2.6 Detectors ................................................................................................................................................................................... 14
8.2.7 Digital Correlators ...................................................................................................................................................................... 14
8.2.8 Wake Generator ........................................................................................................................................................................ 14
8.2.9 Crystal Oscillator ........................................................................................................................................................................ 14
8.2.10 Regulator ................................................................................................................................................................................. 14
8.2.11 Power On Reset (POR) ........................................................................................................................................................... 14
8.3 Basic Operation ..................................................................................................................................................................................15
8.3.1 LF Transmission Protocol .......................................................................................................................................................... 15
8.3.2 Wake Up Detection .................................................................................................................................................................... 16
8.3.3 WAKE Signal Clearing ............................................................................................................................................................... 16
8.3.4 WAKE Signal After POR ............................................................................................................................................................ 16
8.3.5 RSSI Operation .......................................................................................................................................................................... 16
8.4 Serial Programming Interface Timing .................................................................................................................................................16
8.5 Input Signal Waveform Definition .......................................................................................................................................................17
9 Configuring the Product .......................................................................................................................................................... 18
9.1 Serial Programming Interface ............................................................................................................................................................18
9.2 Power On Register .............................................................................................................................................................................18
9.2.1 P0, P1, P2 (Channel Enable) ..................................................................................................................................................... 19
9.2.2 P3 (Regulator Enable) ............................................................................................................................................................... 19
9.2.3 P4, P5 (Antenna Rotator/Input Shortcut) ................................................................................................................................... 19
9.3 RSSI Channel Select Register ...........................................................................................................................................................19
9.3.1 C0, C1 (RSSI Channel Select) .................................................................................................................................................. 20
9.3.2 C2, C3 (RSSI Output Mode) ...................................................................................................................................................... 20
9.3.3 C4 (Channel Attenuator) ............................................................................................................................................................ 20
9.3.4 C5 (WAKE Clear) ....................................................................................................................................................................... 21
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AS3931
Datasheet - Contents
9.4 Test Mode Register ............................................................................................................................................................................21
9.4.1 T0 (Test Mode Enable) .............................................................................................................................................................. 21
9.4.2 T1, T2 (Test Mode Select) ......................................................................................................................................................... 21
9.4.3 T3 ............................................................................................................................................................................................... 22
9.4.4 T4 (RSSI Step Select) ............................................................................................................................................................... 22
9.4.5 T5 (Wake Generator On/Off) ..................................................................................................................................................... 22
9.5 Correlator Mode Register ...................................................................................................................................................................22
9.5.1 M0 (Correlator Off) ..................................................................................................................................................................... 23
9.5.2 M1 (Single/Double Wake Pattern) ............................................................................................................................................. 23
9.5.3 M2, M3 (Zero-Half-Bit Detection Mode) ..................................................................................................................................... 23
9.5.4 M4 (Detector Time Constant) .................................................................................................................................................... 23
9.5.5 M5 .............................................................................................................................................................................................. 23
10 Extended Operation .............................................................................................................................................................. 24
10.1 Power Management .........................................................................................................................................................................24
10.1.1 Sleep Mode .............................................................................................................................................................................. 24
10.1.2 Standby Mode .......................................................................................................................................................................... 24
10.1.3 Receive Mode .......................................................................................................................................................................... 24
10.1.4 Regulator On/Off ...................................................................................................................................................................... 24
10.1.5 Typical Current Consumption in Different Modes .................................................................................................................... 24
10.1.6 RSSI Step ................................................................................................................................................................................ 24
10.1.7 Antenna Rotation ..................................................................................................................................................................... 24
10.2 Input Attenuation and Input Shortcutting ..........................................................................................................................................24
10.3 WAKE Signal at the RSSI Pin ..........................................................................................................................................................25
10.4 Single WAKE Operation ...................................................................................................................................................................25
10.5 Using the Wake Generator ...............................................................................................................................................................25
10.6 Direct DATA Mode ............................................................................................................................................................................26
10.7 Correlator Modes .............................................................................................................................................................................26
10.8 Threshold Adaptation Filter Time Constant ......................................................................................................................................26
10.9 RSSI and WAKE Pin Modes ............................................................................................................................................................26
11 Package Drawings and Markings ......................................................................................................................................... 27
12 Ordering Information ............................................................................................................................................................. 29
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AS3931
Datasheet - Pin Assignments
4 Pin Assignments
Figure 2. Pin Assi gnments 16-pin TSSOP Package
4.1 Pin Descriptions
Table 1. Pin Descriptions
Pin Name Pin
Number Pin
Type Description
VCC 1 Supply Input Positive Supply Voltage
LF1N 2 Analog Input Channel 1 negative input
LF1P 3 Analog Input Channel 1 positive input
LF2N 4 Analog Input Channel 2 negative input
LF2P 5 Analog Input Channel 2 positive input
LF3N 6 Analog Input Channel 3 negative input
LF3P 7 Analog Input Channel 3 positive input
GND 8 Ground Negative Supply Voltage
XIN 9 Analog Input Crystal Oscillator Pin 1
XOUT 10 Analog Output Crystal Oscillator Pin 2
WAKE 11 Open Drain Wake Up Detect output/Reset output
CS 12 Digital Input with
Pulldown Chip Select
SCL 13 Digital Input with
Pulldown Serial Clock
SDA 14 Digital Input with
Pulldown Serial Data
RSSI 15 Analog/Digital
output
Received Signal Strength Indicator signal/
Digital Test mode signal output
VREG 16 Analog Output Regulator Output Voltage
AS3931
1
2
3
4
5
6
7
12
16
15
14
13
LF1N
LF1P
LF2N
LF2P
LF3N
LF3P
RSSI
SDA
SCL
CS
WAKE
XOUT
11
10
VCC VREG
89
GND XIN
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AS3931
Datasheet - Absolute Maximum Ratings
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only. Functional operation of the
device at these or any other conditions beyond those indicated in Section 6 Electrical Characteristics on page 6 is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter Min Max Units Notes
Positive supply voltage
(VCC)-0.5 5.5 V
Analog ground
(GND) 00V
Voltage at any pin except pin 2 to pin 7 (VIN)GND-0.5VCC+0.5 V
Voltage at Pin 2 to Pin 7
(VIN)GND-0.5 GND+0.5 V
Input current (Latchup Immunity)
(Iin)-100 +100 mA JEDEC 78
Electrostatic discharge
(VESD)1000 V Norm: MIL 883 E method 3015
HBM: R=1.5 kΩ, C=100 pF
Total power dissipation
(Ptot)300 mW
Storage temperature
(Tstg)-55 125 ºC
Package body temperature
(Tbody)+260 ºC
The reflow peak soldering temperature (body
temperature) specified is in accordance with IPC/
JEDEC J-STD-020 “Moisture/Reflow Sensitivity
Classification for Non-Hermetic Solid State
Surface Mount Devices”.
The lead finish for Pb-free leaded packages is
matte tin (100% Sn).
Humidity non-condensing 5 85 %
Moisture Sensitive Level 3 Represents a maximum floor life time of 168h
Operating Ambient Temperature Range
(TAMB)-20 +65 ºC
Recommended Operating Conditions
Positive supply voltage
(VCC)2.6 5.5 V Regulator used
Positive supply voltage
(VCC)2.4 3.5 V Regulator not used
Analog Ground
(GND) 00V
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AS3931
Datasheet - Electrical Characteristics
6 Electrical Characteristics
TAMB = -20° to +65° C, VCC = 3.0 V, fIN = 20 kHz, register settings as after POR, CS = low, transmission protocol according to Figure 15,
Figure 16 and application circuit according to Figure 1 unless otherwise specified.
Table 3. Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Units
General
fIN LF input carrier frequency
range 19 150 kHz
BRHalf-bit rate12.704 2.731 2.758 kB/s
BMManchester Bit Rate21.352 1.365 1.379 kB/s
WManchester Code Word396 hex
NPRE Preamble half-bits48
VREG Regulator Voltage5VCC = 2.6 V to 5.5 V 2.30 2.4 2.60 V
TPOR Power On Reset time6VCC = 2.4 V to 5.5 V 5 ms
ICC operating current
regulator off,
VCC = 2.4 V;
TAMB = 27° C
sleep mode 0.3 µA
standby mode 6.5 µA
receive mode 6.7 µA
regulator off,
VCC = 2.4V to
3.5V;
TAMB = 27° C
sleep mode 0.5
standby mode 6.8
regulator on,
TAMB = 27° C
sleep mode 0.8 1.5 µA
standby mode 7.0 8.8 µA
receive mode 7.2 9 µA
regulator on,
RSSI-step =
low;
TAMB = 27° C
standby mode 6.6
IBUF
RSSI buffer operating
current7No load at RSSI-Pin 2 µA
ΔVCC VCC transient compliance8
recovery time = 10 ms; regulator on8,
2.6 V < VCC < 5.5 V for VCC after step 2V
recovery time = 10 ms; regulator off8;
2.4 V < VCC < 5.5 V for VCC before step 0.3 V
ZIN Differential small sig. input
impedance
normal operation; TAMB = 27º 2 MΩ
input attenuator active;
TAMB = 27º 1.5 kΩ
input shortcutting active;
TAMB = 27º 0.5 kΩ
fXTAL crystal oscillator frequency Crystal type: CC4 from MicroCrystal932.768 kHz
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AS3931
Datasheet - Electrical Characteristics
WAKEUP
Vin,min
minimum differential input
voltage for wake up
detection10 NPRE = 8
trise,tfall < 150 µs;
VREG = 2.4 V to 3.5 V11
350 µVpp
Vin,max
maximum differential input
voltage for wake up
detection10 1Vpp
IWAKE WAKE pin current
Voltage at WAKE pin:
VOL < 0.4 V;
VREG = 2.4 V to 3.5 V11 0.33 mA
RSSI
VRSSI RSSI output voltage range 0.5 1.7 V
VRSSI0 RSSI output voltage
(RSSI offset) VIN = 0; 0.5 0.76 1.2 V
VSTEP RSSI output voltage step12 VIN = 1 mVpp;100 290 mV
VLOG logarithmic input voltage
range VIN = 1 mVpp, RSSI step = high 0.3 300 mV
SRSSI RSSI slope in log. range RSSI step = high 12 mV/dB
CRSSI cap. loading of RSSI pin RSSI buffer active 10 pF
IRSSI RSSI buffer output current 5 µA
Tstep RSSI voltage step time13 CL = 10 pF,
RL = 1 MΩ;
Input signal amplitude
100 mVpp; CS from low to high
(Buffer activation in presence of
a strong input signal);
350 µs
channel switching from ChA(100
mVpp) to
ChB (0 mVpp)14,
with CS deactivation of
10 µs
350 µs
VRIP RSSI Ripple Voltage RSSI buffer active, CL = 10 pF, RL = 1 MΩ;
VIN = 1 mVpp;70 mV
Serial Programming Interface
VIL Digital input L level Pins SCL, SDA, CS;
VREG = 2.4 V to 3.5 V11 0.3 *
VREG11 V
VIH Digital input H level Pins SCL, SDA, CS
VREG = 2.4 V to 3.5 V11 0.7 *
VREG11 V
IIH Digital Input current
Pins SCL, SDA, CS
VIH = 2.4 V;
VREG = 2.4 V to 3.5 V11 30 60 100 µA
TCLK Clock period VREG = 2.4 V to 3.5 V11 2µs
TCH Clock high duration VREG = 2.4 V to 3.5 V11 500 ns
TCL Clock low duration VREG = 2.4 V to 3.5 V11 500 ns
Table 3. Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Units
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AS3931
Datasheet - Electrical Characteristics
TDVCH Data valid to pos. Clock
edge VREG = 2.4 V to 3.5 V11 100 ns
TCHDI pos. Clock edge to Data
invalid VREG = 2.4 V to 3.5 V11 100 ns
TSHCH Select active to pos. Clock
edge VREG = 2.4 V to 3.5 V11 100 ns
TCHSL pos. Clock to Select
inactive VREG = 2.4 V to 3.5 V11 100 ns
TSL Select low time VREG = 2.4 V to 3.5 V11 500 ns
1. The half-bit rate correlates with the crystal oscillator clock frequency fclk as follows: BR = fCLK/12
2. The Manchester bit rate correlates with the Half-Bit Rate as follows: BM = BR/2
3. Code word can be changed by metal option
4. 8 preamble half-bits are equivalent to 4 manchester bits
5. VREG output may not be used as a supply for other circuits
6. This is the internal Power on Reset time generated by the chip. To ensure proper start-up conditions, the supply voltage VCC must be
ramped up to its final value during TPOR
7. This is the additional operating current when the RSSI buffer is activated without load
8. ΔVCC means a hard step of the supply voltage down to a lower value by an amount of ΔVCC; after such a step, the analog circuits in the
chip take some time to recover for working properly again. The maximum step value is listed.
9. Crystal tolerance: 100ppm
10.Values refer to production test
11.If regulator is on, then VREG = 2.4 V; If regulator is off, then VREG = VCC, where VCC = 2.4 V to 3.5 V
12.The RSSI step is the change of the RSSI output voltage when the input signal amplitude changes from 0 to specified value
13.Time to step from initial RSSI value to 95% of the final value
14.ChA may be any channel 1 – 3, whereas ChB may be any other remaining channel.
Table 3. Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Units
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AS3931
Datasheet - Typical Operating Characteristics
7 Typical Operating Characteristics
All graphs refer to Tab = 27°C and VREG = 2.4 V, unless otherwise stated.
7.1 RSSI Characteristic
Figure 3. RSSI-Characteristic VRSSI [V] vs Vin [Vpp]
1.70
1.60
1.50
1.40
1.30
1.20
1.10
1.00
900m
800m100µ 1m 10m 100m 1
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AS3931
Datasheet - Typical Operating Characteristics
7.2 Temperature Dependence of RSSI
Figure 4. RSSI-step [V] @ Vin = 1 mVpp and 2 mV Figure 5. RSSI-step [V] @ Vin = 300 µVpp and offset
vs temp [deg C] vs. temp [deg C]
Figure 6. RSSI-step [V] @ Vin = 1 mV and 2 mV vs. Figure 7. RSSI-step [V] @ Vin=300µ Vpp and offset
temp [deg C], reduced step vs. temp [deg C], reduced step
410m
390m
370m
350m
330m
310m
290m
270m
250m
230m
210m -20 -10 0.0 10 20 temp
30 40 50 60 70
920m
900m
880m
860m
840m
820m
800m
70.0m
69.0m
68.0m
67.0m
66.0m
65.0m
-20-100.010203040506070
1.020
1.010
1.000
990.0m
980.0m
970.0m
960.0m
950.0m
45.0m
44.0m
43.0m
42.0m-20 -10 0.0 10 20 30 40 50 60 70
VIN = 300µ V PP
VIN = 0 (offset)
290m
270m
250m
230m
210m
190m
170m
150m -20 -10 0.0 10 20temp
30 40 50 60 70
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AS3931
Datasheet - Typical Operating Characteristics
7.3 Supply Voltage Dependence of RSSI
Figure 8. RSSI-step [V] @ Vin = 1 mVpp and 2 mV Figure 9. RSSI-step [V] @ Vin = 300 µVpp and offset
vs. VCC [V] vs. VCC [V]
Figure 10. RSSI-step [V] @ Vin = 1 mVpp and 2 mV vs Figure 11. RSSI-step [V] @ Vin =300 µVpp and offset
VCC [V], reduced stepvs. VCC [V], reduced step
410m
390m
370m
350m
330m
310m
290m
270m
250m 2.40 2.60 2.80 3.00 3.20 3.40 3.60
87.0m
83.0m
79.0m
75.0m
71.0m
67.0m
2.00m
1.80m
1.60m
1.40m
1.20m
1.00m
800m 2.40 2.60 2.80 3.00 3.20 3.40 3.60
280m
260m
240m
220m
200m
180m
160m2.40 2.60 2.80 3.00 3.20 3.40 3.60
57.0m
55.0m
53.0m
51.0m
49.0m
47.0m
45.0m
43.0m
2.10
1.90
1.70
1.50
1.30
1.10
900m2.40 2.60 2.80 3.00 3.20 3.40 3.60
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AS3931
Datasheet - Typical Operating Characteristics
7.4 Frequency Dependence of RSSI
Figure 12. RSSI-step [V] @ Vin = 1 mVpp vs. fin [Hz],
RSSI high step and low step
280m
260m
240m
220m
200m
180m
160m
140m
120m
100m
80.0m 10.k 100.k 1M
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AS3931
Datasheet - Detailed Description
8 Detailed Description
8.1 Block Diagram
Figure 13. Block Diagram
8.2 Block Description
8.2.1 Antenna Rotator
In order to achieve an optimum assignment of the antennas to the receiving channels, the connection of the antennas to the channels can be
changed cyclically with a multiplexed (antenna rotator), which is controlled by an internal register. The register setting can be changed by the
serial interface.
8.2.2 Input Attenuator
Input signal attenuation is provided for each channel by means of connecting a 1.5 kΩ resistor across the differential inputs. An internal register
controls attenuation.
8.2.3 Input Shortcutt ing
The differential inputs can be shortened by register settings to measure the RSSI offset. In this case, the resistance between the differential
inputs is reduced to approximately 500 Ω.
8.2.4 Input Protection Circuit
Each signal input has a powerful input overload protection circuit consisting of two anti-parallel protection diodes connected to ground (see
Figure 14). This connection ensures that the differential input voltage can never exceed the supply voltage of the chip. To obtain proper
operation, the differential input receiving circuits (resonant RLC-circuits) must be floating and shall be grounded nowhere (see Figure 1)
LF1P
LF1N
LF2P
LF2N
LF3P
LF3N
CS
SCL
SDA
VCC
GND
VREG
XIN
XOUT
RSSI WAKE
Input
Protection1
Input
Protection2
Input
Protection3
Antenna Rota-
tor Input
Attenuator1
Input
Attenuator2
Input
Attenuator3
Log. Env. Amp 1
Log. Env. Amp 2
Log. Env. Amp 3
RSSI1
RSSI2RSSI3
Detector1
Detector2
Detector3
RSSI
Multiplexer
Control Logic
Regulator Regulator POR
RSSI
Buffer
Data
Multiplexer
Wake Generator
Correlator3
Correlator2
Correlator1
Data1
Data2
Data3
Wake1
Wake2
Wake3
Wake
Multiplexer
Multiplexer
AS3931
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AS3931
Datasheet - Detailed Description
Figure 14. Input Protection Circuit
8.2.5 Logarithmic Envelope Amplifiers
The logarithmic envelope amplifiers amplify the ASK coded LF input signals. They generate Received Signal Strength Indicator (RSSI) signals,
which are proportional to the logarithm of the received field strengths within the specified dynamic range. These signals are used for data
detection and distance measurements. The RSSI signals are bandwidth limited to reduce noise influence. The slope of the amplifiers in the low
signal range can be controlled by register settings: a high slope for increased sensitivity but also increased current consumption and a weak
slope with reduced current consumption are possible.
8.2.6 Detectors
The detectors convert the logarithmic envelope signal containing ASK coded data into digital signals. Each detector consists of a lowpass filter
for generation of an adaptive threshold and a slicing comparator. A preamble is required for a proper adaptation of the threshold prior to the
decision of the first valid data bit. A constant positive threshold offset is included in the comparator to ensure no data output in case of no input
signal. This increases the overall system noise immunity.
8.2.7 Digital Correlators
The AS3931 uses a 16-bit digital wakeup pattern. Digital correlators perform the identification of this pattern. They use a sophisticated detection
algorithm that provides high immunity against noise injection as a result of stochastic and periodic interference’s. The AS3931 provides the
possibility to double the length of the wake pattern to 32 bit. This is useful in environments with high noise levels to reduce the possibility of
spurious (parasitic) wakeups. In this case the usual wake pattern must be sent twice before a wake up is recognized and a WAKE signal is
generated. This active low WAKE signal is generated after successful pattern identification. Otherwise WAKE is high. Setting a register bit via the
serial-programming interface resets the correlators. In order to save power the correlators are stopped when no data has been received for a
specified amount of time. The correlators can be configured regarding their error tolerance by register settings.
8.2.8 Wake Generator
A counter, clocked by the 32 kHz crystal oscillator, generates an artificial wake up app. every 2 hours. This wake up can be used to manage the
quiescent current consumption of the AS3931. The idea behind is, to switch off one or more of the receiving channels in case of no true wake up
detection for long times; that is when only parasitic wakeups or no wakeup at all is detected. An external controlling unit (µC) can identify this
case by counting the parasitic wake ups and powering down one or more of the receiver channels to save current. When no wake ups are
detected at all, e.g. if the application device is stored in a stock, then the wake generator’s artificial parasitic wakeups (every 2 hours) can be
used to identify the situation.
8.2.9 Crystal Oscillator
The crystal oscillator generates the clock signal for the digital correlators. It has been optimized for a 32.768 kHz quartz crystal connected to pins
XIN and XOUT. The oscillator provides extremely low current consumption, so it can be operated permanently by a battery.
8.2.10 Regulator
A regulator is implemented to provide the amplifiers and digital circuits with a stable and clean supply. The regulator can be switched off; in this
case the external supply voltage is bypassed to the amplifiers and digital circuits. The regulator shall always be used for external supply voltages
higher then 3.3V, otherwise the current consumption is significantly increased. The regulated voltage can be seen at the VREG pin, but may not
be used to supply any other external circuits.
8.2.11 Power On Reset (POR)
A power on reset circuit guarantees proper circuit operation after power supply starts up. All internal registers are reset to their default states
after power on. After the Power On Reset time, the active low WAKE output is activated and set to low (Power On Wake Up). During the Power
On Reset time, the WAKE output pin is set to high. By this, it is ensured that this triggers the Power On Wake Up triggered only when the internal
registers are reset and ready to be programmed.
LFN
LFP
GND
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AS3931
Datasheet - Detailed Description
8.3 Basic Operation
8.3.1 LF Transmission Protocol
8.3.1.1 Data Pattern
The AS3931 identifies a 16 half-bit binary coded data pattern, which is ASK-modulated on a LF carrier. The pattern must contain 8 LOGIC 0 half-
bits and 8 LOGIC 1 half-bits in order to be DC free. Furthermore, for a proper detector threshold adaptation it has to be ensured that there are no
long groups of LOGIC 0 and LOGIC 1 half-bits. Therefore coding of the 16 half-bit binary data to 8 Manchester bits is common. This means that
8 consecutive half-bit pairs are grouped to Manchester bits whereas a Manchester bit 1 is a HIGH to LOW transition and a Manchester bit 0 is a
LOW to HIGH transition. The AS3931 supports the Manchester bit pattern 96 [hex] which in binary code is: 10 01 01 10 01 10 10 01. MSB is
transmitted first. The Manchester bit pattern i.e. the binary DATA pattern can be changed on demand by a metal mask modification.
8.3.1.2 Double Data Pattern
To increase the immunity against parasitic wakeups, the data pattern necessary for a successful wakeup can be doubled by programming the
AS3931: if the double data pattern is used, the pattern 96 has to be sent twice; after recognition of the first data pattern, the second data pattern
has to be sent immediately after the first one, otherwise no WAKE signal is generated. For the timing see Wake Up Frame on page 15. Setting
the bit M1 to 1 can program the double data pattern feature.
8.3.1.3 Wake Up Frame
The Wake Up Frame of AS3931 consists of a preamble used for detector threshold adaptation followed by the DATA pattern once (normal or
single Wake Up) or twice (double Wake Up) to be identified. We recommend a transmission protocol as shown on Figure 15 and Figure 16. The
preamble consists of a half-bit pattern 1010... with a specified number NPRE of half-bits (NPRE must be an even number in order to get complete
1/0 pairs). NPRE depends on the application and has influence on the wakeup and overload sensitivity. We recommend a minimum of NPRE = 8
half-bits (according to 4 manchester bits “1”).
Figure 15. Wa ke Up Frame of AS3931 with Single W AKE Data Pattern
Figure 16. Wa ke Up Frame of AS3931 with Double WAKE Data Pattern
Preamble
NPRE half-bits Data 96
5.86 ms (16 half-bits)
WAKE
LF Carrier
Amplitude
Preamble
NPRE
half-bits Data 96
5.86 ms (16 half-bits)
WAKE
LF Carrier
Amplitude
Data 96
5.86 ms (16 half-bits)
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AS3931
Datasheet - Detailed Description
8.3.2 Wake Up Detection
A WAKE signal is generated if and only if all 8 LOGIC 1 half-bits and a predefined number of LOGIC 0 half-bits have been identified as correct.
The wakeup detection criteria can be changed: the number of invalid zero half-bits can be programmed from 0 to 3. A valid Wake Up Frame can
be detected at only one of the 3 channels or at more then one channel simultaneously. The single WAKE signals of each channel are ored
together to a common WAKE signal Figure 13.
In case of using the double wake up feature, the settings of the allowed zero half-bit errors apply for each of the sent data pattern individually.
E.g. if you configure the AS3931 to allow 2 zero half-bit errors, the first data pattern can contain up to two invalid zero half-bits as well as the
second data pattern, but it is not possible that the first pattern contains 3 and the second data pattern contains one zero half-bit error (what in
total would give the same number of allowed zero half-bit errors as before). Note that a Double-Wake-Pattern detection is possible also if the two
consecutive Single-Wake-Patterns are assigned to different channels: e.g. if the first pattern is recognized at channel 2 and the second pattern is
recognized at channel 3, then a Double-Wake-Pattern is recognized and the WAKE Pin is activated. All channel combinations are possible. In
case of different channels, it is not possible to decide which channel received the first and which channel received the second data pattern.
8.3.3 WAKE Signal Clearing
After a Wake Up detection, the WAKE output signal must be reset via the Serial Programming Interface. This is done by toggling the bit C5 in the
Channel Select register from low to high and vice versa. This is valid for both cases the Single Wake pattern and the Double Wake pattern
detection. Furthermore, it is also valid for an internal generated Artificial Wakeup (see Extended Operation on page 24).
8.3.4 WAKE Signal After POR
After a power on reset (POR), the WAKE signal is activated (LOW). Therefore, after startup the WAKE signal must be cleared as if a valid Wake
Up would have been detected.
8.3.5 RSSI Operation
The RSSI signal of a selected channel can be measured at the RSSI pin. Each channel can be selected by register settings. To calibrate the
RSSI measurement, the LF inputs can be shortcutted with approximately 500 Ω by internal register settings. Doing so, the RSSI voltage offset
can be measured. The RSSI – signal is buffered at the RSSI pin. The buffer can be deactivated by register settings; in this case the RSSI pin is
tristated (high impedance). However, if the CS signal is not activated, the RSSI pin is tristated. This has to be kept in mind when programming
the AS3931 via the Serial Programming Interface (the CS signal is used to latch the serial data into the selected register at the falling edge of
CS).
8.4 Serial Programming Interface Timing
Figure 17. SPI Ti ming Waveforms
SCL
SDA
CS
A0 A1 D4 D5
TDVCH
TCLK
TCH TCL
TSHCH
TCHSL
TSL
TCHDI
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AS3931
Datasheet - Configuring the Product
9 Configuring the Product
9.1 Serial Programming Interface
The AS3931 is programmed via an unidirectional three wire Serial Programming Interface.The 3 lines are:
CS: Chip Select, used for selecting AS3931 and for data latching
SCL: Serial Clock
SDA: Serial Data
A block of 8 bit data starting with the LSB is sent according to the diagram shown in Figure 19. The received block of 8 bit data is shifted into an
8 bit latch. The two LSBs are register address bits and the remaining 6 bits are data bits. The register address bits A1 and A0 are decoded and
the 6 data bits are stored into one of three 6 bit registers with the falling edge of CS.
Figure 19. Prot ocol of 8 Bi t Data Serial Transmission
9.2 Power On Register
Table 4. Register Data
Bit POR state Description
P0 1 Enable Channel 1
P1 1 Enable Channel 2
P2 1 Enable Channel 3
P3 1 Enable Regulator
P4 0 Antenna Rotator Bit 1
P5 0 Antenna Rotator Bit 2
Table 5. Register Address
Bit Value
A0 0
A1 0
CS
SDA
ADDRESS DATA
A0 A1 D0 D1 D2 D3 D4 D5
D = T : TEST MODE REGISTER
SCL
D = P : POWER ON REGISTER
D = C : CHANNEL SELECT REGISTE R
D = M: CORRELATOR MODE REGIS TER
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AS3931
Datasheet - Configuring the Product
9.2.1 P0, P1, P2 (Channel Enable)
If the bit P0, P1 or P2 is set to 1, the related channel is enabled. That means, the logarithmic envelope amplifier and the correlator are enabled
and ready to receive a Wake Up Frame. When disabled, the channel is off, taking no current except for the bias cell to the amplifier. After a power
on, all channels are enabled.
Note: Shaded cells show POR-states
9.2.2 P3 (Regulator Enable)
Bit P3 enables the regulator (VREG 2.4 V) or switches off the regulator (VREG = VCC). If the regulator is switched off, then the voltage at Pin
VCC is bypassed unregulated to the internal circuits. After a power on, the regulator is on.
9.2.3 P4, P5 (Antenna Rotator/Input Shortcut)
Bits P4 and P5 are used to set the Antenna Connection Mode or to shortcut the differential inputs of each amplifier. See Table 28 for the
description of the rotator modes.
9.3 RSSI Channel Select Register
Table 6. P0, P1, P2 Bit Mode
P0, P1, P2 Mode
0 Channel Disabled
1Channel Enabled
Table 7. P3 Bit Mode
P3 Mode
0 Regulator Disabled
1Regulator Enabled
Table 8. P4, P5 Bit Mode
P4 P5 Mode
0 0 Connection Mode1
1 0 Connection Mode2
0 1 Connection Mode3
1 1 Amplifier Inputs Shorted
Table 9. Antenna Rotation Modes
Connection Mode1 Connection Mode2 Connection Mode3
Antenna 1 → Channel 1 Antenna 2 → Channel 1 Antenna 3 → Channel 1
Antenna 2 → Channel 2 Antenna 3 → Channel 2 Antenna 1 → Channel 2
Antenna 3 → Channel 3 Antenna 1 → Channel 3 Antenna 2 → Channel 3
Table 10. Register Data
Bit POR state Description
C0 0 RSSI select Bit 1
C1 0 RSSI select Bit 2
C2 0 RSSI output mode Bit 1
C3 0 RSSI output mode Bit 2
C4 0 Channel attenuator
C5 0 WAKE clear
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AS3931
Datasheet - Configuring the Product
9.3.1 C0, C1 (RSSI Channel Select)
Bits C0 and C1 are used to select the channel whose RSSI signal is multiplexed to the RSSI pin. In case of both bits C0 and C1 set to 1, a
bandgap voltage VBG (1.25 V) appears at the RSSI pin. After power on, channel 1 is selected.
9.3.2 C2, C3 (RSSI Output Mode)
Bits C2 and C3 define the RSSI pin function.
Note: The RSSI pin function also depends on the signal CS. If CS = 0, the RSSI pin is always in the high impedance state. This is also the
case after power on.
The WAKE or single WAKE function is selected together with bits T0 – T2 and C0 – C1. For more information see Extended Operation
on page 24
9.3.3 C4 (Channel Attenuator)
When bit C4 is set, a resistor (app. 1.5 kΩ) is connected across the differential inputs of each channel. This resistor reduces the Q-factor of the
antenna resonant circuit; therefore the received signal is reduced too. The amount of damping depends on the Q-factor of the antenna circuit.
Table 11. Register Address
Bit Value
A0 1
A1 0
Table 12. C0, C1 Bit Mode
C0 C1 Mode
0 0 Channel 1
1 0 Channel 2
0 1 Channel 3
1 1 VBG (T0=0), WAKE (T0=1)
Table 13. C2, C3 Bit Mode
C2 C3 RSSI Pin Function
0 0 high Z
10
Analog output: RSSI of selected channel or
VBG
01
Digital output: WAKE,
single WAKE or DATA
1 1 not used
Table 14. C4 Bit Mode
C4 Mode
0Input attenuators disabled
1 Input attenuators enabled
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AS3931
Datasheet - Configuring the Product
9.3.4 C5 (WAKE Clear)
Bit C5 is used to reset the active low WAKE pin after the pin has been set as a result of receiving a valid code word (single or double wake
pattern) by one of the 3 channels, a POR or an internally generated Wakeup. Setting Bit C5 to 1, the WAKE pin is reset to high and held in high
state, to enable the channels for the next wake up signal, the bit C5 must be toggled to 0 afterwards. After power on, the WAKE-pin is activated
and the bit C5 has to be toggled high and low after a power on.
9.4 Test Mode Register
9.4.1 T0 (Test Mode Enable)
Bit T0 is used to define the pin function of the WAKE pin. When bit T0 is reset to 0, the WAKE pin is used for normal Wake Up detection (Single
or Double Wakeup from the receiver channels or internally generated wakeup). When bit T0 is set to 1, testmode signals are multiplexed to the
WAKE pin according to the selected test mode (T1, T2). After power on, the normal wake up detection mode is selected.
9.4.2 T1, T2 (Test Mode Select)
When bit T0 is set to 1, the following signals can be mapped to the WAKE pin. For signal description (see Figure 13).
DATA: received bit stream of the selected channel
WAKE: detected wake up of the selected channel
For the DATA and WAKE signal select the desired channel by setting Bits C0 and C1.
Table 15. C5 Bit Mode
C5 Mode
0no effect
1 WAKE=H
Table 16. Register Data
Bit POR state Description
T0 0 Test mode enable
T1 0 Test mode select Bit 1
T2 0 Test mode select Bit 2
T3 0 not used
T4 1 RSSI step
T5 0 WAKE Generator on/off
Table 17. Register Address
Bit Value
A0 0
A1 1
Table 18. T0 Bit Mode
T0 WAKE Pin function
0WAKE
1 Test Mode Signals
Table 19. T1, T2 Bit Mode
T1 T2 WAKE Pin Function
0 0 DATA of selected channel
1 0 WAKE of selected channel
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AS3931
Datasheet - Configuring the Product
9.4.3 T3
Not used; must always be programmed to 0 by the user!
9.4.4 T4 (RSSI Step Select)
Bit T4 is used to switch between a high and a low RSSI step. For more information on RSSI steps see Extended Operation on page 24.
9.4.5 T5 (Wake Generator On/Off)
Bit T5 is used to activate the Wake Generator. If activated, an artificial parasitic wakeup is generated every 2 hours.
9.5 Correlator Mode Register
0 1 not used
1 1 not used
Table 20. T4 Bit Mode
T4 Mode
0Low RSSI step
1High RSSI step
Table 21. T5 Bit Mode
T5 Mode
0 Wake Generator off
1 Wake Generator on
Table 22. Register Data
Bit POR state Description
M0 0 Correlator Off
M1 0 single/double wake pattern
M2 0 Zero-Bit Detection Mode bit1
M3 1 Zero-Bit Detection Mode bit2
M4 1 detector threshold τ select
M5 0 not used
Table 23. Register Address
Bit Value
A0 1
A1 1
Table 19. T1, T2 Bit Mode
T1 T2 WAKE Pin Function
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AS3931
Datasheet - Configuring the Product
9.5.1 M0 (Correlator Off)
Bit M0 is used to simultaneously turn off all 3 correlators. This is done by turning off the correlator clocks. This can be used to reduce power
consumption when the Direct Data Mode is used.
9.5.2 M1 (Single/Double Wake Pattern)
Bit M1 selects the number of data patterns that are necessary for wakeup detection.
9.5.3 M2, M3 (Zero-Half-Bit Detection Mode)
Bits M2 and M3 select the number of Zero-Half-bits that are allowed to be invalid. A high level of allowed invalid Zero-Half-bits increases the error
tolerance related to noise or interference’s, that means that the probability for the detection of a valid WAKE pattern increases. Note that in turn
the immunity against parasitic wakeups (WAKE detection when no data has been sent, due to noise or interference’s) is reduced.
9.5.4 M4 (Detector Time Constant)
Bit M4 is used to switch between a large and a small τ of the detector threshold adoption filter. A large τ is recommended, because it increases
the noise margin. A small τ can be used to improve the wake sensitivity when non-specified wake-patterns are used.
9.5.5 M5
Not used; must always be programmed to 0 by the user!
Table 24. M0 Bit Mode
M0 Mode
0Low RSSI step
1 High RSSI step
Table 25. M1 Bit Mode
M1 Mode
0 Single Data pattern
1 Double Data pattern
Table 26. M2, M3 Bit Mode
M2 M3 WAKE Pin Function
0 0 3 invalid Zero-bits allowed
1 0 2 invalid Zero-bits allowed
0 1 1 invalid Zero-bits allowed
1 1 0 invalid Zero-bits allowed
Table 27. M4 Bit Mode
M4 Mode
0 small τ
1 large τ
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AS3931
Datasheet - Extended Operation
10 Extended Operation
10.1 Power Management
10.1.1 Sleep Mode
In sleep mode, all channels are switched off, taking no current except for the bias cells of the amplifiers. Sleep mode is entered by register
setting, bits P0, P1, P2 set to 0. The remaining elements that take current are the oscillator and the regulator (if used). The Serial Programming
Interface remains active also in the sleep mode.
10.1.2 Standby Mode
In standby mode, selected channels are switched on, ready to receive data. The amplifier of the selected channel is on, whereas the correlator is
powered down as long as no input signal is detected at the input. Enabling the related channel when setting bits P0, P1 or P3 enters the standby
mode. In the standby mode, the current consumption increases by the amplifier currents compared to the sleep mode.
10.1.3 Receive Mode
An enabled channel automatically changes from the standby mode to the receive mode as soon as an input signal is detected. The channel
stays in receive mode as long as an input signal is detected. In receive mode, the correlator of the channel is active, scanning the input signal
waveform for a valid wake up pattern. The channel goes back to standby mode if no input signal is detected for more then a fixed timeout period.
The timeout period is approximately 3.3 ms. by this operating principle it is guaranteed, that the correlators are only active and taking current as
long as it is really necessary.
10.1.4 Regulator On/Off
The regulator can be switched off to reduce the current consumption. When switching off, the supply voltage is bypassed unregulated to the
internal circuits, so VREG = VCC. Otherwise, the internal voltage is regulated to 2.4 V. Switching off the regulator saves about 1 µA of current.
The regulator should only be switched off, when VCC is not higher then 3.3 V, otherwise the current consumption is increased because the
internal circuits will then take more current.
10.1.5 Typical Current Consumption in Different Modes
The Table 28 gives an overview of the typical current consumptions in the different modes. All three channels are used in this case. Power
consumption of course can be further reduced when not all three channels are enabled.
10.1.6 RSSI Step
The RSSI step is defined as the change in the RSSI signal voltage if the input amplitude steps from zero to a defined (small) value. For example
when changing the input signal amplitude from zero to 1 mVpp, the RSSI signal makes a step of app. 175 mV if the bit T4 is set to 1 (compare to
Figure 8 on page 21). If not needed, this step can be reduced to a lower value (T4 = 0), which decreases the current consumption of each
channel by app. 120 nA.
10.1.7 Antenna Rotation
The 3 possible input signals can be distributed to the 3 channels in 3 different connection modes. Using this feature, the differences between the
individual antenna voltages and also the differences of the individual RSSI-voltages of the channels can be handled. For example to eliminate
the differences of the RSSI-voltages it is possible to use only one channel and to multiplex it to each antenna. The Bits P4 and P5 select the
Antenna Rotation Modes.
10.2 Input Attenuation and Input Shortcutting
All differential LF-inputs are each shorted by approximately 500 Ω when setting Bits P4 and P5 both to 1. This can be used to measure the
RSSI-voltage with no input signal present; therefore the RSSI offset can be calibrated. It should be taken into account that the shortcut
resistance can not be made zero due to design restrictions, so the input signal cancellation is not 100% (depending on the antenna circuit).
Table 28. Typical Current Consumption
Operating Mode Regulator on, VCC = 3 V Regulator off, VCC = 2.4 V
Sleep 0.8 µA 0.3 µA
Standby 7.0 µA 6.5 µA
Receive 7.2 µA 6.8 µA
Standby & RSSI low step 6.6 µA 6.1 µA
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AS3931
Datasheet - Extended Operation
Similar to the input shortcutting option, a 1.5 kΩ resistor can be connected across the differential inputs when setting bit C4 to 1. This input
attenuation allows handling of very strong input signals by damping the antenna circuit. The damping depends on the Q-factor of the receiver
circuits.
10.3 WAKE Signal at the RSSI Pin
The WAKE signal, which is normally available at the WAKE pin, can be mapped to the RSSI pin additionally, which then becomes a digital output.
To do this, set the following bits:
C3 = 1 and C2 = 0 in the Channel Select Register (RSSI output mode digital)
C0 = 1 and C1 = 1 in the Channel Select Register
Note: The RSSI pin is only active if the CS signal is active (CS = 1), otherwise RSSI is high Z.
10.4 Single WAKE Operation
The single WAKE signals of each channel can be mapped to the WAKE pin. Normally, the 3 WAKE signals are “ored” together and mapped to
the WAKE pin, so the channel with the strongest input signal will generate a WAKE signal. To map a single WAKE signal to the WAKE pin, follow
the steps:
1. Enable Test Mode: set T0 = 1 in Test Mode Register
2. Select Test Mode: set T1 = 1 and T2 = 0 in Test Mode Register
3. Select Channel: set C0 and C1 in the Channel Select Register
The single WAKE signals can also be mapped to the RSSI pin, which then becomes a digital output pin. To do this, make this step:
Select RSSI output mode digital:set C2 = 0 and C3 = 1 in the Channel Select Register
The RSSI pin is only active if the CS signal is active (CS = 1), otherwise RSSI is high Z.
It is possible to operate the WAKE pin in the normal mode first (that is all three single WAKE signals ored together) and after a wake up
detection, to use the Single WAKE mode to check which channel received the wake pattern. This must be done before clearing the WAKE pin. It
is also possible to operate the WAKE pin in normal WAKE mode and simultaneously to operate the RSSI-pin in single WAKE mode.
10.5 Using the Wake Generato r
The wake generator generates artificial parasitic wakeup’s every 2 hours as a time base for an external-controlling unit to identify situations
where no true wakeup’s can be detected for a long time. For this purpose the external controlling unit must be able to distinguish between a true
wakeup (generated by one of the receiving channels) or an Artificial Wakeup. This is done by checking the receiving channels using the single
WAKE operation (see Single WAKE Operation on page 25). If a wakeup has occurred and no one of the receiving channels can be identified as
the trigger for the wake up, then the Wake Generator has triggered the wakeup. In this case, the WAKE signal has to be cleared as if a receiving
channel would have triggered the Wake Up.
Note: The internal counter, that generates the internal wakeup by an overflow, can not be reset by clearing the wake pin or other actions.
The time between two artificial wakeups is approximately 2 hours (2h 16min 32sec); however, the first artificial wakeup generated by the Wake
Generator after activation of the feature (by setting bit T5 = 1) may come earlier then in 2:16:32 hours. This time is not defined. After the first
artificial wakeup, the time between two wake ups is then 2 hours.
The Wake Generator must be activated by programming the bit T5 = 1 in the Test Mode Register.
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AS3931
Datasheet - Extended Operation
10.6 Direct DATA Mode
In Direct Data Mode, the received DATA of a selected channel can be mapped to the WAKE pin. The DATA signal is the digital output of the
detector and is normally fed to the correlator, where it is scanned for the WAKE pattern (see Figure 13). To get the DATA signal at the WAKE pin,
follow the steps:
1. Enable Test Mode: set T0 = 1 in Test Mode Register
2. Select Test Mode: set T1 = 0 and T2 = 0 in Test Mode Register
3. Select Channel: set C0 and C1 in the Channel Select Register
The Direct DATA signals can also be mapped to the RSSI pin, which then becomes a digital output pin. To do this, make this step:
Select RSSI output mode digital:set C2 = 0 and C3 = 1 in the Channel Select Register
Note: The RSSI pin is only active if the CS signal is active (CS = 1), otherwise RSSI is high Z.
10.7 Correlator Modes
Operation of the correlators can be modified regarding the error tolerances for the Zero-Half-Bits. In this case, the number of Zero-Half-Bits that
is allowed to be invalid can be set from 0 to 2. Please take into account that an increased error tolerance also reduces the immunity against
parasitic wakeups (WAKE detection when no data has been sent, due to noise or interferences).
10.8 Threshold Adaptation Filter Time Constant
Bit M4 is used to switch between a large and a small τ of the detector threshold adaptation filter. A large τ is recommended, because it increases
the noise margin. A small τ can be used to improve the wake sensitivity when non-specified Wake-Patterns are used.
10.9 RSSI and WAKE Pin Modes
This table gives an overview of the different signals that can be mapped to the RSSI and WAKE pin and how to program it.
Table 29. RSSI/W AKE-Pin Modes
Bit/Pin
Chip Select Pin
RSSI Output Mode 2
RSSI Output Mode 1
Channel Select 2
Channel Select 1
WAKE Test Mode Enable
Test Mode Select 2
Test Mode Select 1
Mode CS C3 C2 C1 C0 T0 T2 T1
WAKE-Pin: WAKE X X X X X 0 X X
WAKE-Pin: DATA1 X X X 0 0 1 0 0
WAKE-Pin: DATA2 X X X 0 1 1 0 0
WAKE-Pin: DATA3 X X X 1 0 1 0 0
WAKE-Pin: WAKE1 X X X 0 0 1 0 1
WAKE-Pin: WAKE2 X X X 0 1 1 0 1
WAKE-Pin: WAKE3 X X X 1 0 1 0 1
RSSI-Pin: WAKE 1 1 0 1 1 X X X
RSSI-Pin: DATA1 1 1 0 0 0 X 0 0
RSSI-Pin: DATA2 1 1 0 0 1 X 0 0
RSSI-Pin: DATA3 1 1 0 1 0 X 0 0
RSSI-Pin: WAKE1 1 1 0 0 0 X 0 1
RSSI-Pin: WAKE2 1 1 0 0 1 X 0 1
RSSI-Pin: WAKE3 1 1 0 1 0 X 0 1
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AS3931
Datasheet - Package Drawings and Markings
11 Package Drawings and Markings
The product is available in 16-pin TSSOP package.
Figure 20. 16-pin TSSOP Package
Marking: YYWWMZZ.
YY WW MZZ
Year (i.e. 10 for 2010) Manufacturing Week Assembly plant identifier Assembly traceability code
Symbol Min Nom Max
A- -1.20
A1 0.05 - 0.15
A2 0.80 1.00 1.05
b0.19 - 0.30
c0.09 - 0.20
D 4.905.005.10
E - 6.40 BSC -
E1 4.30 4.40 4.50
e - 0.65 BSC -
L 0.450.600.75
L1 - 1.00 REF -
Symbol Min Nom Max
R0.09 - -
R1 0.09 - -
S0.20 - -
Θ10º 8º
Θ2-12 REF-
Θ3-12 REF-
aaa - 0.10 -
bbb - 0.10 -
ccc - 0.05 -
ddd - 0.20 -
N16
AS3931
YYWWMZZ
Notes:
1. Dimensioning & tolerancing conform
to ASME Y14.5M-1994.
2. All dimensions are in millimeters.
Angles are in degrees.
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AS3931
Datasheet - Revision History
Revision History
Table 30. Revision History
Revision Date Owner Description
6.1 Apr 22, 2010 dhe
Changed to new template
Updated the Ordering table Table 31
6.2 Apr 14, 2011 Updated Absolute Maximum Ratings, Package Drawings and Markings.
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AS3931
Datasheet - Ordering Information
12 Ordering Information
Where:
T = Temperature range
P = Package Type
D = Delivery Form
Z = Others
TS = TSSOP
M = Tape & Reel (500 pcs / reel)
T = Tape & Reel (4500 pcs / reel)
Note: All products are RoHS compliant and Pb-free.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
For further information and requests, please contact us mailto:sales@austriamicrosystems.com
or find your local distributor at http://www.austriamicrosystems.com/distributor
Table 31. Ordering Information
Device ID Part Number Description Delivery Form1
1. Dry pack sensitivity level = 3, according to IPC/JEDEC J-STD-033A
Package
AS3931-TPD AS3931-ZTST Tape and Reel 16-pin TSSOP
AS3931-ZTSM Tape and Reel 16-pin TSSOP
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AS3931
Datasheet - Copyrights
Copyrights
Copyright © 1997-2011, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®.
All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of
the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale.
austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding
the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at
any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are
specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100
parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not
be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use,
interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters
austriamicrosystems AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com/contact
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