19-0352; Rev 2; 7/02 Microprocessor Programmable Universal Active Filters Features Filter Design Software Available Microprocessor Interface 64-Step Center Frequency Control 128-Step Q Control Independent Q and f0 Programming Guaranteed Clock to f0 Ratio-1% (A grade) 75kHz f0 Range (MAX262) Single +5V and 5V Operation Ordering Information PART TEMP RANGE PACKAGE ACCURACY MAX260ACNG 0C to +70C Plastic DIP 1% MAX260BCNG 0C to +70C Plastic DIP 2% MAX260AENG -40C to +85C Plastic DIP 1% MAX260BENG -40C to +85C Plastic DIP 2% MAX260ACWG 0C to +70C Wide SO 1% MAX260BCWG 0C to +70C Wide SO 2% MAX260AMRG -55C to +125C CERDIP 1% P-Tuned Filters MAX260BMRG -55C to +125C CERDIP 2% Anti-Aliasing Filters *All devices--24-pin packages 0.3in-wide packages Digital Signal Processing Ordering Information continued at end of data sheet. Applications Adaptive Filters Pin Configurations Signal Analysis Phase-Locked Loops Functional Diagram OUTPUT INPUT IN +5V V+ LP HP BP IN LP HP BP FILTER B FILTER A TOP VIEW BPA 1 24 LPA BPA 1 24 LPA N.C. 2 23 INB OP OUT 2 23 INB HPA 3 22 LPB HPA 3 22 LPB N.C. 4 21 BPB OP IN 4 GND -5V V- OSC CLKOUT CLKA CLKB 21 BPB MAX261 MAX262 INA 5 D1 6 19 OSC OUT D1 6 19 D0 A3 7 18 GND A3 7 18 OSC OUT CLK OUT 8 MAX260 MAX261 MAX262 MAX260 20 D0 INA 5 17 V- V+ 9 16 WR A2 10 15 A0 CLK OUT 8 20 HPB 17 GND V+ 9 16 V- A2 10 15 WR CLKA 11 14 HPB CLKA 11 14 A0 CLKB 12 13 A1 CLKB 12 13 A1 PROGRAM INPUTS CRYSTAL FOURTH-ORDER BANDPASS FILTER ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX260/MAX261/MAX262 General Description The MAX260/MAX261/MAX262 CMOS dual secondorder universal switched-capacitor active filters allow microprocessor control of precise filter functions. No external components are required for a variety of bandpass, lowpass, highpass, notch, and allpass configurations. Each device contains two second-order filter sections that place center frequency, Q, and filter operating mode under programmed control. An input clock, along with a 6-bit f0 program input, determine the filter's center or corner frequency without affecting other filter parameters. The filter Q is also programmed independently. Separate clock inputs for each filter section operate with either a crystal, RC network, or external clock generator. The MAX260 has offset and DC specifications superior to the MAX261 and MAX262 and a center frequency (f0) range of 7.5kHz. The MAX261 handles center frequencies to 57kHz, while the MAX262 extends the center frequency range to 140kHz by employing lower clock-to-f0 ratios. All devices are available in 24-pin DIP and small outline packages in commercial, extended, and military temperature ranges. MAX260/MAX261/MAX262 Microprocessor Programmable Universal Active Filters ABSOLUTE MAXIMUM RATINGS Total Supply Voltage (V+ to V-) .............................................15V Input Voltage, any pin ..........................(V- - 0.3V) to (V+ + 0.3V) Input Current, any pin ......................................................50mA Power Dissipation Plastic DIP (derate 8.33mW/C above 70C) ...............660mW CERDIP (derate 12.5mW/C above 70C) .................1000mW Wide SO (derate 11.8mW/C above 70C) ..................944mW Operating Temperature Ranges MAX260/MAX261/MAX262XCXG .......................0C to +70C MAX260/MAX261/MAX262XEXG .....................-40C to +85C MAX260/MAX261/MAX262XMXG ..................-55C to +125C Storage Temperature Range .............................-65C to +160C Lead Temperature (Soldering, 10s) ................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V+ = +5V, V- = -5V, CLKA = CLKB = 5V 350kHz for the MAX260 and 1.5MHz for the MAX261/MAX262, fCLK/f0 = 199.49 for MAX260/MAX261 and 139.80 for MAX262, Filter Mode 1, TA = +25C, unless otherwise noted.) PARAMETER CONDITIONS f0 Center Frequency Range TA = TMIN to TMAX 0.2 1.0 MAX260B 0.2 2.0 MAX261/MAX262A 0.2 1.0 MAX261/MAX262B 0.2 2.0 -5 TA = TMIN to TMAX MAX260A 1 6 Q=8 MAX260B 1 10 Q = 32 MAX260A 2 10 Q = 32 MAX260B 2 15 Q = 64 MAX260A 4 20 Q = 64 MAX260B 4 25 Q=8 MAX261/MAX262A 1 6 Q=8 MAX261/MAX262B 1 10 Q = 32 MAX261/MAX262A 2 10 Q = 32 MAX261/MAX262B 2 15 Q = 64 MAX261/MAX262A 4 20 Q = 64 MAX261/MAX262B 4 25 20 0.1 0.3 MAX261/MAX262 0.1 0.5 MAX261/MAX262 MAX260/MAX261/MAX262 % ppm/C MAX260 MAX260 Lowpass (at D.C.) Bandpass (at f0) % ppm/C Q=8 DC Lowpass Gain Accuracy 2 UNITS See Table 1 Q Temperature Coefficient Gain Temperature Coefficient MAX MAX260A f0 Temperature Coefficient Q Accuracy (deviation from ideal continuous filter) (Note 2) TYP See Table 1 Maximum Clock Frequency fCLK/f0 Ratio Error (Note 1) MIN dB -5 -5 +20 _______________________________________________________________________________________ ppm/C Microprocessor Programmable Universal Active Filters (V+ = +5V, V- = -5V, CLKA = CLKB = 5V 350kHz for the MAX260 and 1.5MHz for the MAX261/MAX262, fCLK/f0 = 199.49 for MAX260/MAX261 and 139.80 for MAX262, Filter Mode 1, TA = +25C, unless otherwise noted.) PARAMETER CONDITIONS TA = TMIN to TMAX, Q = 4 Mode 1 Offset Voltage At Filter Outputs--LP, BP, HP (Note 3) Mode 3 Offset Voltage Temperature Coefficient MIN TYP MAX MAX260A 0.05 0.25 MAX260B 0.15 0.45 MAX261A 0.40 1.00 MAX261B 0.80 1.60 MAX262A 0.40 1.20 MAX262B 0.80 1.60 MAX260A 0.075 0.30 MAX260B 0.075 0.50 MAX261A 0.50 1.10 MAX261B 0.90 1.60 MAX262A 0.50 1.30 MAX262B 0.90 1.60 fCLK/f0 = 100.53, Q = 4 TA = TMIN to TMAX UNITS V 0.75 mV/C Clock Feedthrough 4 mV Crosstalk -70 dB Q = 1, 2nd-Order, LP/BP Wideband Noise 90 4th-Order BP (Figure 24) (Note 4) 100 Harmonic Distortion at f0 Q = 4, VIN = 1.5VP-P Supply Voltage Range TA = TMIN to TMAX Power Supply Current (Note 5) Shutdown Supply Current See Typ. Oper. Char. 4th-Order LP (Figure 26) TA = TMIN to TMAX CMOS Level Logic Inputs VRMS -67 2.37 dB 5 6.3 MAX260 15 20 MAX261 16 20 MAX262 16 20 Q0A - Q6A = all 0, CMOS Level Logic Inputs (Note 5) V mA 1.5 mA 4.75 V INTERNAL AMPLIFIERS Output Signal Swing Output Signal Circuit Current Power Supply Rejection Ratio Gain Bandwidth Product Slew Rate TA = TMIN to TMAX, 10k load (Note 6) Source 50 Sink 2 0Hz to 10kHz mA -70 dB 2.5 MHz 6 V/s _______________________________________________________________________________________ 3 MAX260/MAX261/MAX262 ELECTRICAL CHARACTERISTICS (continued) MAX260/MAX261/MAX262 Microprocessor Programmable Universal Active Filters ELECTRICAL CHARACTERISTICS (for V = 2.5V 5%) (V+ = +2.37V, V- = -2.37V, CLKA = CLKB = 2.5V 250kHz for the MAX260 and 1MHz for the MAX261/MAX262, fCLK/f0 = 199.49 for MAX260/MAX261 and 139.80 for MAX262, Filter Mode 1, TA = +25C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP f0 Center Frequency Range (Note 7) Maximum Clock Frequency (Note 7) fCLK/f0 Ratio Error (Notes 1, 8) Q=8 Q=8 fCLK/f0 = 199.49 Q Accuracy (deviation from ideal continuous filter) (Notes 2, 8) fCLK/f0 = 199.49 fCLK/f0 = 139.80 MAX MAX26XA 0.1 1 MAX26XB 0.1 2 MAX260A 2 6 10 MAX260B 2 MAX261A 2 6 MAX261B 2 10 MAX262A 2 6 MAX262B 2 10 UNITS % % Output Signal Swing All Outputs (Note 6) 2 V Power Supply Current CMOS Level Logic Inputs (Note 5) 7 mA Shutdown Current CMOS Level Logic Inputs (Note 5) 0.35 mA Note 1: fCLK/f0 accuracy is tested at 199.49 on the MAX260/MAX261, and at 139.8 on the MAX262. Note 2: Q accuracy tested at Q = 8, 32, and 64. Q of 32 and 64 tested at 1/2 stated clock frequency. Note 3: The offset voltage is specified for the entire filter. Offset is virtually independent of Q and fCLK/f0 ratio setting. The test clock frequency for mode 3 is 175kHz for the MAX260 and 750kHz for the MAX261/MAX262. Note 4: Output noise is measured with an RC output smoothing filter at 4 f0 to remove clock feedthrough. Note 5: TTL logic levels are: HIGH = 2.4V, LOW = 0.8V. CMOS logic levels are: HIGH = 5V, LOW = 0V. Power supply current is typically 4mA higher with TTL logic and clock input levels. Note 6: On the MAX260 only, the HP output signal swing is typically 0.75V less than the LP or BP outputs. Note 7: At 2.5V supplies, the f0 range and maximum clock frequency are typically 75% of values listed in Table 1. Note 8: fCLK/f0 and Q accuracy are a function of the accuracy of internal capacitor ratios. No increase in error is expected at 2.5V as compared to 5V; however, these parameters are only tested to the extent indicated by the MIN or MAX limits. INTERFACE SPECIFICATIONS (Note 9) (V+ = +5V, V+ = -5V, TA = +25C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP 150 UNITS WR Pulse Width tWR 250 Address Setup tAS 25 ns Address Hold tAH 0 ns Data Setup tDS 100 50 ns Data Hold tDH 10 0 ns Logic Input High VIH WR, D0, D1, A0-A3, CLKA, CLKB TA =TMIN to TMAX Logic Input Low VIL WR, D0, D1, A0-A3, CLKA, CLKB TA =TMIN to TMAX Input Leakage Current IIN WR, D0, D1, A0-A3, CLKB CLKA TA =TMIN to TMAX Input Capacitance CIN WR, D0, D1, A0-A3, CLKA, CLKB ns 2.4 V 0.8 V 10 6 Note 9: Interface timing specifications are guaranteed by design and are not subject to test. 4 MAX _______________________________________________________________________________________ 60 A 15 pF Microprocessor Programmable Universal Active Filters PIN PIN MAX260 MAX261/ MAX262 NAME 9 9 V 17 18 11 12 16 17 11 12 FUNCTION MAX260 MAX261/ MAX262 NAME FUNCTION 5, 23 5, 23 INA, INB Filter inputs + Positive supply voltage - Negative supply voltage 1, 21 1, 21 BPA, BPB Bandpass outputs Analog Ground. Connect to the system ground for dual supply operation or mid-supply for single supply operation. GND should be well bypassed in single supply applications. Input to the oscillator and clock input to section A. This clock is internally divided by 2. Clock input to filter B. This clock is internally divided by 2. 24, 22 24, 22 LPA, LPB Lowpass outputs 3, 14 3, 20 HPA, HPB Highpass/notch/allpass outputs V GND CLKA CLKB 8 8 CLK OUT Clock output for crystal and R-C oscillator operation 19 18 OSC OUT Connects to crystal or R-C for self-clocked operation 16 15 WR 15, 13, 10, 7 14, 13, 10, 7 A0, A1, A2, A3 20, 6 19, 6 D0, D1 2 OP OUT 4 OP IN Write enable input Address inputs for f0 and Q input data locations Data inputs for f0 and Q programming Output of uncommitted op amp on MAX261/ MAX262 only. Pin 2 is a noconnect on the MAX260. Inverting input of uncommitted op amp on MAX261/ MAX262 only (noninverting input is internally connected to ground). Pin 4 is a noconnect on the MAX260. _______________________________________________________________________________________ 5 MAX260/MAX261/MAX262 Pin Description Typical Operating Characteristics (TA = +25C, unless otherwise noted.) 20 0 CLOCK (5V, 0V) 18 IDD (mA) 15 CLOCK (2.4V, 0.8V) 19 CLOCKS (5V, 0V) MODES 2 & 3 10 CLK FREQ = 500KHz 25C CONTROL PINS (5V, 0V) IDD (mA) Q ERROR (%) 20 MODE 4 20 MAX260/61/62 toc02 5V 25C Q=8 fCLK/f0 N = 0 IDD vs. CLOCK FREQUENCY IDD vs. POWER SUPPLY VOLTAGE 25 MAX260/61/62 toc01 30 MAX260/61/62 toc03 Q ERROR vs. CLOCK FREQUENCY MAX260 MODE 1 5V CONTROL PINS (5V, 0V) 25C 17 16 CLOCK (5V, -5V) -10 15 CLOCKS (5V, -5V) 10 14 0.4 0.6 1.2 5 1.4 6 7 8 9 10 11 12 1.5 2.5 3.5 Q ERROR vs. CLOCK FREQUENCY MAX261/MAX262 FCLK/F0 ERROR vs. CLOCK FREQUENCY MAX261/MAX262 OUTPUT SIGNAL SWING vs. CLOCK FREQUENCY MODE 2 5V Q=8 TA = 25C -0.2 -0.4 -0.6 MODES 1, 4 fCLK N=0 f0 -0.8 -1.0 0 MODES 1, 4 -4 8 MAX261/MAX262 ALL MODES PEAK TO PEAK, OUTPUT SWING (V) 12 MODES 2, 3 0 FCLK/F0 ERROR (%) MODE 3 8 0.2 MAX260/61/62 toc05 CLOCK FREQUENCY (MHz) 4 7 6 5 MAX260 MODE 4 4 5V 25C Q=8 fCLK/f0 N = 0 3 2 1 -1.2 MAX260 MODES 1, 2, 3 0 0.5 1.0 1.5 2.0 2.5 3.0 1.0 3.5 1.5 2.0 2.5 3.0 3.5 MAX261/ MAX262 Note 1: Note 2: Note 3: 0.6 Q=1 Q=8 1.0 1.4 1.8 2.2 2.8 3.0 CLOCK FREQUENCY (MHz) Wideband RMS Noise (db ref. to 2.47VRMS, 7VP-P) 5V Supplies MODE 0.2 CLOCK FREQUENCY (MHz) CLOCK FREQUENCY (MHz) 6 0.5 V+ TO V- (V) MAX260/61/62 toc04 16 1.0 CLOCK FREQUENCY (MHz) 5V Q=8 TA = 25C fCLK N=0 f0 20 0.8 MAX260/61/62 toc06 0.2 Q ERROR (%) 13 5 -20 MAX260 MAX260/MAX261/MAX262 Microprocessor Programmable Universal Active Filters Noise Spectral Distribution Q = 64 LP BP HP/AP/N LP BP HP/AP/N LP BP HP/AP/N 1 -84 -90 -84 -80 -82 -85 -72 -73 -85 2 -88 -90 -88 -84 -82 -84 -77 -73 -76 3 -84 -90 -88 -80 -82 -82 -73 -73 -74 4 -83 -89 -84 -79 -81 -85 -71 -73 -85 1 -87 -89 -86 -81 -81 -86 -73 -73 -86 2 -89 -88 -85 -83 -80 -82 -75 -72 -74 3 -87 -88 -85 -80 -82 -80 -71 -72 -72 (MAX261, fCLK = 1MHz, dB ref. to 2.47VRMS, 7VP-P) MEASUREMENT Q = 1 Q = 8 Q = 64 BANDWIDTH Wideband -84 -80 -72 3kHz -87 -87 -86 C Message Weighted -93 -93 -93 4 -87 -88 -86 -81 -81 -86 -71 -72 -86 fCLK = 1MHz for MAX261/MAX262, fCLK = 350kHz for MAX260 fCLK/f0 ratio programmed at N = 63 (see Table 2) Clock feedthrough is removed with an RC lowpass ar 4f0, ie., R = 3.9k, C = 2000pF for MAX261. _______________________________________________________________________________________ Microprocessor Programmable Universal Active Filters SCN = SWITCH-CAPACITOR NETWORK N/HP/AP SAMPLE-HOLD MAX260 ONLY S1 SCN BP IN - SCN + + S1 S2 LP S2 S3 MODE SELECT SCN S3 M0 M1 SCN Q0-Q6 (TABLE 3) F0-F5 (TABLE 2) Figure 1. Filter Block Diagram (One Second-Order Section) Introduction Each MAX260/MAX261/MAX262 contains two secondorder switched-capacitor active filters. Figure 1 shows the filter's state variable topology, employed with two cascaded integrators and one summing amplifier. The MAX261 and MAX262 also contain an uncommitted amplifier. On-chip switches and capacitors provide feedback to-control each filter section's f 0 and Q. Internal capacitor ratios are primarily responsible for the accuracy of these parameters. Although these switched-capacitor networks (SCN) are in fact sampled systems, their behavior very closely matches that of continuous filters, such as RC active filters. The ratio of the clock frequency to the filter center frequency (fCLK/f0) is kept large so that ideal second-order statevariable response is maintained. The MAX262 uses a lower range of sampling (fCLK/f0) ratios than the MAX260 or MAX261 to allow higher operating f0 frequencies and signal bandwidths. These reduced sample rates result in somewhat more deviation from ideal continuous filter parameters than with the MAX260/MAX261. However, these differences can be compensated using Figure 20 (see Application Hints) or Maxim's filter design software. The MAX260 employs auto-zero circuitry not included in the MAX261 or MAX262. This provides improved DC characteristics, and improved low-frequency perform- ance at the expense of high-end f0 and signal bandwidth. The N/HP/AP outputs of the MAX260 are internally sample-and-held as a result of its auto-zero operation. Signal swing at this output is somewhat reduced as a result (MAX260 only). See Table 1 for bandwidth comparisons of the three filters. Maxim also provides design programs that aid in converting filter response specifications into the f0 and Q program codes used by the MAX260 series devices. This software also precompensates f0 and Q when low sample rates are used. It is important to note that, in all MAX260 series filters, the filter's internal sample rate is one half the input clock rate (CLKA or CLKB) due to an internal division by two. All clock-related data, tables, and other discussions in this data sheet refer to the frequency at the CLKA or CLKB input, i.e., twice the internal sample rate, unless specifically stated otherwise. Quick Look Design Procedure The MAX260, MAX261, and MAX262, with Maxim's filter design software, greatly simplify the design procedures for many active filters. Most designs can be realized using a three-step process described in this section. If the design software is not used, or if the filter complexity is beyond the scope of this section, refer to the remainder of this data sheet for more detailed applications and design information. _______________________________________________________________________________________ 7 MAX260/MAX261/MAX262 S-H MAX260/MAX261/MAX262 Microprocessor Programmable Universal Active Filters 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 260 270 280 290 300 310 IN AB$ = "FILTER A" : GOSUB 150 : REM GET DATA FOR SECTION A ADD = 0 : GOSUB 220 : REM WRITE DATA TO THE PRINTER PORT AB$ = "FILTER B" : GOSUB 150 : REM GET DATA FOR B ADD = 32 : GOSUB 220 : REM WRITE DATA TO PRINTER PORT GOTO 100 PRINT "MODE (1 to 4, see Table 5) "; AB$; : INPUT M IF M<1 OR M>4 THEN GOTO 150 PRINT "CLOCK RATIO (0 to 63, N of Table 2) "; AB$; : INPUT F IF F<0 OR F>63 THEN GOTO 170 PRINT "Q (0 to 127, N of Table 3) "; AB$; : INPUT Q IF Q<0 OR Q>127 THEN GOTO 190 ELSE : PRINT RETURN LPRINT CHR$(ADD+M-1); : ADD = ADD+4 FOR I = 1 TO 3 X = (ADD + (F - 4*INT(F/4))) : LPRINT CHR$(X); F=INT(F/4) : ADD = ADD + 4 NEXT I FOR I = 1 TO 4 X=(ADD + (Q - 4*INT(Q/4))) : LPRINT CHR$(X); Q=I (Q/4) :: ADD = ADD + 4 NEXT I RETURN 5 24 3 1 23 22 (20)14 21 WR 1 2 INA D0 LPA D1 HPA A0 MAX260 MAX261* MAX262* BPA INB A1 A2 20(19) 6 3 4 5 15(14) 6 7 25 24 23 22 21 20 19 18 13 10 11 12 LPB A3 HPB CLKA BPB CLKB OUT 16(15) V+ 18(17) 0.1F +5V DB-25 MALE PLUG (BACK VIEW) 11 12 V- GND 9 7 17(16) CLK IN 0.1F TTL -5V (SEE FIGURE 4) *PIN NUMBERS IN ( ) ARE FOR MAX261/MAX262 Figure 2. Basic Program and Hardware Connections to Parallel Printer Port for "Quick Look" Using a PC Step 1--Filter Design Start with the program "PZ" to determine what type of filter is needed. This helps determine the type (Butterworth, Chebyshev, etc.) and the number of poles for the optimum choice. The program also plots the fre8 quency response and calculates the pole/zero (f0) and Q values for each second-order section. Each MAX260/MAX261/MAX262 contains two second-order sections, and devices can be cascaded for higher order filters. _______________________________________________________________________________________ Microprocessor Programmable Universal Active Filters Starting with the f0 and Q values obtained in Step 1, use the program "MPP" to generate the digital coefficients that program each second-order section's f0 and Q. The program displays values for "N" ("N = _ for f0" and "N = _ for Q"). N is the decimal equivalent of the binary code that sets the filter section's f0 or Q. These are the same "N"s that are listed in Tables 2 and 3. An input clock frequency and filter mode must also be selected in this step; however, if a specific-clock rate is not selected, "GEN" picks one. With regard to mode selection, mode 1 is the most convenient choice for most bandpass and lowpass filters. Exceptions are elliptic bandpass and lowpass filters, which require mode 3. Highpass filters also use mode 3, while allpass filters use mode 4. For further information regarding these filter modes, see the Filter Operating Modes section. Step 3--Loading the Filter When the N values for the f0 and Q of each secondorder filter section are determined, the filter can then be programmed and operated. What follows is a convenient method of programming the filter and evaluating a design if a PC is available. A short BASIC program loads data into the MAX260/ MAX261/MAX262 through the PC's parallel printer port. The program asks for the filter mode, as well as the N values for the f0 and Q of each section. These coefficients are then loaded into the filter in the form of ASCII characters. This program can be used with or without Maxim's other filter design software. The program and the appropriate hardware connections for a Centronicstype printer port are shown in Figure 2. Filter Design Software Maxim provides software programs to help speed the transition from frequency response design requirements to working hardware. A series of programs are available, including: Program PZ. Given the requirements, such as center frequency, Q, passband ripple, and stopband attenuation, PZ calculates the pole frequencies, Q's, zeros, and the number of stages needed. Program MPP. For programmed filters, MPP computes the input codes to use and describes the expected performance of the design. Program FR. When a design of one or more stages is completed, FR checks the final cascaded assembly. The output frequency response can be compared with that expected from PZ. Program PR.BAS Allows a MAX260/MAX261/MAX262 to be programmed through a personal computer. The mode, f0, and Q of each section are typed in, and the proper codes are sent to the filter through the computer's parallel printer port. This program is also provided in Figure 2. Other design programs are also included for use with other Maxim filter products. Other Filter Products Maxim has developed a number of other filter products in addition to the MAX260, MAX261, and MAX262. PIN-PROGRAMMABLE ACTIVE FILTERS--A dual second-order universal filter that needs no external components. A microprocessor interface is not required. MAX263 0.4Hz to 30kHz f0 range MAX264 1Hz to 75kHz f0 range RESISTOR AND PIN-PROGRAMMABLE FILTERS--A dual second-order universal filter where f0 adjustment beyond pin-programmable resolution employs external resistors. MAX265 0.4Hz to 30kHz f 0 range. Includes two uncommitted op amps. MAX266 1Hz to 75kHz f 0 range. Includes two uncommitted op amps. MF10 Industry Standard, Resistor Programmed Only PIN-PROGRAMMABLE BANDPASS FILTERS--A dual second-order bandpass that needs no external components. A microprocessor interface is not required. MAX267 0.4Hz to 30kHz f0 range MAX268 1Hz to 75kHz f0 range PROGRAMMABLE ANTI-ALIAS FILTER--A programmable dual second-order continuous (not switched) lowpass filter. No clock noise is generated. Designed for use as an anti-alias filter in front of, or as a smoothing filter following, any sampled filter or system. MAX270 1kHz to 25kHz Cutoff Frequency Range 5th-ORDER LOW PASS FILTER--Features zero offset and drift errors for designs requiring high DC accuracy. MAX280, LT1062 0.1Hz to 20kHz Cutoff Frequency Range _______________________________________________________________________________________ 9 MAX260/MAX261/MAX262 Step 2--Generate Programming Coefficients MAX260/MAX261/MAX262 Microprocessor Programmable Universal Active Filters Table 1. Typical Clock and Center Frequency Limits PART MAX260 Q MODE fCLK 8 3 40Hz-1.7MHz 0.4Hz-17kHz 4 40Hz-2.7MHz 0.4Hz-27kHz 1 40Hz-2.0MHz 0.4Hz-20kHz 0.4Hz-18kHz MODE 1 1 1Hz-400kHz 0.01Hz-4.0kHz 1 2 1Hz-425kHz 0.01Hz-6.0kHz 8 64 90 fCLK f0 f0 1 3 1Hz-500kHz 0.01Hz-5.0kHz 1 4 1Hz-400kHz 0.01Hz-4.0kHz 2 40Hz-1.2MHz 8 1 1Hz-500kHz 64 3 40Hz-1.2MHz 0.4Hz-12kHz 64 4 40Hz-2.0MHz 0.4Hz-20kHz MAX261 8 2 1Hz-700kHz 0.01Hz-5.0kHz 0.01Hz-10.0kH 8 3 1Hz-700kHz 0.01Hz-5.0kHz 1 1 40Hz-4.0MHz 1.0Hz-100kHz 8 4 1Hz-600kHz 0.01Hz-4.0kHz 1 2 40Hz-4.0MHz 1.4Hz-140kHz 3 40Hz-4.0MHz 1.0Hz-100kHz 64 1 1Hz-750kHz 0.01Hz-7.5kHz 1 90 2 1Hz-500kHz 0.01Hz-7.0kHz 1 4 40Hz-4.0MHz 1.0Hz-100kHz 64 3 1Hz-400kHz 0.01Hz-4.0kHz 8 1 40Hz-2.5MHz 1.0Hz-60kHz 0.01Hz-7.5kHz 6 2 40Hz-1.4MHz 1.4Hz-50kHz 8 3 40Hz-1.4MHz 1.0Hz-35kHz 64 4 1Hz-750kHz MAX262 1 1 40Hz-4.0MHz 0.4Hz-40kHz 1 2 40Hz-4.0MHz 0.5Hz-57kHz 8 4 40Hz-2.5MHz 1.0Hz-60kHz 0.4Hz-40kHz 64 1 40Hz-1.5MHz 1.0Hz-37kHz 90 2 40Hz-0.9MHz 1.4Hz-32kHz 1 MAX261 PART Q 3 40Hz-4.0MHz 1 4 40Hz-4.0MHz 0.4Hz-40kHz 8 1 40Hz-2.7MHz 0.4Hz-27kHz 64 3 40Hz-0.9MHz 1.0Hz-22kHz 8 2 40Hz-2.1MHz 0.5Hz-30kHz 64 4 40Hz-1.5MHz 1.0Hz-37kHz INA N/HP/APA INB LPA BPA N/HP/APB LPB BPB V+ MODE 2 f0 Q 6 MODE CK 7 A PROGRAM MEMORY MODE, f0, Q f0 2 /2 VQ 6 B PROGRAM MEMORY MODE, f0, Q GND CK 7 /2 MAX261/MAX262 ONLY 15 15 + INTERFACE LOGIC 2 4 D0, D1 A0-A3 WR CLKA OSC OUT CLK OUT CLKB OP IN Figure 3. MAX260/MAX261/MAX262 Block Diagram 10 ______________________________________________________________________________________ OP OUT Microprocessor Programmable Universal Active Filters fCLK/f0 RATIO MAX260/MAX261 MAX262 MODES 1,3,4 MODE 2 MODES 1,3,4 MODE 2 100.53 71.09 40.84 28.88 102.10 72.20 42.41 29.99 103.67 73.31 43.98 31.10 105.24 74.42 45.55 32.21 106.81 75.53 47.12 33.32 108.38 76.64 48.69 34.43 109.96 77.75 50.27 35.54 111.53 78.86 51.84 36.65 113.10 79.97 53.41 37.76 114.67 81.08 54.98 38.87 116.24 82.19 56.55 39.99 117.81 83.30 58.12 41.10 119.38 84.42 59.69 42.21 120.95 85.53 61.26 43.32 122.52 86.64 62.83 44.43 124.09 87.75 64.40 45.54 125.66 88.86 65.97 46.65 127.23 89.97 67.54 47.76 128.81 91.80 69.12 48.87 130.38 92.19 70.69 49.98 131.95 93.30 72.26 51.10 133.52 94.41 73.83 52.20 135.08 95.52 75.40 53.31 136.66 96.63 76.97 54.43 138.23 97.74 78.53 55.54 139.80 98.86 80.11 56.65 141.37 99.97 81.68 57.76 142.94 101.08 83.25 58.87 14.4.51 102.89 84.82 59.98 146.08 103.30 86.39 61.09 147.65 104.41 87.96 62.20 149.23 105.52 89.54 63.31 150.80 106.63 91.11 64.42 152.37 107.74 92.68 65.53 153.98 108.85 94.25 66.64 155.51 109.96 95.82 67.75 157.08 111.07 97.39 68.86 158.65 112.18 98.96 69.98 160.22 113.29 100.53 71.09 161.79 114.41 102.10 72.20 163.36 115.52 102.67 73.31 164.93 116.63 105.24 74.42 166.50 117.74 106.81 75.53 168.08 118.85 108.38 76.64 169.65 119.96 109.96 77.75 171.22 121.07 111.53 78.86 PROGRAM CODE N 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 F5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 F4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 F2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 F1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 ______________________________________________________________________________________ F0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 11 MAX260/MAX261/MAX262 Table 2. fCLK/f0 Program Selection Table MAX260/MAX261/MAX262 Microprocessor Programmable Universal Active Filters Table 2. fCLK/f0 Program Selection Table (continued) fCLK/f0 RATIO MAX260/MAX261 MAX262 MODES 1,3,4 MODE 2 MODES 1,3,4 MODE 2 172.79 122.18 113.10 79.97 174.36 123.29 114.66 81.08 175.93 124.40 11624 82.19 177.50 125.51 117.81 83.30 179.07 126.62 119.38 84.41 180.64 127.73 120.95 85.53 182.21 128.84 122.52 86.64 183.78 129.96 124.09 87.75 185.35 131.07 125.66 88.86 186.92 132.18 127.23 89.97 188.49 133.29 128.81 91.08 190.07 134.40 130.38 92.19 191.64 135.51 131.95 93.30 193.21 136.62 133.52 94.41 194.78 137.73 135.09 95.52 196.35 138.84 136.66 96.63 197.92 139.95 138.23 97.74 199.49 141.06 139.80 98.85 PROGRAM CODE N 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 F5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 F4 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 F3 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 F2 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 F1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 F0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Note 1: For the MAX260/MAX261, fCLK/f0 = (64 + N) / 2 in modes 1, 3, and 4, where N varies from 0 to 63. Note 2: For the MAX262, fCLK/f0 = (26 s N) / 2 in modes 1, 3, and 4, where N varies 0 to 63. Note 3: In mode 2, all fCLK/f0 ratios are divided by 2. The functions are then: MAX260/MAX261 fCLK/f0 = 1.11072 (64 + N), MAX262 fCLK/f0 = 1.11072 (26 + N) Detailed Description f0 and Q Programming Figure 3 shows a block diagram of the MAX260. Each second-order filter section has its own clock input and independent f0 and Q control. The actual center frequency is a function of the filter's clock rate, 6-bit f0 control word (see Table 2), and operating mode. The Q of each section is also set by a separate programmed input (see Table 3). This way, each half of a MAX260/ MAX261/MAX262 is tuned independently so that complex filter polynomials can be realized. Equations that convert program code numbers to fCLK/f0 and Q values are listed in the notes beneath Tables 2 and 3. Oscillator and Clock Inputs The clock circuitry of the MAX260/MAX261/MAX262 can operate with a crystal, resistor-capacitor (RC) network, or an external clock generator as shown in Figure 4. If an RC oscillator is used, the clock rate, fCLK, nominally equals 0.45/RC. 12 The duty cycle of the clock at CLKA and CLKB is unimportant because the input is internally divided by 2 to generate the sampling clock for each filter section. It is important to note that this internal division also halves the sample rate when considering aliasing and other sampled system phenomenon. Microprocessor Interface f0, Q, and mode-selection data are stored in internal program memory. The memory contents are updated by writing to addresses selected by A0-A3. D0, and D1 are the data inputs. A map of the memory locations is shown in Table 4. Data is stored in the selected address on the rising edge of WR. Address and data inputs are TTL and CMOS compatible when the filter is powered from 5V. With other power supply voltages, CMOS logic levels should be used. Interface timing is shown in Figure 5. Note: Clock inputs CLKA and CLKB have no relation to the digital interface. They control the switched-capacitor filter sample rate only. Some noise may be generated on the filter outputs by transitions at the logic inputs. If this is objectionable, ______________________________________________________________________________________ Microprocessor Programmable Universal Active Filters PROGRAMMED Q PROGRAMMED Q PROGRAM CODE MODES 1,3,4 MODE 2 N 0.500* 0.707* 0* Q6 Q5 Q4 Q3 0 0 0 0 PROGRAM CODE Q2 Q1 Q0 MODES 1,3,4 MODE 2 N 0 0 0 0.615 0.870 24 0 0 1 0.879 25 0 0 1 Q6 Q5 Q4 Q3 Q2 Q1 Q0 1 0 0 0 1 0 0 1 0.504 0.713 1 0 0 0 0 0 0 1 0.621 0.508 0.718 2 0 0 0 0 0 1 0 0.627 0.887 26 0 0 1 1 0 1 0 0.512 0.724 3 0 0 0 0 0 1 1 0.634 0.896 27 0 0 1 1 0 1 1 0.905 28 0 0 1 1 1 0 0 0.516 0.730 4 0 0 0 0 1 0 0 0.640 0.520 0.736 5 0 0 0 0 1 0 1 0.646 0.914 29 0 0 1 1 1 0 1 0.525 0.742 6 0 0 0 0 1 1 0 0.653 0.924 30 0 0 1 1 1 1 0 0 0 1 1 1 1 1 0.529 0.748 7 0 0 0 0 1 1 1 0.660 0.933 31 0.533 0.754 8 0 0 0 1 0 0 0 0.667 0.943 32 0 1 0 0 0 0 0 0.538 0.761 9 0 0 0 1 0 0 1 0.674 0.953 33 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0.542 0.767 10 0 0 0 1 0 1 0 0.681 0.963 34 0.547 0.774 11 0 0 0 1 0 1 1 0.688 0.973 35 0 1 0 0 0 1 1 0.552 0.780 12 0 0 0 1 1 0 0 0.696 0.984 36 0 1 0 0 1 0 0 0 1 0 0 1 0 1 0.556 0.787 13 0 0 0 1 1 0 1 0.703 0.995 37 0.561 0.794 14 0 0 0 1 1 1 0 0.711 1.01 38 0 1 0 0 1 1 0 0.566 0.801 15 0 0 0 1 1 1 1 0.719 1.02 39 0 1 0 0 1 1 1 1.03 40 0 1 0 1 0 0 0 1 0.571 0.808 16 0 0 1 0 0 0 0 0.727 0.577 0.815 17 0 0 1 0 0 0 1 0.736 1.04 41 0 1 0 1 0 0 0.582 0.823 18 0 0 1 0 0 1 0 0.744 1.05 42 0 1 0 1 0 1 0 0.587 0.830 19 0 0 1 0 0 1 1 0.753 1.06 43 0 1 0 1 0 1 1 0.593 0.838 20 0 0 1 0 1 0 0 0.762 1.08 44 0 1 0 1 1 0 0 0.598 0.646 21 0 0 1 0 1 0 1 0.771 1.09 45 0 1 0 1 1 0 1 0.604 0.854 22 0 0 1 0 1 1 0 0.780 1.10 46 0 1 0 1 1 1 0 1 0.790 1.12 47 0 1 0 1 1 1 1 0.609 0.862 23 0 0 1 0 1 1 Note 4: * Writing all 0s into Q0A-Q6A on Filter A activates a low-power shutdown mode. BOTH filter sections are deactivated. Therefore, this Q value is only achievable in filter B. ______________________________________________________________________________________ 13 MAX260/MAX261/MAX262 Table 3. Q Program Selection Table MAX260/MAX261/MAX262 Microprocessor Programmable Universal Active Filters Table 3. Q Program Selection Table (continued) PROGRAMMED Q MODES MODE 1,3,4 2 0.800 1.13 0.810 1.15 0.821 1.16 0.831 1.18 0.842 1.19 0.853 1.21 0.865 1.22 0.877 1.24 0.889 1.26 0.901 1.27 0.914 1.29 0.928 1.31 0.941 1.33 0.955 1.35 0.969 1.37 0.985 1.39 1.00 1.41 1.02 1.44 1.03 1.46 1.05 1.48 1.07 1.51 1.08 1.53 1.10 1.56 1.12 1.59 1.14 1.62 1.16 1.65 1.19 1.68 1.21 1.71 1.23 1.74 1.25 1.77 1.28 1.81 1.31 1.85 1.33 1.89 1.36 1.93 1.39 1.97 1.42 2.01 1.45 2.06 1.49 2.10 1.52 2.16 1.56 2.21 Notes 14 PROGRAM CODE N Q6 Q5 Q4 Q3 Q2 Q1 Q0 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PROGRAMMED Q MODES MODE 1,3,4 2 1.60 2.26 1.64 2.32 1.68 2.40 1.73 2.45 1.78 2.51 1.83 2.59 1.88 2.66 1.94 2.74 2.00 2.83 2.06 2.92 2.13 3.02 2.21 3.12 2.29 3.23 2.37 3.35 2.46 3.48 2.56 3.62 2.67 3.77 2.78 3.96 2.91 4.11 3.05 4.31 3.20 4.53 3.37 4.76 3.56 5.03 3.76 5.32 4.00 5.66 4.27 6.03 4.57 6.46 4.92 6.96 5.33 7.54 5.82 8.23 6.40 9.05 7.11 10.1 8.00 11.3 9.14 12.9 10.7 15.1 12.8 18.1 16.0 22.6 21.3 30.2 32.0 45.3 64.0 90.5 PROGRAM CODE N Q6 Q5 Q4 Q3 Q2 Q1 Q0 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 5) In modes 1, 3, and 4: Q = 64 / (128 - N) 6) In mode 2, the listed Q values are those of mode 1 multiplied by 2. Then Q = 90.51 / (128 - N) ______________________________________________________________________________________ Microprocessor Programmable Universal Active Filters FILTER A FILTER B OSC OUT CLKA 11 19(18)* CLK OUT CLKB 8 12 CRYSTAL *OSC OUT IS PIN 18 ON MAX261/MAX262 FILTER A FILTER B OSC OUT CLKA 19(18)* 11 R C CLK OUT CLKB 12 8 fCLK = 0.45 RC FILTER A FILTER B CLKA 11 OSC OUT N.C. DATA BIT D0 D1 FILTER A M0A M1A F0A F1A F2A F3A F4A F5A Q0A Q1A Q2A Q3A Q4A Q5A Q6A FILTER B M0B M1B F0B F1B F2B F3B F4B F5B Q0B Q1B Q2B Q3B Q4B Q5B Q6B A3 ADDRESS A2 A1 LOCATION A0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8 9 10 11 12 13 14 15 Note: Writing 0 into Q0A-Q6A (address locations 4-7) on filter A activates shutdown mode. BOTH filter sections deactivate. CLK OUT CLKB 12 N.C. tAH tAS EXTERNAL CLOCK IN (ANY DUTY CYCLE) A0-A3 VALID ADDRESS Figure 4. Clock Input Connections tWR WR the digital lines should be buffered from the device by logic gates as shown in Figure 6. Shutdown Mode The MAX260/MAX261/MAX262 enters a shutdown/ standby mode when all zeroes are written to the Q addresses of filter A (Q0 A -Q6 A ). When shut down, power consumption with 5V supplies typically drops to 10mW. When reactivating the filter after shutdown, allow 2ms to return to full operation. Filter Operating Modes There are several ways in which the summing amplifier and integrators in each MAX260/MAX261/MAX262 filter section can be configured. The four most versatile interconnections (modes) are selected by writing to tDS D0, D1 tDH VALID DATA SEE INTERFACE SPECIFICATIONS FOR TIMING LIMITS Figure 5. Interface Timing inputs M0 and M1 (see Tables 4 and 5). These modes use no external components. A fifth mode, 3A, makes use of an additional op amp (included in the MAX261 and MAX262) and external resistors, but uses the same internal configuration and is selected with the same programming code, as mode 3. ______________________________________________________________________________________ 15 MAX260/MAX261/MAX262 Table 4. Program Address Locations +5V -5V MODE 1 OCTAL D FLIP-FLOP 74HC374 20 3 A0 4 A1 7 A2 8 A3 13 D1 14 D2 V+ VCC 1D 1Q 2D 2Q 3D 3Q 4D 4Q 5D 5Q 6D 6Q OC 1 N SCN GND 2 V- - SCN + + 5 A2 9 A3 12 MAX260 MAX261 MAX262 LP SCN SCN = SWITCHED-CAPACITOR NETWORK D1 15 - A1 6 BP - IN A0 Figure 7. Filter Mode 1: Second-Order Bandpass, Lowpass, and Notch D2 CK 10 different modes if desired. The f0, fN (notch), Q, and various output gains in each case are shown in Table 5. 11 WR WR GND Filter Mode Selection -5V Figure 6. Buffering/Latching Logic Inputs Figures 7 through 11 show symbolic representations of the MAX260 filter modes. Only one second-order section is shown in each case. The A and B sections of one MAX260/MAX261/MAX262 can be programmed for MODE 1 (Figure 7) is useful when implementing allpole lowpass and bandpass filters such as Butterworth, Chebyshev, Basset, etc. It can also be used for notch filters, but only second-order notches because the relative pole and zero locations are fixed. Higher order notch filters require more latitude in f0 and 1N, which is why they are more easily implemented with mode 3A. Table 5. Filter Modes for Second-Order Functions M1, M0 FILTER FUNCTIONS 1 2 3 0, 0 0, 1 1, 0 LP, BP, N LP, BP, N LP, BP, HP 4 Notes: 1, 1 f0 Q SEE TABLE 3 MODE SEE TABLE 2 MAX260/MAX261/MAX262 Microprocessor Programmable Universal Active Filters f0 LP, BP, AP fN H OLP H OBP f0 f02 -1 -0.5 -1 -Q -Q/2 -Q -1 -Q -2 -2Q RH RL H ON1 (f 0) H ON2 (f fCLK/4) -1 -0.5 -1 -1 HOHP = -1 R + G RL R + G RH f0 = Center Frequency HON1 = Notch Gain as f approaches DC fN = Notch Frequency HON2 = Notch Gain as f approaches fCLK/4 HOLP = Lowpass Gain at DC HOAP = Allpass Gain HOBP = Bandpass Gain at f0 fz, Qz = f and Q of Complex Pole Pair HOHP = Highpass Gain as f approaches fCLK/4 16 OTHER ______________________________________________________________________________________ HOHP = -1 HOAP = -1 fZ = f0, QZ = Q Microprocessor Programmable Universal Active Filters N SCN RG RH BP - IN SCN - + + + LP - HP SCN SCN + SCN Figure 8. Filter Mode 2: Second-Order Bandpass, Lowpass, and Notch BP - IN SCN N RL + LP - SCN SCN MODE 3 SCN = SWITCHED-CAPACITOR NETWORK HP SCN BP - IN SCN + + LP - SCN SCN SCN = SWITCHED-CAPACITOR NETWORK Figure 9. Filter Mode 3: Second-Order Bandpass, Lowpass, and Highpass Mode 1, along with mode 4, supports the highest clock frequencies (see Table 1) because the input summing amplifier is outside the filter's resonant loop (Figure 7). The gain of the lowpass and notch outputs is 1, while the bandpass gain at the center frequency is Q. For bandpass gains other than Q, the filter input or output can be scaled by a resistive divider or op amp. MODE 2 (Figure 8) is used for all-pole lowpass and bandpass filters. Key advantages compared to mode 1 are higher available Qs (see Table 3) and lower output noise. Mode 2's available fCLK/f0 ratios are 2 less than with mode 1 (see Table 2), so a wider overall range of f 0s can be selected from a single clock when both modes are used together. This is demonstrated in the Wide Passband Chebyshev Bandpass design example. Figure 10. Filter Mode 3a: Second-Order Bandpass, Lowpass, Highpass, and Notch. For elliptic LP, BP, HP, and Notch, the N output is used. MODE 3 (Figure 9) is the only mode that produces high-pass filters. The maximum clock frequency is somewhat less than with mode 1 (see Table 1). MODE 3A (Figure 10) uses a separate op amp to sum the highpass and lowpass outputs of mode 3, creating a separate notch output. This output allows the notch to be set independently of f0 by adjusting the op amp's feedback resistor ratio (RH, RL). RH, RL, and RG are external resistors. Because the notch can be independently set, mode 3A is also useful when designing pole-zero filters such as elliptics. MODE 4 (Figure 11) is the only mode that provides an allpass output. This is useful when implementing group delay equalization. In addition to this, mode 4 can also be used in all pole lowpass and bandpass filters. Along with mode 1, it is the fastest operating mode for the filter, although the gains are different than in mode 1. When the allpass function is used, note that some amplitude peaking occurs (approximately 0.3dB when Q = 8) at f0. Also note that f0 and Q sampling errors are highest in mode 4 (see Figure 20). ______________________________________________________________________________________ 17 MAX260/MAX261/MAX262 MODE 3A MODE 2 BANDPASS OUTPUT MODE 4 - IN - SCN + + LP HOBP BP AP SCN GAIN (V/V) MAX260/MAX261/MAX262 Microprocessor Programmable Universal Active Filters 0.707 HOBP fL Q = SCN = SWITCHED-CAPACITOR NETWORK Description of Filter Functions BANDPASS (Figure 12) For all pole bandpass and lowpass filters (Butterworth, Bessel, Chebyshev) use mode 1 if possible. If appropriate fCLK/f0 or Q values are not available in mode 1, mode 2 provides a selection that is closer to the required values. Mode 1, however, has the highest bandwidth (see Table 1). For pole-zero filters, such as elliptics, see mode 3A. s( o / Q) s 2 + s( o / Q) + o 2 HOBP = Bandpass output gain at = o f0 = 0 / 2 = The center frequency of the complex pole pair. Input-output phase shift is -180 at f0. Q = The quality factor of the complex pole pair. Also the ratio of f0 to -3dB bandwidth of the second-order bandpass response. LOWPASS See bandpass text. (Figure 13) G(s) = HOLP o 2 2 s + s( o / Q) + o 2 HOLP = Lowpass output gain at DC f0 = 0 / 2 HIGHPASS (Figure 14) Mode 3 is the only mode with a highpass output. It works for all pole filter types such as Butterworth, Bessel and Chebyshev. Use mode 3A for filters employing both poles and zeros, such as elliptics. 18 fH fO , fO = fLfH fH - fL -1 + fL = fO 2Q 1 + fH = fO 2Q Figure 11. Filter Mode 4: Second-Order Bandpass, Lowpass, and Allpass G(s) = HOBP fO f(LOG SCALE) SCN 2 1 + 1 2Q 2 1 + 1 2Q Figure 12. Second-Order Bandpass Characteristics G(s) = HOHP s2 s 2 + s( o / Q) + o 2 HOHP = Highpass output gain as f approaches fCLK/4 f0 = 0 / 2 NOTCH (Figure 15) Mode 3A is recommended for multi-pole notch filters. In second-order filters, mode 1 can also be used. The advantages of mode 1 are higher bandwidth, compared to mode 3 (higher fN can be implemented), and no need for external components as required in mode 3A. s2 + n 2 s 2 + s( o / Q) + o 2 HON2 = Notch output gain as f approaches fCLK/4 HON1 = Notch output gain as f approaches DC G(s) = HON2 fn = n / 2 ALLPASS Mode 4 is the only configuration in which an allpass function can be realized. ______________________________________________________________________________________ Microprocessor Programmable Universal Active Filters GAIN (V/V) GAIN (V/V) HOP HOLP 0.707 HOLP fP HOP HOHP 0.707 HOHP fC fC fC = fO X fp = fO 1- 2 1 1 - + 1 2Q2 fC = fO 1 1 X 1 - + 2 Q 2 fp = fO 2Q2 HOP = HOLP X fP f(LOG SCALE) f(LOG SCALE) 1 1 - + 2Q2 MAX260/MAX261/MAX262 HIGHPASS OUTPUT LOWPASS OUTPUT 1- 1 1 1 1- Q 4Q2 Figure 13. Second-Order Lowpass Characteristics 2 1 1 - + 1 2Q2 1 2Q2 HOP = HOHP X 1 1 1 1- Q 4Q2 Figure 14. Second-Order Highpass Characteristics 2 - s( o / Q) + o 2 G(s) = HOAP s s 2 + s( o / Q) + o 2 HON2 HOAP = Allpass output gain for DC < f < fCLK / 4 f0 = 0 / 2 Filter Design Procedure The procedure for most filter designs is to first convert the required frequency response specifications to f0s and Qs for the appropriate number of second-order sections that implement the filter. This can be done by using design equations or tables in available literature, or can be conveniently calculated using Maxim's filter design software. Once the f0s and Qs have been found, the next step is to turn them into the digital program coefficients required by the MAX260/MAX261/ MAX262. An operating mode and clock frequency (or clock/center frequency ratio) must also be selected. Next, if the sample rate (fCLK/2) is low enough to cause significant errors, the selected f0s and Qs should be corrected to account for sampling effects by using Figure 20 or Maxim's design software. In most cases, the sampling errors are small enough to require no correction, i.e., less than 1%. In any case, with or without correction, the required f0s and Qs can then be selected from Tables 2 and 3. Maxim's filter design software GAIN (V/V) HON1 HON fN f(LOG SCALE) Figure 15. Second-Order Notch Characteristics Table 6. Cascading Identical Bandpass Filter Sections TOTAL SECTIONS TOTAL B.W. TOTAL Q 1 1.000 B 1.00 Q 2 0.644 B 1.55 Q 3 0.510 B 1.96 Q 4 0.435 B 2.30 Q 5 0.386 B 2.60 Q Note: B = individual stage bandwidth, Q = individual stage Q. ______________________________________________________________________________________ 19 MAX260/MAX261/MAX262 Microprocessor Programmable Universal Active Filters can also perform this last step. The desired f0s and Qs are stated, and the appropriate digital coefficients are supplied. Cascading Filters In some designs, such as very narrow band filters, several second-order sections with identical center frequency can be cascaded. The total Q of the resultant filter is: Q Total QT = 21/ N - 1 ( ) Q is the Q of each individual filter section, and N is the number of sections. In Table 6, the total Q and bandwidth are listed for up to five identical second-order sections. B is the bandwidth of each section. In high-order bandpass filters, stages with different f0s and Qs are also often cascaded. When this happens, the overall filter gain at the bandpass center frequency is not simply the product of the individual gains because f0, the frequency where each sections gain is specified, is different for each second-order section. The gain of each section at the cascaded filter's center frequency must be determined to obtain the total gain. For all-pole filters the gain, H(f0), as each second-order section's f0 is divided by an adjustment factor, G, to obtain that section's gain, H(f0BP), at the overall center frequency: H1(f0BP) = H(f01) / G1 = Section 1's Gain at f0BP 1/ 2 Q1(F12 - 1)2 + (F1 / Q1)2 G1 = F1 where F1 = f01 / fOBP G1, Q1, and f01 are the gain adjustment factor, Q, and f0 for the first of the cascaded second-order sections. The gain of the other sections (2, 3, etc.) at f0BP is determined the same way. The overall gain is: H(f0Bp) = H1(f0BP) x H2(f0BP) x etc. For cascaded filters with zeros (fZ) such as elliptics, the gain adjustment factor for each stage is: 1/ 2 Q1FZ12 - F12 (F12 - 1)2 + (F1 / Q1)2 G1 = F12 FZ12 - 1 where F1Z = fz1 / f0BP, and F1 is the same as above. 20 Application Hints Power Supplies The MAX260/MAX261/MAX262 can be operated with a variety of power supply configurations, including +5V to +12V single supply or 2.5V to 5V dual supplies. When a single supply is used, V- is connected to system ground and the filter's GND pin should be biased at V+/2. The input signal is then either capacitively coupled to the filter input or biased to V +/2. Figure 16 shows circuit connections for single-supply operation. When power supplies other than 5V are used, CMOS input logic levels (HIGH = V+, LOW = GND or V-) are required for WR, D0, D1, A0-A3, OLKA, and CLKB. With 5V supplies, either TTL or CMOS levels can be used. Note, however, that power consumption at 5V is reduced if CLKA and CLKB are driven with 5V, rather than TTL or 0 to 5V levels. Operation with +5V or 2.5V power lowers power consumption, but also reduces bandwidth by approximately 25% compared to +12V or 5V supplies. Best performance is achieved if V+ and V- are bypassed to ground with 4.7F electrolytic (Tantalum is preferred.) and 0.1F ceramic capacitors. These should be located as close to the supply pins as possible. The lead length of the bypass capacitors should be shortest at the V+ and V- pins. When using a single supply, V+ and GND should be bypassed to V- as shown in Figure 16. Output Swing and Clipping MAX260/MAX261/MAX262 outputs are designed to drive 10k loads. For the MAX261 and MAX262, all filter outputs swing to within 0.15V of each supply rail with a 10k load. In the MAX260 only, an internal sample-hold circuit reduces voltage swing at the N/HP/AP output compared to LP and BR. N/HP/AP, therefore, swings to within 1V (10k load) of either rail on the MAX260. To ensure that the outputs are not driven beyond their maximum range (output clipping), the peak amplitude response, individual section gains (H OBP , H OLP , HOHP), input signal level, and filter offset voltages must be carefully considered. It is especially important to check unused outputs for clipping (i.e., the lowpass output in a bandpass hookup), because overload at any filter stage severely distorts the overall response. The maximum signal swing with 4.75V supplies and a 1.0V filter offset is approximately 3.5V. For example, lets assume a fourth-order lowpass filter is being implemented with a Q of 2 using mode 1. With a single 5V supply (i.e., 2.5V with respect to chip GND) the maximum output signal is 2V (w.r.t. GND). Since in ______________________________________________________________________________________ Microprocessor Programmable Universal Active Filters MAX260/MAX261/MAX262 10k 10k + VIN 0V VIN ANY DC - SEE NOTE 7.5k 5V 0V 2.5k TO V+ CMOS LOGIC LEVELS WR A0-A3 D0, D1 INA OR INB TO GND PIN MAX260 MAX261 MAX262 5V VIN V+ +5V 0V 4.7k GND 4.7k 4.7F 0.1F 4.7F 0.1F V- NOTE: OP-AMP LEVEL SHIFT CIRCUIT HAS A GAIN OF 0.5 FROM V*. Figure 16. Power Supply and Input Connections for Single Supply Operation mode 1 the maximum signal is 0 times the input signal, the input should not exceed (2/Q)V, or 1V in this case. Clock Feedthrough and Noise Typical wideband noise for MAX260 series devices is 0.5mV P-P from DC to 100kHz. The noise is virtually independent of clock frequency. In multistage filters, the section with the highest Q should be placed first for lower output noise. The output waveform of the MAX260 series and other switched capacitor filters appears as a sampled signal with stepping or "staircasing" of the output waveform occurring at the internal sample rate (fCLK/2). This stepping, if objectionable, can be removed by adding a single-pole AC filter. With no input signal, clock-related feedthrough is approximately 8mVP-P. This can also be attenuated with an RC-smoothing filter as shown with the MAX261 in Figure 17. Some noise also can be generated at the filter outputs by transitions at the logic inputs. If this is objectionable, the digital lines should be buffered from the device by logic gates as shown in Figure 6. Input Impedance The input to each filter is the switched capacitor circuit shown in Figure 18. In the MAX260, the input capacitor charges to the input voltage VIN during the first half clock cycle. During the second half-cycle, its charge is transferred to the feedback capacitor. The resultant input impedance can be approximated by: RIN = 1 / (CINfCLK / 2) = 2 / (CINfCLK). CIN is around 12pF, hence, for a clock frequency of 500kHz, RIN = 333k. The input also has about 5pF of fixed capacitance to ground. The MAX261/MAX262 input structure is shown in Figure 19. Here CA = 12pF and CB = 0.016pF and only CB is switched, so the input resistance is 750 times larger compared to the MAX260 (R IN = 250M). The MAX261/MAX262 have a fixed capacitance of approximately 5pF to ground. f0 and Q at Low Sample Rates When low fCLK/f0 ratios and low Q settings are selected, deviation from ideal continuous filter response can be noticeable in some designs. This is due to interaction between Q and f0 at low fCLK/f0 ratios and Qs. The data in Figure 20 quantifies these differences. Since the ______________________________________________________________________________________ 21 MAX260/MAX261/MAX262 Microprocessor Programmable Universal Active Filters errors are predictable, the graphs can be used to correct the selected f0 and Q so that the actual realized parameters are on target. These predicted errors are not unique to MAX260 series devices and, in fact, occur with all types of sampled filters. Consequently, these corrections can be applied to other switched capacitor filters. In the majority of cases, the errors are not significant, i.e., less than 1%, and correction is not needed. However, the MAX262 does employ a lower range of fCLK/f0 ratios than the MAX260 or MAX261 and is more prone to sampling errors, as the tables show. Maxim's filter design software applies the previous corrections automatically as a function of desired fCLK/f0, and Q. Therefore, Figure 20 should not be used when Maxim's software determines f0 and Q. This results in overcompensation of the sampling errors since the correction factors are then counted twice. The data plotted in Figure 20 applies for modes 1 and 3. When using Figure 20 for mode 4, the f 0 error obtained from the graph should be multiplied by 1.5 and the Q error should be multiplied by 3.0. In mode 2, the value of fCLK/f0 should be multiplied by 2 and the programmed Q should be divided by 2 before using the graphs. As with all sampled systems, frequency components of the input signal above one half the sampling rate are aliased. In particular, input signal components near the sampling rate generate difference frequencies that often fall within the passband of the filter. Such aliased signals, when they appear at the output, are indistinguishable from real input information. For example, the aliased output signal generated when a 99kHz waveform is applied to a filter sampling at 100kHz (fCLK = 200kHz) is 1kHz. This waveform is an attenuated version of the output that would result from a true 1kHz input. Remember that, with the MAX260 series filters, the nyquist rate (one half the sample rate) is in fact fCLK/4, because fCLK is internally divided by two. A simple, passive RC lowpass input filter is usually sufficient to remove input frequencies that can cause aliasing. In many cases, the input signal itself may be band limited and require no special anti-alias filtering. The wideband MAX262 uses lower fCLK/f0 ratios than the MAX260/MAX261 and, for this reason, is more likely to require input filtering than the MAX260 or MAX281. Trimming DC Offset The DC offset voltage at the LP or notch output can be adjusted with the circuit in Figure 21. This circuit also uses the input op amp to implement a single-pole antialias filter. Note that the total offset is generally less in multistage filters than when only one section is used, 22 A 1V/DIV OV B 5mV/DIV OV C mV/DIV OV 1s/div TRACE B R, 10k INA BPA TRACE C C, 1000pF MAX261 TRACE A 500kHz TTL CLKA Figure 17. MAX261 Bandpass Output Clock Noise fCLK 2 CFB VIN CIN ~5pF 12pF RIN = + 2 CIN fCLK Figure 18. MAX260 Input Model fCLK 2 CB CFB 0.016pF - VIN + ~5pF CA 12pF RIN = 2 750 CA fCLK Figure 19. MAX261/MAX262 Input Model ______________________________________________________________________________________ Microprocessor Programmable Universal Active Filters fO ERROR vs. fCLK/fO RATIO (MODE 1, 3) 20 Design Examples 18 Fourth-Order Chebyshev Bandpass Filter 14 = 1kHz = 200Hz = 600Hz Max passband ripple = 0.5dB fO ERROR (%) 12 Q = 0.512 Q = 0.512 8 Q = 0.512 Q = 0.512 Q = 0.512 4 2 0 40 60 80 100 120 140 160 180 200 fCLK/fO RATIO Q ERROR vs. fCLK/fO RATIO -7 Q ERROR IS PLOTTED FOR MODES 1 AND 3 MODE 2: MULTIPLY fCLK/fO BY 2 and DIVIDE Q BY 2 BEFORE USING GRAPH MODE 4: MUTIPLY Q ERROR BY 1.5 -6 Q ERROR (%) -5 Q = 0.5 -4 Q = 0.6 Q = 0.83 -3 Q = 3.05 Q = 1.21 -2 Q = 7.11 -1 To implement this filter, both halves operate in mode 1 and use the same clock. See Tables 2 and 3. The programmed parameters are: QA = QB = 7.11 (Mode 1, N = 119) Sampling errors are very small at this fCLK/f0 ratio, so the actual realized Q is very close to 7.05 (see Figure 20 or program MPP in the Filter Design Software section). Often the realized Q is not exactly the target value at high Qs because programming resolution lowers as Q increases. This does not affect most filter designs, since three-digit Q accuracy is practically never required, and a Q resolution of 1 is provided up to Qs of 10. The overall filter gain at f0 is 16.4V/V or 24.3dB (see the Cascading Filters section). If another gain is required, amplification or attenuation must be added at the input, output, or between stages. Q = 0.512 10 6 Min stopband attenuation = 15dB From the previous parameters, the order (number of poles) and the f0 and Q of each section can be determined. Such a derivation is beyond the scope of this data sheet; however, there are a number of sources that provide design data for this procedure. These include look-up tables, design texts, and computer programs. Design software is available from Maxim to provide comprehensive solutions for most popular filter configurations. The A and B section parameters for the above filter are: f0A = 904Hz f0B = 1106Hz QA = 7.05 QB = 7.05 CLKA = CLKB = 150kHz fCLK/f0A = 166.50 (Mode 1, N = 42), actual f0A = 902.4Hz f CLK /f 0B = 136.66 (Mode 1, N = 23), actual f 0B = 1099.7Hz f0 ERROR IS PLOTTED FOR MODES 1 AND 3 MODE 2: MULTIPLY ICLKIO BY 2 and DIVIDE Q BY 2 BEFORE USING GRAPH MODE 4: MUTIPLY fO ERROR BY 1.5 16 Figure 22 shows both halves of a MAX260 cascaded to form a fourth-order Chebyshev bandpass filter. The desired parameters are: Center frequency (f0) Pass bandwidth Stop bandwidth MAX260/MAX261/MAX262 since each offset is typical negative and each section inverts. When the HP or BP outputs are used, the offset can be removed with capacitor coupling. 0 40 60 80 100 120 140 160 180 200 fCLK/fO RATIO Figure 20. Sampling Errors in fCLK/f0 and Q at Low fCLK/f0 and Q Settings C1 R2 100k VIN R1 100k R3 270k +5V + 100k -5V OFFSET TRIM GAIN = -R1/R2 1 fLP = 2R1C2 TO FILTER INPUT NOTE: OP AMP INCLUDED WITH MAX261/MAX262 Figure 21. Circuit for DC Offset Adjustment ______________________________________________________________________________________ 23 GAIN GAIN (dB) 15 -180 30 -90 15 0 -10 PHASE GAIN (dB) 40 PHASE (DEGREES) MAX260/MAX261/MAX262 Microprocessor Programmable Universal Active Filters 90 -35 200 500 1K 2K 5K -15 180 20K -60 10K -30 1K FREQUENCY (Hz) VOUT INA 1 23 BPA 21 INB CLKB 11 WR, AX, DX 12 PROGRAM CLK CLKA,B MODE fOA fOB QA QB 150kHz 1 N = 42 N = 23 N = 119 N = 119 Figure 22. Fourth-Order Chebyshev Bandpass Filter In Figure 23, a series of response curves are shown for the previous configuration using a MAX261 with clock frequencies ranging from 750kHz to 4MHz (f 0 from 500Hz to 30kHz). Note that the rightmost curve shows about 2dB of gain peaking compared to the lower frequency curves, indicating the upper limit of usable filter accuracy at this Q (see Table 1). Wide Passband Chebyshev Bandpass In this example (Figure 24), the desired parameters are: Center frequency (f0) = 1kHz Pass bandwidth = 1kHz Stop bandwidth = 3kHz Max passband ripple Min stopband attenuation 24 5K 10K 20K 50K 100K Figure 23. MAX261 Fourth-Order Chebyshev Bandpass Using Coefficients of Figure 22 BPB MAX260 CLKA 2K FREQUENCY (Hz) VIN 5 0 From the previous parameters, we use either lookup tables, design texts, or Maxim's filter design programs to generate the order (number of poles), and the f0 and Q of each second-order section. The A and B parameters are: f0A = 639Hz f0B = 1564Hz QA = 2.01 QB = 2.01 To implement this filter, section A operates in mode 1 and section B uses mode 2 to provide a wider overall range of fCLK/f0 ratios. This way, one clock frequency can drive both sections A and B. See Tables 2 and 3. CLKA = CLKB = 120kHz fCLK/f0A = 188.49 (Mode 1, N = 56), actual f0A = 636.6Hz fCLK/f0B = 76.64 (Mode 2, N = 5), actual f0B = 156.5Hz QA = 2.000 (Mode 1, N = 96), QB = 2.01 (Mode 2, N = 83) The overall passband gain at f 0 is 0.64V/V or -3.9dB. High-Frequency Chebyshev Bandpass The same Chebyshev response shape shown in Figure 24 is implemented at higher frequencies with a MAX262 in Figure 25. The curves show plots for center frequencies of 15.6kHz, 31.3kHz, and 47kHz. Not only is this faster than the MAX260 implementation, but mode 1 can be used in both halves of the MAX262 for this filter because the range of available fCLK/f0 ratios is wider with the MAX262 than the MAX260. = 1dB = 20dB ______________________________________________________________________________________ Microprocessor Programmable Universal Active Filters MAX260/MAX261/MAX262 0 -180 10 fO = 15.6kHz fCLK = 1MHz -30 0 PHASE -50 GAIN (dB) -90 PHASE (DEGREES) GAIN (dB) -10 GAIN -10 90 -20 -30 fO = 31.3kHz fCLK = 2MHz -40 fO = 47kHz fCLK = 3MHz -50 180 -70 100 200 500 1K 2K 5K 1K 10K 2K 5K 10K 20K 50K 100K FREQUENCY (Hz) FREQUENCY (Hz) VIN VIN VOUT VOUT 5 INA 1 23 BPA 5 21 INB INA 1 23 BPA 21 INB BPB BPB MAX262 MAX260 CLKA CLKA CLKB 11 WR, AX, DX 12 2 fOA fOB PROGRAM CLK PROGRAM CLKA,B MODEA MODEB 1 11 WR, AX, DX 12 CLK 120kHz CLKB QB CLKA,B MODE fOA fOB QA QB N = 83 1 to 3MHz 1 N = 38 N=0 N = 96 N = 96 QA N = 56 N = 5 N = 96 Figure 24. Wide Passband Chebyshev Bandpass Filter Fourth-Order Butterworth Lowpass Figure 26 shows a fourth-order Butterworth lowpass with a cutoff frequency of 3kHz. Sections A and B of a MAX260 are cascaded. The f0 and Q parameters for each section are: f0A = 3kHz f0B = 3kHz QA = 1.307 QB = 0.541 Mode 1 and a 400kHz clock are used. Because of low Q values, the sampling errors of Figure 20 begin to look significant in this case. From the graphs, using fCLK/f0 ratio near 133, f0A is about 4% high, f0B is 1.5% high, QA is -1.2% low, and QB is -0.5% low. If these errors are not a problem, the corrections can be ignored. They are included here for best possible accuracy: Figure 25. High-Frequency Chebyshev Bandpass Filter CLKA = CLKB = 400kHz fCLK/f0A = 135.08 (N = 22), f0B = 2961Hz (-1.3% correction) fCLK/f0B = 139.80 (N = 25), f0A = 2861Hz (-4.6% correction) QA = 1.306 (N = 79, Q resolution prevents +0.5% correction) QB = 0.547 (N = 11 +1.1% correction) Measured wideband noise for this filter is 123V RMS. If mode 2 were used, the noise would be 87V RMS. For lower noise with either mode, the first section should have the highest Q (section A in this example). ______________________________________________________________________________________ 25 MAX260/MAX261/MAX262 Microprocessor Programmable Universal Active Filters Ordering Information (continued) PART TEMP RANGE PACKAGE ACCURACY MAX261ACNG 0C to +70C Plastic DIP 1% MAX261BCNG 0C to +70C Plastic DIP 2% MAX261AENG -40C to +85C Plastic DIP 1% MAX261BENG -40C to +85C Plastic DIP 2% MAX261ACWG 0C to +70C Wide SO 1% MAX261BCWG 0C to +70C Wide SO 2% MAX261AMRG -55C to +125C CERDIP 1% MAX261BMRG -55C to +125C CERDIP 2% MAX262ACNG 0C to +70C Plastic DIP 1% MAX262BCNG 0C to +70C Plastic DIP 2% MAX262AENG -40C to +85C Plastic DIP 1% MAX2G2BENG -40C to +85C Plastic DIP 2% MAX262ACWG 0C to +70C Wide SO 1% MAX262BCWG 0C to +70C Wide SO 2% MAX262AMRG -55C to +125C CERDIP 1% MAX262BMRG -55C to +125C CERDIP 2% *All devices--24-pin packages 0.3in-wide packages Chip Topography 0.128in 3.251mm HPA(OP OUT) N.C.(HPA) BPA LPA N.C.(HPB) INB LPB BPB N.C.(OP IN) INA D1 D0 A3 0.199in (5.055mm) OSC OUT CLK OUT GND V+ A2 A1 CLKA CLKB A0 WR VHPB(N.C.) NOTE: LABELS IN PARENTHESES ( ) ARE FOR MAX261/MAX262 ONLY Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. ENGLISH * ???? * ??? * ??? WHAT'S NEW PRODUCTS SOLUTIONS DESIGN APPNOTES SUPPORT BUY COMPANY MEMBERS MAX260 Part Number Table Notes: 1. See the MAX260 QuickView Data Sheet for further information on this product family or download the MAX260 full data sheet (PDF, 952kB). 2. Other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales. 3. Didn't Find What You Need? Ask our applications engineers. Expert assistance in finding parts, usually within one business day. 4. Part number suffixes: T or T&R = tape and reel; + = RoHS/lead-free; # = RoHS/lead-exempt. More: See full data sheet or Part Naming C onventions. 5. * Some packages have variations, listed on the drawing. "PkgC ode/Variation" tells which variation the product uses. Part Number Free Sample Buy Direct Package: TYPE PINS SIZE Temp DRAWING CODE/VAR * MAX260SOFT RoHS/Lead-Free? Materials Analysis RoHS/Lead-Free: No MAX260BMRG -55C to +125C RoHS/Lead-Free: No MAX260AMRG -55C to +125C RoHS/Lead-Free: No MAX260BC NG+ PDIP;24 pin;.300" Dwg: 21-0043D (PDF) Use pkgcode/variation: N24+4* 0C to +70C RoHS/Lead-Free: Yes Materials Analysis MAX260AC NG+ PDIP;24 pin;.300" Dwg: 21-0043D (PDF) Use pkgcode/variation: N24+4* 0C to +70C RoHS/Lead-Free: Yes Materials Analysis MAX260AC NG PDIP;24 pin;.300" Dwg: 21-0043D (PDF) Use pkgcode/variation: N24-4* 0C to +70C RoHS/Lead-Free: No Materials Analysis MAX260BC NG PDIP;24 pin;.300" Dwg: 21-0043D (PDF) Use pkgcode/variation: N24-4* 0C to +70C RoHS/Lead-Free: No Materials Analysis MAX260AENG+ PDIP;24 pin;.300" Dwg: 21-0043D (PDF) Use pkgcode/variation: N24+4* -40C to +85C RoHS/Lead-Free: Yes Materials Analysis MAX260BENG PDIP;24 pin;.300" Dwg: 21-0043D (PDF) Use pkgcode/variation: N24-4* -40C to +85C RoHS/Lead-Free: No Materials Analysis MAX260BENG+ PDIP;24 pin;.300" Dwg: 21-0043D (PDF) Use pkgcode/variation: N24+4* -40C to +85C RoHS/Lead-Free: Yes Materials Analysis MAX260AENG PDIP;24 pin;.300" Dwg: 21-0043D (PDF) Use pkgcode/variation: N24-4* -40C to +85C RoHS/Lead-Free: No Materials Analysis 0C to +70C RoHS/Lead-Free: Yes MAX260AC WG+T MAX260BC WG+ SOIC ;24 pin;.300" Dwg: 21-0042B (PDF) Use pkgcode/variation: W24+3* 0C to +70C RoHS/Lead-Free: Yes Materials Analysis MAX260AC WG+ SOIC ;24 pin;.300" Dwg: 21-0042B (PDF) Use pkgcode/variation: W24+3* 0C to +70C RoHS/Lead-Free: Yes Materials Analysis 0C to +70C RoHS/Lead-Free: No MAX260AC WG-T MAX260BC WG+T SOIC ;24 pin;.300" Dwg: 21-0042B (PDF) Use pkgcode/variation: W24+3* 0C to +70C RoHS/Lead-Free: Yes Materials Analysis MAX260BC WG-T SOIC ;24 pin;.300" Dwg: 21-0042B (PDF) Use pkgcode/variation: W24-3* 0C to +70C RoHS/Lead-Free: No Materials Analysis MAX260BC WG SOIC ;24 pin;.300" Dwg: 21-0042B (PDF) Use pkgcode/variation: W24-3* 0C to +70C RoHS/Lead-Free: No Materials Analysis MAX260AC WG SOIC ;24 pin;.300" Dwg: 21-0042B (PDF) Use pkgcode/variation: W24-3* 0C to +70C RoHS/Lead-Free: No Materials Analysis MAX260BEWG+ SOIC ;24 pin;.300" Dwg: 21-0042B (PDF) Use pkgcode/variation: W24+3* -40C to +85C RoHS/Lead-Free: Yes Materials Analysis -40C to +85C RoHS/Lead-Free: Yes -40C to +85C RoHS/Lead-Free: Yes Materials Analysis -40C to +85C RoHS/Lead-Free: No MAX260AEWG+T MAX260AEWG+ MAX260AEWG-T SOIC ;24 pin;.300" Dwg: 21-0042B (PDF) Use pkgcode/variation: W24+3* MAX260AEWG SOIC ;24 pin;.300" Dwg: 21-0042B (PDF) Use pkgcode/variation: W24-3* MAX260BEWG-T MAX260BEWG SOIC ;24 pin;.300" Dwg: 21-0042B (PDF) Use pkgcode/variation: W24-3* MAX260BEWG+T -40C to +85C RoHS/Lead-Free: No Materials Analysis -40C to +85C RoHS/Lead-Free: No -40C to +85C RoHS/Lead-Free: No Materials Analysis -40C to +85C RoHS/Lead-Free: Yes Didn't Find What You Need? C ONTAC T US: SEND US AN EMAIL C opyright 2 0 0 7 by M axim I ntegrated P roduc ts , Dallas Semic onduc tor * Legal N otic es * P rivac y P olic y