DATA SH EET
Preliminary specification
Supersedes data of 1998 May 25
File under Integrated Circuits, IC01
1999 Apr 08
INTEGRATED CIRCUITS
TDA8586
Power amplifier with load detection
and auto BTL/SE selection
1999 Apr 08 2
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
FEATURES
General
•Operating voltage from 8 to 18 V
•Low distortion
•Few external components, fixed gain
•Automatic mode selection (SE or BTL) depending on
connected ‘rear’ loads
•Can be used as a stereo amplifier in Bridge-Tied Load
(BTL) or quad Single-Ended (SE) amplifiers
•Single-ended mode without loudspeaker capacitor
•Soft clipping, to guarantee good clip behaviour with
inductive loads
•Mute and standby mode with one-pin operation
•Diagnostic information for Dynamic Distortion Detector
(DDD), high temperature (140 °C) mode of operation
and short-circuit
•No switch-on/off plops when switching between standby
and mute and from mute to on
•Load detection on ‘rear’ channels when switching from
standby to mute
•Fast mute on supply voltage drops (low VP mute).
Protection
•Short-circuit proof to ground, positive supply voltage on
all pins and across load
•ESD protected on all pins
•Thermal protection against temperatures exceeding
150 °C
•Load dump protection
•Overvoltage protection.
GENERAL DESCRIPTION
The IC incorporates the following functions:
1. 4 ×6 W SE amplifies without SE capacitor, because of
the availability of 2 half supply voltage power buffers
2. 2 ×20 W BTL amplifiers
3. Automatic switching between 2 and 4 speaker
operation. The mode of operation is determined during
start-up.
This amplifier is protected for all general short-circuit
conditions to battery or ground, overvoltage, 45 V load
dump and short-circuits on the speaker outputs.
The IC is contained in a 20-pin power HSOP package, but
is also available in a 17-pin SIL power package. When
packaged in the 20-pin HSOP package additional
functions are available:
1. DDD level selection between 2 and 10%
2. Overrule pin for changing mode of operation
(from SE to BTL or from BTL to SE).
ORDERING INFORMATION
TYPE
NUMBER PACKAGE
NAME DESCRIPTION VERSION
TDA8586Q DBS17P plastic DIL-bent-SIL power package; 17 leads (lead length 12 mm) SOT243-1
TDA8586TH HSOP20 heatsink small outline package; 20 leads; low stand-off SOT418-2
1999 Apr 08 3
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VPoperating supply voltage 8.0 −18 V
Iq(tot) total quiescent current VP= 14.4 V, SE mode −140 170 mA
Istb standby supply current VP= 14.4 V −1 100 µA
Gvvoltage gain SE mode 25 26 27 dB
BTL mode 31 32 33 dB
Bridge-tied load application
Pooutput power VP= 14.4 V; RL=4Ω
THD = 0.5% 14 15 −W
THD = 10% 17 21 −W
THD total harmonic distortion fi= 1 kHz; Po=1W;
V
P= 14.4 V; RL=4Ω−0.05 0.15 %
VOO DC output offset voltage VP= 14.4 V; RL=4Ω;
mute condition −10 20 mV
VP= 14.4 V; on condition −0 100 mV
Vn(o) noise output voltage Rs=1kΩ; VP= 14.4 V −100 200 µV
Single-ended application
Pooutput power VP= 14.4 V; RL=4Ω
THD = 0.5% 4 4.5 −W
THD = 10% 5 6 −W
THD total harmonic distortion fi= 1 kHz; Po=1W;
V
P= 14.4 V; RL=4Ω−0.08 0.15 %
VOO DC output offset voltage VP= 14.4 V; RL=4Ω;
mute condition −10 20 mV
VP= 14.4 V; on condition −0 100 mV
Vn(o) noise output voltage Rs=1kΩ; VP= 14.4 V −80 150 µV
1999 Apr 08 4
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
BLOCK DIAGRAM
Fig.1 Block diagram SOT243-1.
handbook, full pagewidth
MGR023
1OUT1
ACREF 11
IN3 7
IN2 6
IN1 5
IN4 8
MSO 13
V/I
+
−
OA
+
−
4OUT2
OA
+
−
OA
+
−3HVP1
VPn
VPn
60
kΩ
V/I
+
−
60
kΩ
V/I
+
−
60
kΩ
17 OUT3
V/I
+
−
OA
+
−
14 OUT4
12 DIAG
OA
+
−
OA
+
−15 HVP2
60
kΩ
V/I
+
−
60
kΩ
BUFFER
VPn
30 kΩ
V/I
+
−
60
kΩ
INTERFACE DIAGNOSTIC
10
PGND2
VP1
2
VP2
16
9
PGND1
TDA8586Q
1999 Apr 08 5
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
Fig.2 Block diagram SOT418-2 (HSOP20 heatsink up).
handbook, full pagewidth
MGR024
17 OUT1
ACREF 6
IN3 4
IN2 3
IN1 2
IN4 5
MSO 8
n.c. 1
V/I
+
−
OA
+
−
20 OUT2
OA
+
−
OA
+
−19 HVP1
VPn
VPn
60
kΩ
V/I
+
−
60
kΩ
V/I
+
−
60
kΩ
14 OUT3
V/I
+
−
OA
+
−
11 OUT4
7DIAG
OA
+
−
OA
+
−12 HVP2
60
kΩ
V/I
+
−
60
kΩ
BUFFER
VPn
30 kΩ
V/I
+
−
60
kΩ
INTERFACE DIAGNOSTIC
10
DDDSEL
9
OVERRULE
15
PGND2
VP1
18
VP2
13
16
PGND1
TDA8586TH
1999 Apr 08 6
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
PINNING
SYMBOL PIN
SOT243 PIN
SOT418 DESCRIPTION
n.c. −1 not connected
IN1 5 2 non-inverting input 1
IN2 6 3 inverting input 2
IN3 7 4 non inverting input 3
IN4 8 5 inverting input 4
ACREF 11 6 common signal input
DIAG 12 7 diagnostic output/mode fix
MSO 13 8 mode select mute, standby or on
OVERRULE −9 mode selection overrule
DDDSEL −10 2 or 10% dynamic distortion detection
OUT4 14 11 SE output 4 (negative)
HVP2 15 12 buffer output/BTL output 2 (negative)
VP2 16 13 supply voltage 2
OUT3 17 14 SE output 3/BTL output 2 (positive)
PGND2 10 15 power ground 2
PGND1 9 16 power ground 1
OUT1 1 17 SE output 1/BTL output 1 (positive)
VP1 2 18 supply voltage 1
HVP1 3 19 buffer output/BTL output 1 (negative)
OUT2 4 20 SE output 2 (negative)
1999 Apr 08 7
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
Fig.3 Pin configuration (SOT243-1).
handbook, halfpage
TDA8586Q
MGR025
OUT1
VP1
HVP1
OUT2
IN1
IN2
IN3
IN4
PGND1
PGND2
ACREF
DIAG
MSO
OUT4
HVP2
VP2
OUT3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Fig.4 Pin configuration (SOT418-2).
handbook, halfpage
n.c.
IN1
IN2
IN3
IN4
ACREF
DIAG
MSO
OVERRULE
DDDSEL
OUT2
HVP1
VP1
OUT1
PGND2
OUT3
PGND1
VP2
HVP2
OUT4
1
2
3
4
5
6
7
8
9
10 11
12
20
19
18
17
16
15
14
13
TDA8586TH
MGR026
1999 Apr 08 8
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
FUNCTIONAL DESCRIPTION
The TDA8586 is a multi-purpose power amplifier with four
amplifiers and 2 buffer stages, which can be connected in
the following configurations with high output power and
low distortion:
•Dual Bridge-Tied Load (BTL) amplifiers
•Quad Single-Ended (SE) amplifiers.
In the BTL mode of operation, the 2 buffer amplifiers act as
inverting amplifiers to complete the bridge across the
‘front’ amplifiers (OUT1 and OUT3) and the ‘rear’ outputs
(OUT2 and OUT4) enter a high-impedance state.
In the SE mode of operation, the buffers act as an AC
ground path thereby eliminating the need for series
capacitors on the speaker outputs.
Diagnostics:
•While the IC is in the mute mode, the diagnostic output
will signal the mode of operation when the IC is not
overruled
•In the on mode the diagnostic output will signal any fault
in the IC or if the output of any amplifier is clipping with
a distortion of 10% (or 2% depending on selected
clip-mode).
Special attention is given to the dynamic behaviour as
follows:
•Noise suppression during engine start
•No plops when switching from standby to on
•Slow offset change between mute and on (controlled by
MSO pin)
•Low noise levels, which are independent of the supply
voltage.
Protections are included to avoid the IC being damaged at:
•Over temperature: Tj> 150 °C
•Short-circuit of the output pin(s) to ground or supply rail.
When short-circuited, the power dissipation is limited
•ESD protection (Human Body Model 3000 V and
Machine Model 300 V).
The presence of the load is measured after the transition
between standby and mute. The IC will determine if there
is an acceptable load on both outputs (OUT2 and OUT4).
If both outputs are unloaded, the IC will switch to a
2 speaker mode of operation (BTL mode), unless it is
overruled.
There are two options to overrule:
1. Before transition from mute to on, after a load
detection, pulling the diagnostic output above 9.5 V
will force the IC into 4 speaker mode
2. TDA8586TH: pulling the OVERRULE pin according
pinning table.
Care should be taken with the OVERRULE function as it
works during the on mode. If there is a 2 or 4 speaker
mode change during the on mode a large ‘plop’ can be
heard on the speakers.
The ACREF input (common signal input) acts with the four
signal inputs (IN1 to IN4) to provide quasi differential
inputs. A capacitor must be connected to this pin of which
the ground pin should be connected to the ground at the
signal source (usually the ground at the audio signal
processor). This capacitor has a dual function. During the
speaker detection, the signal ground capacitor is used to
set the time constant of the measurement (and thus
determines the minimum required switch-on time).
The capacitor on the MSO pin allows the integrate function
to provide immunity to outside noises during load
detection.
1999 Apr 08 9
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
Fig.5 Timing diagram including diagnostics.
handbook, full pagewidth
MGR027
state
condition
This voltage must remain present.
Whatever the load detection has found the mode of operation will be inverted.
Toggling between the 2 modes is possible.
The mode is overruled only from
BTL to SE when the diagnostic pin
is excited with a pulse of 10 V.
standby load detect
mute no load detect
mute no clipping/shorts
on clipping
on short-circuit
on
VP
VP
MSO
diagnostic
information
diagnostic
overrule
mode select
amplifier
output
buffer/amplifier
output
0
0
3 V
5 V
10 V
0
5 V
0
0.5VP
0
0.5VP
0
0
9 V
short-circuit to supply
short-circuit over load
short-circuit to ground
short-circuit to supply
short-circuit over load
short-circuit to ground
SE detected
BTL detected
SE detection
BTL detection
minimum 1 s
1999 Apr 08 10
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note
1. A large reverse current will flow, therefore external protection is needed (fuse and reverse diode).
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VPsupply voltage operating 8 18 V
load dump protected;
see Fig.6 −45 V
VDIAG voltage on diagnostic pin −18 V
IOSM non-repetitive peak output current −6A
I
ORM repetitive peak output current −4A
V
rp reverse polarity voltage note 1 −6V
V
sc AC and DC short-circuit voltage of output pins
across loads and to ground or supply pins −18 V
Ptot total power dissipation −75 W
Tjjunction temperature −150 °C
Tstg storage temperature −55 +150 °C
Tamb operating ambient temperature −40 +150 °C
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth(j-a) thermal resistance from junction to ambient in free air 40 K/W
Rth(j-c) thermal resistance from junction to case 2 K/W
Fig.6 Load dump voltage waveform.
handbook, halfpage
MGL404
tr
VP
tf
45 V
14.4 V
t (ms)
1999 Apr 08 11
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
CHARACTERISTICS
VP= 14.4 V; Tamb =25°C; fi= 1 kHz; RL=∞; measured in test circuit of Fig.8; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VPoperating supply voltage 8.0 14.4 18 V
Iq(tot) total quiescent current SE mode −140 170 mA
Istb standby current −1 100 µA
VODC output voltage VP= 14.4 V −7.0 −V
VP(mute) low supply voltage mute 6.0 7.0 8.0 V
Vosingle-ended and bridge-tied
load output voltage VP= 14.4 V; RL=4Ω
mute condition −−20 mV
on condition −−100 mV
VIDC input voltage VP= 14.4 V −4.0 −V
PIN MSO
VMSO voltage at pin MSO standby condition 0 −0.8 V
mute condition; note 1 2.0 3.0 4 V
on condition 8.0 −10.5 V
IMSO input current mute pin at standby condition;
VMSO < 0.8 V −540µA
Diagnostic; output buffer (open-collector); see Figs 7 to 8
VDIAG(L) diagnostic output voltage LOW Isink =1mA −0.3 0.8 V
ILI leakage current VDIAG = 14.4 V −−1µA
V
DIAG(or) diagnostic override voltage in mute mode after load
detection 10.5 −18 V
VDIAG(4ch) diagnostic 4 channel indication
voltage mute, after load detection with
4 speakers connected −0.3 0.8 V
CD2 clip detector LOW THD mode; VDIAG >3V;
R = 10 kΩ0.5 2 3.5 %
CD10 clip detector HIGH THD mode (default);
VDIAG >3V; R=10kΩ71013%
CLIP DETECT CONTROL PIN
VDDDSEL voltage at DDD select pin to
obtain: 10% DDD 0 −1V
2% DDD 3 −6V
I
DDDSEL Input current DDD select pin VDDDSEL =5V 15 −140 µA
1999 Apr 08 12
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
Stereo BTL application (see Fig.7)
THD total harmonic distortion fi= 1 kHz; Po=1W; R
L=4Ω− 0.05 0.15 %
45 Hz < fi< 10 kHz; Po=1W;
R
L=4Ω; filter: f < 30 kHz −0.3 −%
Pooutput power VP= 14.4 V; RL=4Ω; note 2
THD = 0.5% 14 15 −W
THD = 10% 17 21 −W
Gvvoltage gain Vi(rms) =15mV 31 32 33 dB
∆G
vchannel unbalance Vi(rms) =15mV −0.7 0 +0.7 dB
αcs channel separation Po=2W; f
i= 1 kHz; RL=4Ω45 55 −dB
VOO DC output offset voltage VP= 14.4 V; on condition −0 100 mV
VP= 14.4 V; RL=4Ω;
mute condition −10 20 mV
Vn(o) noise output voltage on Rs=1kΩ; VP= 14.4 V; note 3 −100 150 µV
Vn(o)(mute) noise output voltage mute note 3 −020µV
V
o(mute) output voltage mute Vi(rms) =1V −3 500 µV
SVRR supply voltage ripple rejection: Rs=0Ω; fi= 1 kHz;
Vripple = 2 V (p-p)
on condition 45 55 −dB
mute condition 55 70 −dB
Ziinput impedance input referenced to ground 40 60 90 kΩ
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1999 Apr 08 13
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
Notes
1. Tolerances on the mute level is tight because of the usage of this pin for integration during load detection.
2. The output power is measured directly on the pins of the IC.
3. The noise output is measured in a bandwidth of 20 Hz to 20 kHz.
Quad SE application (see Fig.8)
THD total harmonic distortion fi= 1 kHz; Po=1W; R
L=4Ω− 0.05 0.15 %
45 Hz < fi< 10 kHz; Po=1W;
R
L=4Ω; filter: f < 30 kHz −0.5 −%
Pooutput power VP= 14.4 V; RL=4Ω; note 2
THD = 0.5% 4 4.5 −W
THD = 10% 5 6 −W
Gvvoltage gain Vi(rms) =15mV 25 26 27 dB
∆G
vchannel unbalance Vi(rms) =15mV −0.7 0 +0.7 dB
αcs channel separation Po=2W; f
i= 1 kHz; RL=4Ω40 50 −dB
VOO DC output offset voltage VP= 14.4 V; on condition −0 100 mV
VP= 14.4 V; RL=4Ω;
mute condition −10 20 mV
Vn(o) noise output voltage on Rs=1kΩ; VP= 14.4 V; note 3 −80 150 µV
Vn(o)(mute) noise output voltage mute note 3 −020µV
V
o(mute) output voltage mute Vi(rms) =1V −3 500 µV
SVRR supply voltage ripple rejection Rs=0Ω; fi= 1 kHz;
Vripple = 2 V (p-p)
on condition 43 47 −dB
mute condition 55 70 −dB
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1999 Apr 08 14
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
APPLICATION INFORMATION
Fig.7 Stereo bridge-tied load application (SOT243-1).
handbook, full pagewidth
MGR028
1OUT1
11
IN3 7
IN2 6
IN1 5
IN4 8
13
V/I
+
−
OA
+
−
4OUT2
OA
+
−
OA
+
−3HVP1
VPn
VPn
60
kΩ
V/I
+
−
60
kΩ
V/I
+
−
60
kΩ
17 OUT3
V/I
+
−
OA
+
−
14 OUT4
12
OA
+
−
OA
+
−15 HVP2
60
kΩ
V/I
+
−
60
kΩ
BUFFER
VPn
30 kΩ
V/I
+
−
60
kΩ
INTERFACE DIAGNOSTIC
10
PGND2
VP1
2
VP2
16
9
PGND1
TDA8586Q
+
−4 or 8 Ω
+
−4 or 8 Ω
100
nF
(16/40 V)
1000 µFVP
+5 V
10 kΩ
VINL front
220 nF
VINR front
220 nF
47 µF
(10 V)
15 kΩ
30 kΩ
4.7 µF
(10 V)
switch
switched
+9 V
220 nF
220 nF
ACREF
MSO DIAG
1999 Apr 08 15
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
Fig.8 Quad single-ended application (SOT243-1).
handbook, full pagewidth
MGR029
1OUT1
ACREF 11
IN3 7
IN2 6
IN1 5
IN4 8
MSO 13
V/I
+
−
OA
+
−
4OUT2
OA
+
−
OA
+
−3HVP1
VPn
VPn
60
kΩ
V/I
+
−
60
kΩ
V/I
+
−
60
kΩ
17 OUT3
V/I
+
−
OA
+
−
14 OUT4
12 DIAG
OA
+
−
OA
+
−15 HVP2
60
kΩ
V/I
+
−
60
kΩ
BUFFER
VPn
30 kΩ
V/I
+
−
60
kΩ
INTERFACE DIAGNOSTIC
PGND2
VP1
2
VP2
16
9
PGND1
TDA8586Q
+
−
+
−
4 or 8 Ω
4 or 8 Ω
+
−
+
−
4 or 8 Ω
4 or 8 Ω
100
nF
(16/40 V)
1000 µFVP
+5 V
10 kΩ
VINL front
220 nF
VINL rear
220 nF
VINR front
220 nF
47 µF
(10 V)
VINR rear
220 nF
15 kΩ
30 kΩ
4.7 µF
(10 V)
switch
switched
+9 V
10
1999 Apr 08 16
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
Fig.9 Stereo bridge-tied load application (SOT418-2).
handbook, full pagewidth
MGR030
17 OUT1
ACREF 6
IN3 4
IN2 3
IN1 2
IN4 5
MSO 8
V/I
+
−
OA
+
−
20 OUT2
OA
+
−
OA
+
−19 HVP1
VPn
VPn
60
kΩ
V/I
+
−
60
kΩ
V/I
+
−
60
kΩ
14 OUT3
V/I
+
−
OA
+
−
11 OUT4
7DIAG
OA
+
−
OA
+
−12 HVP2
60
kΩ
V/I
+
−
60
kΩ
BUFFER
VPn
30 kΩ
V/I
+
−
60
kΩ
INTERFACE DIAGNOSTIC
10
DDDSEL 9
OVERRULE 15
PGND2
VP1
18
VP2
13
16
PGND1
TDA8586TH
+
−4 or 8 Ω
+
−4 or 8 Ω
100
nF
(16/40 V)
1000 µFVP
+5 V
10 kΩ
VINL front
220 nF
VINR front
220 nF
47 µF
(10 V)
15 kΩ
30 kΩ
4.7 µF
(10 V)
switch
switched
+9 V
n.c. 1
220 nF
220 nF
1999 Apr 08 17
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
Fig.10 Quad single-ended application (SOT418-2).
handbook, full pagewidth
MGR031
17 OUT1
ACREF 6
IN3 4
IN2 3
IN1 2
IN4 5
MSO 8
V/I
+
−
OA
+
−
20 OUT2
OA
+
−
OA
+
−19 HVP1
VPn
VPn
60
kΩ
V/I
+
−
60
kΩ
V/I
+
−
60
kΩ
14 OUT3
V/I
+
−
OA
+
−
11 OUT4
7DIAG
OA
+
−
OA
+
−12 HVP2
60
kΩ
V/I
+
−
60
kΩ
BUFFER
VPn
30 kΩ
V/I
+
−
60
kΩ
INTERFACE DIAGNOSTIC
10
DDDSEL 9
OVERRULE 15
PGND2
VP1
18
VP2
13
16
PGND1
TDA8586TH
+
−
+
−
4 or 8 Ω
4 or 8 Ω
+
−
+
−
4 or 8 Ω
4 or 8 Ω
100
nF
(16/40 V)
1000 µFVP
+5 V
10 kΩ
VINL front
220 nF
VINL rear
220 nF
VINR front
220 nF
47 µF
(10 V)
VINR rear
220 nF
15 kΩ
30 kΩ
4.7 µF
(10 V)
switch
switched
+9 V
n.c. 1
1999 Apr 08 18
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
INTERNAL PIN CONFIGURATION
PIN
TDA8586TH NAME EQUIVALENT CIRCUIT
2, 3, 4, 5 and 6 inputs
11, 12, 14, 17,
19 and 20 outputs
8 mode select
handbook, halfpage
MGE014
VP
IN
handbook, halfpage
MGE015
VP
OUT
0.5 VP
handbook, halfpage
MGE016
VP
1999 Apr 08 19
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
PACKAGE OUTLINES
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT243-1
0 5 10 mm
scale
D
L
E
A
c
A2
L3
Q
wM
bp
1
d
D
Ze
e
xh
117
j
E
h
non-concave
95-03-11
97-12-16
DBS17P: plastic DIL-bent-SIL power package; 17 leads (lead length 12 mm) SOT243-1
view B: mounting base side
m2
e
vM
B
UNIT A e1
A2bpcD
(1) E(1) Z(1)
deD
hLL
3m
mm 17.0
15.5 4.6
4.2 0.75
0.60 0.48
0.38 24.0
23.6 20.0
19.6 10 2.54
v
0.8
12.2
11.8 1.27
e2
5.08 2.4
1.6
Eh
62.00
1.45
2.1
1.8
3.4
3.1 4.3
12.4
11.0
Qj
0.4
w
0.03
x
1999 Apr 08 20
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
UNIT A4(1)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
97-10-29
98-02-25
IEC JEDEC EIAJ
mm +0.12
−0.02
3.5 0.35
DIMENSIONS (mm are the original dimensions)
Note
1. Limits per individual lead.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT418-2
0 5 10 mm
scale
HSOP20: heatsink small outline package; 20 leads; low stand-off SOT418-2
A
max.
detail X
A2
3.5
3.2
D2
1.1
0.9
HE
14.5
13.9
Lp
1.1
0.8
Q
1.7
1.5 2.5
2.0
v
0.25
w
0.25
yZ
8°
0°
θ
0.07
x
0.03
D1
13.0
12.6
E1
6.2
5.8
E2
2.9
2.5
bpc
0.32
0.23
e
1.27
D(2)
16.0
15.8
E(2)
11.1
10.9
0.53
0.40
A3
A4
A2(A3)
Lpθ
A
Q
D
y
x
HE
E
c
vMA
X
A
bpwM
Z
D1D2
E2
E1
e
20 11
110
pin 1 index
1999 Apr 08 21
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
SOLDERING
Introduction
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mount components are mixed on
one printed-circuit board. However, wave soldering is not
always suitable for surface mount ICs, or for printed-circuit
boards with high population densities. In these situations
reflow soldering is often used.
Through-hole mount packages
SOLDERING BY DIPPING OR BY SOLDER WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
MANUAL SOLDERING
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
300 and 400 °C, contact may be up to 5 seconds.
Surface mount packages
REFLOW SOLDERING
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
WAVE SOLDERING
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
•For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
MANUAL SOLDERING
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Apr 08 22
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
Suitability of IC packages for wave, reflow and dipping soldering methods
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
MOUNTING PACKAGE SOLDERING METHOD
WAVE REFLOW(1) DIPPING
Through-hole mount DBS, DIP, HDIP, SDIP, SIL suitable(2) −suitable
Surface mount BGA, SQFP not suitable suitable −
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(3) suitable −
PLCC(4), SO, SOJ suitable suitable −
LQFP, QFP, TQFP not recommended(4)(5) suitable −
SSOP, TSSOP, VSO not recommended(6) suitable −
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
1999 Apr 08 23
Philips Semiconductors Preliminary specification
Power amplifier with load detection and
auto BTL/SE selection TDA8586
NOTES
Internet: http://www.semiconductors.philips.com
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© Philips Electronics N.V. 1999 SCA63
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Printed in The Netherlands 545002/750/02/pp24 Date of release: 1999 Apr 08 Document order number: 9397 750 05483
