Rev.2.00 Mar 30, 2006 page 1 of 6
HD74HC4060
14-stage Binary Counter REJ03D0650-0200
(Previous ADE-205-5 37)
Rev.2.00
Mar 30, 2006
Description
The HD74HC4060 is a 14 stage counter, this device increments on the falling edge (negative transition) of the input
clock, and all their outputs are reset to a low level by applying a logical high on their reset input. The HD74HC4060
also has two additional inputs to enable eas y connectio n of either an RC or crystal oscillator.
Features
• High Speed Operation: tpd (Clock to Q4) = 41.5 ns typ (CL = 50 pF)
• High O utp ut Current: Fanout of 10 LSTTL Load s
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering In formation
Part Name Package Type Package Code
(Previous Code) Package
Abbreviation Taping Abbreviation
(Quantity)
HD74HC4060P DILP-16 pin PRDP0016AE-B
(DP-16FV) P —
HD74HC4060FPEL SOP-16 pin (JEITA) PRSP0016DH-B
(FP-16DAV) FP EL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Function Table
Clock in Reset Outputs State
L No change
L Advance to next stage
X H All outputs are low
X: Irrelevant
HD74HC4060
Rev.2.00 Mar 30, 2006 page 2 of 6
Pin Arrangement
1
2
3
4
5
6
7
8
Q
12
Q
13
Q
14
Q
6
Q
5
Q
7
Q
4
GND
Q
13
Q
14
Q
6
Q
5
Q
7
Q
4
V
CC
Q
10
Q
8
Q
9
Reset
Clock in
Clock out 1
Clock out 2
Q
10
Q
8
Q
9
Reset
Clock in
Clock out 1
16
15
14
13
12
11
10
9
Q
12
(Top view)
Clock out 2
Block Diagram
C
C
Q
RQ
C
C
Q
4
Q
5
Q
6
Q
13
Q
14
Q
12
Q
10
Q
9
Q
8
Q
7
Q
RQ
C
C
Q
RQ
C
C
Q
RQ
C
C
Q
RQ
C
C
Q
RQ
RRRRR RRR
C
C
Q
Q
C
C
Q
Q
C
C
Q
Q
C
C
Q
Q
C
C
Q
Q
C
C
Q
Q
C
C
Q
Q
C
C
Q
Q
Clock out 2
Reset
Clock in
Clock out 1
Timing Diagram
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q
8
Q
9
Q
10
Q
11
Q
12
Q
13
Q
14
Reset
Clock in 148163264
128 256 512
1,024 2,048 4,096 8,192 16,384
2
HD74HC4060
Rev.2.00 Mar 30, 2006 page 3 of 6
Absolute Maximum Ratings
Item Symbol Ratings Unit
Supply voltage range VCC –0.5 to 7.0 V
Input / Output voltage VIN, VOUT –0.5 to VCC +0.5 V
Input / Output diode current IIK, IOK ±20 mA
Output current IOUT ±25 mA
VCC, GND current ICC or IGND ±50 mA
Power dissipation PT 500 mW
Storage temperature Tstg –65 to +150 °C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Recommended Operating Conditions
Item Symbol Ratings Unit Conditions
Supply voltage VCC 2 to 6 V
Input / Output voltage VIN, VOUT 0 to VCC V
Operating temperature Ta –40 to 85 °C
0 to 1000 VCC = 2.0 V
0 to 500 VCC = 4.5 V
Input rise / fall time*1 t
r, tf 0 to 400 ns VCC = 6.0 V
Note: 1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Ta = 25°C Ta = –40 to+85°C
Item Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions
2.0 1.5 — — 1.5 —
4.5 3.15 — — 3.15 —
VIH
6.0 4.2 — — 4.2 —
V
2.0 — — 0.5 — 0.5
4.5 — — 1.35 — 1.35
Input voltage
VIL
6.0 — — 1.8 — 1.8
V
2.0 1.9 2.0 — 1.9 —
4.5 4.4 4.5 — 4.4 —
6.0 5.9 6.0 — 5.9 —
IOH = –20 µA
4.5 4.18 — — 4.13 — IOH = –4 mA
VOH
6.0 5.68 — — 5.63 —
V Vin = VIH or VIL
IOH = –5.2 mA
2.0 — 0.0 0.1 — 0.1
4.5 — 0.0 0.1 — 0.1
6.0 — 0.0 0.1 — 0.1
IOL = 20 µA
4.5 — — 0.26 — 0.33 IOH = 4 mA
Output voltage
VOL
6.0 — — 0.26 — 0.33
V Vin = VIH or VIL
IOH = 5.2 mA
Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND
Quiescent su pply
current ICC 6.0 — — 4.0 — 40 µA Vin = VCC or GND, Iout = 0 µA
HD74HC4060
Rev.2.00 Mar 30, 2006 page 4 of 6
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°C Ta = –40 to +85°C
Item Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions
2.0 — — 4 — 3
4.5 — — 20 — 16
Maximum clock
frequency fmax
6.0 — — 24 — 19
MHz
2.0 — — 300 — 375
4.5 — 42 60 — 75
tPLH
6.0 — — 51 — 63
ns Clock to Q4
2.0 — — 300 — 375
4.5 — 41 60 — 75
tPHL
6.0 — — 51 — 63
ns Clock to Q4
2.0 — — 240 — 300
4.5 — 16 48 — 60
Propagation delay
time
tPHL
6.0 — — 41 — 51
ns Reset to output
2.0 100 — — 125 —
4.5 20 10 — 25 —
Remo val time trem
6.0 17 — — 21 —
ns
2.0 80 — — 100 —
4.5 16 7 — 20 —
Pulse width tw
6.0 14 — — 17 —
ns
2.0 — — 75 — 95
4.5 — 5 15 — 19
Output rise/fall
time tTLH
tTHL 6.0 — — 13 — 16
ns
Input capacitan ce Cin — — 5 10 — 10 pF
Test Circuit
VCC
CL = 50 pF
Clock out1
VCC
Zout = 50 Ω
Q14
Reset
CL = 50 pF
Q4
Zout = 50 Ω
Output
Note : 1. C
L
includes probe and jig capacitance.
See Function Table
Input
Pulse Generator
Output
Input
Pulse Generator
Clock out2
Clock in
HD74HC4060
Rev.2.00 Mar 30, 2006 page 5 of 6
Waveforms
Clock
Reset
0 V
V
CC
0 V
V
CC
Any Q
V
OL
V
OH
•
Wavwform – 2
Q
1
Clock
V
OL
V
OH
0 V
V
CC
t
w
90%
10% 10%
t
THL
t
TLH
90%
•
Waveform – 1
50%
t
PHL
10%
t
f
t
THL
90%
50%
50%
t
w
10%
90%
10%
90%
50% 50% 50%
50% 50%
t
PLH
t
PHL
t
f
10%
90%
t
r
10%
90%
50%
t
rem
t
r
10%
90%
1. Input waveform : PRR ≤ 1 MHz, Zo = 50 Ω, t
r
≤ 6 ns, t
f
≤ 6 nsNote :
1. Input waveform : PRR ≤ 1 MHz, Zo = 50 Ω, t
r
≤ 6 ns, t
f
≤ 6 nsNote :
Any Q
GND
V
CC
HD74HC4060
Rev.2.00 Mar 30, 2006 page 6 of 6
Package Dimensions
7.62
MaxNomMin
Dimension in Millimeters
Symbol
Reference
19.2
6.3
5.06
A
1
Z
b
3
D
E
A
b
p
c
θ
e
L
e
1
0.51
0.56
1.30
0.19 0.25 0.31
2.29 2.54 2.79
0° 15°
20.32
7.4
0.40 0.48
1.12
2.54
1
p
1
3
1 8
16 9
e
b
A
LA
Z
e c
E
D
b
0.89
θ
( Ni/Pd/Au plating )
P-DIP16-6.3x19.2-2.54 1.05g
MASS[Typ.]
DP-16FVPRDP0016AE-B
RENESAS CodeJEITA Package Code Previous Code
0.80
0.15
1.27
7.50 8.00
0.400.34
A
1
10.5
MaxNomMin
Dimension in Millimeters
Symbol
Reference
2.20
0.900.700.50
5.50
0.200.100.00
0.46
0.250.200.15
7.80
8°0°
0.12
1.15
10.06
L
1
Z
H
E
y
x
θ
c
b
p
A
2
E
D
b
1
c
1
e
L
A
*1
*2
E
81
16 9
xM
p
*3
y
F
Index mark
b
D
E
H
Z
A
Terminal cross section
( Ni/Pd/Au plating )
p
c
b
1
1
Detail F
L
L
A
θ
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
e
P-SOP16-5.5x10.06-1.27 0.24g
MASS[Typ.]
FP-16DAVPRSP0016DH-B
RENESAS CodeJEITA Package Code Previous Code
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