CD74HCT14E96 - Texas Instruments - Datasheet.Directory

Data sheet acquired from Harris Semiconductor

SCHS129A

Features

• Unlimited Input Rise and Fall Times

• Exceptionally High Noise Immunity

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating T emperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il≤1µA at VOL, VOH

Description

The ’HC14 and ’HCT14 each contain 6 inverting Schmitt

Triggers in one package.

Pinout

CD54HC14, CD54HCT14

(CERDIP)

CD74HC14, CD74HCT14

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER TEMP. RANGE

(oC) PACKAGE

CD54HC14F -55 to 125 14 Ld CERDIP

CD54HC14F3A -55 to 125 14 Ld CERDIP

CD74HC14E -55 to 125 14 Ld PDIP

CD74HC14M -55 to 125 14 Ld SOIC

CD54HCT14F -55 to 125 14 Ld CERDIP

CD54HCT14F3A -55 to 125 14 Ld CERDIP

CD74HCT14E -55 to 125 14 Ld PDIP

CD74HCT14M -55 to 125 14 Ld SOIC

NOTES:

1. When ordering, use the entire part number. Add the sufﬁx 96 to

obtain the variant in the tape and reel.

2. Die is available which meets all electrical specifications. Please

contact your local TI sales office or customer service for ordering

information.

GND

VCC

January 1998 - Revised May 2000

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC14,

CD54/74HCT14

High Speed CMOS Logic

Hex Inverting Schmitt Trigger

[ /Title

(CD74H

C14,

CD74H

CT14)

Subject

(High

Speed

CMOS

Logic

Hex

Invert-

Functional Diagram

Logic Diagram

TRUTH TABLE

INPUT (A) OUTPUT (Y)

NOTE:

H= High Level

L= Low Level

12 6Y

GND = 7

VCC = 14

nA nY

CD54/74HC14, CD54/74HCT14

FIGURE 1. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SETUP

VOVH

VT-V

T+

VH = VT+ - VT-

VCC

GND

VCC

GND

VT+V

T-

CD54/74HC14, CD54/74HCT14

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, IIK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, IOK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, IO

For -0.5V < VO < VCC +0.5V . . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Source or Sink Current per Output Pin, IO

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC

Input Rise and Fall Time, tr, tf

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)

Thermal Resistance (Typical, Note 3) θJA (oC/W) θJC (oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . . 90 -

CERDIP Package . . . . . . . . . . . . . . . . 130 55

SOIC Package. . . . . . . . . . . . . . . . . . . 120 -

Maximum Junction Temperature (Hermetic P ac kage or Die) . . . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS

VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX

HC TYPES

Input Switch Points VT+ - - 2 0.7 1.5 0.7 1.5 0.7 1.5 V

4.5 1.7 3.15 1.7 3.15 1.7 3.15 V

6 2.1 4.2 2.1 4.2 2.1 4.2 V

VT- - - 2 0.3 1.0 0.3 1.0 0.3 1.0 V

4.5 0.9 2.2 0.9 2.2 0.9 2.2 V

6 1.2 3.0 1.2 3.0 1.2 3.0 V

VH- - 2 0.2 1.0 0.2 1.0 0.2 1.0 V

4.5 0.4 1.4 0.4 1.4 0.4 1.4 V

6 0.6 1.6 0.6 1.6 0.6 1.6 V

High Level Output

Voltage CMOS Loads VOH VT- or

VT+-0.02 2 1.9 - 1.9 - 1.9 - V

-0.02 4.5 4.4 - 4.4 - 4.4 - V

-0.02 6 5.9 - 5.9 - 5.9 - V

High Level Output

Voltage TTL Loads --------V

-4 4.5 3.98 - 3.84 - 3.7 - V

-5.2 6 5.48 - 5.34 - 5.2 - V

CD54/74HC14, CD54/74HCT14

LowLevelOutputVoltage

CMOS Loads VOL VIH or

VIL 0.02 2 - 0.1 - 0.1 - 0.1 V

0.02 4.5 - 0.1 - 0.1 - 0.1 V

0.02 6 - 0.1 - 0.1 - 0.1 V

LowLevel OutputVoltage

TTL Loads --------V

4 4.5 - 0.26 - 0.33 - 0.4 V

5.2 6 - 0.26 - 0.33 - 0.4 V

Input Leakage Current IIVCC or

GND -6-±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 06-2-20-40µA

HCT TYPES

Input Switch Points VT+ - - 4.5 1.2 1.9 1.2 1.9 1.2 1.9 V

5.5 1.4 2.1 1.4 2.1 1.4 2.1 V

VT- 4.5 0.5 1.2 0.5 1.2 0.5 1.2 V

5.5 0.6 1.4 0.6 1.4 0.6 1.4 V

VH4.5 0.4 1.4 0.4 1.4 0.4 1.4 V

5.5 0.4 1.5 0.4 1.5 0.4 1.5 V

High Level Output

Voltage CMOS Loads VOH VIH or

VIL -0.02 4.5 4.4 - 4.4 - 4.4 - V

High Level Output

Voltage TTL Loads -4 4.5 3.98 - 3.84 - 3.7 - V

LowLevelOutputVoltage

CMOS Loads VOL VIH or

VIL 0.02 4.5 - 0.1 - 0.1 - 0.1 V

LowLevel OutputVoltage

TTL Loads 4 4.5 - 0.26 - 0.33 - 0.4 V

Input Leakage Current IIVCC

and

GND

- 5.5 - ±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 0 5.5 - 2 - 20 - 40 µA

Additional Quiescent

Device Current Per Input

Pin: 1 Unit Load

∆ICC

(Note 4) VCC

- 2.1 - 4.5 to

5.5 - 360 - 450 - 490 µA

NOTE:

4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

DC Electrical Speciﬁcations (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS

VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

nA 0.6

NOTE: Unit Load is ∆ICC limit speciﬁed in DC Electrical Speciﬁca-

tions table, e.g., 360µA max at 25oC.

CD54/74HC14, CD54/74HCT14

Switching Speciﬁcations Input tr, tf = 6ns

PARAMETER SYMBOL TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

HC TYPES

Propagation Delay,

A to Y tPLH, tPHL CL= 50pF 2 - - 135 - 170 - 205 ns

CL= 50pF 4.5 - - 27 - 34 - 41 ns

CL= 15pF 5 - 11 - ----ns

CL= 50pF 6 - - 23 - 29 - 35 ns

Output Transition Times tTLH, tTHL CL= 50pF 2 - - 75 - 95 18 110 ns

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

Input Capacitance CI- - - - 10 - 10 - 10 pF

Power Dissipation Capacitance

(Notes 5, 6) CPD - 5-20-----pF

HCT TYPES

Propagation Delay,

A to Y tPLH, tPHL CL= 50pF 4.5 - - 38 - 48 - 57 ns

CL= 15pF 5 - 16 - ----ns

Output Transition Times tTLH, tTHL CL= 50pF 4.5 - - 15 - 19 - 22 ns

Input Capacitance CI- - - - 10 - 10 - 10 pF

Power Dissipation Capacitance

(Notes 5, 6) CPD - 5-20-----pF

NOTES:

5. CPD is used to determine the dynamic power consumption, per inverter.

6. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

Test Circuits and Waveforms

FIGURE 2. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC FIGURE 3. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

tPHL tPLH

tTHL tTLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

VCC

tr = 6ns tf = 6ns

90%

tPHL tPLH

tTHL tTLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

tr = 6ns tf = 6ns

90%

CD54/74HC14, CD54/74HCT14

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