MC33813AER2 - NXP SEMICONDUCTORS - Datasheet.Directory

Document Number: MC33813

Rev. 12, 12/2019

NXP Semiconductors

Data sheet: Technical Data

One cylinder small engine control IC

solution for managing one-cylinder engines. With five drivers, two pre-drivers, a

5.0 V regulator for the MCU, a protected external sensor supply and a high level of

integration, the IC offers an ideal response to contemporary market requirements.

The innovative VRS system optimizes noise immunity under cranking conditions.

Diagnostic and protection features present on all outputs allow applications to

operate with greater safety.

Features:

• Operates over supply voltage range of 4.5 V < VPWR < 36 V

• Start-up/shut-down control and power sequence logic with KEYSW input

• MCU supply: VCC is a 5.0 V (±2.0%, 200 mA) regulated supply

• Sensor supply: VPROT (100 mA) is a VCC tracking protected sensor supply

• Two configurable pre-drivers for IGBT or general purpose gate MOSFETs for

ignition and O2 sensor (HEGO) heater:

•PWM

• Overcurrent shutdown

• Short-to-battery shutdown

• Five low-side drivers with full diagnostics, self-protection and PWM control:

• One fuel injector drivers, RDS(on) = 0.6 Ω, ILIMIT = 1.8 A, to drive typical 12 Ω

high-impedance injectors

• Relay 1 driver, RDS(on) = 0.4 Ω, ILIMIT = 3.0 A, to drive fuel pump

• Relay 2 driver, RDS(on) = 1.5 Ω, ILIMIT = 1.2 A, to drive power relay

• Lamp driver, RDS(on) = 1.5 Ω, ILIMIT = 1.2 A, to drive warning lamp or an LED

• Programmable Tachometer Driver, RDS(on) = 20 Ω, Ishutdown = 60 mA, to drive

a Tachometer display

• Innovative configurable VRS conditioning circuit, with two different parameter

settings for engine cranking and running mode and an optional automatic mode

to improve noise immunity in cranking conditions

• K-line (ISO9141)

• MCU reset generator and programmable watchdog

• MCU Interface: 16-bit SPI and parallel interface with 5.0 V IO capability

Figure 1. 33813 simplified application diagram

98ASA00737D

AE SUFFIX (PB-FREE)

48-PIN LQFP-EP

ONE CYLINDER SMALL ENGINE

CONTROL IC

33813

Applications:

Small engine control for:

• Motor scooters

• Small motorcycles

• Lawn mowers

• Lawn trimmers

• Snow blowers

• Chain saws

• Gasoline-driven electrical generators

• Outboard motors

VPWR

SPI

VRSOUT

MRX

MC33813

SPI

BAT

O2HOUT

LAMPOUT

MCU

RESETB

INJOUT1

ROUT1

Relay 1

MIL

O2 Heater

BAT

Injectors

RESETB

Crankshaft VRS

VRSP

VRSN

MTX

INJIN1

O2HIN

GPIO

KEYSW

ROUT2

VPPSENS

GND

+5.0 V

IGNIN1

IGNOUT1

ISO9141

IGNFB1

O2HFB

VPPREF

BAT

Keyswitch

Relay 2

VPROT

5.0 V Sensor Supply

GPIO

BAT

(Power)

(Fuel Pump)

TACHOUT

TACHOMETER

VCC

BATSW

IGNSENSP

IGNSENSN

O2HSENSP

O2HSENSN

GPIO

RIN1

RIN2

GPIO

2NXP Semiconductors

33813

Table of Contents

1 Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2 Static electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.3 Dynamic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.4 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.5 Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5 General IC functional description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.1 System controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.2 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.3 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.4 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.5 Drivers blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.6 Pre-driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.7 VRS circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.8 ISO9141 bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.9 Mode code and revision number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.10 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.11 SPI registers mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.1 Output OFF open load fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.2 Low voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.3 Low-side injector driver voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.4 Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

7 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

7.1 Package mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

NXP Semiconductors 3

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1 Orderable parts

Table 1. Orderable part variations

Part Number (1) Temperature (TA)Package

MC33813AE -40 °C to 125 °C 48 LQFP-EP

Notes

1. To order parts in tape and reel, add the R2 suffix to the part number.

4NXP Semiconductors

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2 Internal block diagram

Figure 2. Simplified internal block diagram

Oscillator

INJIN1

VPWR

IGNIN1

SCLK

CSB

LOGIC CONTROL

SPI INTERFACE

Gate Control

Current Limit

Temperature Limit

Short/Open

(1 of 5 shown)

lLimit

VClamp

–

Typical of all 5 Driver Outputs

75 µA

INJOUT1

VPPREF

Bandgap

–

PARALLEL

CONTROL

Undervoltage

POR,

V10.0 Analog

V2.5 Logic

Bias

VRSN

VPPSENS

VRS CIRCUIT

VRSOUT

ROUT2

ISO9141

CONTROLLER

MRX

MTX

LAMPOUT

O2HOUT

RESETB

KEYSW

START LOGIC

ISO9141

Ignition 1

IGNOUT1

Pre-drivers

IGNFB1

O2HFB

O2 Heater

GND

O2HIN

INJGND1

INJGND2

TACHOUT

To TACHOUT Driver

PROT

To ROUT2

Watchdog

(SPI CONTROL)

ROUT1

VCC

Pre-

Regulator

Overvoltage

Tracking

+5.0 V

Regulator

+5.0 V

PWR

VAnalog

Logic

BATSW

Parallel Control

SPI Control

Driver

–

lLimit

O2HSENSP

IGNSENSP

IGNSENSN

O2HSENSN

To Logic

Control

To Logic

Control

RIN1

RIN2

Note: All current sinks and sources

50µA except where indicated

Regulator

and REGISTERS

RGND1

RGND2

Divide by “N”

N=1-32

Divider

(SPI)

SLEEP/RUN

VRSP

NXP Semiconductors 5

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3 Pin connections

3.1 Pinout diagram

Figure 3. 33813 Pin connections

3.2 Pin definitions

Table 2. 33813 pin definitions

Pin Pin Name Pin

Function Formal Name Description

1O2HFB Input O2 Sensor Heater

Feedback Input

Voltage feedback from drain of O2 Sensor Heater driver FET. If used as IGBT driver,

voltage feedback from collector of IGBT through 10:1 voltage divider (9R:1R).

2O2HOUT Output O2 Sensor Heater

Output Pre-driver output for O2 Sensor Heater driven by SPI input or O2HIN pin

3IGNSENSP Input Ignition Current

Sense Input Positive

Positive input to the ignition current sense differential amplifier.

Measures current in IGBT emitter resistor (or MOSFET source resistor) for IGNOUT1

and IGNOUT2, if used

4IGNSENSN Input Ignition Current

Sense Input Negative

Negative input to the ignition current sense differential amplifier.

Measures current in IGBT emitter resistor (or MOSFET source resistor) for IGNOUT1

and IGNOUT2, if used

5O2HSENSN Input O2 Heater Current

Sense Input Negative

Negative input to the O2 heater current sense differential amplifier.

Measures current in of O2 heater driver MOSFET source resistor (or IGBT emitter

resistor), if used

6O2HSENSP Input O2 Heater Current

Sense Input Positive

Positive input to the O2 heater current sense differential amplifier.

Measures current in of O2 heater driver MOSFET source resistor (or MOSFET source

resistor) for IGNOUT1 and IGNOUT2, if used

7VRSOUT Output VRS Conditioned

Output 5.0 V Logic Level Output from conditioned VRS differential inputs VRSP, VRSN

O2HFB

O2HOUT

IGNSENSP

IGNSENSN

OH2SENSN

VRSP

VRSN

CSB

VPWR

SCLK

VPPREF

GND

VCC

VPPSENS

RESETB

VPROT

LAMPOUT

RGND2

ROUT2

TACHOUT

MRX

MTX

BATSW

INJIN1

IGNIN1

O2HIN

RIN2

RIN1

KEYSW

INJGND2

RGND1

ROUT1

INJGND1

INJOUT1

ISO9141

IGNFB1

IGNOUT1

OH2SENSP

VRSOUT NC

Transparent Top View

6NXP Semiconductors

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8VRSP Input Variable Reluctance

Sensor Positive Input

The VRSP and VRSN form a differential input for the Variable Reluctance Sensor

attached to the crankshaft toothed wheel.

9VRSN Input

Variable Reluctance

Sensor Negative

Input

The VRSP and VRSN form a differential input for the Variable Reluctance Sensor

attached to the crankshaft toothed wheel.

10 CSB Input SPI Chip Select The Chip Select input pin is an active low signal sent by the MCU to indicate that the

device is being addressed.

11 VPWR Supply Input Main Voltage Supply

Input

VPWR is the main voltage supply input for the device. Should be connected to a 12 Volt

battery with reverse battery protection and adequate transient protection.

12 SCLK Input SPI Clock Input The SCLK input pin is used to clock in and out the serial data on the SI and SO pins

while being addressed by the CSB.

13 SI Input SPI Data Input The SI input pin is used to receive serial data into the device from the MCU.

14 VPPREF Output VPP Reference Base

Drive Base drive for external PNP pass transistor

15 GND Ground Ground Ground pin, return for all voltage supplies

16 SO Output SPI Data Output The SO output pin is used to transmit serial data from the device to the MCU.

17 VCC Supply VCC Supply

Protected Output

5.0 Volt supply output for MCU VCC. This output supplies the VCC voltage for 5.0 Volt

MCUs. It is short-circuit and overcurrent protected.

18 VPPSENS Input Voltage Sense from

VPP Feedback to internal VPP 6.5 Volt regulator from external pass transistor

19 RESETB Output RESETB Output to

MCU

5.0 V Logic level reset signal used to reset the MCU during under and overvoltage

conditions and for initial power-up, down and watchdog timeouts

20 VPROT Output Sensor Supply

Protected Output

The VPROT Output is a protected 5.0 Volt output that tracks the VCC voltage but

isolates the VCC output against shorts to ground and to battery. It is intended to supply

sensors which are located off of the ECU board.

21 LAMPOUT Output Warning Lamp Output Low-side driver output for MIL (warning lamp) driven by SPI input command

22 RGND2 Ground ROUT2 Power

Ground Ground connection for ROUT 2 low-side driver. Must be tied to VPWR Ground.

23 ROUT2 Output Relay Driver 2 Output Low-side relay driver output # 2 driven by SPI input command or RIN2 logic input

24, 25, 30,

32, 39, 47,

N.C. No Connect Unused pin

26 TACHOUT Output Tachometer output This pin provides the low-side drive for a tachometer gauge or alternatively as a SPI

controlled low-side driver, or oscillator output.

27 MRX Output Low-side Driver

Output Output 5.0 V logic level ISO9141 data to the MCU from the ISO9141 IN/OUT pin

28 MTX Input ISO9141 MCU Data

Input Input 5.0 V logic level ISO9141 data from the MCU to the ISO9141 IN/OUT pin

29 BATSW Output Battery Switch This output is a 5.0 V logic level that is high when KEYSW is high. It is only low when

KEYSW is low. It can also be controlled via the SPI.

31 INJIN1 Input Injector Driver Input 1 5.0 V logic level input from the MCU to control the injector 1 driver output. (Can also be

controlled via the SPI)

33 IGNIN1 Input Ignition Input 1 5.0 V logic level input from MCU controlling the ignition coil # 1 current flow and spark.

(Can also be controlled via the SPI)

34 O2HIN Input O2 Sensor Heater

Input

5.0 V logic level input used to turn on and off the O2HOUT driver. The O2HOUT driver

can also be turned on and off via the SPI if this pin is not present in a different package.

35 RIN2 Input Relay Driver Input 2

5.0 V logic level input from the MCU to control the relay 2 driver output ROUT2. The

ROUT2 driver can also be turned on and off via the SPI if this pin is not present in a

different package.

36 RIN1 Input Relay Driver Input 1

5.0 V logic level input from the MCU to control the relay 1 driver output ROUT1. The

ROUT1 driver can also be turned on and off via the SPI if this pin is not present in a

different package.

Table 2. 33813 pin definitions

Pin Pin Name Pin

Function Formal Name Description

NXP Semiconductors 7

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37 KEYSW Input Key Switch Input

The Key Switch Input is a VPWR level signal that indicates that the Key is inserted and

turned to the ON/OFF position. In the ON position the (KEYSW = VBAT) the IC is

enabled and BATSW = HIGH (Relay 2 ON if programmed in the SPI). In the OFF

position the IC is in Sleep mode, only when the PWREN bit in the SPI register is also

low.

38 INJGND2 Ground Injector Driver 2

Ground Ground connection for injector 2 low-side driver. Must be tied to VPWR ground

40 RGND1 Ground ROUT1 Power

Ground Ground connection for ROUT 1 low-side driver. Must be tied to VPWR ground

41 ROUT1 Output Relay Driver 1 Output Low-side relay driver output # 1 driven by the SPI input command or RIN1 logic input

42 INJGND1 Ground Injector Driver 1

Ground Ground connection for injector 1 low-side driver. Must be tied to VPWR ground

43 INJOUT1 Output Injector Driver 1

Output Low-side driver output for injector 1 driven by the SPI input or by parallel input INJIN1

44 ISO9141 Input/Output

ISO9141 K-Line

Bidirectional Serial

Data Signal

ISO9141 pin is VPWR level IN/OUT signal which is connected to an external ECU tester

that uses the ISO9141 protocol.The output is open drain with an internal 32 kΩ pull-up

resistor, and the Input is a ratiometric VPWR level threshold comparator.

45 IGNFB1 Input Feedback from

Collector 1

Voltage feedback from collector of ignition # 1 driver IGBT through 10:1 voltage divider

(9R:1R)(or voltage feedback from the drain of the FET connected to IGNOUT1, if

selected)

46 IGNOUT1 Output Ignition Output 1 Output to gate of IGBT or GPGD for ignition # 1

Table 2. 33813 pin definitions

Pin Pin Name Pin

Function Formal Name Description

8NXP Semiconductors

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4 General product characteristics

4.1 Maximum ratings

Table 3. Maximum ratings

All voltages are with respect to ground, unless mentioned otherwise. Exceeding these ratings may cause malfunction or permanent device

damage.

Symbol Parameter Min. Max. Unit Notes

ELECTRICAL RATINGS

VPWR VPWR Supply Voltage -0.3 45 VDC

VPP_Ext

VPP Supply Voltage (If supplied externally and not using internal VPP regulator)

• VPPREF

• VPPSENSE

-0.3

VDC

VCC VCC Regulator -0.3 7.0 VDC

VPROT VPROT Regulator -0.3 VPWR VDC

VIL, VIH

SPI Interface and Logic Input Voltage (VSI, VSCLK, VCSB, VRIN1, VRIN2, VINJIN1,

VIGNIN1, VO2HIN, VMTX)-0.3 VCC VDC

VIL, VIH SPI Interface and Logic Output Voltage (VSO, VBATSW, VMRX,VVRSOUT)-0.3 VCC VDC

VOUTX

All Low-side Drivers Drain Voltage (VINJOUT1, VROUT1, VROUT2, VLAMPOUT,

VTACHOUT)-0.3 VCLAMP VDC

VGDX All Pre-drivers Output Voltage (VIGNOUT1, VO2HOUT)-0.3 10 VDC

VGDFB All Pre-driver Feedback Inputs Voltage (VIGNFB1, VIGNFB2, VO2HFB)-1.5 60 VDC

VISENS

All Pre-driver Current Sense Inputs Voltage

(VIGNSENSN, VIGNSENSP, VO2HSENSN,VO2HSENSP)-0.3 1.0 VDC

VKEYSW KEYSW Input Voltage (VKEYSW)-18 VPWR VDC

VRESETB RESETB Output Voltage (VRESETB)-0.3 VCC VDC

VISO9141 ISO9141 Input/Output Voltage (VISO9141)-18 VPWR VDC

VVRS_IN Maximum Voltage for VRSN and VRSP inputs to ground -0.5 6.0 VDC

IVRSX_IN Maximum Current for VRSN and VRSP inputs (internal diodes limit voltage) -15 mA

ECLAMP

Output Clamp Energy (INJOUT1, ROUT1, ROUT2)

•T

JUNCTION = 150 °C, IOUT = 1.0 A -100 mJ

ECLAMP_LAMP

Output Clamp Energy (LAMPOUT)

•T

JUNCTION = 150 °C, IOUT = 0.5 A -35 mJ

VESD1

VESD2

VESD3

ESD Voltage

• Human Body Model (HBM)

• Charge Device Model (CDM) (corner pins)

• Charge Device Model (CDM)

±2000

±750

±500

V(2)

Notes

2. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω) and the Charge Device Model.

NXP Semiconductors 9

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THERMAL RATINGS

Operating Temperature (Automotive grade version)

• Ambient

• Junction

•Case

-40

125

150

125

°C

TSTG Storage Temperature -55 150 °C

TPPRT Peak Package Reflow Temperature During Reflow - Note 4 °C(3),(4)

Thermal Resistance and Package Dissipation Ratings

RθJA

RθJC

Thermal Resistance

• Junction-to-Ambient (LQFP-48-EP Package) (Single Layer Board)

• Junction-to-Case (LQFP-48-EP Package)

2.4

°C/W

Notes

3. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause

malfunction or permanent damage to the device.

4. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and

Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number, remove prefixes/suffixes, and enter the core ID to view all orderable

parts (for MC33xxxD enter 33xxx) and review parametrics.

Table 3. Maximum ratings

All voltages are with respect to ground, unless mentioned otherwise. Exceeding these ratings may cause malfunction or permanent device

damage.

Symbol Parameter Min. Max. Unit Notes

10 NXP Semiconductors

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4.2 Static electrical characteristics

Table 4. Power input static electrical characteristics

Characteristics noted under conditions of 6.0 V ≤ VPWR ≤ 18 V, -40 °C ≤ TCASE ≤ 125 °C and Calibrated Timers, unless otherwise noted.

Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 °C.

Symbol Characteristic Min. Typ. Max. Unit Notes

POWER INPUT (VPWR)

VPWR (

)

VPWR (

)

VPWR (

)

Supply Voltage (measured at VPWR pin)

• Logic Stable Range

• Full Operational Range

• Full Parameter Specification Range

2.5

4.5

6.0

V(5)

IVPWR (

)

Supply Current

• All Outputs Disabled (Normal mode), excludes base current to the

external pnp

-10.0 14.0 mA

IVPWR (SS)

Sleep State Supply Current (Must have PWREN = 0 and KEYSW ≤

0.8 V for sleep state),

•V

PWR = 18 V

-10 20 μA

VPWR(OV) VPWR Overvoltage Shutdown Threshold Voltage (OV Reset) 37.5 39 42 V(6)

VPWR(OV-HYS) VPWR Overvoltage Shutdown Hysteresis Voltage 0.5 1.5 3.0 V

VCC(POR) VCC Power On Reset Voltage Threshold (POR), (rising voltage) 3.9 -4.9 V

VCC(UV)

VCC Undervoltage Shutdown Threshold Voltage (UV Reset), (falling

voltage) 2.9 -3.9 V(7)

VCC(UV/POR-HYS) VCC POR and Undervoltage Shutdown Hysteresis Voltage 100 - - mV

VCC,NONOVERLAP VCC POR and Undervoltage Non-overlap (POR-UV) 0.8 1.0 1.2 V

VOLTAGE PRE-REGULATOR OUTPUT (VPPREF, VPPSENS)

VPPSENS VPPSENS Output Voltage 5.85 6.5 7.15 V(8)

IVPPREF_CL VPPREF Current Limit -5.0 -15 -20 mA

VOCE Output Capacitance External (ceramic) 2.2 -25 μF

IVPPSENS VPPSENS Quiescent Current (excluding external PNP current) - - 3 mA

REGLINE_VPP

Line Regulation IVCC = 100 mA, IVPROT = 50 mA, 9.0 V < VPWR < 18 V

and Diodes Inc. FZT753TA PNP -2.0 25 mV

VDROPOUT_VPP

Dropout Voltage (Minimal Input/Output Voltage, tracks input below)

IVCC = 100 mA, IVPROT = 50 mA and Diodes Inc. FZT753TA PNP - - 500 mV

VOLTAGE REGULATOR OUTPUTS (VCC, VPROT)

VCC VCC Output Voltage 0 ≤ IVCC ≤ IVCC_C 4.9 5.0 5.1 V

IVCC_C VCC Output Current Continuous - - 200 mA

IVCC-VPROT|VPROT Output Voltage (tracks VCC)

IVCC = 100 mA, IVPROT = 50 mA 9.0 V < VPWR < 18 V - - 25 mV

IVPROT_C VPROT Output Current Continuous - - 100 mA

IVCC_CL VCC Output Current Limiting 200 -500 mA (8)

IVPROT_CL VPROT Output Current Limiting 110 -260 mA

VOCE

Output Capacitance External (VCC and VPROT) without reverse

protection diode 2.2 -47 μF

Notes

5. This parameter is guaranteed by design but is not production tested.

6. Overvoltage thresholds minimum and maximum include hysteresis.

7. Undervoltage thresholds minimum and maximum include hysteresis

8. Guaranteed at 9.0 V ≤ VPWR ≤ 18 V

NXP Semiconductors 11

33813

VOLTAGE REGULATOR OUTPUTS (VCC, VPROT) (CONTINUED)

VCC VCC Output Voltage 0 ≤ IVCC ≤ IVCC_C 4.9 5.0 5.1 V

REGLINE_VB

Line Regulation (Both VCC and VPROT)

IVCC =100 mA, IPROT = 50 mA, 9.0 V< VPWR < 18 V -2.0 25 mV

REGLOAD_VB

Load Regulation (Both VCC and VPROT) measured from 10% - 90% of

IVCC_C and IPROT_C, VPWR = 13 V -20 35 mV

VDROPOUT_VCC/

VPROT

Dropout Voltage (Both VCC and VPROT) (Minimal Input/Output Voltage

IVCC = 100 mA, IVPROT = 50 mA, tracks input below) - - 500 mV

ALL LOW-SIDE DRIVERS (INJOUT1, ROUT1, ROUT2, LAMPOUT, TACHOUT)

VOUT (FLT-TH)

Output Fault Detection Voltage Threshold, Outputs programmed OFF

(Open Load), Outputs programmed ON (Short to Battery) 2.0 2.5 3.0 V(9)

I(OFF)OCO

Output OFF Open Load Detection Current (INJ1, RELAY1, RELAY2

AND LAMP)

•V

DRAIN = 18 V, Outputs Programmed OFF

40 75 115 μA

I(OFF)TACH Output OFF Open Load Detection Current TachOut 10 -30 μA

IOUT (LKG)

Output Leakage Current

•V

DRAIN = 24 V, Open Load Detection Disabled and Output

commanded OFF - - 20 μA

TLIM Overtemperature Shutdown (OT) 155 -185 °C(9)

TLIM (HYS) Overtemperature Shutdown Hysteresis 5.0 10 15 °C(9)

VOC

Output Clamp Voltage

•I

D = 20 mA 48 53 60 V

INJOUT1

RDS (ON)_INJx

Drain-to-Source ON Resistance

•I

OUT = 1.0 A TJ = 150 °C, VPWR = 13 V - - 0.6 Ω

IOUT (LIM)_INJx Output Self Limiting Current 1.8 -3.0 A

ROUT1

RDS (ON)_R1

Driver Drain-to-Source ON Resistance

•I

OUT = 700 mA, TJ = 150 °C, VPWR = 13 V - - 0.4 Ω

IOUT (LIM)_R1 Output Self-limiting Current (Has inrush current timer) 3.0 -6.0 A

ROUT2

RDS (ON)_R2

Driver Drain-to-Source ON Resistance

•I

OUT = 350 mA, TJ = 150 °C, VPWR = 13 V - - 1.5 Ω

IOUT (LIM)_R2 Output Self-limiting Current 1.2 -2.4 A

LAMPOUT

RDS (ON)_LAMP

Driver Drain-to-Source ON Resistance

•I

OUT = 1.0 A, TJ = 150 °C, VPWR = 13 V - - 1.5 Ω

IOUT (LIM)_LAMP Output Self-limiting Current (Has inrush current timer) 1.2 -2.4 A

Notes

9. This parameter is guaranteed by design, however it is not production tested.

Table 4. Power input static electrical characteristics

Characteristics noted under conditions of 6.0 V ≤ VPWR ≤ 18 V, -40 °C ≤ TCASE ≤ 125 °C and Calibrated Timers, unless otherwise noted.

Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 °C.

Symbol Characteristic Min. Typ. Max. Unit Notes

12 NXP Semiconductors

33813

TACHOUT

RDS (ON)_TACH

Driver Drain-to-Source ON Resistance

•I

OUT = 50 mA, TJ = 150 °C, VPWR = 13 V - - 20 Ω

IOUT (SHUTDOWN)_

TACH

Output Current Shutdown 60 -110 mA

ALL PRE-DRIVERS (IGNOUT1 AND O2HOUT)

VGS(ON)

VGS(OFF)

Pre-driver Output Voltage, VPWR = 13 V

•I

GD = 500 μA

•I

GD = -500 μA

7.0

0.0

8.0

0.375

9.0

0.5

IIGN_GD_H

IGNOUT1 Output Source Current (IGNOUT1 by default)

•1.0 ≤ VGD ≤ 3.0, VPWR = 13 V 10 - - mA

I(OFF)OCO

Output OFF Open Load Detection Current

•V

DRAIN = 18 V, Outputs Programmed OFF 40 75 115 μA

IGPGD_GD_H

GPGD Output Source Current (O2HOUT by default) at 1.0 ≤ VGD ≤ 3.0,

VPWR = 13 V 10 - - mA

VIGNFB (FLT-TH)

VGPGD(FLT_TH)

Pre-driver Fault Detection Voltage Threshold, Outputs programmed

OFF (open load), Outputs programmed ON (short to battery)

•I

GD = 500 μA

•I

GD = -500 μA

100

1.0

250

2.5

400

4.0

VCLAMP Output Clamp Voltage 48 53 60 V

VSENS-TH

Overcurrent Voltage Threshold for O2HOUT

•V

O2HSENSN to VO2HSENSP

180 200 220 mV

VSENS-TH

Overcurrent Voltage Threshold for IGNOUT1

•V

IGNSENSN to VIGNSENSP (IGNIN1 = 1) 180 200 220 mV

ISENS-OFFSET

Current Sense Input Offset Current (IGNSENSP,IGNSENSN,

O2HSENSN, O2HSENSP) - - 15 μA

ISENS-BIAS Current Sense Input Bias Current - - 15 μA

ISO-9141 TRANSCEIVER PARAMETERS (8.0 V < VPWR < 18 V)

VIL_ISO Input Low Voltage at ISO I/O pin - - 0.3xVPWR V

VIH_ISO Input High Voltage at ISO I/O pin 0.7*VPWR - - V

VHYST_ISO Input Hysteresis at ISO I/O pin 0.15x

VPWR

- - V

VOL_ISO Output Low-voltage at ISO I/O pin - - 0.2xVPWR V

VOH_ISO Output High-voltage at ISO I/O pin 0.8x

VPWRR- - V

ILIM_ISO Output current limit at ISO I/O pin (MTX = 0) 50 100 150 mA

CL_ISO Load capacitance at ISO I/O pin 0.01 3.0 10 nF (10)

I_ISO Output load current at ISO I/O pin (MTX = 0, RLOAD = 1.0 kΩ, ±10%) - 12 -mA

TLIM Overtemperature Shutdown (OT) 155 -185 °C(10)

TLIM (HYS) Overtemperature Shutdown Hysteresis 5.0 10 15 °C(10)

Notes

10. This parameter is guaranteed by design, however it is not production tested.

Table 4. Power input static electrical characteristics

Characteristics noted under conditions of 6.0 V ≤ VPWR ≤ 18 V, -40 °C ≤ TCASE ≤ 125 °C and Calibrated Timers, unless otherwise noted.

Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 °C.

Symbol Characteristic Min. Typ. Max. Unit Notes

NXP Semiconductors 13

33813

VRS CONDITIONER INPUT

VVRS_THRESH Comparator Thresholds -See Table variable via

SPI or dynamically mV

AccuTHRESH

Threshold Accuracy

Steady State Condition (±20% only valid for VRS DAC thresholds

110 mV and higher.All other thresholds guaranteed monotonic only.)

- - ±20 %

IBIASRSX Input Bias Current VRSP and VRSN (2.5 V common mode must be off) -5.0 5.0 µA

VCLAMP_P VRS Positive Clamp Voltage at ICLAMP = 10 mA 5.5 -5.8 V

VCLAMP_N VRS Negative Clamp Voltage at ICLAMP = 10 mA -0.45 --0.22 V

DIGITAL INTERFACE (MRX, MTX,CSB, SI, SCLK, SO, RINX,O2HIN, INJIN1, IGNIN1, BATSW, VRSOUT, RESETB)

VIH Input Logic High-voltage Thresholds 0.7 x VCC - VCC + 0.3 V

VIL Input Logic Low-voltage Thresholds GND - 0.3 -0.2 x VCC V

VHYS Input Logic Voltage Hysteresis 500 - - mV

CIN Input Logic Capacitance - - 20 pF

LOGIC_SS

Sleep Mode Input Logic Current

• KEYSW = 0 V -10 -10 μA(11)

ILOGIC_PD

Input Logic Pull-down Current INJIN1, RIN1, RIN2, SI, SCLK, IGNIN1,

O2HIN

•0.8 V to 5.0 V

30 50 100 μA(11)

TRISO

SO Tri-state Output (in Tri-state mode, CSB = 1)

•0 V to 5.0 V -10 -10 μA

ICSB

CSB Input Current

• CSB = VCC -10 -10 μA

ILOGIC_PU

Input Logic Pull-up Current - CSB and MTX

• 0.0 to 4.2 V -20 -40 -90 μA

ICSB(LKG)

CSB Leakage Current to VCC

• CSB = 5.0 V, KEYSW = 0.0 V - - 10 μA

VSO_HIGH

VMRX_HIGH

SO, MRX High-state Output Voltage (CSB =0 for SO)

•I

SO-HIGH = -1.0 mA VCC - 0.4 - - V

VSO_LOW

VMRX_LOW

SO, MRX Low-state Output Voltage (CSB =0 for SO)

•I

SO-LOW = 1.0 mA - - 0.4 V

VBATSW_HIGH

BATSW High-state Output Voltage

•I

SO-HIGH = -10 mA VCC - 1.0 - - V

VBATSW_LOW

BATSW Low-state Output Voltage

•I

SO-LOW = 10 mA - - 1.0 V

VKEYSW_HIGH KEYSW High-state Input Voltage 4.5 - VPWR V

VKEYSW_LOW KEYSW Low-state Input Voltage -0.3 -2.5 V

VKEYSW_HYS KEYSW Hysteresis 100 - - mV

Notes

11. This parameter is guaranteed by design, however it is not production tested.

Table 4. Power input static electrical characteristics

Characteristics noted under conditions of 6.0 V ≤ VPWR ≤ 18 V, -40 °C ≤ TCASE ≤ 125 °C and Calibrated Timers, unless otherwise noted.

Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 °C.

Symbol Characteristic Min. Typ. Max. Unit Notes

14 NXP Semiconductors

33813

DIGITAL INTERFACE (MRX, MTX,CSB, SI, SCLK, SO, RINX,O2HIN, INJIN1, IGNIN1, BATSW, VRSOUT, RESETB) (CONTINUED)

VVRSOUT_LOW

VRS Low-state Output Voltage

•I

VRS-LOW = 1.0 mA - - 0.4 V

VVRSOUT_HIGH

VRS High-state Output Voltage

•I

VRS-HIGH = 1.0 mA VCC -0.4 -5.0 V

VRESET_LOW

RESET Low-state Output Voltage

•I

RESET-LOW = 1.0 mA - - 0.4 V

IRESET_

LEAKAGE_HIGH

RESET High-state Leakage Current - - 25 μA

RRESET_PULDOWN RESET Pull-down Resistor 200 -500 kΩ

Table 4. Power input static electrical characteristics

Characteristics noted under conditions of 6.0 V ≤ VPWR ≤ 18 V, -40 °C ≤ TCASE ≤ 125 °C and Calibrated Timers, unless otherwise noted.

Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 °C.

Symbol Characteristic Min. Typ. Max. Unit Notes

NXP Semiconductors 15

33813

4.3 Dynamic electrical characteristics

Table 5. Dynamic electrical characteristics (13)

Characteristics noted under conditions of 6.0 V ≤ VPWR ≤ 18 V, -40 °C ≤ TCASE ≤ 125 °C and Calibrated Timers, unless otherwise noted.

Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 °C.

Symbol Characteristic Min Typ Max Unit Notes

POWER INPUT

RESET

Required Low State Duration on VCC for Power On Reset

•V

CC ≤ 0.2 V 1.0 - - μs

t(POR) Power on RESET pulse width 100 - - μs

t(KEYSW_FILTER) KEYSW Filter Time -12.7 -ms (12)

WATCHDOG TIMER

WDMAX Maximum Time Value Watchdog can be loaded with (default time) - - 10 sec.

WDMIN Minimum Time Value Watchdog can be loaded with 1.0 - - ms

WDRESET Reset Pulse Width when Watchdog times out 100 - - μs

VRS CONDITIONING INPUT

OUTPUTBLANK Output Blanking Time Programming Range

(% of previous out pulse 0 to 15/32 in 1/32 steps, 15/32 = 46.9%) 0 - 50 %

OUTPUTDEGLITCH Output Deglitch Filter Time (1/128 of the previous output pulse) -1.0 - %

DELAYTHRESH Delay from CSB to Change in VRS Comparator Threshold - - 10 μs(12)

DELAYOBT Delay from CSB to Change in VRS Output Blank Time - - 10 μs(12)

ISO9141 TRANSCEIVER

ISOBR Typical ISO9141 Data Rate - 10 - kbps

tTXDF Turn OFF Delay MTX Input to ISO Output - -2.0 μs

tRXDF, tRXDR Turn ON/OFF Delay ISO Input to MRX Output - - 1.0 μs

tRXR, tRXF Rise and Fall Time MRX Output (measured from 10% to 90%) - - 1.0 μs

tTXR, tTXF Maximum Rise and Fall Time MTX Input (measured from 10% to 90%) - - 1.0 μs

ALL LOW-SIDE DRIVERS

tSC1 Output ON Current Limit Fault Filter Timer 30 60 90 µs

tREF Output Retry Timer 7.0 10 13 ms

tINRUSH Inrush Current Delay Timer 7.0 10 13 ms (12)

t(OFF)OC Output OFF Open-circuit Fault Filter Timer 100 -400 µs

SR(RISE)

Output Slew Rate, INJOUT1, IROUT1, ROUT2 and LAMPOUT

•R

LOAD = 500 Ω, VLOAD = 14 V 1.0 5.0 10 V/μs

SR(FALL)

Output Slew Rate, INJOUT1, ROUT1, ROUT2 and LAMPOUT

•R

LOAD = 500 Ω, VLOAD = 14 V 1.0 5.0 10 V/μs

tPHL

Propagation Delay (Input Rising Edge OR CSB to Output Falling Edge)

• Input at 50% VDD to Output voltage 90% of VLOAD (INJOUT1,

ROUT1, ROUT2, LAMP)

-1.0 5.0 µs

tPHL

Propagation Delay (Input Rising Edge OR CSB to Output Falling Edge)

• Input at 50% VDD to Output voltage 90% of VLOAD

(TACHOMETER)

-1.0 6.0 µs

Notes

12. Guaranteed by Design

13. internal oscillator of 4.0 MHz ±10% typical for VPWR = 13 V, at room temp.

16 NXP Semiconductors

33813

ALL LOW-SIDE DRIVERS (CONTINUED)

tPLH

Propagation Delay (Input Falling Edge OR CSB to Output Rising Edge)

• Input at 50% VDD to Output voltage 10% of VLOAD (INJOUT1,

ROUT1, ROUT2, LAMP)

-1.0 5.0 µs

tPLH

Propagation Delay (Input Falling Edge OR CSB to Output Rising Edge)

• Input at 50% VDD to Output voltage 10% of VLOAD

(TACHOMETER)

-1.0 6.0 µs

SR(FALL)

Output Slew Rate, Tachout

•R

LOAD = 500 Ω, VLOAD = 14 V 6.0 -14 V/μs

ALL GATE PRE-DRIVER (IGN1, AND O2H)

t(OFF)OC Output OFF Open-circuit Fault Filter Timer 100 -400 µs

tSC1 Overcurrent (short-circuit) Fault Filter Timer 30 -90 µs

tPLH

Propagation Delay (Input Rising Edge OR CSB to Output Rising Edge)

• Input at 50% VDD to Output voltage 10% of VGS(ON)

-1.0 5.0 µs

tPHL

Propagation Delay (Input Falling Edge OR CSB to Output Falling Edge)

• Input at 50% VDD to Output voltage 90% of VGS(ON)

-1.0 5.0 µs

SPI DIGITAL INTERFACE TIMING (14)

LEAD

Falling Edge of CSB to Rising Edge of SCLK

• Required Setup Time 100 - - ns

LAG

Falling Edge of SCLK to Rising Edge of CSB

• Required Setup Time 50 - - ns

SI (SU)

SI to Rising Edge of SCLK

• Required Setup Time 16 - - ns

SI (HOLD)

Rising Edge of SCLK to SI

• Required Hold Time 20 - - ns

R (SI) SI, CSB, SCLK Signal Rise Time (15) -5.0 -ns

(SI) SI, CSB, SCLK Signal Fall Time (15) -5.0 -ns

SO (EN) Time from Falling Edge of CSB to SO Low-impedance (16) - - 55 ns

SO (DIS) Time from Rising Edge of CSB to SO High-impedance - - 55 ns

VALID Time from Falling Edge of SCLK to SO Data Valid (17) -25 55 ns

tSTR

Sequential Transfer Rate (14)

• Time required between data transfers - - 1.0 µs

Notes

14. These parameters are guaranteed by design. Production test equipment uses 1.0 MHz, 5.0 V SPI interface (variable with magnitude input

frequency).

15. Rise and Fall time of incoming SI, CSB and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

16. Time required for output states data to be terminated at SO pin.

17. Time required to obtain valid data out from SO following the fall of SCLK with 200 pF load.

Table 5. Dynamic electrical characteristics (13)

Characteristics noted under conditions of 6.0 V ≤ VPWR ≤ 18 V, -40 °C ≤ TCASE ≤ 125 °C and Calibrated Timers, unless otherwise noted.

Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 14 V, TA = 25 °C.

Symbol Characteristic Min Typ Max Unit Notes

NXP Semiconductors 17

33813

4.4 Timing diagrams

Figure 4. Timing diagram

tSO(DIS)

0.7 VDD

0.2 VDD

0.7 VDD

0.2 VDD

tLEAD

tSO(EN)

tSI(SU) tSI(HOLD)

tVALID

tLAG

CSB

SCLK

MSB in

MSB out LSB out

0.7 VDD

0.2 VDD

18 NXP Semiconductors

33813

4.5 Typical electrical characteristics

4.5.1 Driver and gate driver characteristics

Figure 5. Typical electrical specifications

0 5 10 15 20

100uA

500uA

1mA

Iload

G ate Pre - D rive V oh vs V pw r @ 25 d e g C

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

0 5 10 15 20

100uA

500uA

1mA

Vpwr (V)

G ate Pre - Driv e V ol v s V pwr @ 25 d e g C

NXP Semiconductors 19

33813

Figure 6. Typical electrical specifications (continued)

4.5.2 VCC and VPROT characteristics

Figure 7. VCC voltage vs. VPWR at 125 °C

Figure 8. VCC voltage vs. VPWR at 25 °C

Figure 9. VCC voltage vs. VPWR at -40 °C

Figure 10. VPROT voltage vs. VPWR at 125 °C

0.15

0.17

0.19

0.21

0.23

0.25

0.27

4 6 8 10 12 14

Inj Driver Rdson vs Vpwr 25 deg C

Vpwr (V)

(

)

20 NXP Semiconductors

33813

Figure 11. VPROT voltage vs. VPWR at 25 °C Figure 12. VPROT voltage vs. VPWR at -40 °C

NXP Semiconductors 21

33813

5 General IC functional description and application

information

5.1 System controller

5.1.1 System control signals

5.1.1.1 KEYSW input pin

KEYSW is the input from the vehicle ignition key switch. This signal is at VBAT (12 V) when the key is inserted and turned to the ON

position. When the key is in the OFF position and/or removed from the key switch, this input is pulled to ground by an internal pull-down

resistor. This pin is internally protected against a reverse battery condition by an internal diode. The state of the KEYSW input is also

available as a bit in the SPI Status Register.

5.1.1.2 BATSW output pin

The BATSW output pin is a 5.0 V logic level output, which by default is an indication of the state of the KEYSW input.

5.1.1.3 PWREN SPI control register BIT

The PWREN signal is a bit in the SPI Control Register #1 allowing “Prepare to shutdown” state transition.

5.1.2 Operating modes

5.1.2.1 Power On Reset (POR)

Applying VPWR and bringing KEYSW high (VBAT), longer than the KEYSW filter time, generates a Power On Reset (POR) and places the

device in the Normal operating state. The Power On Reset circuit incorporates a timer to prevent high frequency transients from causing

an erroneous POR. Upon enabling the device (KEYSW High), outputs are activated based on the initial state of the control register or

parallel input. All three supplies, VPP, VCC and VPROT, are enabled when KEYSW is brought high.

Table 6. Operational states

KEYSW Input PWREN SPI Bit

Input BATSWB Output All Supplies STATE

LLLOFF Sleep

H L H ON NORMAL

HHHON NORMAL

L H L ON Prepare to shutdown

22 NXP Semiconductors

33813

Figure 13. 33813 functional state diagram

5.1.2.2 Normal state

The default Normal state is entered when power is applied to the VPWR and KEYSW pins. Note that the device is designed to have VPWR

present before KEYSW is brought high. It is acceptable to bring VPWR and KEYSW high simultaneously. However it is not recommended

to bring KEYSW high while VPWR is low.

SPI register settings from Power On Reset (POR) are as follows:

• All outputs turned off

• Off State open load detection enabled (LSD)

• Default values in the SPI Configuration, Control and Status registers

5.1.2.3 Sleep state

When KEYSW signal is low and the PWREN SPI Control register bit is also low, the 33813 enters into Sleep mode. In the Sleep state, all

outputs, current sources and sinks are off and the device consumes less than IVPWR (SS). When KEYSW signal goes high, it wakes up the

IC, turns on the VPP regulator and a Power On Reset signal is generated.

NXP Semiconductors 23

33813

5.1.2.4 Prepare to shutdown state

The purpose of the PWREN signal is to allow the MCU to control the shutdown of power to itself when the user turns off the KEYSW. This

may be necessary to allow the MCU the time required to perform its pre-shutdown routines. When the MCU wants to shutdown the power

supplies in the 33813, it must write a logic zero (0) to the PWREN bit in the SPI Control register. Only the state of the PWREN bit in the

SPI Control register controls the shutdown of the 33813 power supplies. In this state, only the outputs are turned off (except ROUT2 if the

Shutdown Disable bit is set. See 5.5.3.3. Using ROUT2 as a power relay, page 37).

Note: In case of KEYSW = 1 condition, 33813 goes back in Normal mode, retrieving the last register configuration. This suggests that

before entering in Prepare to Shutdown mode, user needs to configure registers as appropriate (switching off drivers and pre-drivers for

example).

5.1.2.5 Power On Self-test (POST)

When a power on occurs after a POR, it may be desired to go through an initial Power On Self-test routine to ensure the SPI is working

correctly and the status registers in the 33813 are viable. After a POR, all the registers in the 33813 contain their ‘default’ values, as

indicated in the SPI register tables later in this document. The watchdog is also set to its default timeout value of 10 seconds, so any POST

routine must be accomplished within this time frame or a WD reset may occur.

To perform a POST routine, the MCU should first send a SPI message to set the POST enable bit in the SPI control register 1, bit 6. Once

this bit is set, the status registers are disconnected from the analog and logic portions of the 33813 and are connected only to the SPI

circuitry. The POST can then write various data patterns to the status registers and verify that none of the bits are ‘stuck’ and state of the

bit is accurately reflected. Note that bits in the status register labeled ‘x’ are not implemented and testing these bits may result in erroneous

data. After testing all the status registers and confirming they are viable, the status registers can be set back to their default values by

clearing the POST Enable bit back to 0. The POST enable bit allows the MCU to write ones (1s) to the Status registers.

Normally, the status register can only be cleared to zeros by the MCU and ones can be written to the status register only by the 33813

internal logic. This is designed to prevent the MCU from missing any reported fault bits and, for the 33813, to prevent system status errors

resulting from the MCU erroneously writing a one (1) to a fault bit.

Once the POST enable bit is set back to a zero (0) by the MCU, the status register returns to the condition where the 33813 can only write

ones(1s) to it and the MCU can only write zeros (0s) to it. Again, it is important to note that any POST routine should be designed to take

less than 10 seconds to avoid a watchdog reset from occurring and truncating the POST routine, because the WD reset clears the POST

Enable bit as well.

5.1.3 BATSW output functionality

The BATSW output pin has several functionalities:

• By default, the BATSW output pin is an indication of the state of the KEYSW input.

• The BATSW output can also be used to control an LS driver, such as the Relay ROUT2 driver by connecting the BATSW output

to the RIN2 input.

• The BATSW output can also be configured as a low current LED high-side driver controlled through the SPI interface.

5.1.3.1 BATSW pin as a KEYSW input indication

When KEYSW is at VBAT (12 V) level, the BATSW output is a logic 1 (5.0 V) and when KEYSW is at ground (0 V) level, BATSW is at a

logic 0. The BATSW output may be used to inform the MCU the user is trying to shutdown the vehicle.

5.1.3.2 BATSW pin as an LS driver control

The BATSW output can also be used to control an LS driver, such as the Relay ROUT2 driver, by connecting the BATSW output to the

RIN2 input. (see 5.5.3.3. Using ROUT2 as a power relay, page 37)

5.1.3.3 BATSW pin as an LED driver

If the BATSW signal is not needed by the MCU or to control the Relay 2 output, it can be configured as a low current LED high-side driver

controlled through the SPI interface. As a high-side driver, BATSW can be PWM’d to allow an LED to be dimmed. A bit in the SPI Battery

Switch Logic Output Configuration register called ‘HSD’, controls whether the BATSW output is a simple high-side driver, or controlled by

KEYSW as indicated previously.

24 NXP Semiconductors

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Figure 14. Recommended Circuit to Use BATSW as an LED Driver

If the BATSW output is used to control an LED, the LED cathode should be tied to ground and the LED anode should be connected to the

BATSW pin through an external resistor. The value of the external resistor should be 340 Ω or greater. Care must be taken if the BATSW

output is sent off-board due to the chance of shorts to the battery or shorts to ground, for which the output is not protected. At a minimum,

this output should be protected by a diode, a current limit resistor and an ESD capacitor (0.01 µF ceramic).

5.1.4 System SPI registers

5.1.4.1 SPI configuration registers

5.1.4.2 SPI control registers

Table 7. Battery switch logic output configuration register

Reg # Hex 76543210

6 6 Battery Switch Logic Output HSD mode xxxxxPWM

Freq.1

PWM

Freq. 0

Reset (0) (0) (0) (0) (0) (0) (0) (0)

Table 8. Battery switch logic output configuration register field

Field Description

7-HSD mode

BATSW mode selection

0 - BATSW is controlled by KEYSW

1 - BATSW is used as a high-side driver

1-0 PWM Freq.x

PWM Frequency and Duty Cycle mode (18)

00 - PWM Freq.: None

01 - PWM Freq.:100 HZ-D/C: Internal

10 - PWM Freq.: 1 kHZ-D/C: Internal

Notes

18. See 5.5.2.2. Pulse Width Modulation mode, page 35

Table 9. Other OFF/ON control register

Reg # Hex 76543210

1 1 Other OFF/ON Control

Pwren

OFF/ON

POST

Enable

OFF/ON

XVProt

ON/OFF XBatsw

OFF/ON

Tach

OFF/ON

RESET

internal

only

Reset (0) (0) (0) (1) (0) (0) (1) (0)

8 8 Batsw XPWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0

Reset (0) (0) (0) (0) (0) (0) (0) (0)

300



OffBoard

MC33814

300



BATSW

LED.01μF

GND

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5.1.4.3 SPI status registers

Table 10. Other OFF/ON control register field description

Field Description

7-Pwren OFF/ON

Power Enable

0-Power Disable (allowing sleep mode entry)

1-Power Enable (allowing Prepare to Shutdown mode entry)

6-POST Enable OFF/ON

Power On Self Test Enable

0-POST Disable

1-POST Enable

2-BATSW OFF/ON

BATSW Output Control

0-BATSW Output OFF

1-BATSW Output ON

Table 11. BATSW control register field description

Field Description

6-0 PWM x

PWM Duty Cycle Setting with 1% increment 0000000 to

1100100 (Dec. 100) represent 0% to 100%

1100100 (Dec. 100) to 1111111 (Dec.127) all map to 100%.

Table 12. Power supply and any system fault status register

Reg # Hex 76543210

13 DPower Supply and Any

System Faults

Any

System

Faults

Keysw Pwren Batsw SPI Error

VPROT

Short to

Battery

VPROT

Overtemp

VPROT

Short to

Ground

Reset (0) (1) (0) (0) (0) (0) (0) (0)

Table 13. Power supply and any system fault status register field description

Field Description

7-Any System Fault

System-wide any fault bit whose stats is the OR of all the other “Any fault” bits in the other status

0-No Fault reported

1-At least one Fault is reported (19)

6-Keysw

KEYSW Pin Status:

0-KEYSW is high (VBAT Present)

1-KEYSW is low (Prepare to Shutdown mode)

5-PWREN

PWREN Status

0-PWREN Control bit is low

1-PWREN Control bit is high

4-Batsw

BATSW Pin Status

0-BATSW Pin is low

1-BATSW Pin is high

Notes

19. The MCU must interrogate all the other status registers to determine the actual fault(s) present.

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5.2 Watchdog

5.2.1 Watchdog Normal operation

The watchdog is a programmable timer used to monitor the operation of the MCU. The timer programming is done by the Watchdog

Parameters SPI Configuration Register by selection the Time Multiplier Value (bit 6-4) and the Time Value (bit 3-0).

Watchdog Timer = Time Multiplier Value (1.0 s,100 ms, or 10 ms) X Time Value (1 to 10)

Using this technique, time values from 1.0 ms. to 10 seconds can be programmed into the watchdog.(default value is 10 s)

When the MCU is executing code properly, its program code should contain instructions to periodically send a SPI message to the

watchdog SPI control register to refresh the watchdog. The watchdog timer, once refreshed, reloads the time interval value stored in the

SPI watchdog configuration register and begins counting time again. Under normal operating conditions this sequence continues until the

MCU shuts down, typically, when the KEYSW is turned off.

5.2.2 Watchdog Fault operation

In the event that something goes wrong during the MCU program execution, such as an unexpected breakpoint or some other program

hang-up such as the execution of a HALT instruction, the watchdog may not be refreshed. When the WD time interval value programmed

in the SPI Configuration register elapses, the watchdog issues a RESETB pulse. This RESETB pulse causes the MCU to restart its

program and correct operation should be restored. After any RESETB (power-on or other), the watchdog SPI configuration register

contains the default value for the refresh time (10 seconds). The watchdog is also enabled by default. The MCU, in its initialization (start-

up) code, can choose to change this default value and/or disable the watchdog by sending a SPI command to write new information in the

watchdog SPI configuration register.

5.2.3 Disabling the Watchdog timer

A watchdog reset occurs, by default, 10 seconds after the POR. If the MCU needs to be programmed in-circuit, a means of disabling the

watchdog must be provided to avoid interrupting the MCU programming procedure. This disable mechanism can be a jumper between the

RESETB pin of the 33813 and the MCU’s Reset input pin. Alternatively, an isolation resistor can be placed between the RESETB pin on

the 33813 and the MCU’s reset input pin, allowing the MCU’s reset pin to be pulled high independently of the 33813 RESETB. The

watchdog can also be disabled via a bit in the SPI WD configuration register.

5.2.4 Watchdog SPI register

5.2.4.1 Watchdog SPI configuration register

Table 14. Watchdog parameters configuration registers

Reg # Hex 76543210

10 AWatchdog Parameters

Disable/

Enable

Load Time

x1 sec

Load Time

x100 ms

Load Time

x10 ms

Load Time

Reset (1) (1) (0) (0) (1) (0) (1) (0)

Table 15. Watchdog parameter - register field descriptions

Field Description

7-Disable/Enable

Watchdog Enable/Disable

0-Watchdog Disable

1-Watchdog Enable (Default State)

6-Load Time x1 sec

Time Multiplier Value (20)

0- Disable

1- Multiplier value = 1.0 sec (Default State)

5-Load Time x100 ms

Time Multiplier Value (20)

0- Disable (Default State)

1- Multiplier value = 100 ms

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5.2.4.2 Watchdog SPI control register

Note: The watchdog SPI Control Register can also be loaded with a time value to temporarily set a different value in the watchdog timer

for the next cycle. When Bits 6 thru 0 in the watchdog SPI control register are zero, the value stored in the watchdog SPI configuration

register loads into the watchdog timer. If there is a temporary time value written into the watchdog SPI control register, the value loads

into the watchdog. The watchdog SPI control register is automatically cleared to zero when the watchdog timer is loaded. Unless a new

temporary time value is again written to the watchdog SPI Control Register, the next watchdog timer load is from the value stored in the

watchdog SPI configuration register,

4-Load Time x10 ms

Time Multiplier Value (20)

0- Disable (Default State)

1- Multiplier value = 10 ms

3-0 Load Time Value

Bits 3, 2, 1, 0 are a binary coded decimal (BCD) value from 1 to 10. (11 to 16

are mapped to 10 and 0 is mapped to 1)

Default state = 1010 = X10

Notes

20. There are three time multiplier values so only one bit, 6, 5, or 4 may be set at one time. Setting

more than one bit results in the highest multiplier value getting precedence.

Table 16. Watchdog control registers

Reg # Hex 76543210

12 CWatchdog WDRFSH Load Time

x1 sec

Load Time

x100 ms

Load Time

x10 ms

Load Time

Reset (0) (0) (0) (0) (0) (0) (0) (0)

Table 17. Watchdog control - register field descriptions

Field Description

7-WDRFSH

Watchdog Refresh

0-No Watchdog refresh action

1-Refresh the watchdog timer. (reload the time value from the Watchdog

Parameters Register)

6-Load Time x1 sec

Temporary Time Multiplier Value (21)

0- Disable

1- Multiplier value = 1.0 sec

5-Load Time x100 ms

Temporary Time Multiplier Value (21)

0- Disable

1- Multiplier value = 100 ms

4-Load Time x10 ms

Temporary Time Multiplier Value (21)

0- Disable

1- Multiplier value = 10 ms

3-0 Load Time Value Bits 3, 2, 1, 0 are a Temporary Binary coded decimal (BCD) value from 1 to 10.

(11 to 16 are mapped to 10 and 0 is mapped to 1)

Notes

21. There are three time multiplier values so only one bit, 6, 5, or 4 may be set at one time. Setting

more than one bit results in the highest multiplier value getting precedence.

Table 15. Watchdog parameter - register field descriptions

Field Description

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5.2.4.3 Watchdog SPI status register

Bits [6:0] represent the value stored in the watchdog timer. If the watchdog is enabled, this value read on the fly represents the time left

before a watchdog reset.

Table 18. Watchdog status register

Reg # Hex 76543210

10 AWatchdog State

Enable/

Disable

WD timer

bit 6

WD timer

bit 5

WD timer

bit 4

WD timer

bit 3

WD timer

bit 2

WD timer

bit 1

WD timer

bit 0

Reset (0) (0) (0) (0) (0) (0) (0) (0)

Table 19. Watchdog status - register field descriptions

Field Description

7-Enable/Disable

Watchdog Enable/Disable Status

0-Watchdog disable

1-Watchdog Enable

6-0 WD Timer bit x Reflecting the Watchdog Timer value

Each step represents the WD timer/127

Table 20. Watchdog timer values

Status register

WD timer bit6 WD timer bit5 WD timer bit4 WD timer bit3 WD timer bit2 WD timer bit1 WD timer bit0 Value in ms

0 0 0 0 0 0 1 1

0 0 0 0 0 1 0 2

0 0 0 0 0 1 1 3

0 0 0 0 1 0 0 4

0 0 0 0 1 0 1 5

0 0 0 0 1 1 0 6

0 0 0 0 1 1 1 7

0 0 0 1 0 0 0 8

0 0 0 1 0 0 1 9

0 0 1 0 0 0 1 10

0 0 1 0 0 1 0 20

0 0 1 0 0 1 1 30

0 0 1 0 1 0 0 40

0 0 1 0 1 0 1 50

0 0 1 0 1 1 0 60

0 0 1 0 1 1 1 70

0 0 1 1 0 0 0 80

0 0 1 1 0 0 1 90

0 1 0 0 0 0 1 100

0 1 0 0 0 1 0 200

0 1 0 0 0 1 1 300

0 1 0 0 1 0 0 400

0 1 0 0 10 0 1 500

0 1 0 0 1 1 0 600

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5.3 System reset

5.3.1 RESETB output pin

The RESETB pin is a 5.0 volt logic, low level output used to reset the MCU.The RESETB pin is an open drain output. Without power on

the 33813 circuit, the RESETB pin is held low by an internal pull-down resistor. In a typical application, the RESETB pin must be pulled

up externally by a pull-up resistor to VCC.

5.3.2 Reset sources

When power is applied to the circuit and the voltage on the VCC pin reaches the lower voltage threshold, the RESETB pin remains at a

low level (open drain FET turned on) for a period of time equal to the time value WDRESET. After this time period, the RESETB pin goes

high and stays high until a reset pulse is generated due to any of the following events:

• A watchdog timer timeout event occurs

• An undervoltage event on VCC occurs

• An overvoltage event on VPWR occurs

A Power On Reset (POR) is always provided upon power ON (anytime the IC goes from sleep state to active state).

5.3.3 Internal reset

The SPI control register includes a bit labeled ‘Reset’. When this bit is set to a one (1) by the MCU, it instructs the 33813 to perform an

internal reset. This reset does NOT toggle the RESETB output pin. However, it causes all internal registers to be initialized back to their

default values (including clearing the reset bit in the SPI control register).

0 1 0 0 1 1 1 700

0 1 0 1 0 0 0 800

0 1 0 1 0 0 1 900

1 0 0 0 0 0 1 1000

1 0 0 0 0 1 0 2000

1 0 0 0 0 1 1 3000

1 0 0 0 1 0 0 4000

1 0 0 0 1 0 1 5000

1 0 0 0 1 1 0 6000

1 0 0 0 1 1 1 7000

1 0 0 1 0 0 0 8000

1 0 0 1 0 0 1 9000

1 0 0 1 0 1 0 10000

Table 21. Other OFF/ON control register

Reg # Hex 76543210

1 1 Other OFF/ON Control

Pwren

OFF/ON

POST

Enable

OFF/ON

XVProt

ON/OFF XBatsw

OFF/ON

Tach

OFF/ON

RESET

internal

only

Reset (0) (0) (0) (1) (0) (0) (1) (0)

Table 20. Watchdog timer values (continued)

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5.4 Power supplies

5.4.1 Pin description

5.4.1.1 PWR supply input

The VPWR pin is the battery input to the 33813 IC. The VPWR pin requires an external reverse battery and adequate transient voltage

protection. The VPWR pin should be bypassed to ground, as close to the IC as possible, with a 0.1 µF ceramic capacitor.

5.4.1.2 VPPREF output

The VPPREF output pin is used to drive the base of an external regulator PNP pass transistor. It is not recommended that this voltage be

brought off of the module PC board, because it may not have adequate protection to prevent damage to the PNP pass transistor under

short-to-ground or short-to-battery conditions.

5.4.1.3 VPPSENS input

The VPPSENS pin is used to monitor the VPP pre-regulator output voltage from the external pass transistor’s collector and to supply the

input voltage to the VCC and VPROT regulators. The VPPSENS pin should be bypassed to ground, as close to the IC as possible, with a

0.1 µF ceramic capacitor and a higher value electrolytic capacitor in parallel. The VPPSENS pin should not be used to supply other

components. The external regulator PNPN pass transistor should be dedicated to the 33813.

5.4.1.4 VCC output (5.0 V supply)

The VCC output supplies 5.0 V power to the system MCU and other on-board peripherals. An external capacitor VOCE is recommend.

5.4.1.5 VPROT output (5.0 V protected supply)

The VPROT Output is a protected 5.0 Volt output that tracks the VCC voltage. The VPROT output should be protected against ESD by

means of a 0.1 µF ceramic capacitor on the output and a higher value electrolytic capacitor in parallel. An external capacitor VOCE is also

recommended.

5.4.1.6 GND

The GND pin provides the ground reference for the VPWR, VPP, VPROT and VCC supplies. The GND pin is used as a return for both the

power supplies, as well as power a ground for some of the lower current output drivers. The higher current output drivers have their own

ground pins. All ground pins (INJGND1, INJGND2, RGND1 and RGND2) and the exposed pad must be directly connected to this pin and

to the negative battery terminal. There is no separate ground pin associated with the LAMPOUT driver. It shares a ground with ROUT2.

5.4.2 Power supplies functions

5.4.2.1 Power supply

The 33813 is designed to operate from VPWRMIN to VPWRMAX on the VPWR pin. The VPWR pin supplies power to all internal regulators

and analog and logic circuit blocks. All IC analog current and internal logic current is provided from the VPWR pin. An overvoltage

comparator monitors this pin. When an overvoltage condition is present, all outputs and voltage regulators are shut off for protection.

Table 22. Other OFF/ON register field descriptions

Field Description

0-RESET Internal Only

Reset Internal Only Command

0-Do not perform an internal reset

1-Perform an internal reset

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5.4.2.2 VPP pre-regulator

The VPP pre-regulator supplies the input voltage to the VCC and VPROT regulators. The VPP regulator is a low drop-out (LDO) regulator.

It provides a regulated output voltage when the input is greater than its specified voltage level and it follows the input voltage when it is

below its specified voltage level.

The VPP regulator uses an external PNP transistor as a pass element. This allows the user to choose the PNP’s size and package

considerations to meet the system requirements. The amount of power the external PNP transistor has to dissipate depends on the

maximum voltage the system can be expected to run at and the maximum expected current drawn from the VCC and VPROT regulators.

The VPPSENS pin is used to feedback the value of the VPP voltage for regulation. Since the VPP regulator is not intended to supply off-

the-board loads, there is no short-to-ground or short-to-battery protection on the output of the external PNP.

5.4.2.3 VCC regulator

The VCC regulator obtains its input voltage from the VPP pre-regulator. The VCC regulator output is used for supplying 5.0 V to the MCU

and for setting communication threshold levels via the internal SPI SO driver. The VCC regulator contains an internal pass transistor

protecting against overcurrent.

A Power On Reset (POR) circuit monitors the VCC output voltage level. When the VCC voltage exceeds the VCC(POR) threshold, the

RESETB line is held low for an additional delay time t(POR) before being brought to a logic one level. An undervoltage (UV) circuit monitors

the output of the VCC regulator. When the voltage goes below the VCC(UV) threshold for more than the VCC filter time, t(VCC-UV), the

RESETB line is asserted to a logic zero state and remains there until the POR condition is met.

5.4.2.4 VPROT regulator

The protected output VPROT is a tracking regulator using the VCC output as a reference. Because the VPROT regulator is expected to supply

5.0 V to external sensors and other off-board peripherals in the vehicle, it is well protected against shorts-to battery, shorts-to-ground,

overcurrent and overtemperature.The VPROT supply is enabled at power-on, but can be disabled via the SPI Control Register.

5.4.2.5 Power up sequence

Table 23. Power up sequence

tActions

t0 Battery connected to VPWR Pin

t1 User turns on ignition switch, KeySw => High

• Internal regulators, band gap reference and bias current generator are enabled

t2 = t1+ ~5.0 μs

Internal PORb de-asserted after internal 2.5 V regulator to the logic core stabilizes

• Logic and oscillator are enabled

• Start KeySw filter time

t3 = t2+ ~12.7 ms

KeySW filter time period expires

• Enable VPP pre-regulator

• Soft start sets turn on ramp to ~ 400 μs

t4 = t3+ (< 400 μs)

VPPSENS exceeds 4.8 V, enables VCC & VPROT regulators

• Soft start sets turn on ramps to ~ 2.0 ms

• BatSw buffer receives power

• Output rises with VCC

t5 = t4+ (< 2.0 ms) VCC exceed POR Threshold ~4.6 V

• Start POR Timing ~128 μs

t6 = t5+ ~128 μsPOR Time period expires

• Release RESETB pin

32 NXP Semiconductors

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Figure 15. Power up sequence

5.4.3 Power supply SPI register

5.4.3.1 SPI control registers

Table 24. OFF/ON control register

Reg # Hex 76543210

1 1 Other OFF/ON Control

Pwren

OFF/ON

POST

Enable

OFF/ON

XVProt

OFF/ON XBatsw

OFF/ON

Tach

OFF/ON

RESET

internal

only

Reset (0) (0) (0) (1) (0) (0) (1) (0)

Table 25. Other OFF/ON register field descriptions

Field Description

4-VPROT OFF/ON

VPROT Regulator Enable

0-Disable

1-Enable (Default)

KEYSW

Internal V2P5

Internal Ibias

VppSens

Vcc

Vprot

ResetB

BatSW

t1 t2 t3 t4

t0 KeySw Filter Time ~12.7ms

~5µs

4.8V

t5 t6

4.6V

<400µs ~128µs<2ms

NXP Semiconductors 33

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5.4.3.2 SPI status registers

Table 26. Power supply and any system fault status register

Reg # Hex 76543210

13 DPower Supply and Any

System Faults

Any

System

Faults

Keysw Pwren Batsw SPI Error

VPROT

Short to

Battery

VPROT

Overtemp

VPROT

Short to

Ground

Reset (0) (1) (0) (0) (0) (0) (0) (0)

Table 27. Power supply and any system fault status register field description

Field Description

2-VPROT Short to Battery

VPROT Short to Battery Status:

0-No Fault reported

1-Fault reported

1-VPROT Overtemp OT

VPROT Overtemp:

0-No Fault reported

1-Fault reported

0-VPROT Short to Ground

VPROT Short To Ground:

0-No Fault reported

1-Fault reported

34 NXP Semiconductors

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5.5 Drivers blocks

5.5.1 Pin description

5.5.1.1 INJIN1 input

The INJIN1 pin is the parallel input controlling the Injector output, INJOUT1. The INJIN1 pin is a 5.0 V logic level input with a built-in pull-

down to ground that prevents accidental actuation of an injector if the connection to the pin is lost.

5.5.1.2 RIN1, RIN2 inputs

The RIN1and RIN2 pins are the parallel inputs controlling the relay outputs ROUT1 and ROUT2 respectively. The RIN1 and RIN2 pins are

5.0 V logic level inputs with built-in pull-downs to ground to prevent accidental actuation of a relay if the connection to the pin is lost.

5.5.1.3 INJOUT1 driver output

This is an output pin for the INJOUT1 low-side driver. This output can be used as an injector driver output. Injector output is forced off

during all RESET events.

5.5.1.4 ROUT1, ROUT2 driver outputs

These are output pins for ROUT1 and ROUT2 low-side drivers and have different current ratings and can be used to drive relays (like fuel

pump, main power relay, …) or other inductive loads.

5.5.1.5 LAMPOUT driver output

The Lamp driver output, LAMPOUT is a low-side driver capable of driving an incandescent lamp even under cold filament conditions and

can also be used to drive a LED if the open load feature is disabled.

5.5.1.6 Tachometer (TACHOUT)

The TACHOUT pin is a low-side driver which can used to drive a tachometer meter movement and can be programmed via the SPI to:

• Output the same signal as VRSOUT divided by a 1 to 32 programmable divider

• Output a PWM signal with a frequency and duty cycle programmable via the SPI

• Output one of eight fixed frequencies

5.5.2 Common functionality

The six open drain low-side drivers (LSDs) are designed to control various automotive loads, such as injectors, fuel pumps, solenoids,

lamps and relays, etc. Each driver includes off-state open load detection, on-state short-to-ground detection, short-circuit to battery

protection, overcurrent protection, overtemperature protection and diagnostic fault reporting via the SPI. The LSD outputs can be Pulse

Width Modulated (PWM’d) based on an internal and/or external frequency for use as variable speed motor drivers, LED/lamp dimming

drivers, or as a fuel pump driver.

All outputs except ROUT2 are disabled when the KEYSW input pin is brought low regardless of the state of the input pins. All outputs,

including ROUT2 are disabled when the RESETB pin is low.

5.5.2.1 LSD input logic control

The three LSDs (INJOUT1, ROUT1 and ROUT2) are controlled individually using a combination of the external pin input (respectively

INJIN1, RIN1 and RIN2) and/or a SPI On/Off Control bit. The two LSDs (LAMPOUT and TACHOUT) are controlled individually using a

SPI On/Off Control bit. The logic can be made to turn the outputs on or off by:

• a logical combination of the external pin ORed with the SPI Control On/Off Bit (Default State)

• a logical combination of the external pin ANDed with the SPI Control On/Off Bit

A separate OR/AND select bit is found in the SPI configuration registers to accomplish this selection.

NXP Semiconductors 35

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5.5.2.2 Pulse Width Modulation mode

Alongside just turning the outputs ON or OFF, the six LSD outputs can be Pulse Width Modulated (PWM’d) to control the outputs with a

variable 0 to 100% duty cycle at a selection of different frequencies. There are two built-in PWM frequencies (100 HZ and 1.0 kHz) and

the external input pin can also be used as either an external PWM frequency input (divided by 100) or a total PWM (frequency and duty

cycle) input.

Two bits (Bits 1, 0) in the SPI configuration register control which mode of input control is selected. The internal PWM duty cycles (D/C)

are controlled by the lower seven bits in the corresponding SPI control register with a 1% increment. The external PWM duty cycles (D/

C) are provided by the MCU on the input pin of the corresponding output driver.

5.5.2.3 Overcurrent (OC) protection

Output protection uses two strategies—overcurrent (OC) protection and/or overtemperature (OT) protection—to detect a fault. When a

fault occurs, the output protection feature automatically controls the output to prevent damage to the output device.

The overcurrent protection scheme senses an overcurrent condition by monitoring the voltage on the individual output device drain.

5.5.2.3.1 Inrush delay

The Inrush Delay bit in the SPI Configuration Register for each output, when set to a one(1), prevents the overcurrent fault bit from being

set and the overcurrent protection from shutting off the output for tINRUSH time (Typ.10 ms) rather than tSC1.(Typ. 60 µs).

This means that during this fixed time period, the device enters into current limitation, and the output is switched off when the fixed period

expires.

Note that for the Lampout Driver, the default state is Inrush Delay equal to 1 (tINRUSH).

5.5.2.3.2 Retry feature

When the Retry feature is enabled (Retry Bit for each output) during an overcurrent condition at the end of the Inrush period, the output

device turns off and waits until a delay time (tRef) has passed. After this off time, the output tries to turn on again. If the short is still present,

the process starts again. This on/off cycling continues until the output is shut off by command or the overtemperature (OT) on the output

device is reached. Note that the Inrush delay resets to its default state for this on/off cycling. See Figure 16.

If the SPI configuration register retry enable bit is set to a zero (0), this on/off cycling does not occur and the output turns off if the

overcurrent threshold is reached. The output does not turn on again until the output is shut off and then on again by command.

Figure 16. Retry and Inrush feature

INJIN1 Off

No Fault

Fault Injected

Fault

12V

CASE RETRY OFF

2.5V (STB Th)

INJOUT1 Tsc1 Or Tinrush*

I_Injout1

~1.3A

Iout(Lim)_Inj1

CASE RETRY ON

2.5V (STB Th)

INJOUT1 Tsc1 Or Tinrush*

I_Injout1

~1.3A

Iout(Lim)_Inj1

*Depending SW setting

Tref Tsc1 Tref Tsc1 Tref

Cylcling till Overtemp

protection is reached

36 NXP Semiconductors

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5.5.2.4 Temperature limit (OT) protection

The second output protection scheme works by sensing the local temperature of the individual output device. During an overcurrent event,

the device enters the current limit and remains there until the output driver maximum temperature limit is exceeded (OT). At this point, the

device shuts down automatically regardless of the input state. The output tries to turn on again only when the junction temperature falls

below the maximum temperature minus the TLIM hysteresis temperature value and the input state is commanding the output to be on. The

TLIM hysteresis value is specified in the static parameter table.

The temperature limit (TLIM) protection is independent of the overcurrent protection and is not controlled by the SPI. TLIM is always enabled

and is always a retry operation. Outputs may be used in parallel to drive higher current loads as long as the turn-off energy of the load

does not exceed the energy rating of a single output driver.

5.5.2.5 Open load (OL) and short-to-battery (OC) strategy

The injector, lamps, relays, and tachometer low-side outputs are capable of detecting an open load in the off state and short-to-battery

condition in the on state. All faults are reported through the SPI status register communication (OL bit for open load fault and OC bit for

short-to-battery fault).

For open load detection, a current source is placed between the MOSFET drain pin and the ground of the IC. An open load fault is reported

when the drain voltage is less than the listed threshold. A shorted load fault is reported if the drain pin voltage is greater than the

programmed short threshold voltage when the device is in the on state. The open load and short-to-battery fault threshold voltage is fixed

and cannot be modified via the SPI.

The open load feature could be disabled (to allow the outputs to be used as LED drivers) by clearing the appropriate bit in the in the LSD

configuration register.

5.5.2.6 Short-to-ground (SG) strategy

The injectors, lamps and relays (but not the Tachometer) low-side driver outputs are capable of detecting a short-to-ground by measuring

the current flow in the output device and comparing it to a known current value. If a short-to-ground is detected, it is annunciated via a bit

in the appropriate SPI status register.

5.5.2.7 Output driver diagnostics

Overcurrent (OC), temperature limit (OT) exceeded, short-to-ground (SG) and open load (OL) conditions are reported through the status

register for each driver (no SG for the tachometer). A bit in the SPI status register indicates when any of the LSDs or pre-drivers are

reporting a fault and when a particular output has any of the four possible fault conditions present. The MCU polls for fault conditions by

looking for a single bit in one register to detect the presence of any fault in the circuit.

5.5.3 Special features

5.5.3.1 LAMP OUT

The Inrush delay bit is set to 1 by default to allow the driver to handle the inrush current of a cold lamp filament. It waits an additional time

before annunciating an overcurrent condition. A pull-down current sink is provided to allow the IC to detect when the bulb is burned out

(open filament). The LAMP is switched on and off via the SPI ON/OFF Control register word. It also has the ability to be PWM’d for

advanced diagnostic (dimming) purposes via the SPI Lamp Control register. The output can also drive an LED if the open load detect

current sink is commanded off via the SPI to prevent ‘ghosting’.

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5.5.3.2 TACHOUT

The TACHOUT pin is a low-side driver used to drive a tachometer meter movement. TACHOUT can be programmed via the SPI to:

• Output the same signal as VRSOUT divided by a 1 to 32 programmable divider

• Output a PWM signal with a frequency and duty cycle programmable via the SPI

• Output one of eight fixed frequencies, as indicated in Ta bl e 30

If a tachometer is not required, the TACHOUT output can also be used as a low current, SPI controlled, low-side driver to drive an LED

or other low current load. The SPI Configuration register for the tachometer is used to determine for which mode this output is used. The

TACHOUT output handles overcurrent (OC) differently than the other low-side drivers. When an overcurrent limit is reached, the

TACHOUT output does not enter a current limiting state, but rather shuts the output off to protect the output device. The retry option works

similarly to the other low-side drivers. In the LSD mode, bit 4 of the SPI Configuration register controls the turn on or turn off of the open

load detect current sink.

5.5.3.3 Using ROUT2 as a power relay

The ROUT2 (Relay 2 Output) can be used to drive a power relay. The RIN2 input or the RIN2 bit in the SPI Control register can be used

to turn the ROUT2 output on or off as desired. The BATSW output can be connected to the RIN2 input to control the power relay, or the

MCU can chose to control the RIN2 bit in the SPI Control register to actuate the power relay. The ROUT2 output is unique in that it can

be kept turned on even after KEYSW is turned off (as long as the PWREN bit is still set to a one), by setting the shutdown disable (SDD)

bit in the ROUT2 Configuration register.

5.5.4 SPI drivers registers

5.5.4.1 SPI configuration registers

Table 28. Injector 1/2, Relay1/2,Lampout configuration registers

Reg # Hex 7 6 5 4 3 2 1 0

0 0 Injector 1 Driver

Retry

Enable X X OL Current

Sink Enable

In-Rush

Delay OR/AND PWM

Freq. 1

PWM

Freq. 0

Reset (0) (0) (0) (1) (0) (0) (0) (0)

1 1 Not Used X X X X X X X X

Reset (0) (0) (0) (0) (0) (0) (0) (0)

2 2 Relay 1 Driver

Retry

Enable X X OL Current

Sink Enable

In-Rush

Delay OR/AND PWM

Freq. 1

PWM

Freq. 0

Reset (0) (0) (0) (1) (0) (0) (0) (0)

3 3 Relay 2 Driver

Retry

Enable

Shutdown

DisableSD

XOL Current

Sink Enable

In-Rush

Delay OR/AND PWM

Freq. 1

PWM

Freq. 0

Reset (0) (0) (0) (1) (0) (0) (0) (0)

5 5 Lamp Driver

Retry

Enable X X OL Current

Sink Enable

In-Rush

Delay XPWM

Freq. 1

PWM

Freq. 0

Reset (0) (0) (0) (1) (1) (0) (0) (0)

Table 29. Injector 1 and Relay 1/2 Lampout configuration. Field description

Field Description

7-Retry Enable

Retry Enable

0-Disable

1-Enable

6-Shutdown Disable SDD

Shutdown Disable mode selection (22) allowing to keep

ROUT2 ON even after KEYSW =0

0- SDD mode disable

1- SDD mode enable

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4-OL Current Sink Enable

Open Load Current Sink Enable

0- Disable (OL Flag in status register will be forced to 0)

1- Enable (Default)

3-In-Rush Delay

In-rush Delay Time disabling overcurrent protection

0-tSC1 (Default)

1- tINRUSH (23)

2-OR/AND

OR/AND logical action to control LS Output (24)

0- OR between Input pin and Control bit (Default)

1-AND between Input pin and Control bit

1/0- PWM Freq1/0

PWM Frequency and Duty Cycle mode (25)

00-PWM Freq.: None or Ext.Pin - D/C: None or ext.Pin

01-PWM Freq.:100 HZ-D/C: Internal

10-PWM Freq.: 1 KHZ-D/C: Internal

11-PWM Freq.:On ext. pin /100 -D/C: Internal

Notes

22. Valid only for Relay 2 Driver.

23. Default For Lampout Driver

24. NA for Lampout Driver

25. No ext Pin for Lampout Driver

Table 30. Tachometer driver configuration registers

Reg # Hex 7 6 5 4 3 2 1 0

4 4 Tachometer Driver

Retry

Enable

Vrsout/

LSD

Vrsout/

Osc. mode

N16/OL

Current Sink

Enable

N8/In-Rush

Delay N4/Osc 2

N2/Osc 1/

PWM

Freq. 1

N1/Osc 0/

PWM

Freq. 0

Reset (0) (0) (0) (0) (0) (0) (0) (1)

Table 31. Tachometer driver configuration registers. Field description

Field Description

7-Retry Enable

Retry Enable

0-Disable

1-Enable

6-VRSOUT/LSD

5-VRSOUT/

Osc.mode

VRSOUT/LSD/OSC mode selection

00 (Default) - VRSOUT Output divided by N

01- Oscillator Output

10- Low-side Driver mode

11- Same as 10 (LSD)

4-N16/ OL

Current Sink

Enable

N16 or Open Load Current Sink Enable

-When used as VRSOUT, see Table 32. .

-When used as LSD:

0- Disable (Open Load Flag in status register will be forced

to 0)

1- Enable (Default)

3-N8/In-Rush

Delay

N8 / In-Rush Delay Time disabling overcurrent protection

-When used as VRSOUT, see Table 32.

-When used as LSD:

0-tSC1

1- tINRUSH

2-1-0:N(4,2,1),

Osc (2,1,0) PWM

freq (x,1,0)

N(4,2,1) or Output Frequency or PWM Output

-When used as VRSOUT, see Table 32.

-When used as Oscillator Output, see Table 33

-When used as PWM output, see Table 34

Table 29. Injector 1 and Relay 1/2 Lampout configuration. Field description

Field Description

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5.5.4.2 SPI control registers

Table 32. Tachout mode configuration when used as VSROUT

SPI Configuration Register Bits 4, 3, 2, 1, 0

(N16, N8, N4, N2, N1)

TACHOUT mode

VRSOUT divided by ‘N’ where ‘N’ is defined by

bits 0 thru 4 of SPI

00000 N=32

00001 (default) N=1

00010 N=2

...... ........

11111 N=31

Table 33. Fixed oscillator frequencies configuration when used as an oscillator output

SPI Configuration Register Bits 2,1,0

(Osc2, Osc1, Osc0) Oscillator Frequencies mode

000 10 Hz

001 (default) 100 Hz

010 1.0 kHz

011 5.0 kHz

100 10 kHz

101 20 kHz

110 40 kHz

111 100 kHz (not recommended for use)

Table 34. PWM frequency configuration when used as LSD

SPI Configuration Register Bits 1, 0

PWM Frequency PWM mode

x00 None

x01 (default) PWM Freq: 100 Hz - D/C: Internal

x10 PWM Freq: 1.0 kHZ - D/C: Internal

x11 None

Table 35. Main OFF/ON control register

Reg # Hex 76543210

0 0 Main OFF/ON Control

INJ1 X REL1 REL2 LAMP IGN1 X O2H

Reset (0) (0) (0) (0) (0) (0) (0) (0)

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Table 36. Main OFF/ON control register field description

Field Description

7-INJ1

INJOUT1 Bit Control

0-OFF

1-ON

5-REL1

ROUT1 Bit Control

0-OFF

1-ON

4-REL2

ROUT2 Bit Control

0-OFF

1-ON

1-LAMP

LAMP Bit Control

0-OFF

1-ON

Table 37. Other OFF/ON control register

Reg # Hex 76543210

1 1 Other OFF/ON Control

Pwren

OFF/ON

POST

Enable

OFF/ON

XVProt

ON/OFF XBatsw

OFF/ON

Tach

OFF/ON

RESET

internal

only

Reset (0) (0) (0) (1) (0) (0) (1) (0)

Table 38. Other OFF/ON control register field description

Field Description

1-Tach OFF/ON

TACHOUT Bit Control

0-OFF

1-ON

Table 39. PWM duty cycle setting control register

Reg # Hex 76543210

2 2 Injector 1 Driver XPWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0

Reset (0) (0) (0) (0) (0) (0) (0) (0)

3 3 Not Used XXXXXXXX

Reset (0) (0) (0) (0) (0) (0) (0) (0)

4 4 Relay 1 Driver XPWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0

Reset (0) (0) (0) (0) (0) (0) (0) (0)

5 5 Relay 2 Driver XPWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0

Reset (0) (0) (0) (0) (0) (0) (0) (0)

6 6 Tachometer Driver XPWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0

Reset (0) (0) (0) (0) (0) (0) (0) (0)

7 7 Lamp Driver XPWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0

Reset (0) (0) (0) (0) (0) (0) (0) (0)

Table 40. PWM duty cycle setting control register field description

Field Description

6-0 -PWMx

PWM Duty Cycle Setting with 1% increment

0000000 to 1100100 (Dec. 100) represent 0% to 100%

1100100(Dec. 100) to 1111111 (Dec.127) all map to 100%.

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5.5.4.3 SPI status registers

Table 41. LS driver status register

Reg # Hex 76543210

0 0 Injector 1 Driver Faults Faults XXXOpen Load

Over -

current OC

Overtemp

Short Gnd

Reset (0) (0) (0) (0) (0) (0) (0) (0)

1 1 Not Used X XXXXXXX

Reset (0) (0) (0) (0) (0) (0) (0) (0)

2 2 Relay 1 Driver Faults Faults XXXOpen Load

Overcurren

t OC

Overtemp

Short Gnd

Reset (0) (0) (0) (0) (0) (0) (0) (0)

3 3 Relay 2 Driver Faults Faults XXXOpen Load

Overcurren

t OC

Overtemp

Short Gnd

Reset (0) (0) (0) (0) (0) (0) (0) (0)

4 4 Tachometer Driver Faults Faults XXXOpen Load

Overcurren

t OC

Overtemp

OT X

Reset (0) (0) (0) (0) (0) (0) (0) (0)

5 5 Lamp Driver Faults Faults XXXOpen Load

Overcurren

t OC

Overtemp

Short Gnd

Reset (0) (0) (0) (0) (0) (0) (0) (0)

Table 42. LS driver status register description field

Field Description

7-Faults

Global Driver Fault bit (by driver)

Logical OR of bit 0-3

0-No Fault

1-Fault detected

3-Open Load OL

Open Load Fault Flag

0-No Fault (Forced to 0 if OL feature disabled)

1-Fault detected

2-Overcurrent OC

Overcurrent Fault Flag

0-No Fault

1-Fault detected

1-Over Temp OT

Over Temp Limit Fault Flag

0-No Fault

1-Fault detected

0-Short GND SG

Over Temp Limit Fault Flag (26)

0-No Fault

1-Fault detected

Notes

26. Not present on Tachometer Driver

Table 43. System On/Off indicators status register

Reg # Hex 76543210

14 ESystem On/Off

Indicators

INJ1

Off/On XREL1

Off/On

REL2

Off/On

LAMP

Off/On

IGN1

Off/On XO2H

Off/On

Reset (0) (0) (0) (0) (0) (0) (0) (0)

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5.6 Pre-driver

5.6.1 Pin description

5.6.1.1 IGNIN1 input

The IGNIN1 pin is the parallel input controlling the IGNOUT1 pre-driver output. The IGNIN1 pin is a 5.0 V logic level inputs with built-in

pull-downs to ground that prevents accidental actuation of a pre-driver output if the connection to the pin is lost.

5.6.1.2 O2HIN input

The O2HIN pin is the parallel input controlling the O2HOUT pre-driver output. The O2HIN pin is a 5.0 V logic level input with a built-in pull-

down to ground that prevents accidental actuation of the pre-driver output if the connection to the pin is lost.

5.6.1.3 IGNOUT1 Pre-driver output with feedback IGNFB1 and current sense inputs

IGNSENSP and IGNSENSN

The IGNOUT1 output is a pre-driver output driving either an ignition (IGBT) pre-driver or a general purpose gate driver (GPGD). INGOUT1

is configured by default as an IGBT driver to control the ignition coil current to produce a spark.

The IGNOUT1 output and its associated feedback pin IGNFB1 provides one short-to-battery and one current sense resistor provides

overcurrent protection for the external driver transistor. When used as an IGBT driver, a 10:1 voltage divider (9R:1R) must be used on the

feedback pins to prevent the 400 V flyback from damaging the IC. More accurate current control can be provided by placing a current

sense resistor between the IGNSENSP and IGNSENSN pins.

5.6.1.4 O2HOUT Pre-driver output with drain feedback input O2HFB and current sense

inputs O2HSENSP and O2HSENSN

The O2HOUT output is a pre-driver output driving either an ignition (IGBT) pre-driver or a general purpose gate driver (GPGD). O2HOUT

is configured by default as GPDC to control the gate of a MOSFET to drive a heater on an O2 (Lamda) sensor. The pre-driver is capable

of driving most power MOSFETs. The O2HOUT output and associated drain feedback pin O2HFB provide short-to-battery, overcurrent

protection for the external driver MOSFET. When used as an IGBT driver, a 10:1 voltage divider (9R:1R) must be used on the feedback

pins to prevent the 400 V flyback from damaging the IC. More accurate current control can be provided by placing a current sense resistor

between the O2HSENSP and O2HSENSN pins.

Table 44. System On/Off indicators status register field description

Field Description

7-3 Driver Off/On

Driver On/Off Status

0- Off

1- On

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5.6.2 Functions description

There are two identical pre-drivers in the 33813. Each pre-driver can be configured as either an ignition (IGBT) pre-driver or a general

purpose gate driver (GPGD). By default, one pre-driver is configured as a GPGD (O2HOUT) and one pre-driver is configured as an ignition

(IGNOUT1) pre-driver. A bit in each pre-driver’s SPI Configuration register defines whether the pre-driver behaves as an ignition or a

GPGD pre-driver.

Each pre-driver includes off-state open load detection and can be Pulse Width Modulated (PWM’d) based on an internal and/or external

frequency for use as variable speed motor drivers, LED/lamp dimming drivers, or as a fuel pump driver.

5.6.2.1 Pre-driver input logic control

The two Pre-drivers (IGNOUT1 and O2HOUT) are controlled individually using a combination of the external pin input (respectively

IGNIN1 and O2HIN) and/or a SPI On/Off Control bit.

The logic can be made to turn the outputs on or off by:

• a logical combination of the external pin ORed with the SPI Control On/Off Bit (Default State)

• a logical combination of the external pin ANDed with the SPI Control On/Off Bit

A separate OR/AND select bit is found in the SPI configuration registers to accomplish this selection.

5.6.2.2 Pulse Width Modulation mode

See 5.5.2.2. Pulse Width Modulation mode, page 35.

5.6.2.3 Open load (OL) and short-to-battery (OC) strategy

The Pre-drivers are capable of detecting an open load in the off state and short-to-battery condition in the on state. All faults are reported

through the SPI status register communication (OL bit for open load fault and OC bit for short-to-battery fault).

For open load detection, a current source is placed between the MOSFET drain pin and ground of the IC. An open load fault is reported

when the drain voltage is less than the specified threshold. A shorted load fault is reported when the drain pin voltage is greater than the

programmed short threshold voltage when the device is in the on state. The open load and short-to-battery fault threshold voltage is fixed

and cannot be modified via the SPI.

The Open Load feature could be disabled (current source disable) by clearing the appropriate bit in the in the pre-driver configuration

5.6.2.4 Current sense protection (OC) strategy

Two current measurement circuits, ISGNSENSP/N and O2HSENSP/N, are available for more accurate current control and better

protection of pre-driver. A current sense resistor should be place between the IGNSENSP and IGNSENSN pins for IGNOUT1 and

between O2HSENSEP and O2HSENSEN for O2HOUT.

The input controls determine the value of the current sense threshold voltage across the current sense resistor (VSENS_Th).

5.6.2.5 Inrush delay

See 5.5.2.3.1. Inrush delay, page 35.

5.6.2.6 Output pre-driver diagnostics.

Overcurrent (OC) and open load (OL) conditions are reported through the status register for each pre-driver. There is also a bit in the SPI

status register to indicate when any of the pre-drivers report a fault and when a particular output has any of the four possible fault

conditions present. The MCU polls for fault conditions by looking for a single bit in one register to detect the presence of any fault in the

circuit.

44 NXP Semiconductors

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5.6.3 SPI drivers registers

5.6.3.1 SPI configuration registers

5.6.3.2 SPI control registers

Table 45. Pre-driver configuration registers

Reg # Hex 76543210

7 7 O2 Heater Pre-driver

GPGD/IGN

Select

Retry

Enable X

Current

Sink

XOR/AND PWM

Freq. 1

PWM

Freq. 0

Reset (0) (0) (0) (1) (0) (0) (0) (0)

8 8 Ignition 1 Pre-driver

GPGD/IGN

Select

Retry

Enable XOL Current

Sink XOR/AND PWM

Freq. 1

PWM

Freq. 0

Reset (1) (0) (0) (0) (0) (0) (0) (0)

Table 46. Pre-driver configuration registers field description

Field Description

7-GPGD/IGN

GPGD/IGN mode selection

0- General Purpose Gate Driver (Default for O2HOUT)

1-IGBT Driver (Default for IGNOUT1)

6-Retry Enable

Retry Enable

0-Disable

1-Enable

4-OL Current Sink

Open Load Current Sink Enable

0- Disable (Open Load Flag in status register will be forced to 0)

1- Enable (Default for O2Heater Pre-driver)

2-OR/AND

OR/AND logical action to control Output

0- OR between Input pin and Control bit (Default)

1-AND between Input pin and Control bit

1/0 -PWM Freq1/0.

PWM Frequency and Duty Cycle mode

00-PWM Freq.: None or Ext.Pin - D/C: None or ext.Pin

01-PWM Freq.:100 HZ-D/C: Internal

10-PWM Freq.: 1 kHZ-D/C: Internal

01-PWM Freq.:On ext. pin /100 -D/C: Internal

Table 47. Main OFF/ON control register

Reg # Hex 76543210

0 0 Main OFF/ON Control INJ1 XREL1 REL2 LAMP IGN1 XO2H

Reset (0) (0) (0) (0) (0) (0) (0) (0)

Table 48. Main OFF/ON control register field description

Field Description

2-IGN1

IGN1 Bit Control

0-OFF

1-ON

0-O2H

O2H Bit Control

0-OFF

1-ON

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5.6.3.3 SPI status registers

Table 49. PWM D/C configuration register

Reg # Hex 76543210

9 9 O2 Heater Pre-driver XPWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0

Reset (0) (0) (0) (0) (0) (0) (0) (0)

10 AIgnition 1 Pre-driver XPWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0

Reset (0) (0) (0) (0) (0) (0) (0) (0)

Table 50. PWM D/C configuration register field description

Field Description

6-0 -PWMx

PWM Duty Cycle Setting with 1% increment

0000000 to 1100100 (Dec. 100) represent 0% to 100%

1100100(Dec. 100) to 1111111 (Dec.127) all map to 100%.

Table 51. Pre-driver status registers

Reg # Hex 76543210

7 7 O2 Heater Pre-driver Faults Faults XXXOpen Load

Overcurrent

OC X X

Reset (0) (0) (0) (0) (0) (0) (0) (0)

8 8 Ignition 1 Pre-driver Faults Faults XXXOpen Load

Overcurrent

OC X X

Reset (0) (0) (0) (0) (0) (0) (0) (0)

Table 52. Pre-driver status registers field description

Field Description

7-Faults

Global Driver Fault bit (by driver) Logical OR of bit 3-2

0-No Fault

1-Fault detected

3-Open Load OL

Open Load Fault Flag

0-No Fault (Forced to 0 if OL feature disabled)

1-Fault detected

2-Overcurrent OC

Overcurrent Fault Flag (including Short To VBAT Fault)

0-No Fault

1-Fault detected

Table 53. System On/Off indicators status register

Reg # Hex 76543210

14 ESystem On/Off

Indicators

INJ1

Off/On XREL1

Off/On

REL2

Off/On

LAMP

Off/On

IGN1

Off/On XO2H

Off/On

Reset (0) (0) (0) (0) (0) (0) (0) (0)

Table 54. System On/Off indicators status register field description

Field Description

2-0 xxx Off/On

Pre-driver On/Off Status

0- Off

1- On

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5.7 VRS circuitry

5.7.1 PIN Description

5.7.1.1 VRSP and VRSN inputs

The VRSP and VRSN form a differential input for the Variable Reluctance Sensor attached to the crankshaft toothed wheel. It is important

to provide an external 15 kΩ current limiting resistors to prevent damage to the VRSP and VRSN inputs (See Figure 17).The VRS can be

connected to the 33813 in either a differential or single-ended fashion.The use of a differential filtering capacitor and grounded capacitors

of at least 100 nF are also advisable. In some applications, placing a damping resistor of approximately 5.0 kΩ directly across the pickup

coil is also useful to minimize high frequency ringing.

5.7.1.2 VRSOUT output

The VRSOUT Pin is the output of the VRS circuit, which is a 5.0 Volt logic level signal provided to the MCU.

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5.7.2 Functions description

The 33813 contains a VRS input conditioning circuit employing a differential input. VRSP and VRSN are the positive and negative inputs

from the VRS (See Figure 17). An internal zener diode clamps to ground and VCC limits the input voltage to within the safe operating range

of the circuit.

The VRS circuit conditions and digitizes the input from the crankshaft mounted toothed wheel to provide an angle clock and RPM data to

the MCU. This circuit provides a comparator with multiple thresholds programmed via the SPI. This allows the VRS circuit to handle

different sensors and a dynamic range of VRS output at engine speeds ranging from cranking to running. The output of this circuit is

provided on the VRSOUT pin to the MCU. The comparator threshold values can also be controlled automatically based on the input signal

amplitude.

The output of the comparator contains a programmable one shot, noise blanking circuit. The time value of this blanking pulse can be

selected via the SPI as a percentage of the last input high (or low) pulse.The VRSOUT output can also be divided and sent to the

TACHOUT pin to drive a tachometer.

Two different SPI registers are provided to control the VRS circuit values in the manual mode. The SPI VRS configuration register is used

to set the ‘engine running’ values for the threshold and blanking filter, and the SPI VRS control register is used to provide the ‘engine

cranking’ threshold and blanking filter values. Once the engine is running, the MCU clears the SPI VRS control register (engine cranking)

and the 33813 uses the values found in the SPI VRS configuration register (engine running).

Figure 17. VRS schematic

5.7.2.1 ‘Engine Running’ and ‘Engine Cranking’ parameters

Two different SPI registers are provided to define two different sets of parameters (Input Threshold and Blanking Time) for ‘engine running’

and ‘engine cranking’ conditions, in the manual mode. The SPI VRS Engine Running Parameters register is used to set the ‘engine

running’ values for the threshold and blanking filter. The SPI VRS Engine Cranking Parameters register is used to set the ‘engine cranking’

values for the threshold and blanking filter.

When the contents of the SPI VRS Engine Cranking Parameters register contains all zeros, the value for parameters is taken from the

value in the SPI VRS Engine Running Parameters register.

When the contents of the SPI VRS Engine Cranking Parameters register is non-zero, the value for parameters is taken from this register.

So from system point of view, once the engine is running, the MCU should clear the SPI VRS Engine Cranking Parameters register and

the 33813 uses the values found in the SPI VRS Engine Running Parameters.

5.7.2.1.1 Input comparator threshold values

The threshold voltage for the input comparator is produced by a 4-bit D/A converter. The SPI VRS Engine Cranking Parameters register

or SPI VRS Engine Running Parameters register controls the output value of the D/A.The values output by this D/A, using one or the other

Variable

Threshold

Comparator

Zero

Threshold

Comparator

Threshold

DAC

(4 Bits)

VCC

SPI VRS

Threshold

value

DEGLITCH

FILTER

1% of previous

output pulse up

time or Zero

DEGLITCH

FILTER

1% of previous

output pulse up

time or Zero

SET

CLR

External

Circuitry

VCC

15K

1 nF

VRSN

VRSP

BLANKING FILTER

OUTPUT PULSE UP-

TIME COUNTER

BLANKING

COUNTER (N/32)

(4 Bits)

VRSOUT

SPI VRS

Blanking

value

4 MHz

48 NXP Semiconductors

33813

5.7.2.1.2 Blanking time definitions

The values for the one shot blanking as a percentage of the last high output pulse period is shown in Table 56.

Table 55. Input comparator threshold value table

SPI VRS Manual Parameter

Configuration Registers

Bits 7, 6, 5, 4

Min. Threshold

Value

Threshold Values

(Nominal)

Max. Threshold

Value Comment

0000 —10 mv 28 mv Tolerance not specified, for information only.

Monotonicity not guaranteed.

0001 —14 mv 36 mv

0010 3.0 mv 20 mv 38 mv

Tolerance not specified, for information only. Only

specified for monotonicity.

0011 5.0 mv 28 mv 50 mv

0100 21 mv 40 mv 55 mv

0101 (default) 25 mv 56 mv 80 mv

0110 56 mv 80 mv 92 mv

0111 -20% 110 mv +20%

Tolerance and monotonicity specified.

1000 -20% 150 mv +20%

1001 -20% 215 mv +20%

1010 -20% 300 mv +20%

1011 -20% 425 mv +20%

1100 -20% 600 mv +20%

1101 -20% 850 mv +20%

1110 -20% 1.21 V +20%

1111 -20% 1.715 V +20%

Table 56. SPI VRS manual configuration register

SPI VRS Configuration/Control

Blanking Time in% (of last

pulse high period)

0000 (default) 0.0

0001 3.12

0010 6.25

0011 9.37

0100 12.5

0101 15.62

0110 18.75

0111 21.87

1000 25

1001 28.1

1010 31.3

1011 34.4

1100 37.5

1101 40.6

1110 43.8

1111 46.9

NXP Semiconductors 49

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5.7.2.2 Manual and Automatic modes

The SPI VRS miscellaneous configuration register has a bit to enable the automatic selection of the comparator threshold (bit 7). At this

time, the operation of automatic mode remains.

Under cranking conditions in Manual mode, the selected threshold value is fixed (VT Selected) by the SPI VRS Engine Cranking

Parameters register. To avoid invalid detection due to noise close to the selected threshold, Automatic mode allows the VRS system to

be less sensitive to noise in the cranking mode.

As soon as the VRS Input signal crosses zero, the VRS system selects the highest Input Comparator Threshold (VT Max 1.715 V Typ.).

A decay circuitry ensures the VRS system decays from VT Max to VT Selected with the correct timing. The setting of the decay timing is

done through the SPI VRS Automatic Parameters Configuration Register.

Figure 18. Automatic mode illustration (VT signal in pink is internal IC signal not observable in application)

Mantissa and Exponent parameters defined in the VRS Automatic mode parameters register set the decay time of the system.

The Mathematical formula is:

E = log2[(Vpeak x Tau)/18.1] - 4 truncated

M = {[(Vpeak x Tau)/18.1]/2E} - 16 rounded to nearest integer

So Tau (timing between zero crossing and VPEAK) and the VPEAK value are required to determine M and E parameters. Tau and VPEAK

could be calculated, based on system specification (number of teeth, minimum RPM,…). However, NXP recommends measuring physical

parameters on the real application to define the best setting. A dedicated application note is available to explain the mathematical principle

and measurement instructions.

50 NXP Semiconductors

33813

5.7.2.3 Disable VRS bit

The disable VRS bit in the SPI VRS miscellaneous configuration register is used to disable the VRS input circuitry when there is no need

for a VRS input conditioning circuit. This would be the case, for example, if the crankshaft wheel sensor was a hall effect device whose

output could be directly input to the MCU. The default for this bit is zero (0) indicating the VRS input conditioning circuitry is active.

5.7.2.4 High/Low reference bit

The High/Low reference bit in the SPI VRS miscellaneous configuration register is used to change the use of the input high pulse timing

to input low pulse timing, in cases where an elongated tooth wheel is being used rather than the missing tooth wheel. The default for this

bit is zero (0), indicating the use of a crankshaft wheel with a missing tooth (or teeth).

5.7.2.5 VRS deglitching filters

The VRS input circuit has additional filters on the rising and falling edges of the input waveforms to reduce the effect of short transitions

occurring during noise sensitive times. The deglitching filters are approximately 1% of the last positive pulse period. The deglitch filters

are enabled by setting the deglitch bit (bit 3) in the SPI VRS miscellaneous parameters configuration register. This bit is, by default, zero

(0), meaning the deglitch filters are disabled.

5.7.2.6 GND VRSN bit

To use the VRS inputs in a single-ended configuration, the “GND VRSN” bit in the SPI Configuration register must be set to indicate to the

33813 that this mode is being used. The VRS is then connected between the VRSP input and ground. The default for this bit is zero (0),

indicating the differential mode is selected. Note that, in a single-ended configuration, the 2.5 V reference should be disconnected from

the associated bit when using a Variable Reluctance Sensor.

Note that a hall effect sensor can be used instead of a VRS. To do so, the bits GND VRSN and disable 2.5 V ref must be 0 and the VRSN

pin must not be connected. In this case, the voltage on VRSN is 2.5 V and the 0 crossing can be done even if low state output of the hall

effect is 0 V or little higher.

5.7.2.7 Inverting inputs

The Inv. Inputs Bit in the SPI VRS Miscellaneous Parameter Register is used to make a logical inversion of all functions. This is swapping

the VRSP and VRSN signals.

5.7.2.8 2.5 Volt reference disconnect bit

The disconnect 2.5 V reference bit in the SPI VRS configuration register is used to disconnect the internal 2.5 V reference signal from the

VRSN and VRSP inputs so an external reference voltage can be employed. The default state of this bit is zero (0), indicating the internal

2.5 Volt reference voltage is connected to the VRSN and VRSP inputs.

5.7.2.9 VRS peak detector

The VRS peak detector determines the magnitude of the positive peak of the VRS input signal and digitizes it. The value of the VRS peak

voltage is reported in the VRS SPI status register bits 7, 6, 5 and 4. The MCU reads the input pulse peak voltage value after the zero

crossing time and uses this information to set the threshold and blanking parameters for subsequent input pulses. Status bits reflect the

last detected peak and only read 0000 after a POR or SPI reset command.

Table 57. Peak detector output in SPI VRS status register

SPI VRS Status Register Bits 7,6,5,4 Peak Values (nominal)

0000 10 mV

0001 14 mV

0010 20 mV

0011 28 mV

0100 40 mV

0101 56 mV

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5.7.2.10 Clamp active status bits

There are two clamp active status bits in the SPI VRS status register. One is for the low pulse clamp and the other is for the high pulse

clamp. When either of these bits are a one (1), it indicates the peak voltage for the part of the input waveform which has exceeded the

clamp voltage and is clamped to the high or low voltage limit. These status bits can be used to indicate the engine has attained the speed

necessary to switch from ‘cranking’ values for the threshold and blanking (in the SPI VRS control register) to the ‘running’ values (in the

SPI VRS configuration register).

5.7.3 SPI drivers registers

5.7.3.1 SPI configuration registers

0110 80 mV

0111 110 mV

1000 150 mV

1001 215 mV

1010 300 mV

1011 425 mV

1100 600 mV

1101 850 mV

1110 1.210 V

1111 1.715 V

Table 58. VRS configuration registers

Reg # Hex 7 6 5 4 3 2 1 0

11 BVRS Engine Running

Parameters

Threshold

Filter Time

Reset (0) (1) (0) (1) (0) (0) (1) (1)

12 CVRS Automatic Parameters mantiss 8 mantiss 4 mantiss 2 mantiss 1 exponent 8 exponent 4 exponent 2 exponent

Reset (0) (0) (1) (0) (0) (0) (0) (1)

13 DVRS Miscellaneous

Parameters

Man./Auto Disable

VRS XHigh/ Low

Ref De-glitch Gnd VRSN Inv Inputs Disable

2.5 V CM

Reset (0) (0) (0) (0) (0) (0) (0)(0)

Table 59. VRS engine running parameters register field description

Field Description

7-4 Threshold x Input Comparator Threshold Value Selection, Table 55

3-0 Filter Time x Blanking Time Selection, Table 56

Table 60. VRS automatic parameters register field

Field Description

7-5 Mantissa x Mantissa parameter to set the decay timing in Automatic

mode

3-0 Exponent x Exponent parameter to set the decay timing in Automatic

mode

Table 57. Peak detector output in SPI VRS status register (continued)

52 NXP Semiconductors

33813

5.7.3.2 SPI control registers

5.7.3.3 SPI status registers

Table 61. VRS miscellaneous parameters register field

Field Description

7-MAN/Auto

Manual/Automatic mode selection

0-Manual mode (Default)

1-Automatic mode

6-Disable VRS

Disabling the VRS System

0- VRS Enable (Default)

1-VRS disable

4-High/Low Ref

High/Low reference

0-High Pulse Timing (Missing tooth Wheel)

1-Low Pulse Timing (Elongated Tooth Wheel)

3-De-glitch

Additional Deglitching Filter

0-De-glitch Disable

1-De-glitch enable

2-Gnd VRSN

Single Ended Configuration (VRSN = GND) or Differential

mode configuration

0-Differential mode configuration

1-Single ended configuration

1-Inv inputs

Logical Inversion of all functions

0-VRSN and VRSP not swapped

1-VRSN and VRSP swapped

0-Disable 2.5V

Disable 2.5 V reference

0-Internal 2.5 V Ref connected to VRSN and VSRP

1-Internal 2.5 V Ref disconnected from VRSN and VRSP

Table 62. VRS engine cranking parameters register

Reg # Hex 76543210

13 DVRS Engine Cranking

Parameters

Threshold

Filter Time

Reset (0) (0) (0) (0) (0) (0) (0) (0)

Table 63. VRS engine cranking parameters register field description

Field Description

7-4 Threshold x Input Comparator Threshold Value Selection, Table 55

3-0 Filter Time x Blanking Time Selection, Table 56

Table 64. VRS status register

Reg # Hex 76543210

11 BVRS Conditioner and

ISO9141 Faults

Peak 8 Peak 4 Peak 2 Peak 1 X

Clamp-

active

VRSP

Clamp-

active

VRSN

ISO

Overtemp

Reset (0) (0) (0) (0) (0) (0) (0) (0)

NXP Semiconductors 53

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5.8 ISO9141 bus

Three pins are used to provide an ISO9141 K-line communication link for the MCU to support system diagnostics.

5.8.1 MTX output pin

MTX is the 5.0 V logic level serial input to the IC from the MCU.

5.8.2 MRX input pin

MRX is the 5.0 V logic level serial output line to the MCU.

5.8.3 ISO9141 pin

The ISO9141 pin is a bi-directional line with an internal 32 kΩ pull-up resistor to VPWR. This allows the customer to save an external pull-

up resistor.

5.8.4 Functions description

Three pins are used to provide an ISO9141 K-line communication link for the MCU to support system diagnostics. This system is

consistent with the ISO9141 specification for signaling to and from the MCU.

K-Line has its own overtemperature protection and fault bit reporting.

5.8.5 SPI drivers registers

There is only one bit in the SPI Status register to indicate an overtemperature fault from the ISO9141 functional block. There are no

Configuration or Control registers associated with this functional block.

Table 65. VRS status register description field

Field Description

7-4 Peak x Reflect the magnitude of the positive peak of the VRS input

according to Table 57

2-Clamp Active

VRSP

Positive Clamp Active status

0-Clamp Value not reached

1-Clamp Value reached

1-Clamp Active

VRSN

Negative Clamp Active status

0-Clamp Value not reached

1-Clamp Value reached

Table 66. ISO status register

Reg # Hex 76543210

11 BVRS Conditioner and

ISO9141 Faults

Peak 8 Peak 4 Peak 2 Peak 1 x

Clamp-

active

VRSP

Clamp-

active

VRSN

ISO

Overtemp

Reset (0) (0) (0) (0) (0) (0) (0) (0)

54 NXP Semiconductors

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5.9 Mode code and revision number

One status register is reserved for reporting the model code and revision of the C circuits. The model code for the 33813 is 001. The

revision code is the current version number for the circuit. This register is read-only.

5.10 SPI

5.10.1 PIN description

5.10.1.1 SCLK input

The serial clock (SCLK) pin clocks the internal SPI shift register of the 33813. The SI data is latched into the input shift register on the

rising edge of SCLK signal. The SO pin shifts status bits out on the falling edge of SCLK. The SO data is available for the MCU to read

on the rising edge of SCLK. With CSB in a logic high state, signals on the SCLK and SI pins are ignored and the SO pin is in a high-

impedance state.The SCLK signal consists of a 50% duty cycle with CMOS logic levels referenced to VCC. All SPI transfers consist of

exactly 16 SCLK pulses. If any more or less than 16 clock pulses are received within one frame of CSB going low and then high, a SPI

error is reported in the SPI Status Register. The SPI error bit also sets whenever an invalid SPI message is received, even though it may

contain 16 bits.

5.10.1.2 CSB input

The system MCU selects which slave is to receive SPI communication using separate chip select (CSB) pins. With the CSB in a logic low

state, SPI words may be sent to the 33813 via the serial input (SI) pin and status information is received by the MCU via the serial output

(SO) pin. The falling edge of CSB enables the SO output and transfers status information into the SO buffer.

The rising edge of the CSB initiates the following operation:

• Disables the SO driver (high-impedance)

• Activates the received command word, allowing the 33813 to activate/deactivate output drivers

To avoid spurious data, the high-to-low and low-to-high transitions of the CSB signal must occur only when SCLK is in a logic low state.

Internal to the 33813 device is an active pull-up to VCC on CSB. In cases where voltage exists on CSB without the application of VCC, no

current flows from CSB to the VCC pin.This input requires CMOS logic levels referenced to VCC and has an internal active pull-up current

source.

Table 67. ISO status register description field

Field Description

0-ISO Overtemp

Overtemp condition fault

0-No over temp condition reached

1-Overtemp condition reached

Table 68. Model code/revision number register

Reg # Hex 76543210

15 F

Model Code/ Revision

Number*

*Read Only except for POST

Enable

Model

Code 2

Model

Code 1

Model

Code 0 Rev # Rev # Rev # Rev # Rev #

Reset (0) (1) (0) (X) (X) (X) (X) (X)

Table 69. Model code/revision number register field description

Field Description

7-5 Model Code Model Code #010 = 33813 device

4-0 Rev # Rev #

NXP Semiconductors 55

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5.10.1.3 SI input

The SI pin is used for serial instruction data input. SI information is latched into the input register on the rising edge of SCLK and the input

data transitions on the falling edge of SCLK. A logic high state present on SI programs a one in the command word on the rising edge of

the CSB signal. To program a complete word, 16 bits of information must be entered into the device.This input requires CMOS logic levels

referenced to VCC.

5.10.1.4 SO output

The SO pin is the output from the SPI shift register. The SO pin remains high-impedance until the CSB pin transitions to a logic low state.

All normal operating drivers are reported as zero, all faulted drivers are reported as one. The negative transition of CSB enables the SO

driver. The SI / SO shifting of the data follows a first-in-first-out protocol with both input and output words transferring the most significant

bit (MSB) first. The serial output data is available to be latched by the MCU on the rising edge of SCLK. The SO data transitions on the

falling edge of the SCLK. This output provides CMOS logic levels referenced to VCC.

5.10.2 MCU SPI interface description

The 33813 device directly interfaces to a 5.0 V microcontroller unit (MCU) using a16-bit serial peripheral interface (SPI) protocol. SPI serial

clock frequencies up to 8.0 MHz can be used when programming and reading output status information (production tested at 1.0 MHz).

Figure 19 illustrates the SPI configuration between an MCU and one 33813.

Data is sent to the 33813 device through the SI input pin. As data is being clocked into the SI pin, other data is being clocked out of the

device by the SO output pin. The response data received by the MCU during SPI communication depends on the previous SPI message

sent to the device. The SPI can be used to read or write data to the configuration and control registers and to read or write the data

contained in the status registers.

The MCU is only allowed to read or clear bits (write zeros) in the status register unless the Power ON Self-test (POST) enable bit in the

control register is set. When the POST enable bit is set, the MCU can read and write zeros or ones to the status register. Note that the

MCU must clear the POST enable bit before operation is resumed or the status register does not update with fault indications.

5.10.2.1 SPI integrity check

One SPI word is reserved as a SPI check message. When bits 12 through15 are all zero, the SPI echoes the remaining 12-bit SPI word

sent and flips bits 12 through14, bit 15 remains a 0. This allows the MCU to poll the SPI and compare the received message to confirm

the integrity of the SPI communication channel to the 33813. There is a SPI error bit in the SPI status register indicating if an incorrect

SPI message has been received. The SPI error bit in the SPI status register is set whenever any SPI message error is detected.

Important A SCLK pulse count strategy has been implemented to ensure integrity of SPI communications. Only SPI messages consisting

of 16 SCLK pulses are acknowledged. SPI messages consisting of other than 16 SCLK pulses are ignored by the device and reported as

a SPI error. Invalid SPI messages, containing invalid commands or addresses are also flagged as a SPI error.

Figure 19. SPI interface with microprocessor

Two or more 33813 devices can be used in a module system. Multiple ICs can be SPI configured in parallel only. Figure 19 demonstrates

the configuration.

33813

Micro controller

Receive

Buffer

Parallel

Ports

To Logic

16-Bit Shift RegisterShift Register

MOSI SI

MISO SO

SCLK

CSB

56 NXP Semiconductors

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Figure 20. SPI parallel interface (only) with microprocessor

5.10.2.2 SPI register definitions

There are three basic SPI register types:

Configuration registers - used to set the operating modes and parameters for the 33813 functional blocks. Each output can be configured

by setting the individual bits in the configuration register for output according to the descriptions in the previous functional descriptions for

each particular output.

Control registers - used to turn outputs on and off and set the PWM duty cycle for outputs used as PWM outputs. Setting the temporary

operating parameters for the watchdog timer and the VRS circuit is also used.

Status registers - used to annunciate faults and other values the MCU may need to act upon. Each output and functional block has a

status register associated with it and the individual fault bits for each of the faults monitored are contained in these registers.

Non-fault bits in the status register can be set and cleared by the 33813 circuit. All status register bits not marked as ‘x’ can be cleared by

the MCU only when the POST bit is zero (0). When the POST bit is one (1), the MCU can read or write any existing bit in the status register.

Non-existing bits (marked with an ‘x’ in the table) cannot be changed from the default zero (0) value.

Entries in the following SPI Registers marked with an ‘x’ are non-existent bits. They are set to zero (0) by default and cannot be changed

by reading or writing to them. They should be ignored when testing registers during POST.

5.10.2.3 SPI command summary

The SPI commands are defined as 16 bits with 4 address control bits and 12 command data bits. There are 7 separate commands used

to set the operational parameters of device. The operational parameters are stored internally in 8-bit registers. Write commands write the

data contained in the present SPI word whereas read commands must wait until the next SPI command is sent to read the data requested.

Table 11 defines the commands and default state of the internal registers at POR. SPI commands may be sent to the device at any time

while the device is in the Normal state. Messages sent are acted upon on the rising edge of the CSB input. The bit value returned equals

bit value sent for this command.

Table 70. SPI command messages

Command

Control Address Bits Data Bits

hex 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SPI Check 0 0 0 0 0 X* X* X* X* X* X* X* X* X* X* X* X*

Read Configuration

Internal Register Address 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1

Write Configuration

Internal Register Address 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1

Parallel

Ports

Micro controller 33813

33879A

SCLK

CSB

SCLK

CSB

SCLK

MISO

MOSI

Shift Register

NXP Semiconductors 57

33813

There are seven SPI commands issued by the MCU to:

• Do a SPI Check verification

• Read the contents of the SPI configuration registers

• Write the contents of the SPI configuration registers

• Read the contents of the SPI status registers

• Write the contents of the SPI status registers

• Read the contents of the SPI control registers

• Write the contents of the SPI control registers

5.10.3 SPI drivers register

5.11 SPI registers mapping

The SPI interface consists of three blocks of four, 8-bit read/write registers. There are three types of SPI registers:

•Configuration registers - These registers allow the MCU to configure the various parameters and options for the various functional

blocks.

•Control registers - These registers are used to command the outputs on and off and set the PWM duty cycle values.

•Status registers - These registers report back faults and other conditions of the various functional blocks.

The following conventions are used in the SPI register tables:

• All default selections are in BOLD fonts.

• Non-default selections are in normal font.

• The first selection listed is the default selection.

• The binary values shown, (0 or 1) are the default values after a reset has occurred.

Read Status Register 3 0 0 1 1 <0000>

Internal Register Address 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1

Write Status Register 4 0 1 0 0 <0000>

Internal Register Address 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1

Read Control Register 5 0 1 0 1 <0000>

Internal Register Address 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1

Write Control Register 6 0 1 1 0 <0000>

Internal Register Address 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1

SPI Check Response 7 0 1 1 1 X* X* X* X* X* X* X* X* X* X* X* X*

Table 71. Power supply and any system fault status register

Reg # Hex 76543210

13 DPower Supply and Any

System Faults

Any

System

Faults

Keysw Pwren Batsw SPI error

VPROT

Short to

Battery

VPROT

Overtemp

VPROT

Short to

Ground

Reset (0) (0) (0) (0) (0) (0) (0) (0)

Table 72. Power supply and any system fault status register description field

Field Description

3-SPI Error

SPI Error fault status

0-No fault reported

1-Fault reported

Table 70. SPI command messages (continued)

Command

Control Address Bits Data Bits

hex1514131211109876543210

58 NXP Semiconductors

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Table 73. SPI configuration registers

Reg # Hex 7 6 5 4 3 2 1 0

0 0 Injector 1 Driver

Retry

Enable X X OL Current

Sink Enable

In-Rush

Delay OR/AND PWM

Freq. 1

PWM

Freq. 0

Reset (0) (0) (0) (1) (0) (0) (0) (0)

1 1 Not Used X X X X X X X X

Reset (0) (0) (0) (0) (0) (0) (0) (0)

2 2 Relay 1 Driver

Retry

Enable X X OL Current

Sink Enable

In-Rush

Delay OR/AND PWM

Freq. 1

PWM

Freq. 0

Reset (0) (0) (0) (1) (0) (0) (0) (0)

3 3 Relay 2 Driver

Retry

Enable

Shutdown

DisableSD

XOL Current

Sink Enable

In-Rush

Delay OR/AND PWM

Freq. 1

PWM

Freq. 0

Reset (0) (0) (0) (1) (0) (0) (0) (0)

4 4 Tachometer Driver

Retry

Enable

Vrsout/

LSD

Vrsout/

Osc. mode

N16/OL

Current Sink

Enable

N8/In-Rush

Delay N4/Osc 2

N2/Osc 1/

PWM

Freq. 1

N1/Osc 0/

PWM

Freq. 0

Reset (0) (0) (0) (0) (0) (0) (0) (1)

5 5 Lamp Driver

Retry

Enable X X OL Current

Sink Enable

In-Rush

Delay XPWM

Freq. 1

PWM

Freq. 0

Reset (0) (0) (0) (1) (1) (0) (0) (0)

6 6 Battery Switch Logic Output HSD Mode X X X X X PWM

Freq.1

PWM

Freq. 0

Reset (0) (0) (0) (0) (0) (0) (0) (0)

7 7 O2 Heater Pre-driver

GPGD/IGN

Select

Retry

Enable XOL Current

Sink XOR/AND PWM

Freq. 1

PWM

Freq. 0

Reset (0) (0) (0) (1) (0) (0) (0) (0)

8 8 Ignition 1 Pre-driver

GPGD/IGN

Select

Retry

Enable XOL Current

Sink XOR/AND PWM

Freq. 1

PWM

Freq. 0

Reset (1) (0) (0) (0) (0) (0) (0) (0)

9 9 Not Used X X X X X X X X

Reset (0) (0) (0) (0) (0) (0) (0) (0)

10 AWatchdog Parameters

Disable/

Enable

Load Time

x1 sec

Load Time

x100 ms

Load Time

x10 ms

Load Time

Reset (1) (1) (0) (0) (1) (0) (1) (0)

11 BVRS Engine Running

Parameters

Threshold

1Threshold 0 Filter Time

Filter Time

Reset (0) (1) (0) (1) (0) (0) (1) (1)

12 CVRS Automatic Parameters mantiss 8 mantiss 4 mantiss 2 mantiss 1 exponent 8 exponent 4 exponent 2 exponent 1

Reset (0) (0) (1) (0) (0) (0) (0) (1)

13 DVRS Miscellaneous

Parameters

Man./Auto Disable

VRS XHigh/ Low

Ref De-glitch Gnd VRSN Inv Inputs Disable

2.5 V CM

Reset (0) (0) (0) (0) (0) (0) (0) (0)

NXP Semiconductors 59

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Table 74. SPI control registers

Reg # Hex 76543210

0 0 Main OFF/ON Control INJ1 XREL1 REL2 LAMP IGN1 XO2H

Reset (0) (0) (0) (0) (0) (0) (0) (0)

1 1 Other OFF/ON Control

Pwren

OFF/ON

POST

Enable

OFF/ON

XVProt OFF/

ON XBatsw

OFF/ON

Tach

OFF/ON

RESET

internal

only

Reset (0) (0) (0) (1) (0) (0) (1) (0)

2 2 Injector 1 Driver XPWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0

Reset (0) (0) (0) (0) (0) (0) (0) (0)

3 3 Not Used XXXXXXXX

Reset (0) (0) (0) (0) (0) (0) (0) (0)

4 4 Relay 1 Driver XPWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0

Reset (0) (0) (0) (0) (0) (0) (0) (0)

5 5 Relay 2 Driver XPWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0

Reset (0) (0) (0) (0) (0) (0) (0) (0)

6 6 Tachometer Driver XPWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0

Reset (0) (0) (0) (0) (0) (0) (0) (0)

7 7 Lamp Driver XPWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0

Reset (0) (0) (0) (0) (0) (0) (0) (0)

8 8 Batsw XPWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0

Reset (0) (0) (0) (0) (0) (0) (0) (0)

9 9 O2 Heater Pre-driver XPWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0

Reset (0) (0) (0) (0) (0) (0) (0) (0)

10 AIgnition 1 Pre-driver XPWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0

Reset (0) (0) (0) (0) (0) (0) (0) (0)

11 BNot Used XXXXXXXX

Reset (0) (0) (0) (0) (0) (0) (0) (0)

12 CWatchdog WDRFSH Load Time

x1 sec

Load Time

x100 ms

Load Time

x10 ms

Load Time

Reset (0) (0) (0) (0) (0) (0) (0) (0)

13 DVRS Engine Cranking

Parameters

Threshold

Filter Time

Reset (0) (0) (0) (0) (0) (0) (0) (0)

Table 75. SPI status registers

Reg # Hex 7 6 5 4 3 2 1 0

0 0 Injector 1 Driver Faults Faults XXXOpen Load

Over -

current OC

Overtemp

Short Gnd

Reset (0) (0) (0) (0) (0) (0) (0) (0)

1 1 Not Used X XXXX X XX

Reset (0) (0) (0) (0) (0) (0) (0) (0)

2 2 Relay 1 Driver Faults Faults XXXOpen Load

Overcurrent

Overtemp

Short Gnd

Reset (0) (0) (0) (0) (0) (0) (0) (0)

60 NXP Semiconductors

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3 3 Relay 2 Driver Faults Faults XXXOpen Load

Overcurrent

Overtemp

Short Gnd

Reset (0) (0) (0) (0) (0) (0) (0) (0)

4 4 Tachometer Driver Faults Faults XXXOpen Load

Overcurrent

Overtemp

OT X

Reset (0) (0) (0) (0) (0) (0) (0) (0)

5 5 Lamp Driver Faults Faults XXXOpen Load

Overcurrent

Overtemp

Short Gnd

Reset (0) (0) (0) (0) (0) (0) (0) (0)

7 7 O2 Heater Pre-driver Faults Faults XXXOpen Load

Overcurrent

OC X X

Reset (0) (0) (0) (0) (0) (0) (0) (0)

8 8 Ignition 1 Pre-driver

Faults

Faults XXXOpen Load

Overcurrent

OC X X

Reset (0) (0) (0) (0) (0) (0) (0) (0)

9 9 Not Used X XXXX X XX

Reset (0) (0) (0) (0) (0) (0) (0) (0)

10 AWatchdog State

Enable/

Disable

WD timer

bit 6

WD timer

bit 5

WD timer

bit 4

WD timer

bit 3

WD timer bit

WD timer

bit 1

WD timer

bit 0

Reset (0) (0) (0) (0) (0) (0) (0) (0)

11 BVRS Conditioner and

ISO9141 Faults

Peak 8 Peak 4 Peak 2 Peak 1 X

Clamp-

active

VRSP

Clamp-

active

VRSN

ISO

Overtemp

Reset (0) (0) (0) (0) (0) (0) (0) (0)

13 DPower Supply and

Any System Faults

Any

System

Faults

Keysw Pwren Batsw SPI Error

VPROT

Short to

Battery

VPROT

Overtemp

VPROT

Short to

Ground

Reset (0) (1) (0) (0) (0) (0) (0) (0)

14 ESystem On/Off

Indicators

INJ1

Off/On XREL1

Off/On

REL2

Off/On

LAMP

Off/On

IGN1

Off/On XO2H

Off/On

Reset (0) (0) (0) (0) (0) (0) (0) (0)

15 F

Model Code/ Revision

Number*

*Read Only except for POST

Enable

Model

Code 2

Model

Code 1

Model

Code 0 Rev # Rev # Rev # Rev # Rev #

Reset (0) (1) (0) (0) (0) (0) (0) (0)

Table 75. SPI status registers (continued)

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Table 76. SPI configuration bits R/W access

x Description 7 6 5 4 3 2 1 0

Configuration registers

0 0 Injector 1

driver

Retry

enable R/W x R(27) x R(27) OL current

sink enable R/W In-rush

delay R/W OR/AND R/W PWM

Freq. 1 R/W PWM

Freq. 0 R/W

1 1 Not used x R(27) x R(27) x R(27) x R(27) x R(27) x R(27) x R(27) x R(27)

2 2 Relay 1 driver Retry

enable R/W x R(27) x R(27) OL current

sink enable R/W In-rush

delay R/W OR/AND R/W PWM

Freq. 1 R/W PWM

Freq. 0 R/W

3 3 Relay 2 driver Retry

enable R/W

Shut

down

disable

SDD

R/W xOL current

sink enable

In-rush

delay R/W OR/AND R/W PWM

Freq. 1 R/W PWM

Freq. 0 R/W

4 4 Tachometer

driver

Retry

enable R/W VRSout

/LSD R/W Vrsout/

Osc mode R/W

N16/OL

current sink

enable

R/W N8/In-rush

delay R/W N4/Osc 2 R/W

N2/OSC

1/ PWM

Freq.1

R/W

N1/OSC

0/ PWM

Freq.0

R/W

5 5 Lamp driver Retry

enable R/W x R(27) x R(27) OL current

sink enable R/W In-rush

delay R/W x R(27) PWM

Freq. 1 R/W PWM

Freq. 0 R/W

6 6 Battery switch

logic output

HSD

mode R/W x R(27) x R(27) x(28) x R(27) x R(27) PWM

Freq. 1 R/W PWM

Freq. 0 R/W

7 7 O2 heater

predriver

CPGD/

IGN

select

R/W Retry

enable R/W x R(27) OL current

sink enable R/W x R(27) OR/AND R/W PWM

Freq. 1 R/W PWM

Freq. 0 R/W

8 8 Ignition 1

predriver

CPGD/

IGN

select

R/W Retry

enable R/W x R(27) OL current

sink enable R/W x R(27) OR/AND R/W PWM

Freq. 1 R/W PWM

Freq. 0 R/W

9 9 Not used x R(27) x R(27) x R(27) x R(27) x R(27) x R(27) x R(27) x R(27)

10 AWatchdog

parameters

Disable/

Enable R/W

Load

time x1

sec

R/W Load time

x100 ms R/W Load time

x10 ms R/W Load time

8R/W Load

time 4 R/W Load time

2R/W Load time

1R/W

11 B

VRS engine

running

parameters

Threshold

3R/W Thresh

old 2 R/W Threshold

1R/W Threshold 0 R/W Filter time

3R/W Filter

time 2 R/W Filter time

1R/W Filter time

0R/W

12 C

VRS

automatic

parameters

Mantiss 8 R/W Mantiss

4R/W Mantiss 2 R/W Mantiss 1 R/W Exponent

8R/W Exponent

4R/W Exponent

2R/W Exponent

1R/W

13 D

VRS

miscellaneous

parameters

Man/Auto R/W Disable

VRS R/W x R(27) High/low ref R/W De-glitch R/W GND

VRSN R/W Inv inputs R/W Disable

2.5 V CM R/W

Notes

27. Only read as 0

28. Cannot be written, always read as 0

62 NXP Semiconductors

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Table 77. SPI control bits R/W access

Hex Description 7 6 5 4 3 2 1 0

Control registers

0 0 Main ON/OFF

control INJ1 R/W INJ2 R/W REL1 R/W REL2 R/W LAMP R/W IGN1 R/W IGN2 R/W O2H R/W

1 1 Other OFF/

ON control

Pwren OFF/

ON R(29)

POST

enable

OFF/

R/W x R(30) Vprot OFF/

ON R/W x R(30) Batsw

OFF/ON R/W Tach

OFF/ON R/W

RESET

internal

only

2 2 Injector 1

driver x R(29) PWM6 R/W PWM5 R/W PWM4 R/W PWM3 R/W PWM2 R/W PWM1 R/W PWM0 R/W

3 3 Not used x R(29) x R(29) x R(29) x R(29) x R(29) x R(29) x R(29) x R(29)

4 4 Relay 1 driver x R(29) PWM6 R/W PWM5 R/W PWM4 R/W PWM3 R/W PWM2 R/W PWM1 R/W PWM0 R/W

5 5 Relay 2 driver x R(29) PWM6 R/W PWM5 R/W PWM4 R/W PWM3 R/W PWM2 R/W PWM1 R/W PWM0 R/W

6 6 Tachometer

driver x R(29) PWM6 R/W PWM5 R/W PWM4 R/W PWM3 R/W PWM2 R/W PWM1 R/W PWM0 R/W

7 7 Lamp driver x R(29) PWM6 R/W PWM5 R/W PWM4 R/W PWM3 R/W PWM2 R/W PWM1 R/W PWM0 R/W

8 8 Batsw x R(29) PWM6 R/W PWM5 R/W PWM4 R/W PWM3 R/W PWM2 R/W PWM1 R/W PWM0 R/W

9 9 O2 heater

predriver x R(29) PWM6 R/W PWM5 R/W PWM4 R/W PWM3 R/W PWM2 R/W PWM1 R/W PWM0 R/W

10 AIgnition 1

predriver x R(29) PWM6 R/W PWM5 R/W PWM4 R/W PWM3 R/W PWM2 R/W PWM1 R/W PWM0 R/W

11 BNot used x R(29) x R(29) x R(29) x R(29) x R(29) x R(29) x R(29) x R(29)

12 CWatchdog WDRFSH (31) Load

time x1

sec

R/W

Load

time

x100

R/W Load time

x10 ms R/W Load time

8R/W Load

time 4 R/W Load

time 2 R/W Load

time 1 R/W

13 D

VRS engine

cranking

parameters

Threshold 3 R/W Thresh

old 2 R/W Thres

hold 1 R/W Threshold

0R/W Filter time

3R/W Filter

time 2 R/W Filter

time 1 R/W Filter

time 0 R/W

Notes

29. Only read as 0

30. Cannot be written, always read as 0

31. Can only be written to 1. Write 0 has no effect. Only read as 0.

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Table 78. SPI status bits R/W access

Hex Description 7 6 5 4 3 2 1 0

Status registers

0 0 Injector 1

driver faults Faults R(32) x R(33) x R(33) x R(33) Openload

OL R(34) Over

current

R(34) Over

temp OT R(34) Short to

GND

(SG)

R(34)

1 1 Not used x R(33) x R(33) x R(33) x R(33) x R(33) x R(33) x R(33) x R(33)

2 2 Relay 1 driver

faults Faults R(32) x R(33) x R(33) x R(33) Openload

OL R(34) Over

current

R(34) Over

temp OT R(34) Short to

GND

(SG)

R(34)

3 3 Relay 2 driver

faults Faults R(32) x R(33) x R(33) x R(33) Openload

OL R(34) Over

current

R(34) Over

temp OT R(34) Short to

GND

(SG)

R(34)

4 4 Tachometer

driver faults Faults R(32) x R(33) x R(33) x R(33) Openload

OL R(34) Over

current

R(34) Over

temp OT R(34) x R(33)

5 5 Lamp driver

faults Faults R(32) x R(33) x R(33) x R(33) Openload

OL R(34) Over

current

R(34) Over

temp OT R(34) Short to

GND

(SG)

R(34)

7 7

O2 heater

predriver

faults

Faults R(32) x R(33) x R(33) x R(33) Openload

OL R(34) Over

current

R(34) x R(33) x R(33)

8 8

Ignition 1

predriver

faults

Faults R(32) x R(33) x R(33) x R(33) Openload

OL R(34) Over

current

R(34) x R(33) x R(33)

9 9 Not used x R(33) x R(33) x R(33) x R(33) x R(33) x R(34) x R(33) x R(33)

10 AWatchdog

state

Disable/

Enable R

timer

bit 6

timer bit

RWD timer

bit 4 RWD timer

bit 3 RWD timer

bit 2 RWD timer

bit 1 RWD timer

bit 0 R

11 B

VRS

conditioner

and ISO 9141

faults

Peak 8 RPeak 4 RPeak 2 RPeak 1 R x R(33) Clamp

active

VRSP

Clamp

active

VRSN

ISO

overtemp

R(34)

13 D

Power supply

and any

system faults

Any

system

faults

R(32) Keysw RPWREN RBATSW RSPI error R(34) Vprot

short to

battery

R(34) Vprot

overtemp R(34) Vprot

short to

ground

R(34)

14 ESystem On/

Off indicators

INJ1

OFF/ON R

INJ12

OFF/

RREL1

OFF/ON RREL2

OFF/ON RLAMP

OFF/ON RIGN1

OFF/ON RIGN2

OFF/ON RO2H

OFF/ON R

15 F

Model code/

revision

number

Model

code 2 RModel

code 1 RModel

code 0 RREV# RRev# RRev# RRev# RRev# R

Notes

32. Can only be written to 0 when faults have disappeared

33. Only read as 0

34. Can only be written to 0 when the fault has disappeared

64 NXP Semiconductors

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6 Typical applications

6.1 Output OFF open load fault

An Output OFF Open Load Fault is the detection and reporting of an open load when the corresponding output is disabled (input bit

programmed to a logic low state). The Output OFF Open Load Fault is detected by comparing the drain-to-source voltage of the specific

MOSFET output to an internally generated reference. Each output has one dedicated comparator for this purpose.

Each output has an internal pull-down current source or resistor. The pull-down current sources are enabled on power-up and must be

enabled for Open Load Detect to function. In cases were the Open Load Detect current is disabled, the status bit always responds with

logic 0. The device only shuts down the pull-down current in Sleep mode or when disabled via the SPI.

During output switching, especially with capacitive loads, a false Output OFF Open Load Fault may be triggered. To prevent this false fault

from being reported, an internal fault filter of 100 to 450 µs is incorporated. The duration for which a false fault may be reported is a function

of the load impedance RDS(ON), COUT of the MOSFET as well as the supply voltage VPWR. The rising edge of CSB triggers the built-in fault

delay timer. The timer must time out before the fault comparator is enabled to detect a faulted threshold. Once the condition causing the

Open Load Fault is removed, the device resumes normal operation. The Open Load Fault, however, is latched in the output SO Response

6.2 Low voltage operation

Low voltage condition (6.5 V< VPWR <9.0 V) operates per the command word, however parameter tables may be out of specification and

status reported on SO pin is not guaranteed.

6.3 Low-side injector driver voltage clamp

Each Injector output of the 33813 incorporates an internal voltage clamp to provide fast turn-OFF and transient protection. Each clamp

independently limits the drain-to-source voltage to VCL. The total energy clamped (EJ) can be calculated by multiplying the current area

under the current curve (IA) times the clamp voltage (VCL) (see Figure 21). Characterization of the output clamps indicates the maximum

energy to be 100 mJ at 125 °C junction temperature per output.

Figure 21. Output voltage clamping

6.4 Reverse battery protection

The 33813 device requires external reverse battery protection on the VPWR pin. All outputs consist of a power MOSFET with an integral

substrate diode. During a reverse battery condition, current flows through the load via the substrate diode. Under this condition load,

devices turn on. If load reverse battery protection is desired, a diode must be placed in series with the load.

Current

Area (I

Clamp Energy

(EJ = I

A x VCL )

Drain Voltage

Time

Dr ai n-to-S ourc e C lamp

Voltage (VCL = 45 V)

Drain Curre nt

(ID = 0.3 A)

GND

Dr ai n-to-S ourc e O N

Voltage (VDS(O N))

50 V)

Drain-to-Source Clamp

Voltage (VCL = 50 V)

Drain-to-Source ON

Voltage (VDS(ON))

Drain Voltage

Clamp Energy

(EJ = IA x VCL)

GND Time

Drain Current

(ID = 0.3 A)

NXP Semiconductors 65

33813

7 Packaging

7.1 Package mechanical dimensions

Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and

perform a keyword search for the drawing’s document number.

Table 79. 98A reference documents

Package Suffix Package outline drawing number

48-Pin LQFP-EP AE 98ASA00737D

66 NXP Semiconductors

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NXP Semiconductors 67

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68 NXP Semiconductors

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NXP Semiconductors 69

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8 Revision history

REVISION DATE DESCRIPTION OF CHANGES

1.0 3/2012 • Initial release

• Removed Freescale Confidential Proprietary on page 1

2.0 8/2012

• Changed second instance of “VRS Low-state Output Voltage” to “VRS High-state Output Voltage” on Page 14

• Changed the word “Voltage” to “Current” on Page 15

• Replaced “ISO914” (incorrect) with “ISO9141” on p.27

• Adjusted Peak Values in Table 57

• Changed VPP Supply Voltage (If supplied externally and not using internal VPP regulator) to reflect two separate

limits

• Changed VPROT Output Voltage (tracks VCC) IVCC = 100 mA, IVPROT = 50 mA 9.0 V< VPWR < 18 V Max limit.

• Changed Typ and Max limit on Load Regulation (Both VCC and VPROT) measured from 10% - 90% of IVCC_C

and IPROT_C, VPWR = 13 V

• Changed Min limit on VRS Negative Clamp Voltage at ICLAMP = 10 mA

• Removed any remaining references to INJIN2, INJOUT2, IGNIN2, IGNOUT2, and IGNFB2

• Added Typical electrical characteristics

• Added VRS schematic

• Updated Table 56

• Added lower limit note for VCC Output Current Limiting

3.0 4/2013

• Updated Output Clamp Energy (INJOUT1, ROUT1, ROUT2) and added Output Clamp Energy (LAMPOUT)

• Added ESD Voltage

• Added clarification to 5.5.1.5. LAMPOUT driver output, page 34

4.0 5/2013

• Added symbol to Output OFF Open Load Detection Current TachOut

• Corrected limits to Pre-driver

• Corrected limits to VRS Positive Clamp Voltage at ICLAMP = 10 mA

• Deleted SCLK Input Current parameter for DIGITAL INTERFACE (MRX, MTX,CSB, SI, SCLK, SO, RINx,O2HIN,

INJIN1, IGNIN1, BATSW, VRSOUT, RESETB)

5.0 5/2013 • Changed part number from PC33813AE to MC33813AE in Table 1, Orderable part variations

6.0 5/2013 • Corrected package from 98ASA00173D to 98ASA00430D

7.0 10/2015 • Corrected package from 98ASA00430D to 98ASA00737D and associated images as per PCN # 16956

8.0 3/2016

• Rewrite of section 4.4. Timing diagrams, page 17

• Updated the IC description and list of features

• Updated Figure 1 with better representations

• Updated description for pre-driver pins in 3.2. Pin definitions, page 5

• Removed Output clamp energy in continuous operation mode

• Corrected VESD1 parameter

• Updated the INJOUT1 Output Self Limiting Current low limit from 1.6A to 1.8A

• Corrected the description in pre-driver section for VIGNFB/GPGD

• ISO9141 section: Added Overtemperature threshold & Hysteresis parameter

• Added KEYSW Filter time parameter

• Updated 4.5.2. VCC and VPROT characteristics, page 19

• Rewrite of section 5. General IC functional description and application information, page 21

• Corrected typo (100 KHz changed to 100 Hz)

• Updated 5.7.2.6. GND VRSN bit, page 50

• Updated data sheet document format and style

4/2016 • Corrected Figure 16

9.0 9/2016

• Added VCC max rating (7.0 V)

• Clarified overcurrent and short to VBAT fault bit reporting for drivers and pre-drivers

• Corrected the effect of open load sink current disable bit

• Added the 32 kΩ internal pull-up present on ISO Pin

• Updated Figure 13

10.0 7/2017

• Design enhancement to fulfill ISO 16750 test, and modification of the state machine related to exit condition from

Prepare to Shutdown mode as per CIN# 201706024I

• Updated Figure 13

• Added note to 5.1.2.4. Prepare to shutdown state, page 23

70 NXP Semiconductors

33813

11.0 6/2018 • Minor typo corrections

• Added Table 20, Table 76, Table 77 and Table 78

12.0 12/2019 • Updated IRESET_LEAKAGE_HIGH minimum value in Table 4 as per CIN 201912008I

REVISION DATE DESCRIPTION OF CHANGES

Document Number: MC33813

Rev. 12

12/2019

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