fax id: 7044 2652T CY74FCT16652T CY74FCT162652T 16-Bit Registered Transceiver Features Functional Description * Low power, pin-compatible replacement for ABT functions * FCT-E speed at 3.8 ns * Power-off disable outputs permits live insertion * Edge-rate control circuitry for significantly improved noise characteristics * Typical output skew < 250 ps * ESD > 2000V * TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages * Industrial temperature range of -40C to +85C * VCC = 5V 10% CY74FCT16652T Features: * 64 mA sink current, 32 mA source current * Typical VOLP (ground bounce) <1.0V at VCC = 5V, TA = 25C CY74FCT162652T Features: * Balanced 24 mA output drivers * Reduced system switching noise * Typical VOLP (ground bounce) <0.6V at VCC = 5V, TA= 25C These 16-bit, high-speed, low-power, registered transceivers that are organized as two independent 8-bit bus transceivers with three-state D-type registers and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. OEAB and OEBA control pins are provided to control the transceiver functions. SAB and SBA control pins are provided to select either real-time or stored data transfer. Data on the A or B data bus, or both, can be stored in the internal D flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (CLKAB or CLKBA), regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. The output buffers are designed with a power-off disable feature that allows live insertion of boards. The CY74FCT16652T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162652T has 24-mA balanced output drivers with current-limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162652T is ideal for driving transmission lines. Logic Block Diagrams 1 OEAB 2 OEAB 1 OEBA 2 OEBA 1 CLKBA 2 CLKBA 1 SBA 2 SBA 1 CLKAB 2 CLKAB 1 SAB 2 SAB B REG B REG D D C C 2 A1 1 A1 A REG A REG D D 1 B1 C TO 7 OTHER CHANNELS Cypress Semiconductor Corporation FCT16652-1 * 3901 North First Street 2 B1 C TO 7 OTHER CHANNELS * San Jose FCT16652-2 * CA 95134 * 408-943-2600 July 1994 - Revision October 30, 1997 \ CY74FCT16652T CY74FCT162652T Pin Configuration SSOP/TSSOP Top View 1 OEAB 1 56 1OEBA 1 CLKAB 2 55 1 CLKBA 1 SAB 3 54 1 SBA GND 4 53 1A 1 5 52 1B1 GND 1A 2 6 51 1B2 VCC 7 50 VCC 1A 3 8 49 1B3 1A 4 9 48 1B4 1A 5 10 47 1B5 GND 11 46 GND 1A 6 12 45 1B6 1A 7 13 44 1B7 1A 8 14 43 1B8 2A 1 15 42 2B1 2A 2 16 41 2B2 2 A3 17 40 2B3 GND 18 39 GND 2A 4 19 38 2B4 2A 5 20 37 2B5 2A 6 21 36 2B6 V CC 22 35 VCC 2A 7 23 34 2B7 2A 8 2B8 GND 24 FCT16652-1 33 25 32 2 SAB 26 31 2SBA 2 CLKAB 27 30 2 CLKBA 2OEAB 28 29 GND 2 OEBA FCT16652-3 Pin Description Name Description A Data Register A Inputs Data Register B Outputs B Data Register B Inputs Data Register A Outputs CLKAB, CLKBA Clock Pulse Inputs SAB, SBA Output Data Source Select Inputs OEAB, OEBA Output Enable Inputs 2 \ CY74FCT16652T CY74FCT162652T Function Table[1] Data I/O[2] Inputs OEAB OEBA CLKAB CLKBA SAB SBA A B L L H H H or L H or L X X X X Input Input Operation or Function X H H H H or L X X[3] X X Input Input Unspecified[2] Output Store A, Hold B Store A in Both Registers L L X L H or L X X X X[3] Unspecified[2] Input Input Hold A, Store B Store B in both Registers L L X X X L Output Input L L X H or L X H Real Time B Data to A Bus Stored B Data to A Bus H H X X L X Input Output H H H or L X H X Real Time A Data to B Bus Stored A Data to B Bus H L H or L H or L H H Output Output Stored A Data to B Bus and Stored B Data to A Bus Isolation Store A and B Data Notes: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care =LOW-to-HIGH Transition 2. The data output functions may be enabled or disabled by various signals at the OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. 3. Select control=L; clocks can occur simultaneously. Select control=H; clocks must be staggered to load both registers. 3 \ CY74FCT16652T CY74FCT162652T BUS A BUS B OEAB L OEBA L CLKAB X CLKBA X SAB X BUS A SBA L OEAB H BUS B OEBA L Real-Time Transfer Bus B to BusA OEBA H X H CLKAB CLKBA X X SAB L CLKBA X SBA X Real-Time Transfer BusA to Bus B BUS A OEAB X L L CLKAB X SAB X X X BUS B BUS A SBA X X X OEAB H BUS A OEBA L Storage from A and/or B CLKAB H or L CLKBA H or L SAB H SBA H Transfer Stored Data to A and/or B Maximum Ratings[4] (Above which the useful life may be impaired. For user guidelines, not tested.) Power Dissipation .......................................................... 1.0W Storage Temperature ..................... Com'l -55C to +125C Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Ambient Temperature with Power Applied ................................. Com'l -55C to +125C Operating Range DC Input Voltage .................................................-0.5V to +7.0V Range DC Output Voltage ..............................................-0.5V to +7.0V Industrial DC Output Current (Maximum Sink Current/Pin) ........................... -60 to +120 mA Ambient Temperature VCC -40C to +85C 5V 10% Note: 4. Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 4 \ CY74FCT16652T CY74FCT162652T DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions[5] Min. 2.0 VIH Input HIGH Voltage Guaranteed Logic HIGH Level VIL Input LOW Voltage Guaranteed Logic LOW Level VH Input Hysteresis VIK Input Clamp Diode Voltage VCC=Min., IIN=-18 mA IIH Input HIGH Current IIL Typ.[6] Max. Unit V 0.8 100 mV -1.2 V VCC=Max., VI=VCC 1 A Input LOW Current VCC=Max., VI=GND 1 A IOZH High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=2.7V 1 A IOZL High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=0.5V 1 A IOS Short Circuit Current[8] VCC=Max., VOUT=GND -80 -200 mA [8] VCC=Max., VOUT=2.5V -50 -180 mA 1 A Max. Unit IO IOFF Output Drive Current VCC=0V, VOUT4.5V Power-Off Disable -0.7 V -140 [7] Output Drive Characteristics for CY74FCT16652T Parameter VOH VOL Test Conditions[5] Min. Typ.[6] VCC=Min., IOH=-3 mA 2.5 3.5 VCC=Min., IOH=-15 mA 2.4 3.5 VCC=Min., IOH=-32 mA 2.0 3.0 Description Output HIGH Voltage Output LOW Voltage VCC=Min., IOL=64 mA V 0.2 0.55 V Min. Typ.[6] Output Drive Characteristics for CY74FCT162652T Parameter IODL Test Conditions[5] Description Max. Unit [8] VCC=5V, VIN=VIH or VIL, VOUT=1.5V 60 115 150 mA [8] -150 mA Output LOW Current IODH Output HIGH Current VCC=5V, VIN=VIH or VIL, VOUT=1.5V -60 -115 VOH Output HIGH Voltage VCC=Min., IOH=-24 mA 2.4 3.3 VOL Output LOW Voltage VCC=Min., IOL=24 mA V 0.3 0.55 V Capacitance (TA = +25C, f = 1.0 MHz) Parameter Description[10] Typ. Max. Unit CIN Input Capacitance VIN = 0V Test Conditions 4.5 6.0 pF COUT Output Capacitance VOUT = 0V 5.5 8.0 pF Notes: 5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 6. Typical values are at VCC=5.0V, +25C ambient. 7. Tested at TA= +25C. 8. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 9. Duration of the condition cannot exceed one second. 10. This parameter is measured at characterization but not tested. 5 \ CY74FCT16652T CY74FCT162652T Power Supply Characteristics Param. Test Conditions[11] Description VIN<0.2V VIN>VCC-0.2V Min. Typ.[12] Max. Unit -- 5 500 A -- 0.5 1.5 mA ICC Quiescent Power Supply Current VCC=Max. ICC Quiescent Power Supply Current TTL Inputs HIGH VCC = Max. VIN=3.4V[13] ICCD Dynamic Power Supply Current[14] VCC=Max. Outputs Open OEAB=OEAB=GND One Input Toggling 50% Duty Cycle VIN=VCC or VIN=GND -- 75 120 A/ MHz IC Total Power Supply Current[15] VCC=Max. Outputs Open fo=10 MHz (CLKBA) 50% Duty Cycle OEAB=OEBA=GND One-Bit Toggling f1=5 MHz 50% Duty Cycle VIN=VCC or VIN=GND -- 0.8 1.7 mA VIN=3.4V or VIN=GND -- 1.3 3.2 mA VIN=VCC or VIN=GND -- 3.8 6.5[16] mA VIN=3.4V or VIN=GND -- 8.3 20.0[16] mA VCC=Max. Outputs Open fo=10 MHz (CLKBA) 50% Duty Cycle OEAB=OEBA=GND Sixteen Bits Toggling f1=2.5 MHz 50% Duty Cycle Notes: 11. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 12. Typical values are at VCC=5.0V +25 ambient. 13. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND. 14. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. = IQUIESCENT + IINPUTS + IDYNAMIC 15. IC IC = I CC+ICCDHN T+ICCD(f0/2 + f 1N 1) ICC = Quiescent Current with CMOS input levels ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) DH = Duty Cycle for TTL inputs HIGH NT = Number of TTL inputs at DH ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) f0 = Clock frequency for registered devices, otherwise zero f1 = Input signal frequency N1 = Number of inputs changing at f1 All currents are in milliamps and all frequencies are in megahertz. 16. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6 \ CY74FCT16652T CY74FCT162652T Switching Characteristics Over the Operating Range[17] CY74FCT16652T CY74FCT162652T Parameter Description CY74FCT16652AT CY74FCT162652AT Min. Max. Min. Max. Unit Fig. No.[18] tPLH tPHL Propagation Delay Bus to Bus 1.5 9.0 1.5 6.3 ns 1, 3 tPZH tPHL Output Enable Time OEAB or OEBA to Bus 1.5 14.0 1.5 9.8 ns 1, 7, 8 tPHZ tPLZ Output Disable Time OEAB or OEBA to Bus 1.5 9.0 1.5 6.3 ns 1, 7, 8 tPLH tPHL Propagation Delay Clock to Bus 1.5 9.0 1.5 6.3 ns 1, 5 tPLH tPHL Propagation Delay SBA or SAB to Bus 1.5 11.0 1.5 7.7 ns 1, 5 tSU Set-Up time HIGH or LOW Bus to Clock 2.0 -- 2.0 -- ns 4 tH Hold Time HIGH or LOW Bus to Clock 1.5 -- 1.5 -- ns 4 tW Clock Pulse Width HIGH or LOW 5.0 -- 5.0 -- ns 5 tSK(O) Output Skew [19] -- 0.5 -- 0.5 ns CY74FCT16652CT CY74FCT162652CT Parameter Description CY74FCT16652ET CY74FCT162652ET Min. Max. Min. Max. Unit Fig. No.[18] tPLH tPHL Propagation Delay Bus to Bus 1.5 5.4 1.5 3.8 ns 1, 3 tPZH tPHL Output Enable Time OEAB or OEBA to Bus 1.5 7.8 1.5 4.8 ns 1, 7, 8 tPHZ tPLZ Output Disable Time OEAB or OEBA to Bus 1.5 6.3 1.5 4.0 ns 1, 7, 8 tPLH tPHL Propagation Delay Clock to Bus 1.5 5.7 1.5 3.8 ns 1, 5 tPLH tPHL Propagation Delay SBA or SAB to Bus 1.5 6.2 1.5 4.2 ns 1, 5 tSU Set-Up Time HIGH or LOW Bus to Clock 2.0 -- 2.0 -- ns 4 tH Hold Time HIGH or LOW Bus to Clock 1.5 -- 0.0 -- ns 4 tW Clock Pulse Width HIGH or LOW 5.0 -- 3.0 -- ns 5 tSK(O) Output Skew[19] -- 0.5 -- 0.5 ns Notes: 17. Minimum limits are guaranteed, but not tested, on propagation delays. 18. See "Parameter Measurement Information" in the General Information section. 19. Skew between any two outputs of the same package switching in the same direction. This parameter guaranteed by design. 7 \ CY74FCT16652T CY74FCT162652T Ordering Information CY74FCT16652 Speed (ns) 3.8 5.4 6.3 9.0 Ordering Code Package Name Package Type CY74FCT16652ETPAC Z56 56-Lead (240-Mil) TSSOP CY74FCT16652ETPVC O56 56-Lead (300-Mil) SSOP CY74FCT16652CTPAC Z56 56-Lead (240-Mil) TSSOP CY74FCT16652CTPVC O56 56-Lead (300-Mil) SSOP CY74FCT16652ATPAC Z56 56-Lead (240-Mil) TSSOP CY74FCT16652ATPVC O56 56-Lead (300-Mil) SSOP CY74FCT16652TPAC Z56 56-Lead (240-Mil) TSSOP CY74FCT16652TPVC O56 56-Lead (300-Mil) SSOP Operating Range Industrial Industrial Industrial Industrial Ordering Information CY74FCT162652 Speed (ns) 3.8 5.4 6.3 9.0 Ordering Code Package Name Package Type CY74FCT162652ETPAC Z56 56-Lead (240-Mil) TSSOP CY74FCT162652ETPVC O56 56-Lead (300-Mil) SSOP CY74FCT162652CTPAC Z56 56-Lead (240-Mil) TSSOP CY74FCT162652CTPVC O56 56-Lead (300-Mil) SSOP CY74FCT162652ATPAC Z56 56-Lead (240-Mil) TSSOP CY74FCT162652ATPVC O56 56-Lead (300-Mil) SSOP CY74FCT162652TPAC Z56 56-Lead (240-Mil) TSSOP CY74FCT162652TPVC O56 56-Lead (300-Mil) SSOP Document #: 38-00384-C 8 Operating Range Industrial Industrial Industrial Industrial \ CY74FCT16652T CY74FCT162652T Package Diagrams 56-Lead Shrunk Small Outline Package O56 56-Lead Thin Shrunk Small Outline Package Z56 (c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.