16-Bit Registered Transceiver
f
ax id: 7044
CY74FCT16652T
CY74FCT162652T
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Jul
y
1994 - Revision October 30
,
1997
2
652T
Features
• Low pow er, pin- com pati ble rep lacement for ABT
functions
• FCT-E speed at 3.8 ns
• Power-off disable outputs permits live insertion
• Edge-rate control cir cuit ry for signif icant ly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6 -mil pit ch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of −40°C to +85°C
•V
CC = 5V ± 10%
CY74FCT16652T Features:
• 64 mA sink current, 32 mA source current
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,
TA = 25°C
CY74FCT162652T Features:
• Balanced 24 mA output dri vers
• Red uced system switching noise
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,
TA= 25° C
Functional Descripti on
These 16-bit, high-speed, low-power, registered transceivers
that are organized as two independent 8-bit bus transceivers
with three-stat e D-type register s and control circui try arran ged
fo r mul tipl exed tra nsmissi on of data dir ectl y from the i nput b us
or from the internal storage registers. OEAB and OEBA control
pins ar e provid ed to contro l the t ransceiv er func tions. SAB and
SBA control pins are provided to select either real-time or
stored data transfer.
Data on the A or B data bus, or both, can be stored in the
internal D flip-flops by LOW-to-HIGH transitions at the appro-
priate clock pins (CLKAB or CLKBA), reg ardless of the select
or enab le contr ol pins . When SAB and SBA a re in the real-time
tran sfer mode, it i s also poss ible t o store d ata withou t using t he
internal D-type flip-flops by simultaneously enabling OEAB
and OEBA. In this configuration, each output reinforces its
input . Thus, when all ot her dat a sources t o the two se ts of bus
lines are at high impedance, each set of bus lines will remain
at its last state. The output buffers are designed with a
power-off disable feature that allows live inser tion of boards.
The CY74FCT16652T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162652T has 24-mA balanced output drivers
with current-limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162652T is ideal for driving transmission lines.
TO7 OTHER CHANNELS
1OEAB
C
D
1A1
1OEBA
1CLKBA
1CLKAB
1SBA
BREG
C
D
AREG
1B1
1SAB
FCT16652-1
2OEAB
2SAB
2OEBA
2CLKBA
2CLKAB
2SBA
2B1
2A1
C
D
BREG
C
D
AREG
TO 7 OTHER CHANNELS FCT16652-2
Logic Block Diagrams
CY74FCT16652T
CY74FCT162652T
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Pin Configuration
SSOP/TSSOP
Top View
FCT16652–1
GND
1OEAB
1CLKAB
1SAB
1A1
1A2
1CLKBA
1SBA
1B1
1OEBA
GND
GND
VCC
1A3
VCC
GND
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
GND
2A5
2A6
VCC
2A7
2A8
2SAB
2CLKAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
2OEAB
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2SBA
2CLKBA
2OEBA
FCT16652-3
Pin Description
Name Description
AData Regi ster A Inputs
Data Regi ster B Outputs
BData Regi ster B Inputs
Data Regi ster A Outputs
CLKAB, CLKBA Clock Pulse In puts
SAB, SBA Output Data Source Select Input s
OEAB, OEBA Output Enable Inputs
CY74FCT16652T
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Function Table[1]
Inputs Data I/O [2]
Operation or FunctionOEAB OEBA CLKAB CLKBA SAB SBA A B
L
LH
HH or L H or L X
XX
XInput Input Isolation
Store A and B Data
X
HH
HH or L X
X[3] X
XInput
Input Unspecified[2]
Output Stor e A, Hol d B
Store A in Both Regis ter s
L
LX
LH or L X
XX
X[3] Unspecified[2] Input
Input Hold A, Store B
Store B in both Registers
L
L
L
L
X
X
X
H or L
X
X
L
H
Output Input Re a l T im e B Da ta to A
Bus
Stored B Data to A Bus
H
H
H
H
X
H or L
X
X
L
H
X
X
Input Output Rea l T ime A Da ta to B
Bus
Stored A Data to B Bus
H L H or L H or L H H Output Output Stor ed A Data t o B Bus
and
Stored B Data to A Bus
Notes:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
=LOW-to-HIGH Transition
2. The data output functions may be enabled or disabled by various signals at the OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at
the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
3. Select control=L; clocks can occur simultaneously.
Select control=H; clocks must be staggered to load both registers.
CY74FCT16652T
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Maximum Ratings[4]
(Above which the useful life may be i mpaired. For use r gui de-
li nes, not tested.)
Sto ra g e Temp e ra tur e ......... ..... .... ...Co m ’ l −55°C to +125°C
Ambient Temperature with
Power Applied.................................Com’l −55°C to +125°C
DC Input Voltage.................................................−0.5V to +7.0V
DC Output Voltage..............................................−0.5V to +7.0V
DC Output Current
(Maximum Sink Current/Pin)...........................−60 to +120 mA
Power Dissipation.......................................................... 1.0W
Static Discharge Voltage ...........................................>2001V
(per MIL- STD-883, Method 3015)
Note:
4. Stresses greater than those listed under Maximum Ratings may cause permanent damage to the de vice. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
BUS BBUS A
OEAB
LOEBA
LCLKAB
XSAB
X
BUS BBUS A
OEAB
X
L
L
OEBA
H
X
H
CLKAB
X
SAB
X
X
X
SBA
X
X
X
BUS BBUS A
OEAB
HOEBA
LSAB
LSBA
X
BUS ABUS A
OEAB
HOEBA
LSAB
HSBA
H
Real-Time Transf er
BusB to BusA Real-Time Transfer
BusA to BusB
Storage from
A and/orB TransferStored Data
to A and/orB
CLKBA
XCLKAB
XCLKBA
X
SBA
L
CLKBA
XCLKAB
HorL CLKBA
HorL
Operating Range
Range Ambient
Temperature VCC
Industrial −40°C to +85°C 5V ± 10%
CY74FCT16652T
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DC Electrical Characteristics Over the Operating Range
Parameter Description Test Conditi ons [5] Min. Typ.[6] Max. Unit
VIH Input HIGH Voltage Guaranteed Logic HIGH Level 2.0 V
VIL Input LO W Volta ge Guaranteed Log ic LOW Lev el 0.8 V
VHInput Hysteresis 100 mV
VIK Input Clamp Diode Voltag e VCC=Min ., IIN=−18 mA −0.7 −1.2 V
IIH Input HIGH Current VCC=Max., VI=VCC ±1µA
IIL Input LO W Cur rent VCC=Max., VI=GND ±1µA
IOZH High Impedance Output
Curre nt
(Three-State Output pins)
VCC=Max., VOUT=2.7V ±1µA
IOZL High Impedance Output
Curre nt
(Three-State Output pins)
VCC=Max., VOUT=0.5V ±1µA
IOS Short Circuit Current[8] VCC=Max., VOUT=GND −80 −140 −200 mA
IOOutput Drive Current[8] VCC=Max., VOUT=2.5V −50 −180 mA
IOFF Power-Off Disable VCC=0V, VOUT≤4.5V[7] ±1µA
Output D rive Characteristics for CY74FCT16652T
Parameter Description Test Conditions[5] Min. Typ.[6] Max. Unit
VOH Output HIGH Voltage VCC=M in ., IOH=−3 m A 2.5 3.5 V
VCC=M in ., IOH=−15 mA 2.4 3.5
VCC=M in ., IOH=−32 mA 2.0 3.0
VOL Ou tp ut LOW Voltag e VCC=M in ., IOL=64 m A 0.2 0.55 V
Output D rive Characteristics for CY74FCT162652T
Parameter Description Test Conditi ons [5] Min. Typ.[6] Max. Unit
IODL Output LOW Current[8] VCC=5V, VIN=VIH or VIL, VOUT=1.5V 60 115 150 mA
IODH Output HIGH Current[8] VCC=5V, VIN=VIH or VIL, VOUT=1.5V −60 −115 −150 mA
VOH Output HIGH Voltage VCC=M i n ., IOH=−24 m A 2.4 3.3 V
VOL Ou tp ut LOW Voltag e VCC=M i n ., IOL=24 mA 0.3 0.55 V
Capacitance (TA = +25°C , f = 1.0 MHz)
Parameter Description[10] Test Conditi ons Typ. Max. Unit
CIN Input Capacitance VIN = 0 V 4.5 6.0 pF
COUT Output Capaci tance VOUT = 0V 5.5 8.0 pF
Notes:
5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
6. Typical values are at VCC=5.0V, +25°C ambient.
7. Tested at TA= +25°C.
8. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
9. Duration of the condition cannot exceed one second.
10. This parameter is measured at characterization but not tested.
CY74FCT16652T
CY74FCT162652T
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Power Supply Characteri stic s
Param. Description Test Conditions[11] Min. Typ.[12] Max. Unit
ICC Quiescent Power Supply
Current VCC=Max. VIN<0.2V
VIN>VCC−0.2V — 5 500 µA
∆ICC Quiescent Power Supply
Current
TTL Inputs HIGH
VCC = Max. VIN=3.4V[13] —0.5 1.5 mA
ICCD Dynamic Power Supply
Current[14] VCC=Max.
Out puts Open
OEAB=OEAB=GND
One Input Toggling
50% Duty Cycle
VIN=VCC or
VIN=GND —75 120 µA/
MHz
ICTotal P ower Supply Current[15] VCC=Max.
Out puts Open
fo=10 MHz (CLKBA)
50% Duty Cycle
OEAB=OEBA=GND
One-Bit Toggling
f1=5 MHz
50% Duty Cycle
VIN=VCC or
VIN=GND —0.8 1.7 mA
VIN=3 .4V o r
VIN=GND —1.3 3.2 mA
VCC=Max.
Out puts Open
fo=10 MHz (CLKBA)
50% Duty Cycle
OEAB=OEBA=GND
Sixt een Bits Togglin g
f1=2.5 MHz
50% Duty Cycle
VIN=VCC or
VIN=GND —3.8 6.5[16] mA
VIN=3 .4V o r
VIN=GND —8.3 20.0[16] mA
Notes:
11. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
12. Typical values are at VCC=5.0V +25° ambient.
13. Per TTL driven input (VIN=3.4V); all other inputs at VCC or G ND.
14. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
15. IC=I
QUIESCENT + IINPUTS + IDYNAMIC
IC=I
CC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
DH= Duty Cycle for TTL inputs HIGH
NT= Number of TTL inputs at DH
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
f0= Clock frequency for registered devices, otherwise zero
f1= Input signal frequency
N1= Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
16. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
CY74FCT16652T
CY74FCT162652T
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Swi tch i ng C h ara cter i sti cs Over the Operating Range[17]
Parameter Description
CY74FCT16652T
CY74FCT162652T CY74FCT16652AT
CY74FCT162652AT
UnitMin. Max. Min. Max. Fig. No.[18]
tPLH
tPHL Propagation Delay
Bus to Bus 1.5 9.0 1.5 6.3 ns 1, 3
tPZH
tPHL Output Enabl e Time
OEAB or OEBA to Bus 1.5 14.0 1.5 9.8 ns 1, 7, 8
tPHZ
tPLZ Output Disab le Ti m e
OEAB or OEBA to Bus 1.5 9.0 1.5 6.3 ns 1, 7, 8
tPLH
tPHL Propagati on Delay
Clo ck to B us 1.5 9.0 1.5 6.3 ns 1, 5
tPLH
tPHL Propagati on Delay
SBA or SAB to Bus 1.5 11.0 1.5 7.7 ns 1, 5
tSU Set-Up time
HIGH or LOW
Bus to Clock
2.0 —2.0 —ns 4
tHHold Time
HIGH or LOW
Bus to Clock
1.5 —1.5 —ns 4
tWCl o ck P ulse Width
HIGH or LOW 5.0 —5.0 —ns 5
tSK(O) Out put Skew[19] —0.5 —0.5 ns
Parameter Description
CY74FCT16652CT
CY74FCT162652CT CY74FCT16652ET
CY74FCT162652ET
UnitMin. Max. Min. Max. Fig. No.[18]
tPLH
tPHL Propagation Delay
Bus to Bus 1.5 5.4 1.5 3.8 ns 1, 3
tPZH
tPHL Output Enable Time
OEAB or OEBA to Bus 1.5 7.8 1.5 4.8 ns 1, 7, 8
tPHZ
tPLZ Output Disable Tim e
OEAB or OEBA to Bus 1.5 6.3 1.5 4.0 ns 1, 7, 8
tPLH
tPHL Propagati on Delay
Clock to Bus 1.5 5.7 1.5 3.8 ns 1, 5
tPLH
tPHL Propagati on Delay
SBA or SAB to Bus 1.5 6.2 1.5 4.2 ns 1, 5
tSU Set-Up Time
HIGH or LOW
Bus to Clock
2.0 —2.0 —ns 4
tHHold Ti me
HIGH or LOW
Bus to Clock
1.5 —0.0 —ns 4
tWClock Pulse Width
HIGH or LOW 5.0 —3.0 —ns 5
tSK(O) Out put Skew[19] —0.5 —0.5 ns
Notes:
17. Minimum limits are guaranteed, but not tested, on propagation delays.
18. See “Parameter Measurement Information” in the General Information section.
19. Skew between any two outputs of the same package switching in the same direction. This parameter guaranteed by design.
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CY74FCT162652T
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Document #: 38-00384-C
Orde ring Information CY74FCT16652
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
3.8 CY74FCT16652ETPAC Z56 56-Lead (240-Mil ) TSSOP Industrial
CY74FCT16652ETPVC O56 56-Lead (300-Mi l) SSOP
5.4 CY74FCT16652CTPAC Z56 56-Lead (24 0-Mil) TSSOP Industrial
CY74FCT16652CTPVC O56 56-Lead (300-Mi l) SSOP
6.3 CY74FCT16652ATPA C Z56 56-Lead (24 0-Mil) TSSOP Industrial
CY74FCT16652ATPVC O56 56-Lead (300-Mi l) SSOP
9.0 CY74FCT16652TPAC Z56 56-Lead (24 0-Mil) TSSOP Industrial
CY74FCT16652TPVC O56 56-Lead (300-Mil) SSOP
Orde ring Information CY74FCT162652
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
3.8 CY74FCT162652ETPAC Z56 56-Lead (24 0-Mil) TSSOP Industrial
CY74FCT162652ETPVC O56 56-Lead (300-Mil) SSOP
5.4 CY74FCT162652CTPAC Z56 56-Lead (24 0-Mil) TSSOP Industrial
CY74FCT162652CTPVC O56 56-Lead (300-Mil) SSOP
6.3 CY74FCT162652ATPAC Z56 56-Lead (24 0-Mil) TSSOP Industrial
CY74FCT162652ATPVC O56 56-Lead (300-Mi l) SSOP
9.0 CY74FCT162652TPAC Z56 56-Lead (240-Mil) TSSOP Industrial
CY74FCT162652TPVC O56 56-Lead (300-Mil) SSOP
CY74FCT16652T
CY74FCT162652T
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© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change wi thout notice. Cypress Semiconductor Corporation assumes no res ponsibility for the use
of any circui try other than circuitry embodied in a Cypress Semiconduc tor produc t. Nor does it conv ey or imply any license under patent or other rights. Cypress Semi conductor does not author ize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in si gnificant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Di ag ra ms
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package Z56
