CM3132 - California Micro Devices

10/13/04 430 N. McCarthy Blvd., Milpitas, CA 95035-51 12 ●Tel: 408.263.3214 ●Fax: 408.263.7846 ●www.calmicro.com 1

CM3132

PRELIMINARY

Triple Linear Voltage Regulator for DDR-I Memory and CPU

Features

• Fully integrated power solution for a CPU/SOC

core and DDR-I memory ICs

• Lowest system cost and smallest footprint with just

three external output capacitors

• Three linear regulators for VCORE (1.5A), VDDQ

(1.5A), and VTT (0.5A, source-sink)

•V

DDQ = 2.5V, VTT = VDDQ/2 ±25mV

•V

CORE is adjustable, with a default output of 1.5V

• Over-temperature and reverse current protection

• Overcurrent protection for all regulators

• PSOP-8 package with integrated heat spreader

• Lead-free version available

Applications

• Core CPU and DDR-I memory power for:

− Set Top Boxes, DVD Players, Games

− Digital TVs, Flat Panel Displays

− Printers, Digital Projectors

− Embedded systems

− Communications systems

Product Description

The CM3132 provides an integrated power solution for a

CPU core and DDR-I memory for consumer and other

embedded applications. It features three independent linear

regulators for V

CORE

, V

DDQ

and V

supply regulation. The

default voltage for V

CORE

is 1.5V. The SENSE_CORE pin

can be tied to GND for the default voltage, or through a

resistor divider for setting the CPU core in the range 1.2V to

1.8V. V

DDQ

is internally set to 2.50V and the V

voltage is

always half the V

DDQ

voltage. A capacitor should be con-

nected to each of the three outputs.

There are two enable pins, EN_CORE and EN_DDR. When

EN_CORE is set high, the CORE regulator is disabled.

When EN_DDR is set high, the two DDR regulators are dis-

abled to minimize overall system power dissipation when

memory is in standby mode. These two enable pins allow

power sequencing of the DDR and CORE regulator blocks

independently.

The CM3132 is available in a PSOP-8 package that has

excellent thermal dissipation.

It is available with optional

lead-free finishing.

REF

SENSE_CORE

=1.25V

DDQ

= 2.5V

DDQ

REGULATOR

CORE

REGULATOR

CORE

EN_DDR

EN_CORE

GND

DDQ

DDR

MEMORY

REF

=1.25V

CORE

CPU

CORE

+ I/O

VCC

Enable DDR

Memory #

Enable CORE#

2.8V to 3.3V

REF

SENSE_CORE

DDQ

REGULATOR

CORE

REGULATOR

CORE

EN_DDR

EN_CORE

GND

Typical Application Circuit Circuit Schematic

2430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ●Tel: 408.263.3214 ●Fax: 408.263.7846 ●www.calmicro.com 10/13/04

CM3132

PRELIMINARY

Ordering Information

Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.

PACKAGE / PINOUT DIAGRAM

Note: This drawing is not to scale.

8-Lead PSOP

VCORE

VCC

VDDQ

VTT

SENSE_CORE

GND

EN_CORE

EN_DDR

TOP VIEW

PIN DESCRIPTIONS

PSOP-8

NAME DESCRIPTIONLEAD

CORE VCORE output.

CC Input supply.

DDQ VDDQ output.

TT VTT output for termination resistors or VREF

5 EN_DDR Enable DDR power. Active low input.

6 EN_CORE Enable VCORE. Active low input.

7 GND Ground reference.

8 SENSE_CORE Sense input. Adjusts VCORE output voltage using external resistor divider. When tied to

GND, VCORE = 1.5V.

PAD GND Tied to ground reference.

PART NUMBERING INFORMATION

Leads Package

Standard Finish Lead-free Finish

Ordering Part

Number1Part Marking

Ordering Part

Number1Part Marking

8 PSOP-8 CM3132-02SB CM3132 02SB CM3132-02SH CM3132 02SH

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CM3132

PRELIMINARY

Specifications

ABSOLUTE MAXIMUM RATINGS

PARAMETER RATING UNITS

ESD (Human Body Model) ±2000 V

Pin Voltages

VCC

EN_CORE, EN_DDR, SENSE_CORE

VDDQ, VTT

[GND - 0.6] to [+6.5]

[GND - 0.6] to [VCC + 0.6]

Storage Temperature Range -40 to +150 °C

Operating Temperature Range

Ambient

Junction

0 to +85

0 to +125

°C

STANDARD OPERATING CONDITIONS

PARAMETER RATING UNITS

Ambient Operating Temperature Range 0 to +85 °C

1. VDDQ Regulator

DDR-I Supply Voltage VCC [VDDQ + 0.3] to 3.6 V

Load Current 0 to 1500 mA

CCC, CDDQ 10, 10 µF

2. VTT Regulator

DDR-I Supply Voltage VDDQ 2.3 to 2.8 V

DDR-I Load Current 0 to ±500 mA

CTT 47 µF

3. VCORE Regulator

Core Supply Voltage VCC [VDDQ or VCORE + 0.3] to 3.6 V

DDR-I Load Current 0 to 1500 mA

CCORE 10 µF

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CM3132

PRELIMINARY

Specifications (cont’d)

ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE1)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

General Parameters

TOVER Shutdown Junction Temperature - 150 - °C

THYST Junction Temp Hysterisis IC in shutdown - 25 - °C

ICCN Normal Mode VCC Supply

Current

EN_DDR = logic "0",

EN_CORE =logic "0"

400 800 µA

ICCQ Shutdown Mode VCC Supply

Current

EN_DDR = logic "1",

EN_CORE =logic "1"

210µA

ISENSE IN SENSE_CORE Input Current VSENSE_CORE=0.6V 0.1 1.0 µA

VIH EN_DDR, EN_CORE Input

High Threshold

VCORE=3.3V 2.0 V

VIL EN_DDR, EN_CORE Input

Low Threshold

VCORE=3.3V 0.4 V

UVLO Under Voltage Lock-Out IDDQ = 10mA 1.8 V

tRISE VDDQ, VCORE Rise TIme VCC = 3.3V, CLOAD = 10µF0.5ms

VDDQ Regulator Parameters

VCC MIN Input Voltage VDDQ = 2.5V, IDDQ = 1.5A, Note 2 2.80 V

VDDQ DEF Default Output Voltage IDDQ = 0.01A, 2.8V ≤ VCC ≤ 3.6V,

Note 2

2.45 2.50 2.55 V

VDDQ LD Load Regulation TA = 25°C, VCC = 3.3V,

0.01A ≤ IDDQ ≤ 1.5A, Note 2

--2.5%

VDDQ LINE Line Regulation TA = 25°C, IDDQ = 0.01A,

2.8V ≤ VCC ≤ 3.6V, Note 2

-1.0 - 1.0 %

eN DDQ Output Noise Voltage BW = 10Hz - 100kHz, CDDQ = 10µF49µVrms

IDDQ LIM Current Limit Note 2 1.7 2.0 A

IDDQ SC Short Circuit Current VDDQ < 0.3V 0.5 A

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CM3132

PRELIMINARY

Note 1: All parameters specified at TA = 0°C to +85°C unless otherwise noted.

Note 2: Note that the IDDQ current specified is the load current output from the VDDQ pin. VDDQ also supplies current internally to the

VTT regulator when it is sourcing current. The maximum source current can be up to 0.5A.The maximum total current from

the VDDQ regulator is the external VDDQ current IDDQ added to the maximum VTT sourcing current ITT. All load currents are

specified as such, but the VDDQ current limit is specified at a current just above the total maximum current.

Note 3: VCORE regulator only. Refer to VDDQ regulator parameters for VDDQ regulator.

Note 4: VCORE = 1.15V X (1 + )

Table 1: Truth Table for CM3132

VTT Regulator Parameters

VTT Output Voltage Range VDDQ = 2.5V, ITT = 0.01A,

IDDQ = 0A

1.20 1.25 1.30 V

VTT REF Output Voltage Range VCC = 0V, VDDQ = 2.500V,

ITT = 0.01A

1.225 1.250 1.275 V

VTT LD Load Regulation TA = 25°C, VDDQ = 2.5V,

0.01A ≤ ITT ≤ ±0.5A

-1.0 - 1.0 %

eN TT Output Noise Voltage BW = 10Hz - 100kHz, CTT = 10µF51µVrms

ITT LIM Current Limit 0.6 0.8 A

ITT SC Short Circuit Current VTT < 0.7V 0.3 A

VCORE Regulator Parameters

VCC MIN Input Voltage VCORE = 1.5V, ICORE = 1.5A,

SENSE_CORE = 0V, Note 3

2.2 V

VCORE DEF Default Output Voltage Range VCC = 3.3V, ICORE = 0.01A,

SENSE_CORE = 0V

1.45 1.50 1.55 V

VCORE ADJ Adjustable Output Voltage

Range

VCC = 3.3V, SENSE_CORE from

resistors R3 & R4, Note 4

1.2 1.8 V

VCORE LD Load Regulation TA = 25°C, VCC = 3.3V,

0.01A ≤ ICORE ≤ ±1.5

--2.5%

VCORE LINE Line Regulation TA = 25°C, 2.8V ≤ VCC ≤ 3.6V,

ICORE = 0.01A

-1.0 - 1.0 %

eN CORE Output Noise Voltage BW = 10Hz - 100kHz, CCORE = 47µF59µVrms

ICORE LIM Current Limit 1.7 2.0 A

ICORE SC Short Circuit Current VCORE < 0.3V 0.5 A

VCC(1) EN_DDR VDDQ OUT VTT OUT

2.8V to 3.6V Low VDDQ VDDQ / 2

X High 0V 0V

ELECTRICAL OPERATING CHARACTERISTICS (CONT’D) (SEE NOTE1)

--------

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CM3132

PRELIMINARY

Performance Information

Power Supply Ripple Rejection

CCC = 10µF, VCC = 3.3V, ILOAD = 50mA, PSRR measured with 50mV pk-pk sin wave on VCC.

Figure 1. VCORE PSRR (VCORE = 1.5V)

Figure 2. VDDQ PSRR (VDDQ = 2.5V)

10 100 1000 10000 100000

Frequency (Hz)

PSRR (dB)

10 100 1000 10000 100000

Frequency (Hz)

PSRR (dB)

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CM3132

PRELIMINARY

Figure 3. VTT PSRR (VTT = 1.25V)

10 100 1000 10000 100000

Frequency (Hz)

PSRR (dB)

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CM3132

PRELIMINARY

Performance Information (cont’d)

Typical Thermal Characteristics

The overall junction to ambient thermal resistance

(θJA) for device power dissipation (PD) consists prima-

rily of two paths in series. The first path is the junction

to the case (θJC) which is defined by the package style,

and the second path is case to ambient (θCA) thermal

resistance which is dependent on board layout. The

final operating junction temperature for any set of con-

ditions can be estimated by the following thermal equa-

tion:

TJUNC = TAMB + PD ( θJC ) + PD ( θCA )

= TAMB + PD ( θJA)

When a CM3132-02SB (PSOP-8) is mounted on a

double-sided printed circuit board with two square

inches of copper allocated for "heat spreading," the

resulting θJA is 40°C/W. Based on the over tempera-

ture limit of 150° C with an ambient of 70°C, the avail-

able power of this package will be:

PD = = 2W

PCB Layout Considerations

The CM3132-02SB/SH has a heat spreader attached

to the bottom of the PSOP-8 package in order for heat

to be transferred more easily from the package to the

PCB. The heat spreader is a copper pad of dimensions

just smaller than the package itself. By positioning the

matching pad on the PCB top layer to connect to the

spreader during manufacturing, the heat will be trans-

ferred between the two pads. The drawing below

shows the recommended PCB layout. Note that there

are six vias on either side to allow the heat to dissipate

into the ground and power planes on the inner layers of

the PCB. Vias can be placed underneath the chip, but

this can cause blockage of the solder. The ground and

power planes should be at least 2 sq in. of copper by

the vias. It also helps dissipation if the chip is posi-

tioned away from the edge of the PCB, and not near

other heat-dissipating devices. A good thermal link

from the PCB pad to the rest of the PCB will assure the

best heat transfer from the CM3132 package to ambi-

ent, θJA, of around 40°C/W.

Figure 4. Recommended Heat Sink PCB Layout

150°C70°C–

40°C/ W

---------------------------------------

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CM3132

PRELIMINARY

Application Information

Other Applications

The CM3132 can be used without any external resis-

tors if a core voltage of 1.5V is required, the

SENSE_CORE pin is connected to GND.

In applications where a reference voltage (VREF) is

required, the VTT pin can be used. The VTT output pin

has an error relative to VDDQ/2 of up to ±25mV, which

is well within most DDR system specs of ±50mV. This

is because the VTT output internally tracks the VDDQ

output very closely due to the matched on-chip resis-

tors R that tap down from the VDDQ rail, and the low

offset voltage of the VTT regulator. It is recommended

that the VREF trace be connected directly to the VTT

pin, as shown in Figure 5, to eliminate noise and ripple

on the VTT trace caused by current switching.

Figure 5. Minimal cost solution for CM3132 supplying DDR memory and core CPU.

REF

SENSE_CORE

=1.25V

DDQ

= 2.5V

DDQ

REGULATOR

CORE

REGULATOR

CORE

=1.5V

EN_DDR

EN_CORE

GND

DDQ

REF

=1.25V

CORE

VCC

Enable DDR

Memory

Enable CORE

2.8V to 3.3V

DDR-I

MEMORY

CPU

CORE

+ I/O

10 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ●Tel: 408.263.3214 ●Fax: 408.263.7846 ●www.calmicro.com 10/13/04

CM3132

PRELIMINARY

Application Information (cont’d)

Figure 6. Power Dissipation Calculations

Figure 7. Power Derating Table

REF

SENSE_CORE

DDQ

REGULATOR

CORE

REGULATOR

EN_DDR

EN_CORE

GND

DDQ

REF

=1.25V, 0.5A MAX,

CORE

Enable DDR

Memory

Enable CORE

VCC

DDR-I

MEMORY

CPU

CORE

+ I/O

0.1A CONTINUOUS

CORE

=1.5V, 1A MAX,

1A CONTINUOUS

DDQ

=2.5V, 1A MAX,

1A CONTINUOUS

With 3.3VCC @ 1A (VDDQ), 0.1A (VTT), 1A (VCORE),

PD = (3.3-2.5) * 1.05 + (2.5-1.25) * 0.1 + (3.3-1.5) * 1 = 0.84 + 0.125 + 1.8 = 2.765W

With 3.0VCC @ 1A (VDDQ), 0.1A (VTT), 1A (VCORE),

PD = (3.0-2.5) * 1.05 + (2.5-1.25) * 0.1 + (3.0-1.5) * 1 = 0.525 + 0.125 + 1.5 = 2.15W

With 2.8VCC @ 1A (VDDQ), 0.1A (VTT), 1A (VCORE),

PD = (2.8-2.5) * 1.05 + (2.5-1.25) * 0.1 + (2.8-1.5) * 1 = 0.315 + 0.125 + 1.3 = 1.74W

1 PSOP-8 IC drives 1-DIMM single channel DDR-I and CPU Core VCORE rail

CM3132-02

PSOP-8

= (Vcc-2.5)*Iddq + (2.5-1.25)*0.1 + (Vcc-Vcore)*Icore

- (Vcc-2.5)*Iddq - 0.125 = (Vcc-Vcore)*Icore

Icore = [P

- (Vcc-2.5)*Iddq - 0.125] / (Vcc-Vcore)

Derating (degC/W) 40 40 40 40 40 40 40 40 40

Ambient (degC) 85 85 85 60 60 60 40 40 40

Max Power (W) 1.6 1.6 1.6 2.3 2.3 2.3 2.8 2.8 2.8

Vcc (V) 3.3 3.0 2.8 3.3 3.0 2.8 3.3 3.0 2.8

Min Vcore (V) 1.5 1.5 1.5 1.5 1.4 1.0 1.5 1.2 1.1

Max Iddq (A) 1.0 0.8 0.5 1.0 1.0 1.0 1.0 1.0 1.0

Max Icore (A) 0.4 0.7 1.0 0.7 1.0 1.0 1.0 1.0 1.4

Derating (degC/W) 60 60 60 60 60 60 60 60 60

Ambient (degC) 85 85 85 60 60 60 40 40 40

Max Power (W) 1.1 1.1 1.1 1.5 1.5 1.5 1.8 1.8 1.8

Vcc (V) 3.3 3.0 2.8 3.3 3.0 2.8 3.3 3.0 2.8

Min Vcore (V) 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.4

Max Iddq (A) 0.3 0.5 0.6 1.0 0.7 0.5 0.5 0.7 1.0

Max Icore (A) 0.4 0.5 0.6 0.3 0.7 0.9 0.7 1.0 1.0

Derating (degC/W) 80 80 80 80 80 80 80 80 80

Ambient (degC) 85 85 85 60 60 60 40 40 40

Max Power (W) 0.8 0.8 0.8 1.1 1.1 1.1 1.4 1.4 1.4

Vcc (V) 3.3 3.0 2.8 3.3 3.0 2.8 3.3 3.0 2.8

Min Vcore (V) 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5

Max Iddq (A) 0.3 0.3 0.3 0.5 0.5 0.5 0.5 0.7 0.5

Max Icore (A) 0.2 0.4 0.5 0.3 0.5 0.7 0.5 0.6 0.8

TJUNC =T

AMB +P

D*(θJA)

PD=(T

AMB -T

JUNC )/(θJA)

θJA=40oC/W

θJA=60oC/W

θJA=80oC/W

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CM3132

PRELIMINARY

Mechanical Details

PSOP-8 Mechanical Specifications

Dimensions for CM3132 devices packaged in an 8-

lead PSOP package with a heatspreader are shown

below.

* This is an approximate number which may vary.

** Centered on package centerline.

Package Dimensions for PSOP-8

PACKAGE DIMENSIONS

Package PSOP-8

Leads 8

Dimensions Millimeters Inches

Min Max Min Max

A1.30 1.62 0.051 0.064

A10.03 0.10 0.001 0.004

B0.33 0.51 0.013 0.020

C0.18 0.25 0.007 0.010

D4.83 5.00 0.190 0.197

E3.81 3.99 0.150 0.157

e1.02 1.52 0.040 0.060

H5.79 6.20 0.228 0.244

L0.41 1.27 0.016 0.050

x** 3.30 3.81 0.130 0.150

y** 2.29 2.79 0.090 0.110

# per tube 100 pieces*

# per tape

and reel

2500 pieces

Controlling dimension: inches

Mechanical Package Diagrams

TOP VIEW

END VIEW

SEATING

PLANE

SIDE VIEW

1234

8765

Pin 1

BOTTOM VIEW

1234

8765

y/2

x/2

Marking

Heat Slug