ATMEGA328P-20MU - Atmel Corporation

Features

•High Pe rformance, Low Power AVR® 8-Bit Microcontroller

•Advanced RISC Architecture

– 131 Po we rful Instructions – Most Single Clock Cy cle Execu tion

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Thro ug hp ut at 20 MHz

– On-chip 2-cycle Multiplier

•High Endurance Non-volatile Memory Segments

– 4/8/16/32K Bytes of In-System Self-Programmable Flash progam memory

(ATmega48P/88P/168P/328P)

– 256/512/512/1K Bytes EEPROM (ATmega48P/88P/168P/328P)

– 512/1K/1K/2K Bytes Internal SRAM (ATmega48P/88P/168P/328P)

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C(1)

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Programming Lock for Software Security

•Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Six PWM Channels

– 8-channel 10-bit ADC in TQFP and QFN/MLF package

Temperature Measurement

– 6-channel 10-bit ADC in PDIP Package

Temperature Measurement

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Byte-oriented 2-wire Serial Interface (Philips I2C compatible)

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

•Special Microcontroller Features

– Power -on Reset and Pr ogrammab le Brown-out Detection

– Internal Calibrated Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, A DC Noise Reduction, Power-save, Power-down, Standby,

and Extended Standby

•I/O and Packages

– 23 Programmable I/O Lines

– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF

•Operating Voltage:

– 1.8 - 5.5V for ATmega48P/88P/168PV

– 2.7 - 5.5V for ATmega48P/88P/16 8P

– 1.8 - 5.5V for ATmega328P

•Temperature Range:

–-40

°C to 85°C

•Speed Grade:

– ATmega48P/88P/168PV: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V

– ATmega48P/88P/168P: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V

– ATmega328P: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V

•Low Power Consumption at 1 MHz, 1.8V, 25°C for ATmega48P/88P/168P:

– Active Mode: 0.3 mA

– Power-down Mode: 0.1 µA

– Power-save Mode: 0.8 µA (Including 32 kHz RTC)

8-bit

Microcontroller

with 4/8/16/32K

Bytes In-System

Programmable

Flash

ATmega48P/V

ATmega88P/V

ATmega168P/V

ATmega328P

Preliminary

Rev. 8025D–AVR–03/08

28025D–AVR–03/08

ATmega48P/88P/168P/328P

1. Pin Configurations

Figure 1-1. Pinout ATmega48P/88P/168P/328P

(PCINT19/OC2B/INT1) PD3

(PCINT20/XCK/T0) PD4

GND

VCC

GND

VCC

(PCINT6/XTAL1/TOSC1) PB6

(PCINT7/XTAL2/TOSC2) PB7

PC1 (ADC1/PCINT9)

PC0 (ADC0/PCINT8)

ADC7

GND

AREF

ADC6

AVCC

PB5 (SCK/PCINT5)

(PCINT21/OC0B/T1) PD5

(PCINT22/OC0A/AIN0) PD6

(PCINT23/AIN1) PD7

(PCINT0/CLKO/ICP1) PB0

(PCINT1/OC1A) PB1

(PCINT2/SS/OC1B) PB2

(PCINT3/OC2A/MOSI) PB3

(PCINT4/MISO) PB4

PD2 (INT0/PCINT18)

PD1 (TXD/PCINT17)

PD0 (RXD/PCINT16)

PC6 (RESET/PCINT14)

PC5 (ADC5/SCL/PCINT13)

PC4 (ADC4/SDA/PCINT12)

PC3 (ADC3/PCINT11)

PC2 (ADC2/PCINT10)

TQFP T op View

(PCINT14/RESET) PC6

(PCINT16/RXD) PD0

(PCINT17/TXD) PD1

(PCINT18/INT0) PD2

(PCINT19/OC2B/INT1) PD3

(PCINT20/XCK/T0) PD4

VCC

GND

(PCINT6/XTAL1/TOSC1) PB6

(PCINT7/XTAL2/TOSC2) PB7

(PCINT21/OC0B/T1) PD5

(PCINT22/OC0A/AIN0) PD6

(PCINT23/AIN1) PD7

(PCINT0/CLKO/ICP1) PB0

PC5 (ADC5/SCL/PCINT13)

PC4 (ADC4/SDA/PCINT12)

PC3 (ADC3/PCINT11)

PC2 (ADC2/PCINT10)

PC1 (ADC1/PCINT9)

PC0 (ADC0/PCINT8)

GND

AREF

AVCC

PB5 (SCK/PCINT5)

PB4 (MISO/PCINT4)

PB3 (MOSI/OC2A/PCINT3)

PB2 (SS/OC1B/PCINT2)

PB1 (OC1A/PCINT1)

PDIP

32 MLF Top View

(PCINT19/OC2B/INT1) PD3

(PCINT20/XCK/T0) PD4

GND

VCC

GND

VCC

(PCINT6/XTAL1/TOSC1) PB6

(PCINT7/XTAL2/TOSC2) PB7

PC1 (ADC1/PCINT

PC0 (ADC0/PCINT

ADC7

GND

AREF

ADC6

AVCC

PB5 (SCK/PCINT5

)

(PCINT21/OC0B/T1) PD5

(

PCINT22/OC0A/AIN0) PD6

(PCINT23/AIN1) PD7

(PCINT0/CLKO/ICP1) PB0

(PCINT1/OC1A) PB1

(PCINT2/SS/OC1B) PB2

(PCINT3/OC2A/MOSI) PB3

(PCINT4/MISO) PB4

PD2 (INT0/PCINT18)

PD1 (TXD/PCINT17)

PD0 (RXD/PCINT16)

PC6 (RESET/PCINT14)

PC5 (ADC5/SCL/PCINT13)

PC4 (ADC4/SDA/PCINT12)

PC3 (ADC3/PCINT11)

PC2 (ADC2/PCINT10)

NOTE: Bottom pad should be soldered to ground.

28 MLF Top View

(PCINT19/OC2B/INT1) PD3

(PCINT20/XCK/T0) PD4

VCC

GND

(PCINT6/XTAL1/TOSC1) PB6

(PCINT7/XTAL2/TOSC2) PB7

(PCINT21/OC0B/T1) PD5

(PCINT22/OC0A/AIN0) PD6

(PCINT23/AIN1) PD7

(PCINT0/CLKO/ICP1) PB0

(PCINT1/OC1A) PB1

(PCINT2/SS/OC1B) PB2

(PCINT3/OC2A/MOSI) PB3

(PCINT4/MISO) PB4

PD2 (INT0/PCINT18)

PD1 (TXD/PCINT17)

PD0 (RXD/PCINT16)

PC6 (RESET/PCINT14)

PC5 (ADC5/SCL/PCINT13)

PC4 (ADC4/SDA/PCINT12)

PC3 (ADC3/PCINT11)

PC2 (ADC2/PCINT10)

PC1 (ADC1/PCINT9)

PC0 (ADC0/PCINT8)

GND

AREF

AVCC

PB5 (SCK/PCINT5)

NOTE: Bottom pad should be soldered to ground.

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ATmega48P/88P/168P/328P

1.1 Pin Descriptions

1.1.1 VCC Digital supply voltage.

1.1.2 GND Ground.

1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/T OSC2

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. Th e Port B pins are tri-stated when a reset co ndition becomes active,

even if the clock is not running.

Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscil-

lator amplifier and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the inverting

Oscillator amplifier.

If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1

input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.

The various special features of Port B are elaborated in ”Alternate Functions of Port B” on page

83 and ”System Clock and Clock Options” on page 27.

1.1.4 Port C (PC5:0) Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

PC5..0 output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

1.1.5 PC6/RESET If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical char-

acteristics of PC6 differ fro m those of the other pins of Port C.

If the RSTDISBL Fuse is unprogrammed, PC6 is use d as a Reset input. A low level on this pin

for longer than the minimum pulse length will generate a Reset, even if the clock is not running.

The minimum pulse length is given in Table 28-3 on page 319. Shorter pu lses are not guaran-

teed to generate a Reset.

The various special features of Port C are elaborated in ”Alternate Functions of Port C” on page

86.

1.1.6 Port D (PD7:0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both hig h sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

48025D–AVR–03/08

ATmega48P/88P/168P/328P

The various special features of Port D are elaborated in ”Alternate Functions of Port D” on page

89.

1.1.7 AVCC AVCC is the supply volta ge pin for the A/D Conver ter, PC3 :0, and ADC7:6. It should be extern ally

connected to VCC, even if the ADC is not u sed. If the ADC is used, it should be conne cted to V CC

through a low-pass filter. Note that PC6..4 use digital supply voltage, V CC.

1.1.8 AREF AREF is the analog reference pin for the A/D Converter.

1.1.9 ADC7:6 (TQFP and QFN/MLF Package Only)

In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter.

These pins are powered from the analog supply and serve as 10-bit ADC channels.

1.2 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of

other AVR micr ocontr ollers m anufa ct ured o n th e same proce ss tech nolo gy. Min a nd Ma x valu es

will be available after the device is characterized.

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ATmega48P/88P/168P/328P

2. Overview The ATmega48P/88P/168P/328P is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the

ATmega48P/88P/168P/328P achieves throughputs approaching 1 MIPS per MHz allowing the

system designer to optimize power consumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

PORT C (7)PORT B (8)PORT D (8)

USART 0

8bit T/C 2

16bit T/C 18bit T/C 0 A/D Conv.

Internal

Bandgap

Analog

Comp.

SPI TWI

SRAMFlash

EEPROM

Watchdog

Oscillator

Watchdog

Timer

Oscillator

Circuits /

Clock

Generation

Power

Supervision

POR / BOD &

RESET

VCC

GND

PROGRAM

LOGIC

debugWIRE

GND

AREF

AVCC

DATA BU S

ADC[6..7]PC[0..6]PB[0..7]PD[0..7]

RESET

XTAL[1..2]

CPU

68025D–AVR–03/08

ATmega48P/88P/168P/328P

architecture is more code efficient while achiev ing throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATmega48P/88P/168P/328 P provides the following features: 4K/8K/16K/32K bytes of In-

System Programmable Flash with Read-While-Write capabilities, 256/512/512/1K bytes

EEPROM, 512/1K/1K/2K bytes SRAM, 23 general purpose I/O lines, 32 general purpose work-

ing registers, three flexible Timer/Counters with compare modes, internal and external

interrupts, a serial programmable USART, a byte-oriented 2-wire Serial Interface, an SPI serial

port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages), a programmable

Watchdog Timer with internal Oscillator, and five software selectable power saving modes. The

Idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Inter-

face, SPI port, a nd interrupt syst em to continue fu nctioning. The Powe r-down mode sav es the

rupt or hardw are reset. In Pow er-save mode , the asynchronous timer continues to run, allowing

the user to main tain a time r base while the r est of the d evice is sleepi ng. The ADC Noi se Reduc-

tion mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize

switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is

running while the re st of the devic e is sleeping . This allows very fast start-up combined with low

power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI

serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro-

gram running on the AVR core. The Boot program can use any interface to download the

application program in the Application Flash memory. Software in the Boot Flash section will

continue to run while the Application Flash section is updated, providing true Read-While-Write

operation. By combining an 8 -bit RISC CPU with In-System Self-Programmable Flash on a

monolithic chip, the Atmel ATmega48P/88P/168P/328P is a powerful microcontroller that pro-

vides a highly flexible and cost effective solution to many embedded control applications.

The ATmega48P/88P/168P/328P AVR is supported with a full suite of program and system

developmen t tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators,

In-Circuit Emulators, an d Evaluation kits.

2.2 Comparison Between ATmega48P, ATmega88P, ATmega168P, and ATmega328P

The ATmega48P, ATmega88P, ATmega168P, and ATmega328P differ only in memory sizes,

boot loader support, and interrupt vector sizes. Table 2-1 summarizes the different memory and

interrupt vector sizes for the three devices.

ATmega88P, ATmega168P, and ATmega328P support a real Read-While-Write Self-Program-

ming mechanism. There is a separate Boot Loader Section, and the SPM instruction can only

execute from there. I n ATmeg a48P, there is no Read-While- Writ e suppor t and no se pa rate Boot

Loader Section. The SPM instruction can execute from the en tire Flash.

Table 2-1. Memory Size Summary

Device Flash EEPROM RAM Interrupt Vector Size

ATmega48P 4K Bytes 256 Bytes 512 Bytes 1 instruction word/vector

ATmega88P 8K Bytes 512 Bytes 1K Bytes 1 instruction word/vector

ATmega168P 16K Bytes 512 Bytes 1K Bytes 2 instruction words/vector

ATmega328P 32K Bytes 1K Bytes 2K Bytes 2 instructions words/vector

8025D–AVR–03/08

ATmega48P/88P/168P/328P

3. Resources A comprehensive set of development tools, application notes and datasheets are available for

download on http://www.atmel.com/avr.

88025D–AVR–03/08

ATmega48P/88P/168P/328P

Note: 1.

4. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

5. About Code Examples

This documentatio n contains simple co de examples that br iefly sh ow how to u se various parts of

the device. These code examp les assume that the part specific header file is included b efore

compilation. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt ha ndlin g in C is com piler d epe nd ent. Please con firm wit h the C com piler d ocume n-

tation for more details.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

8025D–AVR–03/08

ATmega48P/88P/168P/328P

6. AVR CPU Core

6.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core

is to ensure correct program execution. The CPU must therefore be able to access memories,

perform calculations, control peripherals, and handle interrupts.

Figure 6-1. Block Diagram of the AVR Architecture

In order to maximize performance and parallelism , the AVR uses a Harvard architecture – with

separate memories and buses for progr am and data. Instructions in the program memory are

executed with a single level pipelining. While one instruction is being executed, the next instruc-

tion is pre-fetched from the program memory. This concept enables instructions to be executed

in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single

clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-

Flash

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Direct Addressing

Indirect Addressing

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Analog

Comparator

I/O Module 2

I/O Module1

I/O Module n

10 8025D–AVR–03/08

ATmega48P/88P/168P/328P

ical ALU operation, two operands are output from the Register File, the operation is executed,

and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data

Space addressing – enabling efficien t address calculations. One of the these addre ss pointers

can also be used as an address pointer for loo k up tables in Flash prog ram memory. These

added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and

a register. Single regi ster operation s can also be executed in th e ALU. After an ar ithmetic opera-

tion, the Stat us Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to

directly address the whole address space. Most AVR instructions have a single 16-bit word for-

mat. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the

Application Program section. Both sections have dedicated Lock bits for write and read/write

protection. The SPM instruction that writes into the Application Flash memory section must

reside in the Boot Program section.

During interrupts an d subroutine calls, the retur n address Program Count er (PC) is stored on the

Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack

size is only limited by the total SRAM size and the usage of the SRAM. All user programs must

initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack

Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed

through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the

Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-

tion. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-

ters, SPI, and other I/O fun ctions. The I/O Memory can be access ed directly, or as the Data

Space locations following those of the Register File, 0x20 - 0x5F. In addition, the

ATmega48P/88P/168P/328P has Extended I/O space from 0x60 - 0xFF in SRAM where only

the ST/STS/STD and LD/LDS/LDD instructions can be used.

6.2 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose

working registers. Within a single clock cycle, arithmetic operations between general purpose

registers or betwee n a re gister an d an immedi ate ar e execut ed . The ALU ope ra tio ns are divided

into three main categories – arithmetic, logical, and bit-functions. Some implementations of the

architecture also provide a powerful multiplier supporting both signed/unsigned multiplication

and fractional format. See the “Instruction Set” section for a detailed description.

6.3 Status Register

The Status Register contains information about the result of the most recently executed arith-

metic instruction. This information can be used for altering program flow in order to perform

conditional operations. Note that the Status Register is updated after all ALU operations, as

8025D–AVR–03/08

ATmega48P/88P/168P/328P

specified in the I nstru ction Se t Re ference. This will in many case s re move the n eed f or using t he

dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored

when returning from an inte rr up t. T his mu st be ha nd le d by so ftw ar e.

6.3.1 SREG – AVR Status Register

The AVR Status Register – SREG – is defined as:

• Bit 7 – I: Globa l Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-

rupt enable control is then performed in separate control registers. If the Global Interrupt Enable

enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by

the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by

the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-

nation for the operated bit. A bit from a register in the Register File can be copied into T by the

BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the

BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful

in BCD arithmetic. See t he “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or betwee n the Negative Flag N and the Two’s Complement

Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the

“Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the

“Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction

Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set

Description” for detailed information.

Bit 76543210

0x3F (0x5F) I T H S V N Z C SREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

12 8025D–AVR–03/08

ATmega48P/88P/168P/328P

6.4 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruc tion set. In order t o achieve

the required performance and flexibility, the following input/output schemes are supported by the

• One 8-bit outpu t operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 6-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 6-2. AVR CPU General Purpose Working Registers

Most of the instructions operating on the Register File have direct access to all registers, and

most of them are single cycle instructions.

As shown in Figure 6-2, each register is also assigned a data me mory address, mapping them

directly into the first 32 locations of the user Data Space. Although not being physically imple-

mented as SRAM locations, this memo ry organization provides great fle xibility in access of the

registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file .

7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R28 0x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-regist er Low Byte

R31 0x1F Z-register High Byte

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ATmega48P/88P/168P/328P

6.4.1 The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These reg-

isters are 16-bit address pointers for indirect ad dressing of the data space. The three indirect

address registers X, Y, and Z are defined as described in Figure 6- 3.

Figure 6-3. The X-, Y-, and Z-registers

In the differ ent a ddr essing modes the se ad dr ess regist er s have fun cti ons a s fi xed d isp lacement ,

automatic increment, and automatic decrement (see the instruction set reference for details).

6.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing

return addresses after interrupts and subroutine calls. The Stack Pointer Register always points

to the top of th e Stack. No te that the Sta ck is implement ed as growing from hig her memor y loca-

tions to lower memor y locat io ns. This im plies t hat a Stack PUSH co mmand decr ease s th e Stack

Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt

Stacks are located. This Stack space in the data SRAM must be defined by the program before

any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to

point above 0x0100, preferably RAMEND. The Stack Pointer is decremented by one when data

is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the

return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is

incremented by one whe n data is popped fro m the Stack with the POP inst ruction, and it is incre-

mented by two when data is popped from the Stack with return from subroutine RET or return

from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of

bits actually used is implementation dependent. Note that the data space in some implementa-

tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register

will not be present.

15 XH XL 0

X-register 707 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 707 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 70 7 0

R31 (0x1F) R30 (0x1E)

14 8025D–AVR–03/08

ATmega48P/88P/168P/328P

6.5.1 SPH and SPL – Stack Pointer High and Stack Pointer Low Register

6.6 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR

CPU is driven by the CPU clock clkCPU, directly generate d f rom th e selected clo ck source f or the

chip. No internal clock division is used.

Figure 6- 4 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast-access Register File concept. This is the basic pipelining concept

to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,

functions per clocks, and functions per power-unit.

Figure 6-4. The Parallel Instruction Fetches and Instruction Executions

Figure 6-5 shows the int ernal timi ng con cept for th e Regi ster File . In a single clock cycl e an ALU

operation using two register operands is executed, and the result is stored back to the destina-

tion register.

Figure 6-5. Single Cycle ALU Operation

Bit 151413121110 9 8

0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND

RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

egister Operands Fetch

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clkCPU

8025D–AVR–03/08

ATmega48P/88P/168P/328P

6.7 Reset and Interrupt Handling

The AVR provides several different inte rrupt sources. These interrupts and the separate Reset

Vector each have a separate program vector in the program memory space. All interrupts are

assigned individual enable bits which must be wr itten logic one to gether with th e Global Inter rupt

Enable bit in the Status Register in orde r to enable the interrupt. Depending on the Program

Counter value, interrupts ma y be automatically disabled when Boot Lock bits BLB02 or BLB12

are programmed. This feature improves software security. See the section ”Memory Program-

ming” on page 294 for details.

The lowest addresses in the progra m memory space are by default defined as the Reset and

Interrupt Vectors. The complete list of vectors is shown in ”Interrupts” on page 58. The list also

determines the priority levels of the different interrupts. The lower the address the higher is the

priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0. The Interru pt Vectors can be moved t o the star t of the Bo ot Flash sect ion by setti ng the IVSEL

bit in the MCU Control Register (MCUCR). Refer to ”Interrupt s” on page 58 for more information.

The Reset Vector can also be moved to the start of the Boot Flash section by programming the

BOOTRST Fuse, see ”Boot Loader Support – Read-While-Write Self-Programming,

ATmega88P, ATmega168P and ATmega328P” on page 278.

When an interrupt occurs, th e Global Interrupt Enable I-bit is cleared and all interrup ts are dis-

abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled

interrupts can then interrupt the current interrupt routine. The I-bit is au tomatically set when a

Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the

Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-

tor in order to execute the interrupt handling routine, and hardware clears the corresponding

Interrupt Flag. Interrupt Flags can also be cleared by writ ing a logic one to the flag bit position(s)

to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is

cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is

cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt

Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the

Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. The se

interrupts do not nece ssarily have I nterrupt Fla gs. If t he interr upt condit ion disappear s before the

interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one

more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor

restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.

No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the

CLI instruction. The f ollowing e xa mple sho ws how this can be used to a void interrupts during the

timed EEPROM write sequence.

16 8025D–AVR–03/08

ATmega48P/88P/168P/328P

When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-

cuted before any pending interrupts, as shown in this example.

6.7.1 Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-

mum. After four clo ck cycles t he pr og ram vect or add ress fo r t he actua l interr up t ha nd ling rout ine

is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.

The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If

an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed

before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt

execution response time is in creased by fo ur clock cycles. This incre ase comes in additi on to the

start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock

cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is

incremented by two, and t he I-bit in SREG is set.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMPE ; start EEPROM write

sbi EECR, EEPE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

8025D–AVR–03/08

ATmega48P/88P/168P/328P

7. AVR Memories

7.1 Overview This section describes the different memories in the ATmega48P/88P/168P/328P. The AVR

architecture has two main memory spaces, the Data Memory and the Program Memory space.

In addition, t he ATmega4 8P/ 88P/ 168P/ 32 8P fe atur es an EEPRO M Memor y for da ta stor ag e. All

three memory space s are linear and regular.

7.2 In-System Reprogrammable Flash Program Memory

The ATmega48P/88P/168P/328P contains 4/8/16/32K bytes On-chip In-System Reprogramma-

ble Flash me mory for program st orage. Since all AVR instruct ions are 16 or 32 bits wid e, the

Flash is organized as 2/4/8/16K x 16. For software security, the Flash Program memory space is

divided into two sections, Boot Loader Section and Application Program Section in ATmega88P

and ATmega168P. ATmega48P does not have separate Boot Loader and Application Program

sections, and the SPM instruction can be executed fro m the entire Flash. See SELFPRGEN

description in section ”SPMCSR – Store Program Memory Cont rol and Status Register ” on p age

276 and page 292for more details.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The

ATmega48P/88P/168P/328P Program Counter (PC) is 11/12/13/14 bits wide, thus addressing

the 2/4/8/16K program memory locations. The operation of Boot Program section and associ-

ated Boot Lock bits for software protection are described in detail in ”Self-Programming the

Flash, ATmega48P” on page 270 and ”Boot Loader Support – Read-While-Write Self-Program-

ming, ATmega88P, ATmega168P and ATmega328P” on page 278. ”Memory Programming” on

page 294 contain s a detailed description on Flash Progr amming in SPI- or Parallel Program ming

mode.

Constant tables can be allocated within the entire program memory address space (see the LPM

– Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in ”Instruction Execution Tim-

ing” on page 14.

18 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 7-1. Program Memory Map, ATmega48P

Figure 7-2. Program Memory Map, ATmega88P, ATmega168P, and ATmega328P

0x0000

0x7FF

Program Memory

Application Flash Section

0x0000

0x0FFF/0x1FFF/0x3FF

Program Memory

Application Flash Section

Boot Flash Section

8025D–AVR–03/08

ATmega48P/88P/168P/328P

7.3 SRAM Data Memory

Figure 7-3 shows how the ATmega48P/88P/168P/328P SRAM Memory is organized.

The ATmega48P/88P/168P/328P is a complex microcontroller with more peripheral units than

can be supported within the 64 locations reserved in the Opcode for the IN and OUT instruc-

tions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and

LD/LDS/LDD instructions can be used.

The lower 768/1280/1280/2303 data memory locations address both the Register File, the I/O

memory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the

memory, and th e next 512/1024/1024/2048 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displace-

ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register

File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacemen t mode reaches 63 add ress locations from the base address given

by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decrement ed or incremented.

The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and

the 512/102 4/102 4/ 20 48 b yte s of in t ernal d at a SRAM in th e ATme ga4 8P/88 P/1 68P/ 328P ar e a ll

accessible through all these addressing modes. The Register File is described in ”General Pur-

pose Register File” on page 12.

Figure 7-3. Data Memory Map

32 Registers

64 I/O Registers

Internal SRAM

(512/1024/1024/2048 x 8)

0x0000 - 0x001F

0x0020 - 0x005F

0x02FF/0x04FF/0x04FF/0x08F

0x0060 - 0x00FF

Data Memory

160 Ext I/O Reg.

0x0100

20 8025D–AVR–03/08

ATmega48P/88P/168P/328P

7.3.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clkCPU cycles as described in Figure 7-4.

Figure 7-4. On-chip Data SRAM Access Cycles

7.4 EEPROM Data Memory

The ATmega48P/88P/168P/328P contains 256/512/512/1K bytes of data EEPROM memory. It

is organized as a separate data space, in which single bytes can be read and written. The

EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the

EEPROM and the CPU is described in the follow ing, specifying the EEPROM Address Regis-

ters, the EEPROM Data Register, and the EEPROM Control Register.

”Memory Programmi ng” on pag e 29 4 contains a detailed description on EEPROM Programming

in SPI or Parallel Programming mode.

7.4.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in T able 7-2. A self-timing function, however,

lets the user software detect when the next byte can be written. If the user code contains inst ruc-

tions that write the EEPROM, some precautions must be taken. In heavily filtered power

supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for some

period of time to r un at a voltage lo wer th an spe cified as minim um for the cloc k freq uen cy used .

See ”Preventing EEPROM Corruption” on page 21 for details on h ow to avoid problems in these

situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

clk

Data

ddress Address valid

T1 T2 T3

Compute Address

Read Write

CPU

Memory Access Instruction Next Instruction

8025D–AVR–03/08

ATmega48P/88P/168P/328P

7.4.2 Preventing EEPROM Corruption

During periods of low VCC, the EEPROM data can be co rrupted because the supply voltage is

too low for the CPU and the EEPROM to operate properly. These issues a re the same as for

board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First,

a regular write seque nce to the EEPROM requires a minimum voltage to operate correctly. Sec-

ondly, the CPU itself can execute instructions incorrectly , if the su pp ly voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal

BOD does not match th e needed d etection le vel, an e xternal low VCC reset Protection circuit can

be used. If a reset occurs while a write operation is in progress , the write operation will be com-

pleted provided that the power supply voltage is sufficient.

7.5 I/O Memory The I/O space definition of the ATmega48P/88P/168P/328P is shown in ”Re gister Summary” on

page 400.

All ATmega48P/88P/168P/328P I/Os and peripherals are placed in the I/O space. All I/O loca-

tions may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data

between the 32 general purpose working registers and the I/O space. I/O Registers within the

address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In

these registers, the value of single bits can be checked by using the SBIS a nd SBIC instructions.

Refer to the instruction set sec tion for more details. When using the I/O specific comman ds IN

and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data

space using LD and ST instructions, 0x20 must be added to these addresses. The

ATmega48P/88P/168P/328P is a complex microcontroller with more peripheral units than can

be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the

Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/ STD and LD/LDS/LDD instruc-

tions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most

other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore

be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-

isters 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

7.5.1 General Purpos e I/O Registers

The ATmega48P/88P/168P/328P contains three General Purpose I/O Registers. These regis-

ters can be used for storing any information, and they are particularly useful for storing global

variables and Status Flags. General Purpose I/O Registers within the address range 0x00 -

0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

22 8025D–AVR–03/08

ATmega48P/88P/168P/328P

7.6 Register Description

7.6.1 EEARH and EEARL – The EEPROM Address Register

• Bits 15..9 – Res: Reserved Bits

These bits are reserved bits in the ATmega48P/88P/168P/328P and will always read as zero.

• Bits 8..0 – EEAR8..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the

256/512/512/1K bytes EEPROM space. The EEPROM data bytes are addressed linearly

between 0 and 255/511/511/1023. The initial value of EEAR is undefined . A proper value must

be written before the EEPROM may be accessed.

EEAR8 is an unused bit in ATmega48P and must always be written to zero.

7.6.2 EEDR – The EEPROM Data Register

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write oper ation, the EEDR Register contains the data to be written to the

EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the

EEDR contains the data read out from the EEPROM at the address given by EEAR.

7.6.3 EECR – The EEPROM Control Register

• Bits 7..6 – Res: Reserved Bits

These bits are reserved bits in the ATmega48P/88P/168P/328P and will always read as zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bit setting defines which programming action that will be trig-

gered when writing EEPE. It is possible to program data in one atomic operation (erase the old

value and program the new value) or to split the Erase and Write operations in two different

operations. The Pr ogramming t imes for the d ifferen t modes ar e shown in Table 7-1. While EEPE

Bit 151413121110 9 8

0x22 (0x42) – – – – – – – EEAR8 EEARH

0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

76543210

Read/Write RRRRRRRR/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 X

XXXXXXXX

Bit 76543210

0x20 (0x40) MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

0x1F (0x3F) – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 X X 0 0 X 0

8025D–AVR–03/08

ATmega48P/88P/168P/328P

is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00

unless the EEPROM is busy programming.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interr upt if the I bit in SREG is set. Writing

EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-

rupt when EEPE is cleared. The interrupt will not be generated during EEPROM write or SPM.

• Bit 2 – EEMPE: EEPROM Master Write Enable

The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written.

When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the

selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been

written to one by software, hardware clears the bit to zero after four clock cycles. See the

description of the EEPE bit for an EEPROM write procedure.

• Bit 1 – EEPE: EEPROM Write Enable

The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address

and data are correctly set up, the EEPE bit must be written to one to write the value into the

EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, other-

wise no EEPROM write takes place. The following procedure should be followed when writing

the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEPE becomes zero.

2. Wait until SELFPRGEN in SPMCSR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.

6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software

must check that the Flash programming is completed before initiating a new EEPROM write.

Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the

Flash. If t he F l as h is n e ve r b ein g up da te d by the CPU, s tep 2 ca n b e om itt ed . Se e ”Boot Loader

Support – Read-While-Write Self-Programming, ATmega88P, ATmega168P and ATmega328P”

on page 278 for details about Boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is

interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the

interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared

during all the steps to avoid these problems.

Table 7-1. EEPROM Mode Bits

EEPM1 EEPM0 Programming

Time Operation

0 0 3.4 ms Erase and Write in one operation (Atomic Operation)

0 1 1.8 ms Erase Only

1 0 1.8 ms Write Only

1 1 – Reserved for future use

24 8025D–AVR–03/08

ATmega48P/88P/168P/328P

When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft-

ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set,

the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct

address is se t up in t he EEAR Regist er, the EERE bit must be writ ten to a log ic one to trigge r the

EEPROM read. The EEPROM read access takes one instruction, and the requested data is

available immediately. When the EEPROM is read, the CPU is halted for four cycles before the

next instruction is executed.

The user should poll the EEPE bit before starting the read operation. If a write operation is in

progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM access es. Table 7-2 lists the ty pical pro-

gramming time for EEPROM access from the CPU.

The following code examples show one assembly and one C function for writing to the

EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glo-

bally) so that no interrupts will occur during execution of these functions. The examples also

assume that no Flash Boot Loader is present in the software. If such code is present, the

EEPROM write function must also wait for any ongoing SPM command to finish.

Table 7-2. EEPROM Programming Time

Symbol Number of Calibrated RC Oscillator Cycles Typ Programming Time

EEPROM write

(from CPU) 26,368 3.3 ms

8025D–AVR–03/08

ATmega48P/88P/168P/328P

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to Data Register

out EEDR,r16

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address and Data Registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMPE */

EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

26 8025D–AVR–03/08

ATmega48P/88P/168P/328P

The next code examples show assembly and C functions for reading the EEPROM. The exam-

ples assume that interrupts are controlled so that no interrupts will occur during execution of

these functio ns.

7.6.4 G PIO R2 – Ge n eral Purp ose I/O Re gi st er 2

7.6.5 G PIO R1 – Ge n eral Purp ose I/O Re gi st er 1

7.6.6 G PIO R0 – Ge n eral Purp ose I/O Re gi st er 0

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from Data Register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from Data Register */

return EEDR;

}

Bit 76543210

0x2B (0x4B) MSB LSB GPIOR2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

0x2A (0x4A) MSB LSB GPIOR1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

0x1E (0x3E) MSB LSB GPIOR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

8025D–AVR–03/08

ATmega48P/88P/168P/328P

8. System Clock and Clock Options

8.1 Clock Systems and their Distribution

Figure 8-1 presents the principal clock systems in the AVR and th eir distribution . All of th e clocks

need not be active at a given time . In order to red uce power co nsumption, the clo cks to modu les

not being used can be halted by using different sleep modes, as described in ”Power Manage-

ment and Sleep Modes” on page 40. The clock systems are detailed below.

Figure 8-1. Clock Distribution

8.1.1 CPU Clock – clkCPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core.

Examples of such modules are the General Purpose Register File, the Status Register and the

data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing

general operations and calculations.

8.1.2 I/O Clock – clkI/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.

The I/O clock is also used by the External Interrupt module, but note that some external inter-

rupts are detecte d by asynchronous logic, allowing such interrupts to be detected even if the I/O

clock is halted. Also no te that start co ndition det ection in th e USI module is carried out asynchro-

nously when clkI/O is halted, TWI address recognition in all sleep modes.

8.1.3 Flash Cl ock – clkFLASH

The Flash clock controls o peration of t he Flash in terface. Th e Flash clock is usually active simul-

taneously with the CPU clock.

General I/O

Modules

Asynchronous

Timer/Counter CPU Core RAM

clk

I/O

clk

ASY

AVR Clock

Control Unit clk

CPU

Flash and

EEPROM

clk

FLASH

Source clock

Watchdog Timer

Watchdog

Oscillator

Reset Logic

Clock

Multiplexer

Watchdog clock

Calibrated RC

Oscillator

Timer/Counter

Oscillator Crystal

Oscillator Low-frequency

Crystal Oscillator

External Clock

ADC

clkADC

System Clock

Prescaler

28 8025D–AVR–03/08

ATmega48P/88P/168P/328P

8.1.4 Asynchronous Timer Clock – clkASY

The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly

from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows

using this Timer/Counter as a real-time counter even when the device is in sleep mode.

8.1.5 ADC Clock – clkADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks

in order to re duce noise ge ner ated by digital cir cuit ry. Th is gives mo re accurat e ADC conversion

results.

8.2 Clock SourcesThe device has the follo wing clock source options, selectable by Flash Fuse bits as shown

below. The cloc k fr om t he se lected so ur ce is i npu t t o th e AVR clo c k gene ra to r, an d rou te d t o the

appropriate modules.

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

8.2.1 Default Clock Source

The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 pro-

grammed, resulting in 1.0MHz system clock. The startup time is set to maximum and time-out

period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default setting ensures that

all users can make their de sired clock sour ce se tting usi ng any available prog ramming inter face.

8.2.2 Clock Startup Sequence

Any clock source needs a sufficient VCC to start os cillating and a minimum number of oscillating

cycles before it can be considered stable.

To ensure sufficient VCC, the device issues an internal reset with a time-out delay (tTOUT) after

the device reset is released by all other reset sources. ”System Control and Reset” on page 47

describes the start condit ions for t he intern al reset. The d elay (tTOUT) is timed from the Watchdog

Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The

Table 8-1. Device Clocking Options Select(1)

Device Clocking Option CKSEL3..0

Low Power Crystal Oscillator 1111 - 1000

Full Swing Crystal Oscillator 0111 - 0110

Low Frequency Crystal Oscil lator 0101 - 0100

Internal 128 kHz RC Oscillator 0011

Calibrated Internal RC Oscill ator 0010

Exter nal Clock 0000

Reserved 0001

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ATmega48P/88P/168P/328P

selectable delays are shown in Table 8-2. The freque ncy of the Watchdog Oscillator is voltage

dependent as shown in ”Typical Characteristics” on page 32 7.

Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum VCC. The

delay will not monitor the actual voltage and it will be required to select a delay longer than the

VCC rise time. If this is not possible, an int ernal or external Bro wn-Out Detection circuit should be

used. A BOD circuit will ensure sufficient VCC before it rele ases t he re set, a nd the t i me-o ut de lay

can be disabled. Disabling the time-out delay without utilizing a Brown-Out Detection circuit is

not recommended.

The oscillator is required to oscillate for a minimum number of cycles before the clock is consid-

ered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal

reset active for a given number of clock cycles. The reset is then released and the device will

start to execute. The recommended oscillator start-up time is dependent on the clock type, and

varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal.

The start-up sequence for the clock includes both the time-out delay and the start-up time when

the device starts up from re se t. When startin g up from Power -save or Power -down mod e, VCC is

assumed to be at a sufficient level and only the start-up time is included.

8.3 Low Power Crystal Oscillator

Pins XTAL1 and XTAL2 are inpu t and output, respectively, of an inverting amplifier which can be

configured for use as an On-chip Oscillator, as shown in Figure 8-2 on page 30. Either a quartz

crystal or a ceramic resonator may be used.

This Crystal Oscillator is a low power oscillator, with reduced volta ge swing on the XTAL2 out-

put. It gives the lowest power consumption, but is not capable of driving other clock inputs, and

may be more susceptible t o noise in noisy envir on ments. In t hese cases, re fer t o th e ”Full Swing

Crystal Oscillator” on page 31.

C1 and C2 should always be equal for both crystals and resonators. The optim al value of the

capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the

electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for

use with crystals are given in Table 8-3 on page 30. For ceramic resonators, the capacitor val-

ues given by th e manufacturer should be used.

Table 8-2. Number of Watchdog Oscillator Cycles

Typ Time-out (VCC = 5.0V) Typ Time -o ut ( VCC = 3.0V) Nu m be r of C ycles

0 ms 0 ms 0

4.1 ms 4.3 ms 512

65 ms 69 ms 8K (8,192)

30 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 8-2. Crystal Oscillator Connections

The Low Power Oscillator can operate in three different modes, each optimized for a specific fre-

quency range. The opera ting mode is selected by the fuses CKSEL3..1 as sho wn in Table 8-3

on page 30.

Notes: 1. The frequency ranges are preliminary values. Actual values are TBD.

2. This option should not be used with crystals, only with ceramic resonators.

3. If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8

Fuse can be programmed in order to divide the inter nal frequency by 8. It must be ensured

that the resulting divided clock meets the frequency specification of the device.

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table

8-4.

Table 8-3. Low Power Crystal Oscillator Operating Modes(3)

Frequency Rang e (1)

(MHz) Recommended Range for

Capacitors C1 and C2 (pF) CKSEL3..1

0.4 - 0.9 – 100(2)

0.9 - 3.0 12 - 22 101

3.0 - 8.0 12 - 22 110

8.0 - 16.0 12 - 22 111

Table 8-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection

Oscillator Source /

Power Conditions

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset

(VCC = 5.0V) CKSEL0 SUT1..0

Ceramic resonator, fast

rising power 258 CK 14CK + 4.1 ms(1) 000

Ceramic resonator , slowly

rising power 258 CK 14CK + 65 ms(1) 001

Ceramic resonator, BOD

enabled 1K CK 14CK(2) 010

Ceramic resonator, fast

rising power 1K CK 14CK + 4.1 ms(2) 011

Ceramic resonator , slowly

rising power 1K CK 14CK + 65 ms(2) 100

XTAL2 (TOSC

XTAL1 (TOSC

GND

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ATmega48P/88P/168P/328P

Notes: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These

options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability

at start-up. They can also be used with crystal s when not operating close to the maximum fre-

quency of the device, and if frequency stability at start-up is not important for the application.

8.4 Full Swing Crystal Oscillator

Pins XTAL1 and XTAL2 are inpu t and output, respectively, of an inverting amplifier which can be

configured for use as an On-chip Oscillator, as shown in Figure 8-2 on page 30. Either a quartz

crystal or a ceramic resonator may be used.

This Crystal Oscillator is a full swing oscillator, with rail-to-rail swing on the XTAL2 output. This is

useful for driving other clock inputs and in noisy environments. The current consumption is

higher than the ”Low Power Crystal Oscillator” on page 29. Note that the Full Swing Crystal

Oscillator will only operate for VCC = 2.7 - 5.5 volts.

C1 and C2 should always be equal for both crystals and resonators. The optim al value of the

capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the

electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for

use with crystals are given in Table 8-6 on page 32. For ceramic resonators, the capacitor val-

ues given by th e manufacturer should be used.

The operating mode is selected by the fuses CKSEL3..1 as shown in Table 8-5.

Notes: 1. The frequency ranges are preliminary values. Actual values are TBD.

2. If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8

Fuse can be programmed in order to divide the inter nal frequency by 8. It must be ensured

that the resulting divided clock meets the frequency specification of the device.

Crystal Oscillator, BOD

enabled 16K CK 14CK 1 01

Crystal Oscillator, fast

rising power 16K CK 14CK + 4.1 ms 1 10

Crystal Oscillator, slowly

rising power 16K CK 14CK + 65 ms 1 11

Table 8-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection (Continued)

Oscillator Source /

Power Conditions

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset

(VCC = 5.0V) CKSEL0 SUT1..0

Table 8-5. Full Swing Crystal Oscillator operating modes(2)

Frequency Range(1)

(MHz) Recommended Range for

Capacitors C1 and C2 (pF) CKSEL3..1

0.4 - 20 12 - 22 011

32 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 8-3. Crystal Oscillator Connections

Notes: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These

options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability

at start-up. They can also be used with crystal s when not operating close to the maximum fre-

quency of the device, and if frequency stability at start-up is not important for the application.

Table 8-6. Start-up Times for the Full Swing Crystal Oscillator Clock Selection

Oscillator Source /

Power Conditions

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset

(VCC = 5.0V) CKSEL0 SUT1..0

Ceramic resonator, fast

rising power 258 CK 14CK + 4.1 ms(1) 000

Ceramic resonator , slowly

rising power 258 CK 14CK + 65 ms(1) 001

Ceramic resonator, BOD

enabled 1K CK 14CK(2) 010

Ceramic resonator, fast

rising power 1K CK 14CK + 4.1 ms(2) 011

Ceramic resonator , slowly

rising power 1K CK 14CK + 65 ms(2) 100

Crystal Oscillator, BOD

enabled 16K CK 14CK 1 01

Crystal Oscillator, fast

rising power 16K CK 14CK + 4.1 ms 1 10

Crystal Oscillator, slowly

rising power 16K CK 14CK + 65 ms 1 11

XTAL2 (TOSC

XTAL1 (TOSC

GND

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ATmega48P/88P/168P/328P

8.5 Low Frequency Crystal Oscillator

The Low-frequency Crystal Oscillator is optimized for use with a 32.768 kHz watch crystal.

When selecting crystals, load capasitance and crystal’s Equivalent Series Resistance, ESR

must be taken into consideration. Both values are specified by the crystal vendor.

ATmega48P/88P/168P/328P oscillator is optimized for very low power consumption, and thus

when selecting crystals, see Table 8-7 on page 33 for maximum ESR recommendations on

6.5 pF, 9.0 pF and 12.5 pF crystals

Table 8-7. Maximum ESR Recommendation for 32.768 kHz Crystal

Note: 1. Maximum ESR is typical value based on characterization

The Low-frequency Crystal Oscillator provides an internal load capacitance of typical 6 pF. Crys-

tals with recommended 6 pF load capacitance can be without external capacitors as shown in

Figure 8-4 on page 33.

Figure 8-4. Crystal Oscillator Connections

Crystals specifying load capacitance (CL) higher than 6 pF, require external capacitors applied

as described in Figure 8-2 on page 30.

To find suitable load capa citance for a 32.768 kHz crysal, please consult the crystal datasheet.

The Low-frequency Crystal Oscillator must be selected by setting the CKSEL Fuses to “0110” or

“0111”, as s hown in Table 8-9. Start-up times are determined by th e SUT Fuses as shown in

Table 8-8.

Crystal CL (pF) Max ESR [kΩ](1)

6.5 75

9.0 65

12.5 30

Table 8-8. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

SUT1..0 Additional Delay from Reset (VCC = 5.0V) Re co mmended Usage

00 4 CK Fast rising power or BOD enabled

01 4 CK + 4.1 ms Slowly rising power

10 4 CK + 65 ms Stable frequency at start-up

11 Reserved

XTAL2 (TOSC

XTAL1 (TOSC

34 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Note: 1. This option should only be used if frequency stability at start-up is not important for the

application

8.6 Calibrated Internal RC Oscillator

By default, the Internal RC Oscillator provides an approximat e 8.0 MHz clock. Though voltage

and temperature dependent, this clock can be very accurately calibrated by the user. See Table

28-1 on page 318 for more details. The device is shipped with the CKDIV8 Fuse programmed.

See ”System Clock Prescaler” on page 36 for more details.

This clock may be sele ct ed as th e s ystem c loc k by p ro gram m in g th e CKS E L F us es as sh own in

Table 8-10. If selected, it will operate with no external components. During reset, hardware loads

the pre-progra mme d calibr at ion value into th e OSCCAL Re giste r a nd the re by automat ica lly cal-

ibrates the RC Oscillator. The accurac y of this calibration is shown as Factory calibration in

Table 28-1 on page 318.

By changing the OSCCAL register from SW, see ”OSCCAL – Oscillator Calibration Register” on

page 38, it is possible to get a higher calibration accuracy than by using the factory calibration.

The accuracy of th is calibration is shown as User calibration in Table 28-1 on page 318.

When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the

Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed cali-

bration value, see the section ”Calibration Byte” on page 299.

Notes: 1. The device is shipped with this option selected.

2. The frequency ranges are preliminary values. Actual values are TBD.

3. If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8

Fuse can be programmed in order to divide the internal frequency by 8.

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in

Table 8-11 on page 34.

Note: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to

14CK + 4.1 ms to ensure programming mode can be entered.

2. The device is shipped with this option selected.

Table 8-9. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

CKSEL3..0 Start-up Time from

Power-down and Power-save Recommended Usage

0110(1) 1K CK

0111 32K CK Stable frequency at start-up

Table 8-10. Internal Calibrated RC Oscillator Operating Modes(1)(3)

Frequency Range(2) (MHz) CKSEL3..0

7.3 - 8.1 0010

Table 8-11. Start-up times for the internal calibrated RC Oscillator clock selection

Power Conditions Start-up Time from Power-

down and Power-save Additional Delay from

Reset (VCC = 5.0V) SUT1..0

BOD enabled 6 CK 14CK(1) 00

Fast rising power 6 CK 14CK + 4.1 ms 01

Slowly rising power 6 CK 14CK + 65 ms(2) 10

Reserved 11

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ATmega48P/88P/168P/328P

8.7 128 kHz Internal Oscillator

The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-

quency is nominal at 3V and 25°C. This clock may be select as the system clock by

programming the CKSEL Fuses to “11” as shown in Table 8-12.

Note: 1. The frequency is preliminary value. Actual value is TBD.

When this clock source is selected, start-up times are det ermined by the SUT Fuses as sh own in

Table 8-13.

Note: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to

14CK + 4.1 ms to ensure programming mode can be entered.

8.8 External Cloc kTo drive the device from an external clock source, XTAL1 should be driven as shown in Figure

8-5 on page 35 . To run the device on an external cloc k, the CKSEL Fuses must be programmed

to “0000” (see Table 8-14).

Figure 8-5. External Clock Drive Configuration

When this clock source is selected, start-up times are det ermined by the SUT Fuses as sh own in

Table 8-15.

Table 8-12. 128 kHz Internal Oscillator Operating Modes

Nominal Frequency CKSEL3..0

128 kHz 0011

Table 8-13. Start-up Times for the 128 kHz Internal Oscillator

Power Conditions Start-up Time from Power-

down and Power-save Additional Delay from

Reset SUT1..0

BOD enabled 6 CK 14CK(1) 00

Fast rising power 6 CK 14CK + 4 ms 01

Slowly rising power 6 CK 14CK + 64 ms 10

Reserved 11

Table 8-14. Crystal Osc illator Clock Frequency

Frequency CKSEL3..0

0 - 20 MHz 0000

EXTERNAL

CLOCK

SIGNAL

XTAL2

XTAL1

GND

36 8025D–AVR–03/08

ATmega48P/88P/168P/328P

When applying an external clock, it is required t o avoid sudden changes in the applied clock fre-

quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from

one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is

required, ensure that the MCU is kept in Reset during the changes.

Note that the System Clock Prescaler can be used to implemen t run-time change s of the interna l

clock frequency while still ensuring stable operation. Refer to ”System Clock Prescaler” on page

36 for details.

8.9 Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT

Fuse has to be programme d. This mode is suitable wh en the chip clock is u sed to d rive other cir-

cuits on the system. The clock also will be output during reset, and the normal operation of I/O

pin will be overridden when the fuse is programmed. Any clock source, including the internal RC

Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is

used, it is the divided system clock that is output.

8.10 Timer/Counter Oscillator

ATmega48P/88P/168P/328 P uses the same crystal oscillator for Low-frequency Oscillator and

Timer/Counter Oscillator. See ”Low Frequency Crystal Oscillator” on page 33 for details on the

oscillator and crystal requirements.

ATmega48P/88P/168P/328P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with

XTAL1 and XTAL2. When using the Timer/Counter Oscillator, the system clock needs to be four

times the oscillator frequency. Due to this and the pin sharing, the Timer/Counter Oscillator can

only be used when the Calibrated Internal RC Oscillator is selected as system clock source.

Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is

written to logic one. See ”Asynchronous Operation of Timer/Counter2” on page 156 for further

description on selecting external clock as input instead of a 32.768 kHz watch crystal.

8.11 System Clock Prescaler

The ATmega48P/8 8P/168P/328P has a system clock prescaler, and the system clock can be

divided by setting the ”CLKPR – Clock Prescale Register” on page 387. This feature ca n be

used to decrease the system clo ck f requen cy and the p ower consumpt ion wh en the r equir ement

for processing power is low. This can be used with all clock sour ce options, and it will affect the

clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH

are divided by a factor as shown in Table 28-3 on page 319.

When switching between prescaler settings, the System Clock Prescaler ensures that no

glitches occurs in t he clock syst em. It a lso en sures th at no in te rme diate f reque ncy is higher t han

Table 8-15. Start-up Times for the External Clock Selection

Power Conditions Start-up Time from Power-

down and Power-save Additional Delay from

Reset (VCC = 5.0V) SUT1..0

BOD enabled 6 CK 14CK 00

Fast rising po wer 6 CK 14CK + 4.1 ms 01

Slowly rising power 6 CK 14CK + 65 ms 10

Reserved 11

8025D–AVR–03/08

ATmega48P/88P/168P/328P

neither the cl ock f reque ncy corr espondin g to the pr eviou s sett ing, nor t he clock fr equency co rr e-

sponding to the new setting. The ripple counter that implements the prescaler runs at the

frequency of the undivided cloc k, which ma y b e faste r tha n the CPU's clock fr equen cy. Hence, it

is not possible to determine the state of the prescaler - even if it were readable, and the exact

time it takes to switch from one clock division to the other cannot be exactly predicted. From the

time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new

clock frequency is active. In this int er val, 2 active clock edges ar e pr od uced. Her e, T1 is the pr e-

vious clock period, and T2 is the period corresponding to the new prescaler setting.

To avoid uninte ntion al ch anges o f clock freq ue ncy, a sp ecial writ e p roce dure mu st b ef ollowe d to

change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bitsin

CLKPR to zero.

2. Within four cycles, write the desired v alue to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing presca ler setting to make sure the write proce dure is

not interrupted.

38 8025D–AVR–03/08

ATmega48P/88P/168P/328P

8.12 Register Description

8.12.1 OSCCAL – Oscillator Calibration Register

• Bits 7..0 – CAL7..0: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to

remove process variations from the oscillator frequency. A pre-programmed calibration v alue is

automatically writt en to this register du ring chip reset, giving the Factory calibrated frequency as

specified in Table 28-1 on page 318. The application software can write this register to change

the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 28-

1 on page 318. Calibration outside that range is not guaranteed.

Note that this oscillator is used to time EEPROM and Flash write acc esses, and these write

times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more

than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.

The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the

lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-

quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher

frequency than OSCCAL = 0x80.

The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00

gives the lowe st frequ ency in that range, a nd a setting of 0x7F g ives the highest fr equency in t he

range.

8.12.2 CLKPR – Clock Prescale Register

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE

bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is

cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the

CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the

CLKPCE bit.

• Bits 3..0 – CLKPS3..0: Cloc k Prescaler Select Bit s 3 - 0

These bits define the division factor between the selected clock source and the internal system

clock. These bits can be written run-time to vary the clock frequency to suit the application

requirements. As t he divider divide s the master clock input t o the MCU, the spe ed of all synchro-

nous peripherals is reduced when a division factor is used. The division factors are given in

Table 8-16 on page 39.

Bit 76543210

(0x66) CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value Device Specific Calibration Value

Bit 76543210

(0x61) CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR

Read/Write R/W R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 See Bit Description

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ATmega48P/88P/168P/328P

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,

the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to

“0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock

source has a higher frequency than the maximum frequency of the device at the present operat-

ing conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8

Fuse setting. The Application softwar e must ensure that a sufficient division factor is chosen if

the selected clock source has a higher frequency than the maximum frequency of the device at

the present operating conditions. The device is shipped with t he CKDIV8 Fuse programmed.

Table 8-16. Clock Presc aler Select

CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor

0000 1

0001 2

0010 4

0011 8

0100 16

0101 32

0110 64

0111 128

1000 256

1001 Reserved

1010 Reserved

1011 Reserved

1100 Reserved

1101 Reserved

1110 Reserved

1111 Reserved

40 8025D–AVR–03/08

ATmega48P/88P/168P/328P

9. Power Management and Sleep Modes

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving

power. The AVR provides vario us sleep modes allowing the user to tailor the power consump-

tion to the application’s requirements.

When enabled, the Brown-ou t Detector (BOD) actively monitor s the power supply volt age during

the sleep per iods. To furth er save po wer, it is po ssible to d isable the BO D in some sleep modes.

See ”BOD Disable” on page 41 for more details.

9.1 Sleep Modes Figure 8-1 on page 27 presents the different clock systems in the ATmega48P/88P/168P/328P,

and their distribution. The figure is h elpful in selecting an appropriate sleep mode. Table 9-1

shows the different sleep modes, their wake up sources BOD disable ability.

Notes: 1. Only recommended with external crystal or resonator selected as clock source.

2. If Timer/Counter2 is runnin g in asynchronous mode.

3. For INT1 and INT0, only level interrupt.

To enter any of the six slee p modes, the SE bit in SMCR must be written to logic o ne and a

SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select

which sleep mode ( Idle, ADC Noise Reducti on, Po wer-down, Power-save, St andby, or Extended

Standby) will be activated by the SLEEP instruction. See Table 9-2 on page 45 for a summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU

is then halted for four cycles in addition to the start-up time, exe cutes the interrupt routine, and

resumes execution from the instruction following SLEEP. The contents of the Register File and

SRAM are unaltered when the device wake s u p fr om slee p. I f a r eset occurs d uri ng sle ep mod e,

the MCU wakes up and executes from the Reset Vector.

Table 9-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.

Active Clock Domains Oscillators Wake-up Sources

Software

BOD Disable

Sleep Mode

clkCPU

clkFLASH

clkIO

clkADC

clkASY

Main Clock

Source Enabled

Timer Oscillator

Enabled

INT1, INT0 and

Pin Change

TWI Address

Match

Timer2

SPM/EEPROM

Ready

ADC

WDT

Other/O

Idle XXX X X

(2) X X X X XXX

ADC Noise

Reduction XX X X

(2) X(3) XX

(2) XXX

Power-down X(3) XXX

Power-save X X(2) X(3) XX X X

Standby(1) XX

(3) XXX

Extended

Standby X(2) XX

(2) X(3) XX X X

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ATmega48P/88P/168P/328P

9.2 BOD Disable

When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, Table 27-7 on page 297,

the BOD is actively monitoring the po wer sup ply voltage durin g a sleep period . To save power, it

is possible to disable the BOD by software for some of the sleep modes, see Table 9-1 on page

40. The sleep mode power consumption will then be at the same level as when BOD is globally

disabled by fuses. If BOD is disabled in software, the BOD function is turned off immediately

after entering the sleep mode. Upon wake-up from sleep, BOD is automatically enabled again.

This ensures safe operation in case the VCC level has dropped during the sleep period.

When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60

µs to ensure that the BOD is working correctly before the MCU continues executing code.

BOD disable is controlled by bit 6 , BODS (BOD Sleep) in the control register MCUCR , see

”MCUCR – MCU Control Register” on page 45. Writing this bit to one turns off the BOD in rele-

vant sleep modes, while a zero in this bit keeps BOD active. Default setting keeps BOD active,

i.e. BODS set to zero.

Writing to the BODS bit is controlled by a timed sequence and an enable bit, see ”MCUCR –

MCU Control Register” on page 45.

9.3 Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle

mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, 2-wire Serial

Interface, Timer /Co unte rs, Wa tchdog, a nd the int erru pt syste m to con tinue o pe ratin g. This sleep

mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.

Idle mode enables the M CU to wake up from external triggered interrupts as well a s internal

ones like the Timer O verflow and USART Transmit Complete interru pts. If wake-up from the

Analog Comparato r interrupt is not required , the Analog Comparator can b e powered down by

setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will

reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-

cally when this mode is entered.

9.4 ADC Noise Reduction Mode

When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC

Noise Reduction mode, stopping the CPU but allow ing the ADC, the external interrupts, the 2-

wire Serial I nterfa ce ad dres s watc h, Time r/Cou nter2 (1), and the Watchdog to continue operating

(if enabled). T his sleep mode basically ha lts clkI/O, clkCPU, and clk FLASH, while allowing the other

clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If

the ADC is enabled, a conve rsion star ts automa tically when this mode is enter ed. Apart from the

ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a

Watchdog Interrupt, a Brown-out Reset, a 2-wire Serial Interface address match, a

Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT0

or INT1 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode.

Note: 1. Timer/Counter2 will only keep running in asynchronous mode, see ”8-bit Timer/Counter2 with

PWM and Asynchronous Operation” on page 145 for details.

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ATmega48P/88P/168P/328P

9.5 Power-down Mode

When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-

down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2-

wire Serial Interface address watch, and the Watchdog continue operating (if enabled). Only an

External Reset, a Watchdog System Reset, a Watchdog Interrupt, a Brown-out Reset, a 2-wire

Serial Interface address match, an external level interrupt on INT0 or INT1, or a pin change

interrupt can wake up the MCU. This sleep mode basically halts all generated clocks, allowing

operation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed

level must be held for some time to wake up the MCU. Refer to ”External Interrupts” on page 71

for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs

until the wake-up becomes effective. This allows the clock to restart and become stable after

having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the

Reset Time-out period, as described in ”Clock Sources” on page 28.

9.6 Power-save Mode

When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-

save mode. This mode is identical to Power-down, with one exception:

If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from

either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding

Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in

SREG is set.

If Timer/Counter2 is not running, Power-down mode is recommended instead of Power-save

mode.

The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save

mode. If Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is

stopped during sleep. If Timer/Counter2 is not using the synchronous clock, the clock source is

stopped during sleep. Note that even if the synchronous clock is running in Power-save, this

clock is only available for Timer/Counter2.

9.7 Standby ModeWhen the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the

SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down

with the exception that the Oscillator is kept running. From Standby mode, the device wakes up

in six clock cycles.

9.8 Extended Standb y Mode

When the SM2..0 bits are 111 and an external crystal/resonator clock o ption is selected, the

SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to

Power-save with the exception that the Oscillator is kept running. From Extended Standby

mode, the device wakes up in six clock cycles.

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9.9 Power Reduction Register

The Power Reduction Register (PRR), see ”PRR – Power Reduction Register” on page 46, pro-

vides a method to stop the clock to individual peripherals to reduce power consumption. The

current state of the peripheral is frozen and the I/O registers can not be read or written.

Resources used by the peripheral when stopping the clock will remain occupied, hence the

peripheral should in most cases be disabled before stopping the clock. Waking up a module,

which is done by clearing the bit in PRR, puts the module in the sa me state as before shutdo wn.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall

power consumption. In all other sleep modes, the clock is already stopped.

9.10 Minimizing Power Consumption

There are several possibilities to consider when trying to minimize the power consumption in an

AVR controlled system. In general, sleep mo des should be used as much as p ossible, and the

sleep mode should be selected so that as few as possible of the device’s functions are operat-

ing. All functions not needed should be disabled. In particular, the following modules may need

special consideration when trying to achieve th e lowest possible power consumption.

9.10.1 Ana log to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-

abled before entering any sleep mode. When the ADC is turned off and on again, the next

conversion will be an extended conversion. Refer to ”Analog-to-Digital Converter” on page 251

for details on ADC operation.

9.10.2 Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering

ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes,

the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up

to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all

sleep modes. Otherwise, the Inte rnal Voltage Reference will be enabled, indepe ndent of sleep

mode. Refer to ”Analog Comparator” on page 247 for details on how to configure the Analog

Comparator.

9.10.3 Brown-out Detector

If the Brown-ou t Detector is not needed by th e application, this mo dule should be turned off . If

the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep

modes, and hence, always consume power. In the deeper sleep modes, this will contribute sig-

nificantly to the total current consumption. Refer to ”Brown-out Detec tion” on page 49 for details

on how to configure the Brown-out Detector.

9.10.4 Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the

Analog Comparator or the ADC. If these modules are disable d as described in the sections

above, the internal voltage reference will be disabled and it will not be consuming power. When

turned on again, the user must allow the reference to start up before the output is used. If the

reference is kept on in sleep mode, the output can be used immediately. Refer to ”Internal Volt-

age Reference” on page 50 for details on the start-up time.

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ATmega48P/88P/168P/328P

9.10.5 Watchdog Timer

If the Watchdog Timer is not needed in the application , the module should be turned off. If th e

Watchdog Timer is enabled, it will be enabled in all sleep modes and hence always consume

power. In the deeper sleep modes, this will contribute significantly to the total current consump-

tion. Refer to ”Watchdog Timer” on pa ge 51 for d et ails on ho w to configu re the Wa tchd og Time r.

9.10.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The

most important is then to ensure that no pins drive resistive loads. In sleep modes where both

the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will

be disabled. This ensures that no power is consumed by the input logic when not needed. In

some cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. Refer to the section ”Digital Input Enable and Sleep Modes” on page 80 for details on

which pins are enabled. If the input buffer is enabled and the input signal is left floating or have

an analog signal level close to VCC/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to VCC/2 on an input pin can cause significan t current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and

DIDR0). Refer to ”DIDR1 – Digital Input Disable Register 1” on page 250 and ”DIDR0 – Digital

Input Disable Register 0” on page 267 for details.

9.10.7 On-chip Debug System

If the On-chip deb ug system is enabled by the DWEN Fuse and the chip enters sleep mode, the

main clock source is enabled and hence always consumes power. In the deeper sleep modes,

this will contribute significantly to the total current consumption.

8025D–AVR–03/08

ATmega48P/88P/168P/328P

9.11 Register Description

9.11.1 SMCR – Sleep Mode Control Register

The Sleep Mode Control Register contains control bits for power management.

• Bits 7..4 Res: Reserved Bits

These bits are unused bits in the ATmega48P/88P/168P/328P, and will always read as zero.

• Bits 3..1 – SM2.. 0: Sleep Mode Select Bits 2, 1, and 0

These bits select between the five available sleep modes as shown in Table 9-2.

Note: 1. Standby mode is only recommended for use with external crystals or resonators.

• Bit 0 – SE: Sleep Enable

The SE bit must be written to lo gic one to make the MCU enter the sle ep mode when the SLEEP

instruction is execut ed. To avoid t he MCU ent erin g the sleep mode un less it is the programmer’s

purpose, it is recomm ended to write the Sle ep Enable ( SE) bit to o ne just bef ore the e xecution of

the SLEEP instruction and to clear it immediately after waking up.

9.11.2 MCUCR – MCU Control Register

• Bit 6 – BODS: BOD Sleep

The BODS bit must be written to logic one in order to turn off BOD during sleep, see Table 9-1

on page 40. Writing to the BODS bit is controlled by a timed sequence and an enable bit,

BODSE in MCUCR. To disable BOD in relevant sleep mod es, both BODS and BODSE must first

Bit 76543210

0x33 (0x53) – – – – SM2 SM1 SM0 SE SMCR

Read/Write R R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 9-2. Sleep Mode Select

SM2 SM1 SM0 Sleep Mode

000Idle

0 0 1 ADC Noise Reduction

0 1 0 Power-down

0 1 1 Power-save

100Reserved

101Reserved

1 1 0 Standby(1)

1 1 1 External Standby(1)

Bit 7 6 5 4 3 2 1 0

0x35 (0x55) – BODS BODSE PUD – – IVSEL IVCE MCUCR

Read/Write R R R R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

46 8025D–AVR–03/08

ATmega48P/88P/168P/328P

be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be set to

zero within four clock cycles.

The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed

while BODS is active in orde r to turn off the BOD for the actual sleep mode . The BODS bit is

automatically cleared after three clock cycles.

• Bit 5 – BODSE: BOD Sl eep Enable

BODSE enables setting of BODS control bit, as explained in BODS b it de scr ipt ion . BO D disa b le

is controlled by a timed sequence.

9.11.3 PRR – Power Reduction Register

• Bit 7 - PRTWI: P ower Reduction TWI

Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When

waking up the TWI again, the TWI should be re initialized to ensure proper operation.

• Bit 6 - PRTIM2: Power Reduction Timer/Counter2

Writing a logic on e to t his bit shut s down the Timer /Coun ter2 module in synchrono us mode ( AS2

is 0). When the Timer/Counter2 is enabled, operation will continue like before the shutdown.

• Bit 5 - PRTIM0: Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 mo dule. When the Timer/Counter0

is enabled, operation will continue like before the shutdown.

• Bit 4 - Res: Reserved bit

This bit is reserved in ATmega48P/88P/168P/328P and will always read as zero.

• Bit 3 - PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 mo dule. When the Timer/Counter1

is enabled, operation will continue like before the shutdown.

• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface

If using debugWIRE On-chip Debug System, this bit shou ld not be written to one.

Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to

the module. When waking up the SPI again, the SPI should be re initialized to ensure proper

operation.

• Bit 1 - PRUSART0: Power Reduction USART0

Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When

waking up the USART again, the USART should be re initialized to ensure proper ope ration.

• Bit 0 - PRADC: Power Reduction ADC

Writing a logic one to th is bit shuts down t he ADC. The ADC must be disabled before sh ut down.

The analog comparator cannot use the ADC input MUX when the ADC is shut down.

Bit 76543210

(0x64) PRTWI PRTIM2 PRTIM0 – PRTIM1 PRSPI PRUSART0 PRADC PRR

Read/Write R/W R/W R/W R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

8025D–AVR–03/08

ATmega48P/88P/168P/328P

10. System Control and Reset

10.1 Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution

from the Reset Vector. Fo r the ATm ega168P, the instruct ion placed at the Reset Vecto r must be

a JMP – Absolute Jump – instruc tion to the reset handling routine. Fo r the ATmega48P and

ATmega88P, the ins truction placed at the Reset Vect or must be an RJMP – Relative Jump –

instruction to the reset handling routine. If the program never enables an interrupt source, the

Interrupt Vectors are not used, and regular program code can be placed at these locations. This

is also the case if the Reset Vector is in the Application section while the In terr up t Vecto rs are in

the Boot section or vice versa (ATmega88P/168P only). The circuit diagram in Figure 10-1 on

page 48 shows the reset logic. Table 28-3 on page 319 defines the electrical parameters of the

reset circuitry.

The I/O ports of the AVR are im mediately reset to their initial state when a reset source goes

active. This does not require any clock source to be running.

After all reset sources have g one inactive, a delay counter is invoked, stretching the internal

reset. This allows the power to reach a stable level before normal operation starts. The time-out

period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-

ferent selections f or the delay period are presented in ”Clock Sources” on page 28.

10.2 Reset SourcesThe ATmega48P/88P/168P/328P has four sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power- on Reset

threshold (VPOT).

• External Reset. The MCU is reset when a low le vel is present on the RESET p in f or longer than

the minimum pulse length.

• Watchdog System Reset. The MCU is reset when the Watchdog Timer pe riod expires and the

Watchdog System Reset mode is enabled.

• Brown- out Reset. The MCU is reset when th e supply voltage VCC is below the Bro wn-out Reset

threshold (VBOT) and the Brown-out Detecto r is enabled.

48 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 10-1. Reset Logic

10.3 Po wer-on Reset

A Power-on Reset (POR) pulse is ge nerated by an On-chip detection circuit. The detection level

is defined in ”System and Reset Characteristics” on page 319. The POR is activated whenever

VCC is below the detection level. The POR circuit can be used to trigger the start-up Reset, as

well as to detect a failure in supply voltage.

A Power-on Reset (POR) cir cuit ensures that the device is reset from Power-on . Reaching the

Power-on Reset threshold voltage invokes the delay counter, which determines how long the

device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay,

when VCC decreases below the detection level.

Figure 10-2. MCU Start-up, RESET Tied to VCC

MCU Status

Brown-out

Reset Circuit

BODLEVEL [2..0]

Delay Counters

CKSEL[3:0]

TIMEOUT

WDRF

BORF

EXTRF

PORF

DATA BU S

Clock

Generator

SPIKE

FILTER

Pull-up Resistor

Watchdog

Oscillator

SUT[1:0]

Power-on Reset

Circuit

RSTDISBL

RESET

IME-OUT

NTERNAL

RESET

TOUT

POT

RST

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ATmega48P/88P/168P/328P

Figure 10-3. MCU Start-up, RESET Extended Externally

10.4 External ResetAn External Reset is generated by a low level on the RESET pin. Reset pulses longer than the

minimum pulse width (see ”System and Reset Characteristics” on page 319) will generate a

reset, even if the clock is not running. Sh orter pulses are not guaranteed to generate a re set.

When the applied signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the

delay counter starts the MCU after the Time-out period – tTOUT – has expired. The External Reset

can be disabled by the RSTDISBL fuse, see Table 27-7 on page 297.

Figure 10-4. External Reset During Operation

10.5 Brown-out Detection

ATmega48P/88P/168P/328P has an On-chip Brown-out Detection (BOD) circuit for monitoring

the VCC level during ope ration by comparing it to a fixed trigger level. The trigge r level for the

BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure

spike free Brown-o ut Detection. The hyster esis on the detection lev el should be interpret ed as

VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.When the BOD is enabled, and VCC

decreases to a value below the trigger level (VBOT- in Figure 10-5 on page 50), the Brown-out

Reset is immediately activated. When VCC increases above the trigger level (VBOT+ in Figure 10 -

5 on page 50), the delay counter starts the MCU after the Time-out period tTOUT has expired.

The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for

longer than tBOD given in ”System and Reset Characteristics” on page 319.

RESET

IME-OUT

NTERNAL

RESET

TOUT

POT

RST

VCC

50 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 10-5. Brown-out Reset During Operation

10.6 Watchdog System Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On

the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to

page 51 fo r details on operation of the Watchdog Timer.

Figure 10-6. Watchdog System Reset During Operation

10.7 Internal Voltage Reference

ATmega48P/88P/168P/328P features an internal bandgap reference. This reference is used for

Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC.

10.7.1 Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time tha t may influence the way it should be used. T he

start-up time is given in ”System and Reset Characteristics” on page 319. To save power, the

reference is not always turned on. The reference is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [2:0] Fuses).

2. When the bandg ap reference is connected to the Analog Comparator (by setting the

AC BG bit in ACSR ).

3. When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user

must always allow the reference to start up before the output from the Analog Comparator or

VCC

RESET

IME-OUT

NTERNAL

RESET

VBOT- VBOT+

tTOUT

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ATmega48P/88P/168P/328P

ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three

conditions above to ensure that the reference is turned off before entering Power-down mode.

10.8 Watchdog Timer

10.8.1 Features •Clocked from separate On-chip Oscillator

•3 Operating modes

–Interrupt

– System Reset

– Interrupt and System Reset

•Selectable Time-out period from 16ms to 8s

•Possible Hardware fuse Watchdog al ways on (WDTON) for fail-safe mode

10.8.2 Overview ATmega48P/88P/168P/328P has an Enhanced Watchdog Timer (WDT). The WDT is a timer

counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a sys-

tem reset when the counter reaches a given time-out value. In normal operation mode, it is

required that the system uses the WDR - Watchdog Timer Reset - instr uction to restart the

counter before the time-out value is reached. If the system doesn't restart the counter, an inter-

rupt or system reset will be issued.

Figure 10-7. Watchdog Timer

In Interrupt mo de, the WDT gives an int errupt wh en the time r expires. This int errupt can be used

to wake the device from sleep-modes, and also as a general system timer. One example is to

limit the maximum time allowed for certain operations, giving an interrupt when the operation

has run longer than e xpected. In System Reset mode, th e WDT gives a reset when the timer

expires. This is typically used to prevent system hang-up in case of runaway code. The third

mode, Interrupt and System Reset mode, combines the other two modes by first giving an inter-

rupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown

by saving critical parameters before a system reset.

The Watchdog always on (WD T ON) fuse, if programmed, w ill force the W atchdog Timer to Sys-

tem Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt

128kHz

OSCILLATOR

OSC/2K

OSC/4K

OSC/8K

OSC/16K

OSC/32K

OSC/64K

OSC/128K

OSC/256K

OSC/512K

OSC/1024K

WDP0

WDP1

WDP2

WDP3

WATCHDOG

RESET

WDE

WDIF

WDIE

MCU RESET

INTERRUPT

52 8025D–AVR–03/08

ATmega48P/88P/168P/328P

mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alter-

ations to the Watchdog set-up m ust follow timed sequences. The sequen ce for clearing WDE

and changing time-out configuration is as follows:

1. In the same oper ation, write a logic one to the W atc hdog change enable bit (WDCE) and

WDE. A logic one must be written to WDE regardless of the previous value of the WDE

bit.

2. Within the next four clock cycles, write the WDE and Watchd og prescaler bits (WDP) as

desired, but with the WDCE bit cleared. This must be done in one operation.

The following code example shows one assembly and one C function for turning off the Watch-

dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts

globally) so that no interrupts will occur during the execution of these functions.

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ATmega48P/88P/168P/328P

Note: 1. See ”About Code Examples” on page 8.

Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out

condition, the device will be reset and the Watchdog Timer will stay enabled. If the cod e is not

set up to handle t he Watchdog , this might lead t o an eternal loop o f time-out r esets. To avoid this

situation, the application software should always clear the Watchdog System Reset Flag

(WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use.

Assembly Code Example(1)

WDT_off:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Clear WDRF in MCUSR

in r16, MCUSR

andi r16, (0xff & (0<<WDRF))

out MCUSR, r16

; Write logical one to WDCE and WDE

; Keep old prescaler setting to prevent unintentional time-out

lds r16, WDTCSR

ori r16, (1<<WDCE) | (1<<WDE)

sts WDTCSR, r16

; Turn off WDT

ldi r16, (0<<WDE)

sts WDTCSR, r16

; Turn on global interrupt

sei

ret

C Code Example(1)

void WDT_off(void)

{

__disable_interrupt();

__watchdog_reset();

/* Clear WDRF in MCUSR */

MCUSR &= ~(1<<WDRF);

/* Write logical one to WDCE and WDE */

/* Keep old prescaler setting to prevent unintentional time-out */

WDTCSR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCSR = 0x00;

__enable_interrupt();

}

54 8025D–AVR–03/08

ATmega48P/88P/168P/328P

The following code example shows one assembly and one C function for changing the time-out

value of the Watchdog Timer.

Note: 1. See ”About Code Examples” on page 8.

Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change

in the WDP bits can result in a time -out when switching to a shorter time-out perio d.

Assembly Code Example(1)

WDT_Prescaler_Change:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Start timed sequence

lds r16, WDTCSR

ori r16, (1<<WDCE) | (1<<WDE)

sts WDTCSR, r16

; -- Got four cycles to set the new values from here -

; Set new prescaler(time-out) value = 64K cycles (~0.5 s)

ldi r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)

sts WDTCSR, r16

; -- Finished setting new values, used 2 cycles -

; Turn on global interrupt

sei

ret

C Code Example(1)

void WDT_Prescaler_Change(void)

{

__disable_interrupt();

__watchdog_reset();

/* Start timed equence */

WDTCSR |= (1<<WDCE) | (1<<WDE);

/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */

WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);

__enable_interrupt();

}

8025D–AVR–03/08

ATmega48P/88P/168P/328P

10.9 Register Description

10.9.1 MCUSR – MCU Status Register

The MCU Status Register provides information on which reset source caused an MCU reset.

• Bit 7..4: Res: Reserved Bits

These bits are unused bits in the ATmega48P/88P/168P/328P, and will always read as zero.

• Bit 3 – WDRF: Watchdog System Reset Flag

This bit is set if a Watchdog System Reset occurs. The bit is reset by a Power-on Reset, or by

writing a logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Po wer-on Reset, or by writing a

logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occu rs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then

Reset the MCUSR as early as possible in the program. If the register is cleared before another

reset occurs, the source of the reset can be found by examining the Reset Flags.

10.9.2 WDTCSR – Watchdog Timer Control Register

• Bit 7 - WDIF: Watchdog Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-

ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt

handling vector. Altern atively, WDIF is cle ared by writ ing a logic on e to the flag. Whe n the I -bit in

SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.

• Bit 6 - WDIE: Watchdog Interrupt Enable

When this bit is written to o ne and the I-bit in t he Status Regist er is set, the Watchdog Interrupt is

enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt

Mode, and the corresponding in terrupt is executed if time-out in the Watchdog Timer occurs. If

WDE is set, the Watchdog Timer is in Inte rrupt a nd Syst em Reset Mode . The firs t time -out in t he

Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and

Bit 76543210

0x35 (0x55) ––––WDRFBORFEXTRFPORFMCUSR

Read/Write RRRRR/WR/WR/WR/W

Initial Value0000 See Bit Description

Bit 76543210

(0x60) WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 WDTCSR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 X 0 0 0

56 8025D–AVR–03/08

ATmega48P/88P/168P/328P

WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for

keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System

Reset Mode, WDIE must be se t afte r e ach in terr up t. Th is sh ou ld ho wever not b e done with in t he

interrupt service routine itself, as this might compromise the safety-function of the Watchdog

System Reset mode. If the interrupt is not executed before the next time-out, a System Reset

will be applied.

Note: 1. WDTON Fuse set to “0” means programmed and “1” means unprogrammed.

• Bit 4 - WDCE: Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,

and/or change the prescaler bits, WDCE must be set.

Once written to one, hardware will clear WDCE after four clock cycles.

• Bit 3 - WDE: Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is

set. To clear WDE, WDRF must be cleared fir st. This feature ensures multiple r esets during con-

ditions causing failure, and a safe start-up after the failure.

• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0

The WDP3..0 bits determine the Watchdo g Timer prescaling when the Wa tchdog Timer is run-

ning. The different prescaling values and their corresponding time-out periods are shown in

Table 10-2 on page 56.

Table 10-1. Watchdog Timer Configuration

WDTON(1) WDE WDIE Mode Action on Time-out

1 0 0 Stopped None

1 0 1 Interrupt Mode Interrupt

1 1 0 System Reset Mode Reset

111

Interrupt and System Reset

Mode Interrupt, then go to System

Reset Mode

0 x x System Reset Mode Reset

Table 10-2. Watchdog Timer Prescale Select

WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator

Cycles Typical Time-out at

VCC = 5.0V

0 0 0 0 2K (2048) cycles 16 ms

0 0 0 1 4K (4096) cycles 32 ms

0 0 1 0 8K (8192) cycles 64 ms

0 0 1 1 16K (16384) cycles 0.125 s

0 1 0 0 32K (32768) cycles 0.25 s

0 1 0 1 64K (65536) cycles 0.5 s

0 1 1 0 128K (131072) cycles 1.0 s

0 1 1 1 256K (262144) cycles 2.0 s

8025D–AVR–03/08

ATmega48P/88P/168P/328P

1 0 0 0 512K (524288) cycles 4.0 s

1 0 0 1 1024K (1048576) cycles 8.0 s

1010

Reserved

1011

1100

1101

1110

1111

Table 10-2. Watchdog Timer Prescale Select (Continued)

WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator

Cycles Typical Time-out at

VCC = 5.0V

58 8025D–AVR–03/08

ATmega48P/88P/168P/328P

11. Interrupts This section describes the specifics of the interrupt handling as performed in

ATmega48P/88P/1 68P/328P. For a general explana tion of the AVR interrupt handling , refer to

”Reset and Interrupt Handling” on page 15.

The interrupt vectors in ATmega48P, ATmega88P, ATmega168P, and ATmega328P are gener-

ally the same, with the following differences:

• Each Interrupt Vector occupies two instruction words in ATmega168P and ATmega328P, and

one instruction word in ATmega48P and ATmega88P.

• ATmega48P does not hav e a separate Boot Loader Section. In ATmega88P, ATmega168P,

and ATmega328P, the Reset Vector is aff ected b y the BOO TRST fuse , and the Inter rupt Vector

start address is affected by the IVSEL bit in MCUCR.

11.1 Interrupt Vectors in ATmega48P

Table 11-1. Reset and Interrupt Vectors in ATmega48P

Vector No. Program Address Source Interrupt Definition

1 0x000 RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset

2 0x001 INT0 Exter nal Interrupt Request 0

3 0x002 INT1 Exter nal Interrupt Request 1

4 0x003 PCINT0 Pin Change Interrup t Request 0

5 0x004 PCINT1 Pin Change Interrup t Request 1

6 0x005 PCINT2 Pin Change Interrup t Request 2

7 0x006 WDT Watchdog Time-out Interrupt

8 0x007 TIMER2 COMPA Ti mer/Counter2 Compare Ma tch A

9 0x008 TIMER2 COMPB Ti m er/Counter2 Compare Ma tch B

10 0x009 TIMER2 OVF Timer/Counter2 Overflow

11 0x00A TIMER1 CAPT Timer/Counter1 Capture Event

12 0x00B TIMER1 COMPA Timer/Counter1 Compare Match A

13 0x00C TIMER1 COMPB Timer/Coutner1 Compare Match B

14 0x00D TIMER1 OVF Timer/Counter1 Overflow

15 0x00E TIMER0 COMPA Timer/Counter0 Compare Match A

16 0x00F TIMER0 COMPB Timer/Counter0 Co mpare Match B

17 0x010 TIMER0 OVF Timer/Counter0 Overflow

18 0x011 SPI, STC SPI Serial Transfer Complete

19 0x012 USART, RX USART Rx Complete

20 0x013 USART, UDRE USART, Data Register Empty

21 0x014 USART, TX USART, Tx Complete

22 0x015 ADC ADC Conversion Complete

23 0x016 EE READY EEPROM Ready

8025D–AVR–03/08

ATmega48P/88P/168P/328P

The most typical and general program setup for the Reset and Interrupt Vector Addresses in

ATmega48P is:

Address Labels Code Comments

0x000 rjmp RESET ; Reset Handler

0x001 rjmp EXT_INT0 ; IRQ0 Handler

0x002 rjmp EXT_INT1 ; IRQ1 Handler

0x003 rjmp PCINT0 ; PCINT0 Handler

0x004 rjmp PCINT1 ; PCINT1 Handler

0x005 rjmp PCINT2 ; PCINT2 Handler

0x006 rjmp WDT ; Watchdog Timer Handler

0x007 rjmp TIM2_COMPA ; Timer2 Compare A Handler

0x008 rjmp TIM2_COMPB ; Timer2 Compare B Handler

0x009 rjmp TIM2_OVF ; Timer2 Overflow Handler

0x00A rjmp TIM1_CAPT ; Timer1 Capture Handler

0x00B rjmp TIM1_COMPA ; Timer1 Compare A Handler

0x00C rjmp TIM1_COMPB ; Timer1 Compare B Handler

0x00D rjmp TIM1_OVF ; Timer1 Overflow Handler

0x00E rjmp TIM0_COMPA ; Timer0 Compare A Handler

0x00F rjmp TIM0_COMPB ; Timer0 Compare B Handler

0x010 rjmp TIM0_OVF ; Timer0 Overflow Handler

0x011 rjmp SPI_STC ; SPI Transfer Complete Handler

0x012 rjmp USART_RXC ; USART, RX Complete Handler

0x013 rjmp USART_UDRE ; USART, UDR Empty Handler

0x014 rjmp USART_TXC ; USART, TX Complete Handler

0x015 rjmp ADC ; ADC Conversion Complete Handler

0x016 rjmp EE_RDY ; EEPROM Ready Handler

0x017 rjmp ANA_COMP ; Analog Comparator Handler

0x018 rjmp TWI ; 2-wire Serial Interface Handler

0x019 rjmp SPM_RDY ; Store Program Memory Ready Handler

;

0x01ARESET: ldi r16, high(RAMEND); Main program start

0x01B out SPH,r16 ; Set Stack Pointer to top of RAM

0x01C ldi r16, low(RAMEND)

0x01D out SPL,r16

0x01E sei ; Enable interrupts

0x01F <instr> xxx

... ... ... ...

24 0x017 ANALOG COMP Anal og Comparator

25 0x018 TWI 2-wire Serial Interface

26 0x019 SPM READY Store Program Memory Ready

Table 11-1. Reset and Interrupt Vectors in ATmega48P (Continued)

Vector No. Program Address Source Interrupt Definition

60 8025D–AVR–03/08

ATmega48P/88P/168P/328P

11.2 Interrupt Vectors in ATmega88P

Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see ”Boot Loader Sup-

port – Read-While-Write Self-Programming, ATmega88P, ATmega168P and ATmega328P” on page 278.

2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of

each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section.

Table 11-3 on page 61 shows reset and Interrupt Vectors placement for the various combina-

tions of BOOTRST and IVSEL settings. If the program never en ables an interrupt source, the

Interrupt Vectors are not used, and regular program code can be placed at these locations. This

is also the case if the Reset Vector is in the Application section while the In terr up t Vecto rs are in

the Boot section or vice versa.

Table 11-2. Reset and Interrupt Vectors in ATmega88P

Vector No. Program

Address(2) Source Interrupt Definition

1 0x000(1) RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset

2 0x001 INT0 External Inte rrupt Request 0

3 0x002 INT1 External Inte rrupt Request 1

4 0x003 PCINT0 Pin Change Interrupt Request 0

5 0x004 PCINT1 Pin Change Interrupt Request 1

6 0x005 PCINT2 Pin Change Interrupt Request 2

7 0x006 WDT Watchdog Time-out Interrupt

8 0x007 TIMER2 COMPA Timer/Counter2 Compare Match A

9 0x008 TIMER2 COMPB Timer/Counter2 Compare Match B

10 0x009 TIMER2 OVF Timer/Counter2 Overflow

11 0x00A TIMER1 CAPT Timer/Counter1 Capture Event

12 0x00B TIMER1 COMPA Timer/Counter1 Compare Match A

13 0x00C TIMER1 COMPB Timer/Coutner1 Compare Match B

14 0x00D TIMER1 OVF Timer/Counter1 Overflow

15 0x00E TIMER0 COMPA Timer/Counter0 Compare Match A

16 0x00F TIMER0 COMPB Timer/Counter0 Compare Match B

17 0x010 TIMER0 OVF Timer/Counter0 Overflow

18 0x011 SPI, STC SPI Serial Transfer Complete

19 0x012 USART, RX USART Rx Complete

20 0x013 USART, UDRE USART, Data Register Empty

21 0x014 USART, TX USART, Tx Complete

22 0x015 ADC ADC Conversion Complete

23 0x016 EE READY EEPROM Ready

24 0x017 ANALOG COMP Ana log Comparator

25 0x018 TWI 2-wire Serial Interface

26 0x019 SPM READY Store Program Memory Ready

8025D–AVR–03/08

ATmega48P/88P/168P/328P

Note: 1. The Boot Reset Address is shown in Table 26-6 on page 289. For the BOOTRST Fuse “1”

means unprogrammed while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt Vector Addresses in

ATmega88P is:

Address Labels Code Comments

0x000 rjmp RESET ; Reset Handler

0x001 rjmp EXT_INT0 ; IRQ0 Handler

0x002 rjmp EXT_INT1 ; IRQ1 Handler

0x003 rjmp PCINT0 ; PCINT0 Handler

0x004 rjmp PCINT1 ; PCINT1 Handler

0x005 rjmp PCINT2 ; PCINT2 Handler

0x006 rjmp WDT ; Watchdog Timer Handler

0x007 rjmp TIM2_COMPA ; Timer2 Compare A Handler

0X008 rjmp TIM2_COMPB ; Timer2 Compare B Handler

0x009 rjmp TIM2_OVF ; Timer2 Overflow Handler

0x00A rjmp TIM1_CAPT ; Timer1 Capture Handler

0x00B rjmp TIM1_COMPA ; Timer1 Compare A Handler

0x00C rjmp TIM1_COMPB ; Timer1 Compare B Handler

0x00D rjmp TIM1_OVF ; Timer1 Overflow Handler

0x00E rjmp TIM0_COMPA ; Timer0 Compare A Handler

0x00F rjmp TIM0_COMPB ; Timer0 Compare B Handler

0x010 rjmp TIM0_OVF ; Timer0 Overflow Handler

0x011 rjmp SPI_STC ; SPI Transfer Complete Handler

0x012 rjmp USART_RXC ; USART, RX Complete Handler

0x013 rjmp USART_UDRE ; USART, UDR Empty Handler

0x014 rjmp USART_TXC ; USART, TX Complete Handler

0x015 rjmp ADC ; ADC Conversion Complete Handler

0x016 rjmp EE_RDY ; EEPROM Ready Handler

0x017 rjmp ANA_COMP ; Analog Comparator Handler

0x018 rjmp TWI ; 2-wire Serial Interface Handler

0x019 rjmp SPM_RDY ; Store Program Memory Ready Handler

;

0x01ARESET: ldi r16, high(RAMEND); Main program start

0x01B out SPH,r16 ; Set Stack Pointer to top of RAM

0x01C ldi r16, low(RAMEND)

0x01D out SPL,r16

0x01E sei ; Enable interrupts

0x01F <instr> xxx

Table 11-3. Reset and Interrupt Vectors Placement in ATmega88P(1)

BOOTRST IVSEL Reset Address Interrupt Vectors Start Address

1 0 0x000 0x001

1 1 0x000 Boot Reset Address + 0x001

0 0 Boot Reset Address 0x001

0 1 Boot Reset Address Boot Reset Address + 0x001

62 8025D–AVR–03/08

ATmega48P/88P/168P/328P

When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the

IVSEL bit in the MCUCR Register is set before an y interrupts are enabled, the most typical and

general program setup for the Reset and Interrupt Vector Addresses in ATmega88P is:

Address Labels Code Comments

0x000 RESET: ldi r16,high(RAMEND); Main program start

0x001 out SPH,r16 ; Set Stack Pointer to top of RAM

0x002 ldi r16,low(RAMEND)

0x003 out SPL,r16

0x004 sei ; Enable interrupts

0x005 <instr> xxx

;

.org 0xC01

0xC01 rjmp EXT_INT0 ; IRQ0 Handler

0xC02 rjmp EXT_INT1 ; IRQ1 Handler

... ... ... ;

0xC19 rjmp SPM_RDY ; Store Program Memory Ready Handler

When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most

typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega88P

is:

Address Labels Code Comments

.org 0x001

0x001 rjmp EXT_INT0 ; IRQ0 Handler

0x002 rjmp EXT_INT1 ; IRQ1 Handler

... ... ... ;

0x019 rjmp SPM_RDY ; Store Program Memory Ready Handler

;

.org 0xC00

0xC00 RESET: ldi r16,high(RAMEND); Main program start

0xC01 out SPH,r16 ; Set Stack Pointer to top of RAM

0xC02 ldi r16,low(RAMEND)

0xC03 out SPL,r16

0xC04 sei ; Enable interrupts

0xC05 <instr> xxx

When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL

bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general

program setup for the Reset and Interrupt Vector Addresses in ATmega88P is:

Address Labels Code Comments

;

.org 0xC00

0xC00 rjmp RESET ; Reset handler

0xC01 rjmp EXT_INT0 ; IRQ0 Handler

0xC02 rjmp EXT_INT1 ; IRQ1 Handler

... ... ... ;

0xC19 rjmp SPM_RDY ; Store Program Memory Ready Handler

;

0xC1A RESET: ldi r16,high(RAMEND); Main program start

8025D–AVR–03/08

ATmega48P/88P/168P/328P

0xC1B out SPH,r16 ; Set Stack Pointer to top of RAM

0xC1C ldi r16,low(RAMEND)

0xC1D out SPL,r16

0xC1E sei ; Enable interrupts

0xC1F <instr> xxx

11.3 Interrupt Vectors in ATmega168P

Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see ”Boot Loader Sup-

port – Read-While-Write Self-Programming, ATmega88P, ATmega168P and ATmega328P” on page 278.

2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of

each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section.

Table 11-4. Reset and Interrupt Vectors in ATmega168P

VectorNo. Program

Address(2) Source Interrupt Definition

1 0x0000(1) RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset

2 0x0002 INT0 External Interrupt Requ est 0

3 0x0004 INT1 External Interrupt Requ est 1

4 0x0006 PCINT0 Pin Change Interrupt Request 0

5 0x0008 PCINT1 Pin Change Interrupt Request 1

6 0x000A PCINT2 Pin Change Interrupt Request 2

7 0x000C WDT Watchdog Time-out Interrupt

8 0x000E TIMER2 COMPA Timer/Counter2 Comp are Match A

9 0x0010 TIMER2 COMPB T imer/Counter2 Compare Match B

10 0x0012 TIMER2 OVF Timer/Counter2 Overflow

11 0x0014 TIMER1 CAPT Timer/Counter1 Capture Event

12 0x0016 TIMER1 COMPA Timer/Counter1 Compare Match A

13 0x0018 TIMER1 COMPB Timer/Coutner1 Compare Match B

14 0x001 A TIMER1 OVF Timer/C ounter1 Overflow

15 0x001C TIMER0 COMPA Timer/Counter0 Compare Match A

16 0x001E TIMER0 COMPB Timer/Counter0 Compare Match B

17 0x0020 TIMER0 OVF Timer/Counter0 Overflow

18 0x0022 SPI, STC SPI Serial Transfer Complete

19 0x0024 USART, RX USART Rx Complete

20 0x0026 USART, UDRE USART, Data Register Empty

21 0x0028 USART, TX USART, Tx Complete

22 0x002 A ADC ADC Conversion Complete

23 0x002C EE READY EEPROM Ready

24 0x002E ANALOG COMP Analog Comparator

25 0x0030 TWI 2-wire Serial Interface

26 0x0032 SPM READY Store Program Memory Ready

64 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Table 11-5 on page 64 shows reset and Interrupt Vectors placement for the various combina-

tions of BOOTRST and IVSEL settings. If the program never en ables an interrupt source, the

Interrupt Vectors are not used, and regular program code can be placed at these locations. This

is also the case if the Reset Vector is in the Application section while the In terr up t Vecto rs are in

the Boot section or vice versa.

Note: 1. The Boot Reset Address is shown in Table 26-6 on page 289. For the BOOTRST Fuse “1”

means unprogrammed while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt Vector Addresses in

ATmega168P is:

Address Labels Code Comments

0x0000 jmp RESET ; Reset Handler

0x0002 jmp EXT_INT0 ; IRQ0 Handler

0x0004 jmp EXT_INT1 ; IRQ1 Handler

0x0006 jmp PCINT0 ; PCINT0 Handler

0x0008 jmp PCINT1 ; PCINT1 Handler

0x000A jmp PCINT2 ; PCINT2 Handler

0x000C jmp WDT ; Watchdog Timer Handler

0x000E jmp TIM2_COMPA ; Timer2 Compare A Handler

0x0010 jmp TIM2_COMPB ; Timer2 Compare B Handler

0x0012 jmp TIM2_OVF ; Timer2 Overflow Handler

0x0014 jmp TIM1_CAPT ; Timer1 Capture Handler

0x0016 jmp TIM1_COMPA ; Timer1 Compare A Handler

0x0018 jmp TIM1_COMPB ; Timer1 Compare B Handler

0x001A jmp TIM1_OVF ; Timer1 Overflow Handler

0x001C jmp TIM0_COMPA ; Timer0 Compare A Handler

0x001E jmp TIM0_COMPB ; Timer0 Compare B Handler

0x0020 jmp TIM0_OVF ; Timer0 Overflow Handler

0x0022 jmp SPI_STC ; SPI Transfer Complete Handler

0x0024 jmp USART_RXC ; USART, RX Complete Handler

0x0026 jmp USART_UDRE ; USART, UDR Empty Handler

0x0028 jmp USART_TXC ; USART, TX Complete Handler

0x002A jmp ADC ; ADC Conversion Complete Handler

0x002C jmp EE_RDY ; EEPROM Ready Handler

0x002E jmp ANA_COMP ; Analog Comparator Handler

0x0030 jmp TWI ; 2-wire Serial Interface Handler

0x0032 jmp SPM_RDY ; Store Program Memory Ready Handler

;

0x0033RESET: ldi r16, high(RAMEND); Main program start

Table 11-5. Reset and Interrupt Vectors Placement in ATmega168P(1)

BOOTRST IVSEL Reset Address Interrupt Vectors Start Address

1 0 0x000 0x002

1 1 0x000 Boot Reset Address + 0x0002

0 0 Boot Reset Address 0x002

0 1 Boot Reset Address Boot Reset Address + 0x0002

8025D–AVR–03/08

ATmega48P/88P/168P/328P

0x0034 out SPH,r16 ; Set Stack Pointer to top of RAM

0x0035 ldi r16, low(RAMEND)

0x0036 out SPL,r16

0x0037 sei ; Enable interrupts

0x0038 <instr> xxx

... ... ... ...

When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the

IVSEL bit in the MCUCR Register is set before an y interrupts are enabled, the most typical and

general program setup for the Reset and Interrupt Vector Addresses in ATmega168P is:

Address Labels Code Comments

0x0000 RESET: ldi r16,high(RAMEND); Main program start

0x0001 out SPH,r16 ; Set Stack Pointer to top of RAM

0x0002 ldi r16,low(RAMEND)

0x0003 out SPL,r16

0x0004 sei ; Enable interrupts

0x0005 <instr> xxx

;

.org 0x1C02

0x1C02 jmp EXT_INT0 ; IRQ0 Handler

0x1C04 jmp EXT_INT1 ; IRQ1 Handler

... ... ... ;

0x1C32 jmp SPM_RDY ; Store Program Memory Ready Handler

When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most

typical and general program setup for the Reset and Interrupt Vector Addresses in

ATmega168P is:

Address Labels Code Comments

.org 0x0002

0x0002 jmp EXT_INT0 ; IRQ0 Handler

0x0004 jmp EXT_INT1 ; IRQ1 Handler

... ... ... ;

0x0032 jmp SPM_RDY ; Store Program Memory Ready Handler

;

.org 0x1C00

0x1C00 RESET: ldi r16,high(RAMEND); Main program start

0x1C01 out SPH,r16 ; Set Stack Pointer to top of RAM

0x1C02 ldi r16,low(RAMEND)

0x1C03 out SPL,r16

0x1C04 sei ; Enable interrupts

0x1C05 <instr> xxx

When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL

bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general

program setup for the Reset and Interrupt Vector Addresses in ATmega168P is:

66 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Address Labels Code Comments

;

.org 0x1C00

0x1C00 jmp RESET ; Reset handler

0x1C02 jmp EXT_INT0 ; IRQ0 Handler

0x1C04 jmp EXT_INT1 ; IRQ1 Handler

... ... ... ;

0x1C32 jmp SPM_RDY ; Store Program Memory Ready Handler

;

0x1C33 RESET: ldi r16,high(RAMEND); Main program start

0x1C34 out SPH,r16 ; Set Stack Pointer to top of RAM

0x1C35 ldi r16,low(RAMEND)

0x1C36 out SPL,r16

0x1C37 sei ; Enable interrupts

0x1C38 <instr> xxx

11.4 Interrupt Vectors in ATmega328P

Table 11-6. Reset and Interrupt Vectors in ATmega328P

VectorNo. Program

Address(2) Source Interrupt Definition

1 0x0000(1) RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset

2 0x0002 INT0 External Interrupt Requ est 0

3 0x0004 INT1 External Interrupt Requ est 1

4 0x0006 PCINT0 Pin Change Interrupt Request 0

5 0x0008 PCINT1 Pin Change Interrupt Request 1

6 0x000A PCINT2 Pin Change Interrupt Request 2

7 0x000C WDT Watchdog Time-out Interrupt

8 0x000E TIMER2 COMPA Timer/Counter2 Comp are Match A

9 0x0010 TIMER2 COMPB T imer/Counter2 Compare Match B

10 0x0012 TIMER2 OVF Timer/Counter2 Overflow

11 0x0014 TIMER1 CAPT Timer/Counter1 Capture Event

12 0x0016 TIMER1 COMPA Timer/Counter1 Compare Match A

13 0x0018 TIMER1 COMPB Timer/Coutner1 Compare Match B

14 0x001 A TIMER1 OVF Timer/C ounter1 Overflow

15 0x001C TIMER0 COMPA Timer/Counter0 Compare Match A

16 0x001E TIMER0 COMPB Timer/Counter0 Compare Match B

17 0x0020 TIMER0 OVF Timer/Counter0 Overflow

18 0x0022 SPI, STC SPI Serial Transfer Complete

19 0x0024 USART, RX USART Rx Complete

20 0x0026 USART, UDRE USART, Data Register Empty

21 0x0028 USART, TX USART, Tx Complete

8025D–AVR–03/08

ATmega48P/88P/168P/328P

Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see ”Boot Loader Sup-

port – Read-While-Write Self-Programming, ATmega88P, ATmega168P and ATmega328P” on page 278.

2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of

each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section.

Table 11-7 on page 67 shows reset and Interrupt Vectors placement for the various combina-

tions of BOOTRST and IVSEL settings. If the program never en ables an interrupt source, the

Interrupt Vectors are not used, and regular program code can be placed at these locations. This

is also the case if the Reset Vector is in the Application section while the In terr up t Vecto rs are in

the Boot section or vice versa.

Note: 1. The Boot Reset Address is shown in Table 26-6 on page 289. For the BOOTRST Fuse “1”

means unprogrammed while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt Vector Addresses in

ATmega328P is:

Address Labels Code Comments

0x0000 jmp RESET ; Reset Handler

0x0002 jmp EXT_INT0 ; IRQ0 Handler

0x0004 jmp EXT_INT1 ; IRQ1 Handler

0x0006 jmp PCINT0 ; PCINT0 Handler

0x0008 jmp PCINT1 ; PCINT1 Handler

0x000A jmp PCINT2 ; PCINT2 Handler

0x000C jmp WDT ; Watchdog Timer Handler

0x000E jmp TIM2_COMPA ; Timer2 Compare A Handler

0x0010 jmp TIM2_COMPB ; Timer2 Compare B Handler

0x0012 jmp TIM2_OVF ; Timer2 Overflow Handler

0x0014 jmp TIM1_CAPT ; Timer1 Capture Handler

0x0016 jmp TIM1_COMPA ; Timer1 Compare A Handler

0x0018 jmp TIM1_COMPB ; Timer1 Compare B Handler

0x001A jmp TIM1_OVF ; Timer1 Overflow Handler

22 0x002 A ADC ADC Conversion Complete

23 0x002C EE READY EEPROM Ready

24 0x002E ANALOG COMP Analog Comparator

25 0x0030 TWI 2-wire Serial Interface

26 0x0032 SPM READY Store Program Memory Ready

Table 11-6. Reset and Interrupt Vectors in ATmega328P (Continued)

VectorNo. Program

Address(2) Source Interrupt Definition

Table 11-7. Reset and Interrupt Vectors Placement in ATmega328P(1)

BOOTRST IVSEL Reset Address Interrupt Vectors Start Address

1 0 0x000 0x002

1 1 0x000 Boot Reset Address + 0x0002

0 0 Boot Reset Address 0x002

0 1 Boot Reset Address Boot Reset Address + 0x0002

68 8025D–AVR–03/08

ATmega48P/88P/168P/328P

0x001C jmp TIM0_COMPA ; Timer0 Compare A Handler

0x001E jmp TIM0_COMPB ; Timer0 Compare B Handler

0x0020 jmp TIM0_OVF ; Timer0 Overflow Handler

0x0022 jmp SPI_STC ; SPI Transfer Complete Handler

0x0024 jmp USART_RXC ; USART, RX Complete Handler

0x0026 jmp USART_UDRE ; USART, UDR Empty Handler

0x0028 jmp USART_TXC ; USART, TX Complete Handler

0x002A jmp ADC ; ADC Conversion Complete Handler

0x002C jmp EE_RDY ; EEPROM Ready Handler

0x002E jmp ANA_COMP ; Analog Comparator Handler

0x0030 jmp TWI ; 2-wire Serial Interface Handler

0x0032 jmp SPM_RDY ; Store Program Memory Ready Handler

;

0x0033RESET: ldi r16, high(RAMEND); Main program start

0x0034 out SPH,r16 ; Set Stack Pointer to top of RAM

0x0035 ldi r16, low(RAMEND)

0x0036 out SPL,r16

0x0037 sei ; Enable interrupts

0x0038 <instr> xxx

... ... ... ...

When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the

IVSEL bit in the MCUCR Register is set before an y interrupts are enabled, the most typical and

general program setup for the Reset and Interrupt Vector Addresses in ATmega328P is:

Address Labels Code Comments

0x0000 RESET: ldi r16,high(RAMEND); Main program start

0x0001 out SPH,r16 ; Set Stack Pointer to top of RAM

0x0002 ldi r16,low(RAMEND)

0x0003 out SPL,r16

0x0004 sei ; Enable interrupts

0x0005 <instr> xxx

;

.org 0x3C02

0x3C02 jmp EXT_INT0 ; IRQ0 Handler

0x3C04 jmp EXT_INT1 ; IRQ1 Handler

... ... ... ;

0x3C32 jmp SPM_RDY ; Store Program Memory Ready Handler

When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most

typical and general program setup for the Reset and Interrupt Vector Addresses in

ATmega328P is:

Address Labels Code Comments

.org 0x0002

0x0002 jmp EXT_INT0 ; IRQ0 Handler

0x0004 jmp EXT_INT1 ; IRQ1 Handler

... ... ... ;

0x0032 jmp SPM_RDY ; Store Program Memory Ready Handler

;

8025D–AVR–03/08

ATmega48P/88P/168P/328P

.org 0x3C00

0x3C00 RESET: ldi r16,high(RAMEND); Main program start

0x3C01 out SPH,r16 ; Set Stack Pointer to top of RAM

0x3C02 ldi r16,low(RAMEND)

0x3C03 out SPL,r16

0x3C04 sei ; Enable interrupts

0x3C05 <instr> xxx

When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL

bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general

program setup for the Reset and Interrupt Vector Addresses in ATmega328P is:

Address Labels Code Comments

;

.org 0x3C00

0x3C00 jmp RESET ; Reset handler

0x3C02 jmp EXT_INT0 ; IRQ0 Handler

0x3C04 jmp EXT_INT1 ; IRQ1 Handler

... ... ... ;

0x3C32 jmp SPM_RDY ; Store Program Memory Ready Handler

;

0x3C33 RESET: ldi r16,high(RAMEND); Main program start

0x3C34 out SPH,r16 ; Set Stack Pointer to top of RAM

0x3C35 ldi r16,low(RAMEND)

0x3C36 out SPL,r16

0x3C37 sei ; Enable interrupts

0x3C38 <instr> xxx

11.5 Register Description

11.5.1 Moving Interrupts Between Application and Boot Space, ATmega88P, ATmega168P and ATmega328P

The MCU Control Register controls the placement of the Interrupt Vector table.

11.5.2 MCUCR – MCU Control Register

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash

memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot

Loader section of the Flash. The actual add ress of the start of the Boot Flash Section is deter-

mined by the BOOTSZ Fuses. Refer to the section ”Boot Loader Support – Read-While-Write

Self-Programming, ATmega8 8P, ATmega168P and ATmega328P” on p age 278 for details. To

avoid unintentional changes of Interrupt Vector tables, a special write procedure must be fol-

lowed to change the IVSEL bit:

Bit 76543210

0x35 (0x55) –BODS BODSE PUD –– IVSEL IVCE MCUCR

Read/Write R R R R/W R R R/W R/W

Initial Value00000000

70 8025D–AVR–03/08

ATmega48P/88P/168P/328P

a. Write the Interrupt Vector Change Enable (IVCE) bit to one.

b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled

in the cycle IVCE is set, and they remain disabled until after the instruction following the write to

IVSEL. If IVSEL is not written, interrupts remain disa bled for four cycles. The I-bit in the Status

Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,

interrupts are disabled while ex ecuting from the Application section. If Interrupt Vectors are placed

in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while

executing from the Boot Loader section. Refer to the section ”Boot Loader Support – Read-While-

Write Self-Programming, ATmega88P, ATmega168P and ATmega328P” on page 278 for details

on Boot Lock bits.

This bit is not available in ATmega48P.

• Bit 0 – IVCE: Interrupt Vector Change Enable

The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by

hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable

interrupts, as explai ned in the IVSEL description above. See Code Example below.

This bit is not available in ATmega48P.

Assembly Code Example

Move_interrupts:

; Enable change of Interrupt Vectors

ldi r16, (1<<IVCE)

out MCUCR, r16

; Move interrupts to Boot Flash section

ldi r16, (1<<IVSEL)

out MCUCR, r16

ret

C Code Example

void Move_interrupts(void)

{

/* Enable change of Interrupt Vectors */

MCUCR = (1<<IVCE);

/* Move interrupts to Boot Flash section */

MCUCR = (1<<IVSEL);

}

8025D–AVR–03/08

ATmega48P/88P/168P/328P

12. External Interrupts

The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23..0 pins.

Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT23..0 pins

are configured as outputs. This feature provides a way of generating a software interrupt. The

pin change interrupt PCI2 will trigger if any enabled PCINT23..16 pin toggles. The pin change

interrupt PCI1 will trigger if any enabled PCINT14..8 pin toggles. The pin change interrupt PCI0

will trigger if any enabled PCINT7..0 pin toggles. The PCMSK2, PCMSK1 and PCMSK0 Regis-

ters control which pins contribute to the pin change interrupts. Pin change interrupts on

PCINT23..0 are detected asynchronously. This implies that these interrupts can be used for

waking the part also from sleep modes other than Idle mode.

The INT0 and INT1 interrupts can be triggered by a falling o r rising edge or a low level. This is

set up as indicated in the specification for the External Interrupt Control Register A – EICRA.

When the INT0 or INT1 interrupts are enabled and are configured as level triggered, the inter-

rupts will trigger as long as the pin is held low. Note that recognition of falling or rising edge

interrupts on INT0 or INT1 requires the presence of an I/O clock, described in ”Clock Systems

and their Distributio n” on page 27. Low le vel interrupt on INT0 and INT1 is dete cted asynchro-

nously. This implies that this interrupt can be used for waking the part also from sleep modes

other than Idle mod e. The I/O clock is halted in all sleep modes except Idle mode.

Note that if a level trigger ed interrupt is used for wake-up from Power-down, the required le vel

must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If

the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-

rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described

in ”System Clock and Clock Options” on page 27.

12.1 Pin Change Interrupt Timing

An example of timing of a pi n change interrupt is shown in Figure 12-1.

Figure 12-1. Timing of pin change interrupts

clk

PCINT(0)

pin_lat

pin_sync

pcint_in_(0)

pcint_syn

cint_setflag

PCIF

PCINT(0) pin_sync pcint_syn

pin_lat

D Q

pcint_setflag PC

clk clk

PCINT(0) in PCMSK(x)

pcint_in_(0) 0

72 8025D–AVR–03/08

ATmega48P/88P/168P/328P

12.2 Register Description

12.2.1 EICRA – External Interrupt Control Register A

The External Interrupt Control Register A contains control bits for interrupt sense control.

• Bit 7..4 – Res: Reserved Bits

These bits are unused bits in the ATmega48P/88P/168P/328P, and will always read as zero.

• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre-

sponding interrupt mask are set. The level and edges on the external INT1 pin that activate the

interrupt are defined in Table 12-1. The value on the INT1 pin is sampled before detecting

edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will

generate an interr upt. Shorter pulses are not gu aranteed to generate an int errupt. If low level

interrupt is selected, the low level must be held until the comple tion of the currently executing

instruction to generate an interrupt.

• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-

sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the

interrupt are defined in Table 12-2. The value on the INT0 pin is sampled before detecting

edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will

generate an interr upt. Shorter pulses are not gu aranteed to generate an int errupt. If low level

interrupt is selected, the low level must be held until the comple tion of the currently executing

instruction to generate an interrupt.

Bit 76543210

(0x69) – – – – ISC11 ISC10 ISC01 ISC00 EICRA

Read/Write R R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 12-1. Interrupt 1 Sense Control

ISC11 ISC10 Description

0 0 The low level of INT1 generates an interrupt request.

0 1 Any logical change on INT1 generates an interrupt request.

1 0 The falling edge of INT1 generates an interrupt request.

1 1 The rising edge of INT1 generates an interrupt request.

Table 12-2. Interrupt 0 Sense Control

ISC01 ISC00 Description

0 0 The low level of INT0 generates an interrupt request.

0 1 Any logical change on INT0 generates an interrupt request.

1 0 The falling edge of INT0 generates an interrupt request.

1 1 The rising edge of INT0 generates an interrupt request.

8025D–AVR–03/08

ATmega48P/88P/168P/328P

12.2.2 EIMSK – External Interrupt Mask Register

• Bit 7..2 – Res: Reserved Bits

These bits are unused bits in the ATmega48P/88P/168P/328P, and will always read as zero.

• Bit 1 – INT1: External Interrupt Request 1 Enab le

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-

nal pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the

External Interrupt Control Register A (EICRA) define whether the external interrupt is activated

on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an

interrupt reque st even if INT1 is conf igured as an out put. The corre sponding inte rrupt of Ext ernal

Interrupt Request 1 is executed from the INT1 Interrupt Vector.

• Bit 0 – INT0: External Interrupt Request 0 Enab le

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-

nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the

External Interrupt Control Register A (EICRA) define whether the external interrupt is activated

on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an

interrupt reque st even if INT0 is conf igured as an out put. The corre sponding inte rrupt of Ext ernal

Interrupt Request 0 is executed from the INT0 Interrupt Vector.

12.2.3 EIFR – External Interrupt Flag Register

• Bit 7..2 – Res: Reserved Bits

These bits are unused bits in the ATmega48P/88P/168P/328P, and will always read as zero.

• Bit 1 – INTF1: External Interrupt Flag 1

When an edge or logic chang e on the INT1 pin trigger s an interr upt requ est, INT F1 becomes set

(one). If the I-bit in SREG and the INT1 bit in EIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT1 is configured as a level interrupt.

• Bit 0 – INTF0: External Interrupt Flag 0

When an edge or logic chang e on the INT0 pin trigger s an interr upt requ est, INT F0 becomes set

(one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT0 is configured as a level interrupt.

Bit 76543210

0x1D (0x3D) ––––––INT1INT0EIMSK

Read/Write RRRRRRR/WR/W

Initial Value00000000

Bit 76543210

0x1C (0x3C) ––––––INTF1INTF0EIFR

Read/Write RRRRRRR/WR/W

Initial Value00000000

74 8025D–AVR–03/08

ATmega48P/88P/168P/328P

12.2.4 PCICR – Pin Change Interrupt Control Register

• Bit 7..3 - Res: Reserved Bits

These bits are unused bits in the ATmega48P/88P/168P/328P, and will always read as zero.

• Bit 2 - PCIE2: Pin Change Interrupt Enable 2

When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 2 is enabled. Any change on any enabled PCINT23..16 pin will cause an inter-

rupt. The corres ponding interrupt of Pin Change Inter rupt Request is executed from the PCI2

Interrupt Vector. PCINT23..16 pins are enabled individually by the PCMSK2 Register.

• Bit 1 - PCIE1: Pin Change Interrupt Enable 1

When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 1 is enabled. Any change on any enabled PCINT14..8 pin will cause an inter-

rupt. The corres ponding interrupt of Pin Change Inter rupt Request is executed from the PCI1

Interrupt Vector. PCINT14..8 pins are enabled indi vidually by the PCMSK1 Register.

• Bit 0 - PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt.

The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Inter-

rupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.

12.2.5 PCIFR – Pin Change Interrupt Flag Register

• Bit 7..3 - Res: Reserved Bits

These bits are unused bits in the ATmega48P/88P/168P/328P, and will always read as zero.

• Bit 2 - PCIF2: Pin Change Interrupt Flag 2

When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set

(one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

• Bit 1 - PCIF1: Pin Change Interrupt Flag 1

When a logic change on any PCINT14..8 pin triggers an interrupt request, PCIF1 becomes set

(one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

Bit 76543210

(0x68) –––––PCIE2PCIE1PCIE0PCICR

Read/Write R R R R R R/W R/W R/W

Initial Value00000000

Bit 76543210

0x1B (0x3B) –––––PCIF2PCIF1PCIF0PCIFR

Read/Write R R R R R R/W R/W R/W

Initial Value00000000

8025D–AVR–03/08

ATmega48P/88P/168P/328P

• Bit 0 - PCIF0: Pin Change Interrupt Flag 0

When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set

(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

12.2.6 PCMSK2 – Pin Change Mask Register 2

• Bit 7..0 – PCINT23..16: Pin Change Enable Mask 23..16

Each PCINT23..16-bit selects whether pin change interrupt is enabled on the corresponding I/O

pin. If PCINT23. .16 is set a nd the PCIE2 b it in PCICR is set, pin change interrupt is enabled on

the corresponding I/O pin. If PCINT23..16 is cleared, pin change interrupt on the corresponding

I/O pin is disabled.

12.2.7 PCMSK1 – Pin Change Mask Register 1

• Bit 7 – Res: Reserved Bit

This bit is an unused bit in the ATmega48P/88P/168P/328P, and will always read as zero.

• Bit 6..0 – PCINT14..8: Pin Change Enable Mask 14..8

Each PCINT14..8-bit selects whether pin change interrupt is enabled on the corresponding I/O

pin. If PCINT14..8 is set and the PCIE1 bit in PCICR is set, pin change interrupt is enab led on

the corresponding I/O pin. If PCINT14..8 is cleared, pin change interrupt on the corresponding

I/O pin is disabled.

12.2.8 PCMSK0 – Pin Change Mask Register 0

• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0

Each PCINT7..0 bit selects whether pin change interru pt is enabled on the corresponding I/O

pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the

corresponding I /O pin . If PCI NT7. .0 is cle ar ed, p i n ch ang e int errup t on t he correspo nd ing I/ O pin

is disabled.

Bit 76543210

(0x6D) PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 PCMSK2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

(0x6C) – PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1

Read/Write R R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

(0x6B) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

76 8025D–AVR–03/08

ATmega48P/88P/168P/328P

13. I/O-Ports

13.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.

This means that the direction of one port pin can be changed without unintentionally changing

the direction of any other pin with the SBI and CBI instructions. The same applies when chang-

ing drive value (if conf igured a s output) or enablin g/disabling o f pull-up resistors (if con figured as

input). Each output buffer has symmetrical drive characteristics with both hig h sink and source

capability. The pin driver is strong enough to drive LED displays directly. All port pins have indi-

vidually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have

protection diodes to both VCC and Ground as indicated in Figure 13-1. Refer to ”Electrical Char-

acteristics” on page 313 for a complete list of parameters.

Figure 13-1. I/O Pin Equivalent Schematic

All registers and bit references in this sect ion are written in g eneral form. A lower case “x” repre-

sents the numbering letter for the p ort, and a lower case “n” represe nts the bit numb er. However,

when using the regist er or bit defin es in a program , the precise f orm must be used. For examp le,

PORTB3 for bit no. 3 in Port B, her e docume nt ed ge ner ally as PO RT xn. The physical I /O Regis-

ters and bit locations are listed in ”Register Descri ption” on page 93.

Three I/O memory address locations are allocated for each port, one each for the Data Register

– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins

I/O location is read only, while the Data Register and the Data Direction Register are read/write.

However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond-

ing bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the

pull-up function for all pins in all po rts when set.

Using the I/O port as G eneral Digital I/O is described in ”Ports as General Digital I/O” on page

77. Most port pins are m ultiplexed with alternate function s for the peripheral features o n the

device. How each alternate function interferes with the port pin is described in ”Alternate Port

Functions” on page 81. Refer to the individual module sections for a full description of the alter-

nate functions.

Cpin

Logic

Rpu

See Figure

"General Digital I/O" for

Details

Pxn

8025D–AVR–03/08

ATmega48P/88P/168P/328P

Note that enabling the alternate function of some of the port pins does not affect the use of the

other pins in the por t as general digital I/O.

13.2 Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 13-2 show s a func-

tional description of one I/O-port pin, here generically called Pxn.

Figure 13-2. General Digital I/O(1)

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,

SLEEP, and PUD are common to all ports.

13.2.1 Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in ”Register

Description” on page 93, the DDxn bits are accessed at t he DDRx I/O add re ss, the PO RT xn bits

at the PORTx I/O address, and the PINxn bits at the PINx I/O add ress.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,

Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input

pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is

activated. To switch t he pull-up resist or off, PORTxn h as to be written logic zero or the pi n has to

be configured as an output pin. The port pins are tr i-stated when rese t condition becomes a ctive,

even if no clocks are runn in g.

clk

RPx

RRx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WRx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

clk

I/O

: I/O CLOCK

RDx: READ DDRx

RESET

Q D

CLR

PORTxn

Q D

CLR

DDxn

PINxn

DATA BU S

SLEEP

SLEEP: SLEEP CONTROL

Pxn

I/O

WPx

WRx

WPx: WRITE PINx REGISTER

78 8025D–AVR–03/08

ATmega48P/88P/168P/328P

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven

high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port

pin is driven low (zero).

13.2.2 Toggling the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.

Note that the SBI instruction can be used to toggle one single bit in a port.

13.2.3 Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}

= 0b11), an intermediate state with either pull- up enabled {DDxn, PORTxn} = 0b01) or output

low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-

able, as a high-impedance environment will not notice the difference between a strong high

driver and a pu ll-up. If t his is n ot t he case, t he PUD bit in t he MCUCR Reg i ster can be set to di s-

able all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user

must use e ither the tri-st ate ({DDxn, PORTxn} = 0b00) or th e output high state ({DDxn, PORTxn}

= 0b11) as an intermediate step.

Table 13-1 summarizes the control signals for the pin value.

13.2.4 Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the

PINxn Register bit . As shown in Figur e 13-2, t he PINxn Register bit a nd the p recedin g latch con-

stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value

near the edge of the internal clock, bu t it also introduces a delay. Figure 1 3-3 shows a timing dia-

gram of the synchronization when reading an externally ap plied pin value. The maximum and

minimum prop a ga tio n dela ys ar e de no te d tpd,max and tpd,min respectively.

Table 13-1. P ort Pin Configurations

DDxn PORTxn PUD

(in MCUCR) I/O Pull-up Comment

0 0 X Input No Tri-state (Hi-Z)

0 1 0 Input Yes Pxn will source current if ext. pulled low.

0 1 1 Input No Tri-state (Hi-Z)

1 0 X Output No Output Low (Sink)

1 1 X Output No Output High (Source)

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ATmega48P/88P/168P/328P

Figure 13-3. Synchronization when Reading an Externally Applied Pin value

Consider the clock period starting shortly after the first falling edge of the system clock. The latch

is closed when the clock is low, and goes transpa rent when the clock is high, as indicated by the

shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock

goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-

cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed

between ½ and 1½ system clock pe riod depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indi-

cated in Figure 13-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of

the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.

Figure 13-4. Synchronization when Rea ding a Software Assigned Pin Value

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define

the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin

values are read back again, but as previously discussed, a nop instruction is included to be able

to read back the value recently assigned to some of the pins.

XXX in r17, PINx

0x00 0xFF

INSTRUCTIONS

SYNC LATCH

PINxn

r17

XXX

SYSTEM CLK

pd, max

pd, min

out PORTx, r16 nop in r17, PINx

0xFF

0x00 0xFF

SYSTEM CLK

r16

INSTRUCTIONS

SYNC LATCH

PINxn

r17

80 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Note: 1. For the assembly program, tw o temporary registers are used to minimize the time from pull-

ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3

as low and redefining bits 0 and 1 as strong high drivers.

13.2.5 Digital Input Enable and Sleep Modes

As shown in Figure 13-2, the digital input signa l can be clamped to ground at the input of the

Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in

Power-down mode , Power-save mode, and Stan dby mode to avoid high powe r consumption if

some input signals are left float ing, or have an analog signal level close to VCC/2.

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt

request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various

other alternate functions as described in ”Alternate Port Functions” on page 81.

If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as

“Interrupt on Rising Edge , Falling Edge, or Any Logic Change on Pin” while the ext ernal interrupt

is not enabled, the corresponding External Interrupt Flag will be set when resuming from the

above mentioned Sleep mode, as the clamping in these sleep mode produces the requested

logic change.

13.2.6 Unconnected Pins

If some pins are unused, it is recommended to ensur e that these pins have a def ined level. Even

though most of t he digital inputs are d isabled in the deep sleep modes as descr ibed above, fl oat-

Assembly Code Example(1)

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in r16,PINB

...

C Code Example

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

__no_operation();

/* Read port pins */

i = PINB;

...

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ATmega48P/88P/168P/328P

ing inputs should be avoided to reduce current consumption in all other modes where the digital

inputs are enabled (Reset, Active mode and Idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.

In this case, the pull-up will be disabled during reset. If low power consumption during reset is

important, it is recommended to use an external pull-up or pull-down. Connecting unused pins

directly to VCC or GND is not recommended, sin ce this may ca use excess ive curr ents if the pin is

accidentally configured as an output.

13.3 Alternate Port Functions

Most port pins have alternate functions in addition to being general digital I/Os. Figure 13-5

shows how the port pin control signals from the simplified Figure 13-2 on page 77 can be over-

ridden by alternate functions. The overriding signals may not be present in all port pins, but the

figure serves as a generic description applicable to all port pins in the AVR microcontroller

family.

Figure 13-5. Alternate Port Funct ions(1)

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,

SLEEP, and PUD are common to all ports. All other signals are unique for each pin.

clk

RPx

RRx

WRx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WRx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

clk

I/O

: I/O CLOCK

RDx: READ DDRx

SET

CLR

DIxn

AIOxn

DIEOExn

PVOVxn

PVOExn

DDOVxn

DDOExn

PUOExn

PUOVxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE

PUOVxn: Pxn PULL-UP OVERRIDE VALUE

DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE

DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE

PVOExn: Pxn PORT VALUE OVERRIDE ENABLE

PVOVxn: Pxn PORT VALUE OVERRIDE VALUE

DIxn: DIGITAL INPUT PIN n ON PORTx

AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx

RESET

CLR

PINxn

PORTxn

DDxn

DATA B U S

DIEOVxn

SLEEP

DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE

DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE

SLEEP: SLEEP CONTROL

Pxn

I/O

PTOExn

PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE

WPx: WRITE PINx

WPx

82 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Table 13-2 summarizes th e fu nction of the overri ding signals. The pin and p ort ind exes from Fig-

ure 13-5 on page 81 are not shown in the succeeding tables. The overriding signals are

generated int ernally in the modules having the alternate function.

The following subsections shortly describe the alternate functions for each port, and relate the

overriding signals to the alternate function. Refer to the alternate function description for further

details.

Table 13-2. Generic Description of Overriding Signals for Alternate Functions

Signal Name Full Name Description

PUOE Pull-up Override

Enable

If this signal is set, the pull-up enable is controlled b y the PUO V

signal. If this signal is cleared, the pull-up is ena bled when

{DDxn, PORT xn, PUD} = 0b010.

PUOV Pull-up Override

Value

If PUOE is set, the pull-up is enabled/disabled when PUOV is

set/cleared, regardless of the setting of the DDxn, PORTxn,

and PUD Register bits.

DDOE Data Direct io n

Override Enable

If this signal is set, the Output Driver Enab le is controlled by the

DDOV signal. If this signal is cleared, the Outp ut driver is

enabled by the DDxn Register bit.

DDOV Data Dire ct io n

Override Value

If DDOE is set, the Output Driver is enabled/disabled when

DDOV is set/cleared, regardless of the setting of the DDxn

PVOE Port Value

Override Enable

If this signal is set and the Output Dr iver is enabled, the port

value is controlled b y the PVOV signal. If PVOE is cleared, and

the Output Driver is enabled, the port Value is controlled by the

PORTxn Register bit.

PVOV Port Value

Override Value If PVOE is set, the port value is set to PVOV, regardless of the

setting of the PORTxn Register bit.

PTOE Port Toggle

Override Enable If PTOE is set, the PORTxn Register bit is inverted.

DIEOE Digital Input

Enable Override

Enable

If this bit is set, the Digital Input Enable is controlled by the

DIEOV signal. If this signal is cleared, the Digital Input Enable

is determi ned by MCU state (Normal mode, sleep mode).

DIEOV Digital Input

Enable Override

Value

If DIEOE is set, the Digital Input is enabled/disabled when

DIEOV is set/cleared, regardless of the MCU state (Normal

mode, sleep mode).

DI Digital Input

This is the Digital Input to alternate functions. In the figure , the

signal is connected to the output of the Schmitt Trigger but

before the synchronizer. Unless the Digital Input is used as a

clock source, the module with the alternate function will use its

own synchronizer.

AIO Analog

Input/Output

This is the Analog Input/output to/from alternate functions. The

signal is connected directly to the pad, and can be used bi-

directionally.

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ATmega48P/88P/168P/328P

13.3.1 Alternate Functions of Port B

The Port B pins with alternate functions are sh own in Table 13-3.

The alternate pin configuration is as follows:

• XTAL2/TOSC2/PCINT7 – Port B, Bit 7

XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency

crystal Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.

TOSC2: Timer Oscillator pin 2. Used only if internal calibrated RC Oscillator is selected as chip

clock source, and the asynchronous timer is enabled by the correct setting in ASSR. When the

AS2 bit in ASSR is set (one) and the EXCLK bit is cleared (zero) to enable asynchronous clock-

ing of Timer/Counter2 using the Crystal Oscillator, pin PB7 is disconnected from the port, and

becomes the inverting output of the Oscillator amplifier. In this mode, a crystal Oscillator is c on-

nected to this pin, and the pin cannot be used as an I/O pin.

PCINT7: Pin Change Interrupt source 7. The PB7 pin can serve as an external interrupt source.

If PB7 is used as a clock pin, DDB7, PORTB7 and PINB7 will all read 0.

• XTAL1/TOSC1/PCINT6 – Port B, Bit 6

XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC

Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.

TOSC1: Timer Oscillator pin 1. Used only if internal calibrated RC Oscillator is selected as chip

clock source, and the asynchronous timer is enabled by the correct setting in ASSR. When the

Table 13-3. Port B Pins Alternate Functions

Port Pin Alternate Functions

PB7 XTAL2 (Chip Clock Oscillator pin 2)

TOSC2 (Timer Oscillator pin 2)

PCINT7 (Pin Change Interrupt 7)

PB6 XTAL1 (Chip Clock Oscillator pin 1 or External clock input)

TOSC1 (Timer Oscillator pin 1)

PCINT6 (Pin Change Interrupt 6)

PB5 SCK (SPI Bus Master clock Input)

PCINT5 (Pin Change Interrupt 5)

PB4 MISO (SPI Bus Master Input/Slave Output)

PCINT4 (Pin Change Interrupt 4)

PB3 MOSI (SPI Bus Master Output /Slave Input)

OC2A (Timer/Counter2 Output Compare Match A Output)

PCINT3 (Pin Change Interrupt 3)

PB2 SS (SPI Bus Master Slave select)

OC1B (Timer/Counter1 Output Compare Match B Output)

PCINT2 (Pin Change Interrupt 2)

PB1 OC1A (Timer/Counter1 Output Compare Match A Output)

PCINT1 (Pin Change Interrupt 1)

PB0 ICP1 (Timer/Counter1 Input Capture Input)

CLKO (Divided System Clock Output)

PCINT0 (Pin Change Interrupt 0)

84 8025D–AVR–03/08

ATmega48P/88P/168P/328P

AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2, pin PB6 is dis-

connected from the port, and becomes the input of the invertin g Oscillator amplifier. In this

mode, a crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin.

PCINT6: Pin Change Interrupt source 6. The PB6 pin can serve as an external interrupt source.

If PB6 is used as a clock pin, DDB6, PORTB6 and PINB6 will all read 0.

• SCK/PCINT5 – Por t B, Bit 5

SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a

Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is

enabled as a Master, the data direction of this pin is controlled by DDB5. When the pin is forced

by the SPI to be an input, the pull-up can still be controlled by the PORTB5 bi t.

PCINT5: Pin Change Interrupt source 5. The PB5 pin can serve as an external interrupt source.

• MISO/PCINT4 – Port B, Bit 4

MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a

Master, this pin is configured as an input regardless of the setting of DDB4. When the SPI is

enabled as a Slave, the data direction of this pin is controlled by DDB4. When the pin is forced

by the SPI to be an input, the pull-up can still be controlled by the PORTB4 bi t.

PCINT4: Pin Change Interrupt source 4. The PB4 pin can serve as an external interrupt source.

• MOSI/OC2/PCINT3 – Por t B, Bit 3

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a

Slave, this pin is configured as an input regardless of the setting of DDB3. When the SPI is

enabled as a Master, the data direction of this pin is controlled by DDB3. When the pin is forced

by the SPI to be an input, the pull-up can still be controlled by the PORTB3 bi t.

OC2, Output Compare Match Output: The PB3 pin can serve as an external output for the

Timer/Counter2 Compare Match. The PB3 pin has to be configured as an output (DDB3 set

(one)) to serve this function. The OC2 pin is also the output pin for the PWM mode timer

function.

PCINT3: Pin Change Interrupt source 3. The PB3 pin can serve as an external interrupt source.

•SS

/OC1B/PCINT2 – Port B, Bit 2

SS: Slave Select input. When the SPI is enabled as a Slave, this pin is configured as an input

regardless of the sett ing of DDB2. As a Slave, the SPI is activated when this p in is driven low.

When the SPI is ena bled as a Master, the data direction of this pin is controlled by DDB2. When

the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB2 bit.

OC1B, Output Compare Match output: The PB2 pin can serve as an external output for the

Timer/Counter1 Compare Match B. The PB2 pin has to be configured as an output (DDB2 set

(one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer

function.

PCINT2: Pin Change Interrupt source 2. The PB2 pin can serve as an external interrupt source.

• OC1A/PCINT1 – Por t B, Bit 1

OC1A, Output Compare Match output: The PB1 pin can serve as an external output for the

Timer/Counter1 Compare Match A. The PB1 pin has to be configured as an output (DDB1 set

8025D–AVR–03/08

ATmega48P/88P/168P/328P

(one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer

function.

PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt source.

• ICP1/CLKO/PCINT0 – Port B, Bit 0

ICP1, Input Capture Pin: The PB0 pin can act as an Input Capture Pin for Timer/Counter1.

CLKO, Divided System Clock: The divided system clock can be output on the PB0 pin. The

divided system clock will be output if the CKOUT Fuse is programmed, regardless of the

PORTB0 and DDB0 settings. It will also be output during reset.

PCINT0: Pin Change Interrupt source 0. The PB0 pin can serve as an external interrupt source.

Table 13-4 and Table 13-5 on page 86 relate the alternate functions of Port B to the overriding

signals shown in Figur e 13-5 on page 81. SPI MSTR INPUT and SPI SLAVE OUTPUT consti-

tute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.

Notes: 1. INTRC means that one of the internal RC Oscillators are selected (by the CKSEL fuses),

EXTCK means that external clock is selected (by the CKSEL fuses)

Table 13-4. Overriding Signals for Alternate Functions in PB7..PB4

Signal

Name PB7/XTAL2/

TOSC2/PCINT7(1) PB6/XTAL1/

TOSC1/PCINT6(1) PB5/SCK/

PCINT5 PB4/MISO/

PCINT4

PUOE INTRC • EXTCK+

AS2 INTRC + AS2 SPE • MSTR SPE • MSTR

PUOV 0 0 PORTB5 • PUD PORTB4 • PUD

DDOE INTRC • EXTCK+

AS2 INTRC + AS2 SPE • MSTR SPE • MSTR

DDOV0000

PVOE 0 0 SPE • MSTR SPE • MSTR

PVOV 0 0 SCK OUTPUT SPI SLAVE

OUTPUT

DIEOE INTRC • EXTCK +

AS2 + PCINT7 •

PCIE0

INTRC + AS2 +

PCINT6 • PCIE0 PCINT5 • PCIE0 PCINT4 • PCIE0

DIEOV (INTRC + EXTCK) •

AS2 INTRC • AS2 11

DI PCINT7 INPUT PCINT6 INPUT PCINT5 INPUT

SCK INPUT PCINT4 INPUT

SPI MSTR INPUT

AIO Oscillator Output Oscillator/Clock

Input ––

86 8025D–AVR–03/08

ATmega48P/88P/168P/328P

13.3.2 Alternate Functions of Port C

The Port C pins with alternate functions are shown in Table 13-6.

Table 13-5. Overriding Signals for Alternate Functions in PB3..PB0

Signal

Name PB3/MOSI/

OC2/PCINT3 PB2/SS/

OC1B/PCINT2 PB1/OC1A/

PCINT1 PB0/ICP1/

PCINT0

PUOE SPE • MSTR SPE • MSTR 00

PUOV PORTB3 • PUD PORTB2 • PUD 00

DDOE SPE • MSTR SPE • MSTR 00

DDOV 0 0 0 0

PVOE SPE • MSTR +

OC2A ENABLE OC1B ENABLE OC1A ENABLE 0

PVOV SPI MSTR OUTPUT

+ OC2A OC1B OC1A 0

DIEOE PCINT3 • PCIE0 PCINT2 • PCIE0 PCINT1 • PCIE0 PCINT0 • PCIE0

DIEOV1111

DI PCINT3 INPUT

SPI SLAVE INPUT PCINT2 INPUT

SPI SS PCINT1 INPUT PCINT0 INPUT

ICP1 INPUT

AIO––––

Table 13-6. Port C Pins Alternate Functions

Port Pin Alternate Function

PC6 RESET (Reset pin)

PCINT14 (Pin Change Interrupt 14)

PC5 ADC5 (ADC Input Channel 5)

SCL (2-wire Serial Bus Clock Line)

PCINT13 (Pin Change Interrupt 13)

PC4 ADC4 (ADC Input Channel 4)

SDA (2-wire Ser ial Bus Data Input/Output Line)

PCINT12 (Pin Change Interrupt 12)

PC3 ADC3 (ADC Input Channel 3)

PCINT11 (Pin Change Interrupt 11)

PC2 ADC2 (ADC Input Channel 2)

PCINT10 (Pin Change Interrupt 10)

PC1 ADC1 (ADC Input Channel 1)

PCINT9 (Pin Change Interrupt 9)

PC0 ADC0 (ADC Input Channel 0)

PCINT8 (Pin Change Interrupt 8)

8025D–AVR–03/08

ATmega48P/88P/168P/328P

The alternate pin configuration is as follows:

• RESET/PCINT14 – Port C, Bit 6

RESET, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a normal I/O

pin, and the part will have to rely on Power-on Reset and Brown- out Reset as its reset sources.

When the RSTDISBL Fuse is unprogrammed, th e reset circuitry is connecte d to the pin, and the

pin can not be used as an I/O pin.

If PC6 is used as a reset pin, DDC6, PORTC6 and PINC6 will all read 0.

PCINT14: Pin Change Interrupt source 14. The PC6 pin can serve as an external interrupt

source.

• SCL/ADC5/PCINT13 – Port C, Bit 5

SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2-

wire Serial Interface, pin PC5 is disconnected from the port and becomes the Serial Clock I/O

pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress

spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with

slew-rate limitation.

PC5 can also be used as ADC input Channel 5. Note that ADC input channel 5 uses digital

power.

PCINT13: Pin Change Interrupt source 13. The PC5 pin can serve as an external interrupt

source.

• SDA/ADC4/PCINT12 – Port C, Bit 4

SDA, 2-wire Serial Interface Da ta: When the TWEN bit in TWCR is set (one) to enable the 2-wire

Serial Interface, pin PC4 is disconnected from the port and becomes the Serial Data I/O pin for

the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes

shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-

rate limitation.

PC4 can also be used as ADC input Channel 4. Note that ADC input channel 4 uses digital

power.

PCINT12: Pin Change Interrupt source 12. The PC4 pin can serve as an external interrupt

source.

• ADC3/PCINT11 – Port C, Bit 3

PC3 can also be used as ADC input Channel 3. Note that ADC input channel 3 uses analog

power.

PCINT11: Pin Change Interrupt source 11. The PC3 pin can serve as an external interrupt

source.

• ADC2/PCINT10 – Port C, Bit 2

PC2 can also be used as ADC input Channel 2. Note that ADC input channel 2 uses analog

power.

PCINT10: Pin Change Interrupt source 10. The PC2 pin can serve as an external interrupt

source.

88 8025D–AVR–03/08

ATmega48P/88P/168P/328P

• ADC1/PCINT9 – Port C, Bit 1

PC1 can also be used as ADC input Channel 1. Note that ADC input channel 1 uses analog

power.

PCINT9: Pin Change Interrupt source 9. The PC1 pin can serve as an external interrupt source.

• ADC0/PCINT8 – Port C, Bit 0

PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses analog

power.

PCINT8: Pin Change Interrupt source 8. The PC0 pin can serve as an external interrupt source.

Table 13-7 and Table 13 -8 relate the alternate functions of Port C to the overriding sign als

shown in Figure 13-5 on page 81.

Note: 1. W hen enabled, the 2-wire Serial Interface enables slew-rate controls on the output pins PC4

and PC5. This is not shown in the figure. In addition, spike filters are connected between the

AIO outputs shown in the port figure and the digital logic of the TWI module.

Table 13-7. Overriding Signals for Alternate Functions in PC6..PC4(1)

Signal

Name PC6/RESET/PCINT14 PC5/SCL/ADC5/PCINT13 PC4/SDA/ADC4/PCINT12

PUOE RSTDISBL TWEN TWEN

PUOV 1 PORTC5 • PUD PORTC4 • PUD

DDOE RSTDISBL TWEN TWEN

DDOV 0 SCL_OUT SDA_OUT

PVOE 0 TWEN TWEN

PVOV 0 0 0

DIEOE RSTDISBL + PCINT14 •

PCIE1 PCINT13 • PCIE1 + ADC5D PCINT12 • PCIE1 + ADC4D

DIEOV RSTDISBL PCINT13 • PCIE1 PCINT12 • PCIE1

DI PCINT14 INPUT PCINT13 INPUT PCINT12 INPUT

AIO RESET INPUT ADC5 INPUT / SCL INPUT ADC4 INPUT / SDA INPUT

8025D–AVR–03/08

ATmega48P/88P/168P/328P

13.3.3 Alternate Functions of Port D

The Port D pins with alternate functions are shown in Table 13-9.

Table 13-8. Overriding Signals for Alternate Functions in PC3..PC0

Signal

Name PC3/ADC3/

PCINT11 PC2/ADC2/

PCINT10 PC1/ADC1/

PCINT9 PC0/ADC0/

PCINT8

PUOE0000

PUOV0000

DDOE 0 0 0 0

DDOV 0 0 0 0

PVOE0000

PVOV0000

DIEOE PCINT11 • PCIE1 +

ADC3D PCINT10 • PCIE1 +

ADC2D PCINT9 • PCIE1 +

ADC1D PCINT8 • PCIE1 +

ADC0D

DIEOV PCINT11 • PCIE1 PCINT10 • PCIE1 PCINT9 • PCIE1 P CINT8 • PCIE1

DI PCINT11 INPUT PCINT10 INPUT PCINT9 INPUT PCINT8 INPUT

AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT

Table 13-9. Port D Pins Alternate Functions

Port Pin Alternate Function

PD7 AIN1 (Analog Comparator Negative Input)

PCINT23 (Pin Change Interrupt 23)

PD6 AIN0 (Analog Comparator Positive Input)

OC0A (Timer/Counter0 Output Compare Match A Output)

PCINT22 (Pin Change Interrupt 22)

PD5 T1 (Timer/Counter 1 External Counter Input)

OC0B (Timer/Counter0 Output Compare Match B Output)

PCINT21 (Pin Change Interrupt 21)

PD4 XCK (USART External Clock Input/Output)

T0 (Timer/Counter 0 External Counter Input)

PCINT20 (Pin Change Interrupt 20)

PD3 INT1 (External Interrupt 1 Input)

OC2B (Timer/Counter2 Output Compare Match B Output)

PCINT19 (Pin Change Interrupt 19)

PD2 INT0 (External Interrupt 0 Input)

PCINT18 (Pin Change Interrupt 18)

PD1 TXD (USAR T Output Pin)

PCINT17 (Pin Change Interrupt 17)

PD0 RXD (USART Input Pin)

PCINT16 (Pin Change Interrupt 16)

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ATmega48P/88P/168P/328P

The alternate pin configuration is as follows:

• AIN1/OC2B/PCINT23 – Port D, Bit 7

AIN1, Analog Compara tor Negative Inp ut. Configure the port pin as input wit h the internal pull-up

switched off to avoid the digital port function from interfering with the function of the Analog

Comparator.

PCINT23: Pin Change Interrupt source 23. The PD7 pin can serve as an external interrupt

source.

• AIN0/OC0A/PCINT22 – Port D, Bit 6

AIN0, Analog Comparator Positive Input. Configure the port pin as input with the internal pull-up

switched off to avoid the digital port function from interfering with the function of the Analog

Comparator.

OC0A, Output Compare Match output: The PD6 pin can serve as an external output for the

Timer/Counter0 Compare Match A. The PD6 pin has to be configured as an output (DDD6 set

(one)) to serve this function. The OC0A pin is also the output pin for the PWM mode timer

function.

PCINT22: Pin Change Interrupt source 22. The PD6 pin can serve as an external interrupt

source.

• T1/OC0B/PCINT21 – Port D, Bit 5

T1, Timer/Counter1 counter source.

OC0B, Output Compare Match output: The PD5 pin can serve as an external output for the

Timer/Counter0 Compare Match B. The PD5 pin has to be configured as an output (DDD5 set

(one)) to serve this function. The OC0B pin is also the output pin for the PWM mode timer

function.

PCINT21: Pin Change Interrupt source 21. The PD5 pin can serve as an external interrupt

source.

• XCK/T0/PCINT20 – Port D, Bit 4

XCK, USART external clock.

T0, Timer/Counter0 counter source.

PCINT20: Pin Change Interrupt source 20. The PD4 pin can serve as an external interrupt

source.

• INT1/OC2B/PCINT19 – Port D, Bit 3

INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source.

OC2B, Output Compare Match output: The PD3 pin can serve as an external output for the

Timer/Counter0 Compare Match B. The PD3 pin has to be configured as an output (DDD3 set

(one)) to serve this function. The OC2B pin is also the output pin for the PWM mode timer

function.

PCINT19: Pin Change Interrupt source 19. The PD3 pin can serve as an external interrupt

source.

8025D–AVR–03/08

ATmega48P/88P/168P/328P

• INT0/PCINT1 8 – Port D, Bit 2

INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source.

PCINT18: Pin Change Interrupt source 18. The PD2 pin can serve as an external interrupt

source.

• TXD/PCINT17 – Por t D, Bit 1

TXD, Transmit Data (Data output pin for the USART). When the USART Transmitter is enabled,

this pin is configured as an output regardless of the value of DDD1.

PCINT17: Pin Change Interrupt source 17. The PD1 pin can serve as an external interrupt

source.

• RXD/PCINT16 – Port D, Bit 0

RXD, Receive Data (Data input pin for the USART). When the USART Receiver is enabled this

pin is configured as an input regardless of the value of DDD0. When the USART forces this pin

to be an input, the pull-up can still be controlled by the PORTD0 bit.

PCINT16: Pin Change Interrupt source 16. The PD0 pin can serve as an external interrupt

source.

Table 13-10 and Table 13- 11 relate the alternate functions of Port D to the overriding signals

shown in Figure 13-5 on page 81.

Table 13-10. Overriding Signals for Alternate Fu nctions PD7..PD4

Signal

Name PD7/AIN1

/PCINT23 PD6/AIN0/

OC0A/PCINT22 PD5/T1/OC0B/

PCINT21 PD4/XCK/

T0/PCINT20

PUOE0000

PUO0000

DDOE 0 0 0 0

DDOV 0 0 0 0

PVOE 0 OC0A ENABLE OC0B ENABLE UMSEL

PVOV 0 OC0A OC0B XCK OUTPUT

DIEOE PCINT23 • PCIE2 PCINT22 • PCIE2 PCINT21 • PCIE2 PCINT20 • PCIE2

DIEOV1111

DI PCINT23 INPUT PCINT22 INPUT PCINT21 INPUT

T1 INPUT

PCINT20 INPUT

XCK INPUT

T0 INPUT

AIO AIN1 INPUT AIN0 INPUT – –

92 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Table 13-11. Overriding Signals for Alternate Functions in PD3..PD0

Signal

Name PD3/OC2B/INT1/

PCINT19 PD2/INT0/

PCINT18 PD1/TXD/

PCINT17 PD0/RXD/

PCINT16

PUOE 0 0 TXEN RXEN

PUO000PORTD0 • PUD

DDOE 0 0 TXEN RXEN

DDOV 0 0 1 0

PVOE OC2B ENABLE 0 TXEN 0

PVOV OC2B 0 TXD 0

DIEOE INT1 ENABLE +

PCINT19 • PCIE2 INT0 ENABLE +

PCINT18 • PCIE1 PCINT17 • PCIE2 PCINT16 • PCIE2

DIEOV1111

DI PCINT19 INPUT

INT1 INPUT PCINT18 INPUT

INT0 INPUT PCINT17 INPUT PCINT16 INPUT

RXD

AIO––––

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ATmega48P/88P/168P/328P

13.4 Register Description

13.4.1 MCUCR – MCU Control Register

• Bit 4 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disab led even if the DDxn and

PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See ”Con-

figuring the Pin” on page 77 for more details about this feature.

13.4.2 PORTB – The Port B Data Register

13.4.3 DDRB – The Port B Data Direction Register

13.4.4 PINB – The Port B Input Pins Address

13.4.5 PORTC – The Port C Data Register

13.4.6 DDRC – The Port C Data Direction Register

13.4.7 PINC – The Port C Input Pins Address

Bit 7 6 5 4 3 2 1 0

0x35 (0x55) –BODS BODSE PUD – – IVSEL IVCE MCUCR

Read/Write R R R R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

0x05 (0x25) PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

0x04 (0x24) DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

0x03 (0x23) PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB

Read/WriteRRRRRRRR

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

0x08 (0x28) – PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC

Read/Write R R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

0x07 (0x27) – DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC

Read/Write R R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

0x06 (0x26) – PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC

Read/WriteRRRRRRRR

Initial Value 0 N/A N/A N/A N/A N/A N/A N/A

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ATmega48P/88P/168P/328P

13.4.8 PORTD – The Port D Data Register

13.4.9 DDRD – The Port D Data Direction Register

13.4.10 PIND – The Port D Input Pins Address

Bit 76543210

0x0B (0x2B) PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

0x0A (0x2A) DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

0x09 (0x29) PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND

Read/WriteRRRRRRRR

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

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ATmega48P/88P/168P/328P

14. 8-bit Timer/Counter0 with PWM

14.1 Features •Two In depend ent Ou tpu t Compare Units

•Double Buffered Output Compare Registers

•Clear Timer on Compare Match (Auto Reload)

•Glitch Free, Phase Correct Pulse Width Modulator (PWM)

•Variable PWM Period

•Frequency Generator

•Three Independent Interrupt Sources (TOV0, OCF0A, and OCF 0B)

14.2 Overview Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output

Compare Units, and wit h PWM support. It allows accurate program execut ion timing (eve nt man-

agement) and wave ge neration.

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 14-1. For the actual

placement of I/ O pi ns, r efer to ”Pino ut ATmega4 8P/88P/ 16 8P/328 P” on page 2. CPU accessible

I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register

and bit locations are listed in the ”Register Description” on page 107.

The PRTIM0 bit in ”Minimizing Power Consumption” on page 43 must be written to zero to

enable Timer/Counter0 module.

96 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 14-1. 8-bit Timer/Counter Block Diagram

14.2.1 Definitions Many register an d bit references in this section are written in gen eral form. A lower case “n”

replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-

pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or

bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing

Timer/Counter 0 counter value and so on.

The definitions in Table 14-1 are also used extensively throughout the documen t.

14.2.2 Registers The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and O CR0B) are 8-bit

registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the

Timer Interrup t Flag Regist er (T IFR0). All inte rrupts are ind ividually masked with the Timer Inte r-

rupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.

Clock Select

Timer/Counter

DATA BUS

OCRnA

OCRnB

TCNTn

Waveform

Generation

Waveform

Generation

OCnA

OCnB

Fixed

TOP

Value

Control Logic

TOP BOTTOM

Count

Clear

Direction

TOVn

(Int.Req.)

OCnA

(Int.Req.)

OCnB

(Int.Req.)

TCCRnA TCCRnB

Edge

Detector

( From Prescaler )

clk

Table 14-1. Definitions

BOTTOM The counter reaches the BOTTOM when it become s 0x00.

MAX The counter reache s its MAXimum when it becomes 0xFF (decimal 255).

TOP The counter reaches the TOP whe n it becom es equal to the high est value in the

count sequence. The TOP value can be assigned to be the fixed value 0xFF

(MAX) or the value stored in the OCR0A Register. The assignment is depen-

dent on the mode of operation.

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ATmega48P/88P/168P/328P

The Timer/Counter can be clocked inter nally, via the pre scaler, or by an external clock source on

the T0 pin. T he Clock Se lect logic blo ck controls which clock so urce and edge the Timer/Cou nter

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0).

The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the

Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-

erator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and

OC0B). See Section “15.7.3” on pa ge 124. for details. The compare match event will also set the

Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt

request.

14.3 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source

is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits

located in the Tim er/Counter Cont rol Regi ster ( TCCR0B). For deta ils on clock sources an d pres-

caler, see ”Timer/Counter0 and Timer/Counter1 Prescalers” on page 142.

14.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

14-2 shows a block diagram of the counter and its surroundings.

Figure 14-2. Counter Unit Block Diagram

Signal description (internal signals):

count Increment or de cre m en t TCNT0 by 1.

direction Select between increment and decrement.

clear Clear TCNT0 (set all bits to zero).

clkTnTimer/Co un te r clo ck, re fe rr ed to as clk T0 in the following.

top Signalize that TCNT0 has reached maximum value.

bottom Signalize that TCNT0 has reached minimum value (zero).

Depending of the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clkT0). clkT0 can be generated from an external or inte rnal clock source,

selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the

timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of

whether clkT0 is present or not. A CPU write overrides (has priority over ) all counter clear or

count operations.

DATA BUS

TCNTn Control Logic

count

TOVn

(Int.Req.)

Clock Select

top

Edge

Detector

( From Prescaler )

clk

bottom

direction

clear

98 8025D–AVR–03/08

ATmega48P/88P/168P/328P

The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in

the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter

Control Register B (TCCR0B). There are close connections between how the counter behaves

(counts) and how waveforms are generated on the Output Compare outputs OC0A and OC0B.

For more details about advanced counting sequences and waveform generation, see ”Modes of

Operation” on page 100.

The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by

the WGM02:0 bits. TOV0 can be used for generating a CPU interrupt.

14.5 Output Compare Unit

The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers

(OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a

match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock

cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output

Compare interrupt . Th e Outp ut Co mpare Flag is aut om atica lly cleare d wh en the int errup t is exe-

cuted. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit

location. The Waveform Generator uses the match signal to generate an output according to

operating mode set by the WGM02:0 bits and Co mpare Outpu t mode (COM0x1: 0) bits. The max

and bottom signals are used by the Waveform Generator for handling the special cases of the

extreme values in some modes of operation (”Modes of Operation” on page 100).

Figure 14-3 shows a block diagram of the Output Compare unit.

Figure 14-3. Output Compare Unit, Block Diagram

The OCR0x Registers are double buffered when using any of the Pulse Width Modulation

(PWM) modes. Fo r the nor mal and Clear Tim er on Compare ( CTC) modes of operation, the dou-

ble buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare

Registers to either top or bottom of the coun ting sequence. The synchronization prevents the

occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

OCFnx (Int.Req.)

= (8-bit Comparator )

OCRnx

OCnx

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMnx1:0

bottom

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ATmega48P/88P/168P/328P

The OCR0x Register access may seem co mplex, but this is not case. Wh en the double buff ering

is enabled, the CPU has access to the OC R0x Buffer Register, and if double buffering is dis-

abled the CPU will access the OCR0x directly.

14.5.1 Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC0x) bit. Forcing compare match will not set the

OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real compare

match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or

toggled).

14.5.2 Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 Register will block any compare match that occur in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initial-

ized to the same value as TCNT0 wit hout trigg ering an inte rrupt when t he Timer/Coun ter clock is

enabled.

14.5.3 Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNT0 when usin g the Output Compare Unit,

independently of whether the Timer/Counter is running or not. If the value written to TCNT0

equals the OCR0x value, the compare match will be missed, resulting in incorrect waveform

generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is

downcounting.

The setup of the OC0x should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OC0x value is to use the Force Output Com-

pare (FOC0x) strobe bits in Normal mode. T he OC0x Registers keep their valu es even when

changing between Wa veform Generation modes.

Be aware that the COM0x1:0 bits are not double buffered together with the compare value.

Changing the COM0x1:0 bits will take effect immediately.

14.6 Compare Match Output Unit

The Compare Outpu t mode (COM0x1: 0) bits ha ve two funct ions. The Wavef orm Genera tor uses

the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next compare match.

Also, the COM0x1:0 bits control the OC0x pin output source. Figure 14-4 shows a simplified

schematic of th e logic affecte d by the COM0x1: 0 bit setting. The I/O Registers, I/O bits, and I/O

pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR

and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the OC0x

state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset occur,

the OC0x Register is reset to “0”.

100 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 14-4. Compare Match Output Unit, Schematic

The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform

Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

ble on the pin. The port override function is independent of the Waveform Generation mode.

The design of the Output Compare pin logic allows initializat ion of the OC0x state before t he out-

put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of

operation. See Sectio n “14.9” on page 10 7.

14.6.1 Compare Output Mode and Waveform Generation

The Waveform Generat or uses the COM0 x1:0 bits d ifferently in Nor mal, CTC, and PWM mo des.

For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the

OC0x Register is t o be performed on the next com pare match. F or compare output actions in t he

non-PWM modes refer to Table 14-2 on page 107. For fast PWM mode, refer to Table 14-3 on

page 107, and for phase correct PWM refer to Table 14-4 on page 108 .

A change of the COM0x1:0 bits state will have effect at the first compare match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC0x strobe bits.

14.7 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the comb ination of the Wave form Generati on mode (WGM02: 0) and Compare Ou tput

mode (COM0x1:0) bits. T he Compare Output mode bits do no t affect the counting sequence,

while the Waveform Gener ation mode bits do . The COM0x1:0 bi ts control whether th e PWM out-

put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes

the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a compare

match (See Section “14. 6” on page 99.).

For detailed timing information refer to ” T imer/Counter Timing Diagrams” on page 105.

PORT

DDR

OCnx

Waveform

Generator

COMnx1

COMnx0

DATA BUS

FOCn

clk

I/O

101

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ATmega48P/88P/168P/328P

14.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-

tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same

timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth

bit, except that it is only set, not cleared. However, combined with the timer overflo w interrupt

that automatically clears the TOV0 Flag, the timer resolution can be increased by software.

There are no special cases to consider in the Normal mode, a new counter value can be written

anytime.

The Output Compar e u nit can be used to ge nerat e int errup t s at so me given time . Usin g the Ou t-

put Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time.

14.7.2 Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to

manipulate the count er resolut io n. In CTC mode the counter is clear ed to zero wh en the counter

value (TCNT0) matches the OCR0A. The OCR0A de fines the top value for the counter, hence

also its resolution. This m ode allows greater control of the compare ma tch output frequency. It

also simplifies the op e ra tio n of coun tin g exte rn al ev en ts.

The timing diagram for the CTC mode is shown in Figure 14-5. The counter value (TCNT0)

increases until a compare match occurs between TCNT0 and OCR0A, and then counter

(TCNT0) is cleared.

Figure 14-5. CTC Mode, Timing Diagram

An interrupt can be generated each time the counter value reaches the TOP value by using the

OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-

ning with none or a low pres caler value must be done with care since the CTC mode does not

have the double buffering feature. If the new value written to OCR0A is lower than the current

value of TCNT0, the counter will miss the compare match. The counter will then have to count to

its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can

occur.

For generatin g a wavefor m out put in CT C mod e, t he OC0A ou tput can be se t to toggle it s logica l

level on each compare match by setting the Compare Output mode bits to toggle mode

(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for

CNTn

(

Toggle)

OCnx Interrupt Flag Set

1 4

eriod

2 3

(COMnx1:0 = 1)

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ATmega48P/88P/168P/328P

the pin is set to output. The waveform generated will have a maximum frequency of fOC0 =

fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following

equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the Normal mode of op erat ion, the T OV0 Flag is se t in the same tim er clock cycle tha t the

counter counts from MAX to 0x00.

14.7.3 Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM02 :0 = 3 or 7) provides a high fre-

quency PWM waveform generation option. The fast PWM differs from the other PWM option by

its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOT-

TOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In non-

inverting Compare Output mode, the Output Compare (OC0x) is cleared on the compare match

between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the out-

put is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the

operating fr equency of the fast PWM mode can be twice as high as the phase correct PWM

mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited

for power regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the TOP value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

PWM mode is shown in Figure 14-6. The TCNT0 value is in the timing diagram shown as a his-

togram for illustrating the single-slope operation. The diagram includes non-inverted and

inverted PWM outputs. Th e small horizo ntal line marks on th e TCNT0 slopes represe nt compare

matches between OCR0x and TCNT0.

Figure 14-6. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

fOCnx fclk_I/O

2N1OCRnx+()⋅⋅

----------------------------------------------

----

CNTn

OCRnx Update and

TOVn Interrupt Flag Set

eriod

2 3

Cnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Interrupt Flag Se

4 5 6 7

103

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In fast PWM mode, the compare un it allows generation of PWM waveforms on the OC0x pins.

Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows

the OC0A pin to toggle on Compar e Matches if the WGM02 bit is set. This opt ion is no t available

for the OC0B pin (see Table 14-6 on page 108). The actual OC0x value will only be visible on

the port pin if the data direction for the port pin is set as output. The PWM waveform is gener-

ated by setting (or clearing) the OC0x Register at the compare match between OCR0x and

TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is

cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

The N variable represents the pre scale factor (1, 8, 64, 256, or 1024).

The extreme values for th e OCR0A Re gister rep resents sp ecial cases wh en gen erating a PW M

waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will

be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result

in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0

bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC0x to toggle its logical level on each compare match (COM0x1:0 = 1). The waveform

generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero. This

feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out-

put Compare unit is enabled in the fast PWM mode.

14.7.4 Phase Correct PWM Mode

The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct

PWM waveform generation option. The phase correct PWM mode is based on a dual-slope

operation. The coun ter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-

TOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In non-

inverting Compare Output mode, the Output Compare (OC0x) is cleared on the compare match

between TCNT0 and OCR0 x while upco unting, and set on the compar e match while do wncoun t-

ing. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has

lower maximum operation frequency than single slope operation. However, due to the symmet-

ric feature of the dual-slope PWM modes, these modes are preferred for motor control

applications.

In phase correc t PWM mode the counter is increm ented until the counte r value matches TOP.

When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal

to TOP for one timer clo ck cycle. The tim ing dia gram fo r th e pha se correct PWM mode is shown

on F igure 14- 7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating

the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The

small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x

and TCNT0.

fOCnxPWM fclk_I/O

N256⋅

------------------=

104 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 14-7. Phase Correct PWM Mode , Tim in g Dia gr am

The Timer/Counter Over flow Flag (TOV0) is set each time the counter reache s BOTTOM. The

Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted

PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to

one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is

not available for the OC0B pin (see Table 1 4-7 on pag e 109). The actual OC0x value will only be

visible on the port pin if the data dir ection fo r th e por t pin is se t as o utput . The PWM wa ve f orm is

generated by clear ing (or setting) the OC0x Register a t the compare ma tch between OCR0x and

TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at compare

match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the

output when using phase correct PWM can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represent special cases wh en generating a PWM

waveform output in the phase correct PWM mo de. If the OCR0A is set equal to BO TTOM, the

output will be continuously low and if set equal to MAX the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of period 2 in Figure 14-7 O Cnx has a transition from high to low even though

there is no Compare Match. The point of this transition is to guarantee sym metry around BOT-

TOM. There are two cases that give a transition without Compare Match.

• OCRnx changes its value from MAX, like in Figure 14-7. When the OCR0A value is MAX the

OCn pin value is the same as the result of a down-counting Compare Match. To ensure

TOVn Interrupt Flag Set

OCnx Interrupt Flag Set

1 2 3

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Update

fOCnxPCPWM fclk_I/O

N510⋅

------------------=

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symmetry around BOTTOM the OCnx v alue at MAX must correspond to the result of an up-

counting Compare Match.

• The timer starts counting from a v alue higher than the one in OCRnx, and for that reason

misses the Compare Match and hence the OCnx change that would have happened on the

way up.

14.8 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a

clock enable signal in the following figures. The figures include information on when interrupt

flags are set. Figure 14-8 contains timing data for basic Timer/Counter operation. The figur e

shows the count sequence close to the MAX value in all modes other than phase correct PWM

mode.

Figure 14-8. Timer/Counter Timing Diagram, no Prescaling

Figure 14-9 shows the same timing data, but with the prescaler enabled.

Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

Figure 14-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC

mode and PWM mode, where OCR0A is TOP.

clk

(clk

I/O

/1)

TOVn

clk

I/O

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

TOVn

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

clk

I/O

clk

(clk

I/O

/8)

106 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8)

Figure 14-11 shows the setting of OCF0 A and the clearing of TCNT0 in CTC mode and fast

PWM mode where OCR0A is TOP.

Figure 14-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (fclk_I/O/8)

OCFnx

OCRnx

TCNTn

OCRnx Value

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

clkI/O

clkTn

(clk

I/O

/8)

OCFnx

OCRnx

TCNTn

(CTC)

TOP

TOP - 1 TOP BOTTOM BOTTOM + 1

clkI/O

clkTn

(clk

I/O

/8)

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14.9 Register Description

14.9.1 T CCR 0A – Ti mer/ Co un t er Cont rol Register A

• Bits 7:6 – COM0A1:0 : Compare Match Output A Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0

bits are set, the OC0A outpu t overr ides the no rmal por t functi onality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin

must be set in order to enable the output dr iver.

When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the

WGM02:0 bit setting. Table 14- 2 shows the COM0A1:0 bit functionality when the WGM02:0 bits

are set to a normal or CTC mode (non-PWM).

Table 14-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM

mode.

Note: 1. A speci al case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at BOTTOM. See ”Fast PWM Mode” on

page 102 for more details.

Bit 7 6 5 4 3 2 1 0

0x24 (0x44) COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 TCCR0A

Read/Write R/W R/W R/W R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 14-2. Compare Output Mode, non-PWM Mode

COM0A1 COM0A0 Description

0 0 Normal port operation, OC0A disconnected.

0 1 Toggle OC0A on Compare Match

1 0 Clear OC0A on Compare Match

1 1 Set OC0A on Compare Match

Table 14-3. Compare Output Mode, Fast PWM Mode(1)

COM0A1 COM0A0 Description

0 0 Normal port operation, OC0A disconnected.

WGM02 = 0: Norm al Port Operation, OC0A Disconnected.

WGM02 = 1: Toggle OC0A on Compare Match.

Clear OC0A on Compare Match, set OC0A at BOTT OM,

(non-inverti ng mode).

Set OC0A on Compare Match, clear OC0A at BOTTOM,

(inverting mode).

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Table 14-4 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor-

rect PWM mode.

Note: 1. A speci al case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at T OP. See ”Phase Correct PWM Mode” on

page 129 for more details.

• Bits 5:4 – COM0B1:0 : Compare Match Output B Mode

These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0

bits are set, the OC0B outpu t overr ides the no rmal por t functi onality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin

must be set in order to enable the output dr iver.

When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the

WGM02:0 bit setting. Table 14- 5 shows the COM0B1:0 bit functionality when the WGM02:0 bits

are set to a normal or CTC mode (non-PWM).

Table 14-6 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM

mode.

Note: 1. A speci al case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at TOP. See ”Fast PWM Mode” on page 102

for more details.

Table 14-4. Compare Output Mode, Phase Correct PWM Mod e(1)

COM0A1 COM0A0 Description

0 0 Normal port operation, OC0A disconnected.

WGM02 = 0: Normal Port Operation, OC0A Disconnecte d.

WGM02 = 1: Toggle OC0A on Compare Match.

Clear OC0A on Compare Match when up-counting . Set OC0A on

Compare Match when down-counting.

Set OC0A on Compare Match when up-counting. Clear OC0A on

Compare Match when down-counting.

Table 14-5. Compare Output Mode, non-PWM Mode

COM0B1 COM0B0 Description

0 0 Normal port operation, OC0B disconnected.

0 1 Toggle OC0B on Compare Match

1 0 Clear OC0B on Compare Match

1 1 Set OC0B on Compare Match

Table 14-6. Compare Output Mode, Fast PWM Mode(1)

COM0B1 COM0B0 Description

0 0 Normal port operation, OC0B disconnected.

01Reserved

Clear OC0B on Compare Match, set OC0B at BOTT OM,

(non-inverting mode)

Set OC0B on Compare Match, clear OC0B at BOTTOM,

(inverting mode).

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Table 14-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor-

rect PWM mode.

Note: 1. A speci al case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at T OP. See ”Phase Correct PWM Mode” on

page 103 for more details.

• Bits 3, 2 – Res: Reserved Bits

These bits are reserved bits in the ATmega48P/88P/168P/328P and will always read as zero.

• Bits 1:0 – WGM01: 0: Waveform Generation Mode

Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 14-8. Modes of operation supported by th e Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of

Pulse Width Modulation (PWM) mod es (s ee ”Modes of Operation” on page 100).

Notes: 1. MAX = 0xFF

2. BOTTOM = 0x00

Table 14-7. Compare Output Mode, Phase Correct PWM Mod e(1)

COM0B1 COM0B0 Description

0 0 Normal port operation, OC0B disconnected.

01Reserved

Clear OC0B on Compare Match when up-counting . Set OC0B on

Compare Match when down-counting.

Set OC0B on Compare Match when up-counting. Clear OC0B on

Compare Match when down-counting.

Table 14-8. Wa ve fo rm Ge ne ra tion Mo d e Bit Des crip tio n

Mode WGM02 WGM01 WGM00

Timer/Counter

Mode of

Operation TOP Update of

OCRx at TOV Flag

Set on(1)(2)

0 0 0 0 Normal 0xFF Immediate MAX

10 0 1

PWM, Phase

Correct 0xFF TOP BOTTOM

2 0 1 0 CTC OCRA Immediate MAX

3 0 1 1 Fast PWM 0xFF BOTT OM MAX

4 1 0 0 Reserved – – –

51 0 1

PWM, Phase

Correct OCRA TOP BOTTOM

6 1 1 0 Reserved – – –

71 1 1Fast PWMOCRABOTTOMTOP

110 8025D–AVR–03/08

ATmega48P/88P/168P/328P

14.9.2 T CCR 0B – Ti mer/ Co un t er Cont rol Register B

• Bit 7 – FOC0A: Force Output Compare A

The FOC0A bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit,

an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is

changed according to its COM0A1:0 bits setting. Note th at the FOC0A bit is implemented as a

strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the

forced compare.

A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR0A as TOP.

The FOC0A bit is always read as zero.

• Bit 6 – FOC0B: Force Output Compare B

The FOC0B bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit,

an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is

changed according to its COM0B1:0 bits setting. Note th at the FOC0B bit is implemented as a

strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the

forced compare.

A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR0B as TOP.

The FOC0B bit is always read as zero.

• Bits 5:4 – Res: Reserved Bits

These bits are reserved bits in the ATmega48P/88P/168P/328P and will always read as zero.

• Bit 3 – WGM02: Waveform Generation Mode

See the descript ion in the ”TCCR0A – Timer/Counter Control Register A” on page 107.

• Bits 2:0 – CS02:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter.

Bit 7 6 5 4 3 2 1 0

0x25 (0x45) FOC0A FOC0B – – WGM02 CS02 CS01 CS00 TCCR0B

Read/Write W W R R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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ATmega48P/88P/168P/328P

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

14.9.3 TCNT0 – Timer/Counter Regis ter

The Timer/Counter Register gives direct access, both for read and write operations, to the

Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare

Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,

introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.

14.9.4 OCR0A – Output C om pa r e Re gi st er A

The Output Compare Register A contains an 8-bit value that is continuously compared with the

counter value (TCNT0 ). A match can be used to generate an Output Com pare interrupt, or to

generate a waveform output on the OC0A pin.

14.9.5 OCR0B – Output C om pa r e Re gi st er B

The Output Compare Register B contains an 8-bit value that is continuously compared with the

counter value (TCNT0 ). A match can be used to generate an Output Com pare interrupt, or to

generate a waveform output on the OC0B pin.

Table 14-9. Clock Select Bit Description

CS02 CS01 CS00 Description

0 0 0 No clock source (Timer/Counter stopped )

001clk

I/O/(No prescaling)

010clk

I/O/8 (From prescaler)

011clk

I/O/64 (From prescaler)

100clk

I/O/256 (From prescaler)

101clk

I/O/1024 (From prescaler)

1 1 0 External clock source on T0 pin. Clock on falling edge.

1 1 1 External clock source on T0 pin. Clock on rising edge.

Bit 76543210

0x26 (0x46) TCNT0[7:0] TCNT0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

0x27 (0x47) OCR0A[7:0] OCR0A

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

0x28 (0x48) OCR0B[7:0] OCR0B

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

112 8025D–AVR–03/08

ATmega48P/88P/168P/328P

14.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register

• Bits 7..3 – Res: Reserved Bits

These bits are reserved bits in the ATmega48P/88P/168P/328P and will always read as zero.

• Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable

When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter Compar e Match B inte rrupt is enab led. The correspondin g interrup t is executed if

a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter

Interrupt Flag Register – TIFR0.

• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counte r0 Compare M a tch A interrup t is en ab le d. T h e co rr esponding int er rup t is execute d

if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the

Timer/Counter 0 Interrupt Flag Register – TIFR0.

• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer /Counter0 occurs, i.e., when th e TOV0 bit is set in the Timer/ Counter 0 Inter-

rupt Flag Register – TIFR0.

14.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register

• Bits 7..3 – Res: Reserved Bits

These bits are reserved bits in the ATmega48P/88P/168P/328P and will always read as zero.

• Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag

The OCF0B bit is set when a Compare Ma tch occurs be tween th e Timer/Co unter and the da ta in

OCR0B – Output Compare Reg ister0 B. O CF0B is cleared by ha rdware when execut ing the cor-

responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),

and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.

• Bit 1 – OCF0A: Timer/Counter 0 Output Compare A Match Flag

The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data

in OCR0A – Output Compare Regist er0. OCF0A is cleared by har dware when executin g the cor-

responding interrupt handling vector. Alternatively, OCF 0A is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),

and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.

Bit 7 6 5 4 3 2 1 0

(0x6E) – – – – – OCIE0B OCIE0A TOIE0 TIMSK0

Read/Write RRRRRR/WR/WR/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

0x15 (0x35) – – – – – OCF0B OCF0A TOV0 TIFR0

Read/Write R R R R R R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

113

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ATmega48P/88P/168P/328P

• Bit 0 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware

when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by

writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt

Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.

The setting of this fl ag is depen dent of t he WGM02: 0 bit set ting. Re fer t o Ta ble 14-8 , ”Waveform

Generation Mode Bit Description” on page 109.

114 8025D–AVR–03/08

ATmega48P/88P/168P/328P

15. 16-bit Timer/Counter1 with PWM

15.1 Features •Tru e 16-b it Desig n (i.e., Allow s 16-bit PWM)

•Two independent Output Compare Units

•Double Buffered Output Compare Registers

•One Input Capture Unit

•Input Capture Noise Canceler

•Clear Timer on Compare Match (Auto Reload)

•Glitch-free, Phase Correct Pulse Width Modulator (PWM)

•Variable PWM Period

•Frequency Generator

•External Event Counter

•Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)

15.2 Overview The 16-bit Timer/Counter unit allows accurate program execution timing (event management),

wave generation, and signal timing measurement.

Most register and bit references in this section are written in general form. A lower case “n”

replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit

channel. However, when using the register or bit defines in a progra m, the precise form must be

used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.

A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 15-1. For the actual

placement of I/ O pi ns, r efer to ”Pino ut ATmega4 8P/88P/ 16 8P/328 P” on page 2. CPU accessible

I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register

and bit locations are listed in the ”Register Description” on page 135.

The PRTIM1 bit in ”PRR – Power Reduction Register” on page 46 must be written to zero to

enable Timer/Counter1 module.

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Figure 15-1. 16-bit Timer/Counter Block Diagram(1)

Note: 1. Refer to Figure 1-1 on page 2, Table 13-3 on page 83 and Table 13-9 on page 89 for

Timer/Counter1 pin placement and description.

15.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capt ure Regis-

ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-

bit registers. These proced ures are described in the section ”Accessing 16-bit Registers” on

page 116. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no

CPU access re strictions. Int errupt requests (abbreviated to Int.Req. in the figure) signals are all

visible in the Timer Interrupt Flag Register (TIFR1). All interrupts are individually masked with

the Timer Interrupt Ma sk Re gist er (TI M SK1) . TI FR1 and TIMSK1 ar e no t sho wn in the figu re .

The Timer/Counter can be clocked inter nally, via the pre scaler, or by an external clock source on

the T1 pin. T he Clock Se lect logic blo ck controls which clock so urce and edge the Timer/Cou nter

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the Clock Select logic is referred to as the timer clock (clkT1).

The double buffered Output Compare Registers (OCR1A/B) are compared with the

Timer/Counter valu e at all tim e. T he r esult of the co mpare can b e used b y t he Wave fo rm Gene r-

ator to gene rate a PWM o r varia ble f requency ou tput on th e Out put Comp are pin (OC1A/B) . See

Clock Select

Timer/Counter

DATA B US

OCRnA

OCRnB

ICRn

TCNTn

Waveform

Generation

Waveform

Generation

OCnA

OCnB

Noise

Canceler

ICPn

Fixed

TOP

Values

Edge

Detector

Control Logic

TOP BOTTOM

Count

Clear

Direction

TOVn

(Int.Req.)

OCnA

(Int.Req.)

OCnB

(Int.Req.)

ICFn (Int.Req.)

TCCRnA TCCRnB

( From Analog

Comparator Ouput )

Edge

Detector

( From Prescaler )

clk

116 8025D–AVR–03/08

ATmega48P/88P/168P/328P

”Output Compare Units” on pa ge 123. The compare match eve nt will also set the Compare

Match Flag (OCF1A/B) which can be used to gen erate an Output Compare interrupt request.

The Input Capture Register can capture the Timer/Counter value at a given external (edge trig-

gered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (See

”Analog Comparator” on page 247) The Input Capture unit includes a digital filtering unit (Noise

Canceler) for reducing the chance of capturing noise spikes.

The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined

by either the OCR1A Register, the ICR1 Register, or by a set of fixed values. When using

OCR1A as TOP value in a PWM mode, the OCR1A Register can not be used for generating a

PWM output. However, the TOP value will in this case be double buffered allowing the TOP

value to be changed in ru n ti me. I f a fixed TOP valu e is req uired , t he ICR1 Reg i ster ca n be used

as an alternative, freeing the OCR1A to be used as PWM output.

15.2.2 Definitions The following definitions are used extensively throughout the section:

15.3 Accessing 16-bit Registers

The TCNT1, OCR1A/B, a nd ICR1 a re 16-b it re gisters tha t can b e acce ssed by t he AVR CPU via

the 8-bit data bu s. Th e 1 6- bit re giste r must be byte accessed u s ing tw o rea d o r write op erat ions.

Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit

access. The same temporary register is shared between all 16-bit registers within each 16-bit

timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a

16-bit register is written by the CPU, the high byte stored in the temporary register, and the low

byte written are bo th copied into the 16-bit re gister in the sam e clock cycle. When the lo w byte of

a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the tempo-

rary register in the same clock cycle as the low byte is read.

Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16-

bit registers does not involve using the temporary register.

To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low

byte must be read before the high byte.

The following code examples show how to access the 16-bit Timer Registers assuming that no

interrupts updates the temporary register. The same principle can be used directly for accessing

the OCR1A/B and ICR1 Registers. Not e that when using “C”, the compiler hand les the 16-bit

access.

BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.

MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the count

sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF,

or 0x03FF, or to the value stored in the OCR1A or ICR1 Register. The assignment is

dependent of the mode of operati on.

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Note: 1. See ”Abou t Code Examples” on page 8.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions th at allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “C BR”.

The assembly code examp le returns the TCNT1 value in the r17:r16 register pair.

It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt

occurs between the two instructions accessing the 16-bit register, and the interrupt code

updates the temporary register by accessing the same or any other of the 16-bit Timer Regis-

ters, then the result of the access outside the interrupt will be corrupted. Therefore, when both

the main code and the inte rrupt code updat e th e te mpora ry reg iste r, th e main code must di sable

the interrupts during the 16-bit access.

The following code examples show how to do an atomic read of the TCNT1 Register contents.

Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.

Assembly Code Examples(1)

...

; Set TCNT1 to 0x01FF

ldi r17,0x01

ldi r16,0xFF

out TCNT1H,r17

out TCNT1L,r16

; Read TCNT1 into r17:r16

in r16,TCNT1L

in r17,TCNT1H

...

C Code Examples(1)

unsigned int i;

...

/* Set TCNT1 to 0x01FF */

TCNT1 = 0x1FF;

/* Read TCNT1 into i */

i = TCNT1;

...

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Note: 1. See ”Abou t Code Examples” on page 8.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions th at allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “C BR”.

The assembly code examp le returns the TCNT1 value in the r17:r16 register pair.

The following code examples show how to do an atomic write of the TCNT1 Register contents.

Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.

Assembly Code Example(1)

TIM16_ReadTCNT1:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Read TCNT1 into r17:r16

in r16,TCNT1L

in r17,TCNT1H

; Restore global interrupt flag

out SREG,r18

ret

C Code Example(1)

unsigned int TIM16_ReadTCNT1( void )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Read TCNT1 into i */

i = TCNT1;

/* Restore global interrupt flag */

SREG = sreg;

return i;

}

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Note: 1. See ”Abou t Code Examples” on page 8.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions th at allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “C BR”.

The assembly code example requires that the r17:r16 register pair contains the value to be writ-

ten to TCNT1.

15.3.1 Reusing the Temporary High Byte Register

If writing to more t han one 16 -bit regist er where the high byte is the same f or all regi sters writte n,

then the high byte on ly needs to be written once. However, note that the same rule of atomic

operation described previously also applies in this case.

15.4 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source

is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits

located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and

prescaler, see ”Timer/Counter0 and Timer/Counter1 Prescalers” on page 142.

Assembly Code Example(1)

TIM16_WriteTCNT1:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Set TCNT1 to r17:r16

out TCNT1H,r17

out TCNT1L,r16

; Restore global interrupt flag

out SREG,r18

ret

C Code Example(1)

void TIM16_WriteTCNT1( unsigned int i )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Set TCNT1 to i */

TCNT1 = i;

/* Restore global interrupt flag */

SREG = sreg;

}

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15.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.

Figure 15-2 shows a block diagram of the counter and its surroundings.

Figure 15-2. Counter Unit Block Diagram

Signal description (internal signals):

Count Increment or de cre m en t TCNT1 by 1.

Direction Select between increment and decrement.

Clear Clear TCNT1 (set all bits to zero).

clkT1Timer/Counter clock.

TOP Signalize that TCNT1 has reached maximum value.

BOTTOM Signalize that TCNT1 has reached minimum value (zero).

The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) con-

taining the upper ei ght bits of the co unter, an d Counter Low (TCNT1L) containing the lower eight

bits. The TCNT1H Regist er can only be ind irect ly accessed by the CPU. When the CPU d oes an

access to the TCNT1H I/O locat ion, the CPU accesses the h igh byte tempor ary register (TEMP).

The temporary register is updated with the TCNT1H value when the T CNT1L is read, and

TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the

CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.

It is important to notice that there are special cases of writing to the TCNT1 Register when the

counter is counting that will give unpredictable results. The special cases are described in the

sections where they are of importance.

Depending on the mo de o f oper at ion us ed, the cou nt er is cleared , in cr eme nted , o r decr em ent ed

at each timer clock (clkT1). The clkT1 can be generated from an external or internal clock source,

selected by the Clock Select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the

timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of

whether clkT1 is present or not. A CPU write overrides (h as priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the Waveform Generation mode bits

(WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B).

There are close connectio ns between how the counter behaves (counts) and how wavefor ms

are generate d on the Out put Compare ou tputs OC1x. For more details abo ut advanced co unting

sequences and waveform generation, see ” Modes of Operation” on page 126.

TEMP (8-bit)

DATA BUS

(8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit) TCNTnL (8-bit) Control Logic

Count

Clear

Direction

TOVn

(Int.Req.)

Clock Select

TOP BOTTOM

Edge

Detector

( From Prescaler )

clkTn

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The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by

the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.

15.6 Input Capture Unit

The Timer/Counter incorporates an Input Capture unit that can capture external events and give

them a time -stamp in dicating t ime o f occurre nce. The externa l signal indica ting an e vent, or mul-

tiple events, ca n be app lied via the ICP1 pin o r al ter natively, via the analog- comparator unit. The

time-stamps can then be used to calculate frequency, duty-cycle, and other features of the sig-

nal applied. Alternatively the time-stamps can be used for creating a log of the events.

The Input Capture unit is illustrated by the block diagram shown in Figure 15-3. The elements of

the block diagram t hat are not directly a part of the Input Capture unit are gray shaded. The

small “n” in register and bit names indicates the Timer/Counter number.

Figure 15-3. Input Capture Unit Block Diagram

When a change of the lo gic level (a n event) oc curs on the Input Capt ure pin ( ICP1), a lt ernat ively

on the Analog Comparat or output (ACO), and this change confirms to the setting of the edge

detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter

(TCNT1) is written to the Input Capture Re gister (ICR1). The Input Capture Flag (ICF1) is set at

the same system clock as the TCNT1 value is copied into ICR1 Register. If enabled (ICIE1 = 1),

the Input Capture Fla g generates an Input Capture interru pt. The ICF1 Flag is automatically

cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software

by writing a logical one to its I/O bit location.

Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low

byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is copied

into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will

access the TEMP Register.

The ICR1 Register can only be written when using a Waveform Generation mode that utilizes

the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera-

ICFn (Int.Req.)

Analog

Comparator

WRITE ICRn (16-bit Register)

ICRnH (8-bit)

Noise

Canceler

ICPn

Edge

Detector

TEMP (8-bit)

DATA BUS

(8-bit)

ICRnL (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit) TCNTnL (8-bit)

ACIC* ICNC ICES

ACO*

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tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1

before the low byte is written to ICR1L.

For more information on how to access the 16-bit registers refer to ”Accessing 16-bit Registers”

on page 116.

15.6.1 Input Capture Trigger Source

The main trigger source for the Input Capture unit is the Input Capture pin (ICP1).

Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the

Input Capture unit. The An alog Comparator is selected as trigger source by setting the Analog

Comparator In put Capture (ACIC) bit in the Analog Comparator Control and Status Register

(ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag

must therefore be cleared after the change.

Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled

using the same techniqu e as for th e T1 pin (Figur e 16-1 on page 1 42). The edge d etector is a lso

identical. However, when the noise canceler is ena bled, additional logic is inserted before the

edge detector, which increases the delay by four system clock cycles. Note that the input of the

noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Wave-

form Generation mode that uses ICR1 to define TOP.

An Input Capture can be triggered by software by controlling the port of the ICP1 pin.

15.6.2 Noise Canceler

The noise canceler improves noise immunity by using a simple digital filtering scheme. The

noise canceler input is monit ored over four samples, and all four must be equal for changing the

output that in turn is used by the edge detector.

The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in

Timer/Counter Control Register B (TCCR1B). When enabled t he noise can celer intr oduces addi-

tional four system clock cycles of delay from a change applied to the input, to the update of the

ICR1 Register. The noise canceler uses the sy stem clock and is therefore not affected by the

prescaler.

15.6.3 Using the Input Capture Unit

The main challeng e when using the Inpu t Capture unit is to assign enoug h processor capacity

for handling the incoming events. The time between two events is critica l. If the processor has

not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be

overwritten with a new value. In this case the result of the capture will be incorrect.

When using the Input Capture interrupt, the ICR1 Register should be read as early in the inter-

rupt handler routine as possible. Even though the Input Capture interrupt has relatively high

priority, the maximum interrupt response time is dep endent on the maximum number of clock

cycles it takes to hand le an y of th e ot he r int er ru pt req ue sts .

Using the Input Capture unit in any mode of operation when the TOP value (resolution) is

actively changed during op eration, is not recommended.

Measurement of an external signal’s duty cycle requires that the trigger edge is changed after

each capture. Changin g the edge sensing must be done as early as po ssible after the ICR1

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cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,

the clearing of the ICF1 Flag is not required (if an interrupt handler is used).

15.7 Output Compare Units

The 16-bit comparator continuously compares TCNT1 with the Output Compare Register

(OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set th e Output

Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Com-

pare Flag generates an Output Compare interru pt. The OCF1x Flag is auto matically cleared

when the inter rupt is executed. Alternatively the OCF1x Flag can be cleared by software by writ-

ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to

generate an output according to operating mode set by the Waveform Generation mode

(WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals

are used by the Waveform Generator for handling the special cases of the extreme values in

some modes of operation (See Section “15.9” on page 126.)

A special feature of Output Co mpare unit A allows it to def ine the Timer/Coun ter TOP value (i.e.,

counter resolution). In addition to the counter resolution, the TOP value defines the period time

for waveforms generated by the Waveform Generator.

Figure 15-4 shows a b lock diagram o f the Ou tput Comp are u nit. The small “n” in the re gister and

bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output

Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output

Compare unit are gray shaded.

Figure 15-4. Output Compare Unit, Block Diagram

The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation

(PWM) modes. For the Normal and Clear Time r on Compare (CTC) modes of ope ration, the

double buffering is disabled. The double buffering synchronizes the update of the OCR1x Com-

pare Register to either TOP or BOTTOM of the counting sequence. The synchronization

OCFnx (Int.Req.)

(16-bit Comparator )

OCRnx Buffer (16-bit Register)

OCRnxH Buf. (8-bit)

OCnx

TEMP (8-bit)

DATA BUS

(8-bit)

OCRnxL Buf. (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit) TCNTnL (8-bit)

COMnx1:0WGMn3:0

OCRnx (16-bit Register)

OCRnxH (8-bit) OCRnxL (8-bit)

Waveform Generator

TOP

BOTTOM

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prevents the occurrence of odd-length, non-symm etrical PWM pulses, thereby making the out-

put glitch-free.

The OCR1x Register access may seem co mplex, but this is not case. Wh en the double buff ering

is enabled, the CPU has access to the OC R1x Buffer Register, and if double buffering is dis-

abled the CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Compare)

automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte

temporary register (TEMP). Howeve r, it is a good practice to read the low byte first as whe n

accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Reg-

ister since the compare of all 16 bits is done continuously. The high byte (OCR1xH) has to be

written first. When the high byte I/O location is written by the CPU, the TEMP Register will be

updated by the va lue written. Then whe n the low byte (OCR1xL) is written to the lower eight bits,

the high byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare

For more information of how to access the 16-bit registers refer to ”Accessing 16-bit Registers”

on page 116.

15.7.1 Force Output Compare

In non-PWM Waveform Generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC1x) bit. Forcing compare match will not set the

OCF1x Flag or reload/clear the timer, but the OC1x pin will be updated as if a real compare

match had occurred (the COM11:0 bits settings define wheth er the OC1x pin is set, cleared or

toggled).

15.7.2 Compare Match Blocking by TCNT1 Write

All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer

clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the

same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled.

15.7.3 Using the Output Compare Unit

Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNT1 when using any of the Output Compare

channels, independent of whether the Timer/Counter is running or not. If the value written to

TCNT1 equals the OCR1x value, the compare match will be missed, resulting in incorrect wave-

form generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP

values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF.

Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is downcounting.

The setup of the OC1x should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OC1x value is to use the Force Output Com-

pare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when

changing between Wa veform Generation modes.

Be aware that the COM1x1:0 bits are not double buffered together with the compare value.

Changing the COM1x1:0 bits will take effect immediately.

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15.8 Compare Match Output Unit

The Compare Output mode (COM1x1:0) bit s have two functions. Th e Waveform Gen erator uses

the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match.

Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 15-5 shows a simplified

schematic of th e logic affecte d by the COM1x1: 0 bit setting. The I/O Registers, I/O bits, and I/O

pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers

(DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the

OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a system reset

occur, the OC1x Register is reset to “0”.

Figure 15-5. Compare Match Output Unit, Schematic

The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform

Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

ble on the pin. The port override function is generally independent of the Waveform Generation

mode, but there are some exceptions. Refer to Table 15-1, Table 15-2 and Table 15-3 for

details.

The design of the Output Compare pin logic allows initializat ion of the OC1x state before t he out-

put is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of

operation. See Sectio n “15.11” on page 135 .

The COM1x1:0 bi ts have no effect on the Input Capture unit.

15.8.1 Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes.

For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the

OC1x Register is t o be performed on the next com pare match. F or compare output actions in t he

PORT

DDR

OCnx

Waveform

Generator

COMnx1

COMnx0

DATA B U S

FOCnx

clk

I/O

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non-PWM modes refer to Table 15-1 on pag e 135. For fast PWM mode refer to Table 15-2 on

page 136, and for phase correct and phase and frequency correct PWM refer to Table 15-3 on

page 136.

A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC1x strobe bits.

15.9 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the comb ination of the Wave form Generati on mode (WGM1 3:0) and Compare Output

mode (COM1x1: 0) bits. The Compare Output mode bits do no t affect the counting sequence,

while the Waveform Gener ation mode bits do . The COM1x1:0 bi ts control whether th e PWM out-

put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes

the COM1x1:0 bits control whe ther the output should be set, cleared or to ggle at a compare

match (See Section “15.8” on page 125.)

For detailed timing information refer to ” T imer/Counter Timing Diagrams” on page 133.

15.9.1 Normal Mode The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the

BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in

the same timer clock cycle as the TCNT1 becomes zero. The TOV1 Flag in this case behaves

like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow

interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by soft-

ware. There are no special cases to consider in the Normal mode, a new counter value can be

written anytime.

The Input Capture unit is easy to use in Normal mode. However, obse rve that the maximum

interval betwee n the e xtern al event s must not exceed the r esolutio n of t he count er. If the inter val

between events are too long, the timer overflow interrupt or the prescaler must be used to

extend the resolution for the capture unit.

The Output Compare units can be used to generate interrupts at some given time. Using the

Output Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time.

15.9.2 Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), th e OCR1A or ICR1 Register

are used to manipulat e th e counte r re so lut ion . I n CT C mode t he coun te r is cleare d to zero when

the counter value (TCNT1) matche s either th e OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 =

12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This

mode allows greate r contr ol of the co mpa re mat ch out put f reque ncy. I t also simpl ifie s the o per a-

tion of counting exter nal events.

The timing diagram for the CTC mode is shown in Figure 15-6. The counter value (TCNT1)

increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1)

is cleared.

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Figure 15-6. CTC Mode, Timing Diagram

An interrupt can be generated at each time the counter value reach es the TOP value by either

using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the

interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. How-

ever, changing th e TOP to a value close to BOTTOM when the cou nter is run ning with no ne or a

low prescaler value must be done with care since the CTC mode does not have the double buff-

ering feature. If the new value written to OCR1A or ICR1 is lower than the curre nt value of

TCNT1, the counter will miss the compare match. The counter will then have to count to its max-

imum value (0xFFFF) and wr ap around startin g at 0x0000 before the compare match can occur.

In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode

using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered.

For generatin g a wavefor m out put in CT C mod e, t he OC1A ou tput can be se t to toggle it s logica l

level on each compare match by setting the Compare Output mode bits to toggle mode

(COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless the data direction for

the pin is set to output (DDR_OC1A = 1). The waveform generated will have a maximum fre-

quency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The wavefo rm frequency is

defined by the fo llow i ng equation:

The N variable represents th e pr escaler factor (1 , 8, 64, 256, or 1024).

As for the Normal mode of op erat ion, the T OV1 Flag is se t in the same tim er clock cycle tha t the

counter counts from MAX to 0x0000.

15.9.3 Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a

high frequency PWM waveform generation optio n. The fast PWM differs from the other PWM

options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts

from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared

on the compare match between TCNT1 and OCR1x, and set at BOTTOM. In inverting Compare

Output mode output is set on compar e match and clear ed at BOTTOM. Due to th e single-slope

operation, t he operating fr equency of the f ast PWM mode can be twice as high as the phase cor-

rect and phase and frequency correct PWM modes that use dual-slope operation. This high

frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC

applications. High frequency allows physically small sized external components (coils, capaci-

tors), hence reduces total system cost.

TCNTn

OCnA

(Toggle)

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

1 4

Period

2 3

(COMnA1:0 = 1)

OCnA fclk_I/O

2N1OCRnA+()⋅⋅

-----------------------------------------------

----

128 8025D–AVR–03/08

ATmega48P/88P/168P/328P

The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or

OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the max-

imum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolutio n in bits can be

calculated by using the following equation:

In fast PWM mode the counter is incremented until the counter value matches either one of the

fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 =

14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer

clock cycle. The timing diagram for the fast PWM mode is shown in Figure 15-7. The figure

shows fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the

timing diagram shown as a histogram for illustrating the single-slope operation. The diagram

includes non-invert ed an d inver ted PWM ou tput s. The small ho rizonta l lin e m arks on th e TCNT1

slopes represent compare matches between OCR1x a nd TCNT1. The OC1x Interrupt Flag will

be set when a comp ar e m atch occurs.

Figure 15-7. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition

the OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A

or ICR1 is used fo r defining t he TOP value. If o ne of the inte rrupts are enab led, the interr upt han-

dler routine can be used for updating the TOP and compare values.

When changing the TOP value the prog ram must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.

Note that when using fixed TOP values the unused bits are masked to zero when any of the

OCR1x Registers are written.

The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP

value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low

value when the counter is ru nning wit h none or a low prescaler value, there is a r isk that t he new

ICR1 value written is lower than the current value of TCNT1. The result will then be that the

counter will miss the compare match at the TOP value. The counter will then have to count to the

MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.

The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location

RFPWM TOP 1+()log 2()log

-------------------------------

----

CNTn

OCRnx/TOP Update and

TOVn Interrupt Flag Set an

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

1 7

Period

2 3 4 5 6 8

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

129

8025D–AVR–03/08

ATmega48P/88P/168P/328P

to be written anytime. When the OCR1A I/O location is written the value written will be put into

the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value

in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done

at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set.

Using the ICR1 Regis ter for defining TOP work s well when using fixed TOP values. By using

ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,

if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A

as TOP is clearly a better choice due to its double buffer feature.

In fast PWM mode, the compare units allow ge neration of PWM waveforms on the OC1x pins.

Setting the COM1x1:0 bits to two will produce a inverted PWM and an non-inverted PWM output

can be generated by setting the COM1x1:0 to three (see Table on page 136). The actual OC1x

value will only be visible o n the port pin if the data direction for the port pin is set a s output

(DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at

the compare match between OCR1x and TCNT1, and clearing (or setting) the OC1x Register at

the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

The N variable re pr esents the pres cale r divider (1, 8, 64, 25 6, or 10 24 ).

The extreme values for the OCR1x Register represents special cases when generating a PWM

waveform output i n the fast PWM mode. If the OCR1x is set equal to BOTT OM (0x0000) the ou t-

put will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP

will result in a constant high or low output (depending on the polarity of the output set by the

COM1x1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC1A to toggle its logical level on each compare match (COM1A1:0 = 1). This applies only

if OCR1A is used to define the TOP v alue (WGM13:0 = 15). The waveform generated will have

a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). This feature is

similar to the OC1A toggle in CTC mode, except the double buffer feature of the Output Com-

pare unit is enabled in the fast PWM mode.

15.9.4 Phase Correct PWM Mode

The ph ase correct Pulse Width Modulation or phase co rrect PWM mode (WGM13:0 = 1, 2, 3,

10, or 11) provides a high resolution phase correct PWM waveform generation option. The

phase correct PWM mode is, like the phase and fre quency correct PWM m ode, based on a du al-

slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from

TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is

cleared on the compare match between TCNT1 and OCR1x while upcounting, and set on the

compare match while downcounting. In inverting Output Compare mode, the operation is

inverted. The dual-slope operation has lower m aximum operation frequency than single slope

operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes

are preferre d for motor control applications.

The PWM resolution for the phase corre ct PWM mode can be fixed t o 8-, 9-, or 10-b it, or defined

by either ICR1 or OCR1 A. The minimum resolution allowed is 2 -bit (ICR1 or OCR1A set to

OCnxPWM fclk_I/O

N1TOP+()⋅

-------------------------------

----

130 8025D–AVR–03/08

ATmega48P/88P/168P/328P

0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolu-

tion in bits can be calcul ated by using the following equation:

In phase correct PWM mode the counter is incremented until the counter value matches either

one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1

(WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the

TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock

cycle. The timing dia gram for the phase correct PWM mode is shown on Figure 15-8. The figure

shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1

value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The

diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on

the TCNT1 slopes repre sent compare matches betwe en OCR1x and TCNT1. The OC1x Inter-

rupt Flag will be set when a compare match occurs.

Figure 15-8. Phase Correct PWM Mode , Tim in g Dia gr am

The Timer/Count er Ove rfl ow Flag (TOV1) is se t each t ime th e co unte r r ea ches BO TTOM. When

either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accord-

ingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer

value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter

reaches the TOP or BOTTOM value.

When changing the TOP value the prog ram must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.

Note that when using fixed TOP values, the unused bits are masked to zero when any of the

OCR1x Registers are written. As the third period shown in Figure 15-8 illustrates, changing the

TOP actively while the Timer/Counter is running in the phase correct mode can result in an

unsymmetrical out put. T he rea son for this can be fo und in th e time of up date of the OCR1x Re g-

ister. Since the OCR 1x update occurs at TOP, the PWM period starts and ends at TOP. Th is

RPCPWM TOP 1+()log 2()log

-------------------------------

----

OCRnx/TOP Update and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

1 2 3 4

TOVn Interrupt Flag Set

(Interrupt on Bottom)

CNTn

eriod

Cnx

(COMnx1:0 =

131

8025D–AVR–03/08

ATmega48P/88P/168P/328P

implies that the length of the falling slo pe is determined by the previous TOP value, while the

length of the rising slope is determined by the new TOP value. When these two values differ the

two slopes of the period will differ in length. The difference in length gives the unsymmetrical

result on the output.

It is recommended to use the phase and frequency correct mode instead of the phase correct

mode when changin g the TOP value while the Timer/ Counter is running. When using a static

TOP value there are pr actically no differences betw een the two modes of operation.

In phase correct PWM mode, the compare units allow generation of PWM waveforms on the

OC1x pins. Setting the COM1x1:0 bits to tw o will produce a non-inverted PWM and an inverted

PWM output can be generated by setting the COM1x1:0 to three (See Ta ble on pa ge 136). The

actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as

output (DDR_O C1x) . The PWM wavef orm is gene rate d by set ting (or cle aring ) the OC 1x Regis-

ter at the compare match between OCR1x and TCNT1 when the counter increments, and

clearing (or setting) the OC1 x Register at compare match between OCR1x and TCNT1 when

the counter decreme nts. The PWM fre quency for the output when using phase correct PWM can

be calculated by the following equation:

The N variable re pr esents the pres cale r divider (1, 8, 64, 25 6, or 10 24 ).

The extreme values for the OCR1x Register represent special cases when generating a PWM

waveform output in the phas e correct PWM mode. If the OCR1x is set equal to BOTTOM the

output will be continuously low and if set equal to TOP the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If

OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the OC1A output

will toggle with a 50% duty cycle.

15.9.5 Phase and Frequency Correct PWM Mode

The phase and frequency correct Pu lse Width Mod ulation, or phase and frequen cy correct PWM

mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM wave-

form generation option. The phase and frequency correct PWM mode is, like the phase correct

PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM

(0x0000) to TOP and then from TO P to BOTTOM. In non-inverting Compare Output mode, the

Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while

upcounting, and set on the com pare match while downcounting. In inverting Comp are Output

mode, the operation is inverted. The dual-slope operation gives a lower maximum operation fre-

quency compared to the single-slope operation. However, due to the symmetric feature of the

dual-slope PWM mo de s, th es e mo de s ar e pr eferred for moto r co ntr ol applications.

The main difference between the phase correct, and the phase and frequency correct PWM

mode is the time the OCR1x Register is updated by the OCR1x Buffer Register, (see Figure 15-

8 and Figure 15-9).

The PWM resolution for the phase and frequency correct PWM m ode can be defin ed by either

ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and

fOCnxPCPWM fclk_I/O

2NTOP⋅⋅

----------------------------=

132 8025D–AVR–03/08

ATmega48P/88P/168P/328P

the maximum resolution is 16-bit (ICR1 or OCR1A set t o MAX). The PWM resolution in bits can

be calculated using the following equation:

In phase and frequency correct PWM mode the counter is incremented until the counter value

matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). Th e

counter has then reached the TOP and changes the count direction. The TCNT1 value will be

equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency

correct PWM mode is shown on Figure 15-9. Th e figure shows phase and frequency correct

PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing dia-

gram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-

inverted and in verted PWM o utputs. The small horizonta l line marks on the TCNT1 slopes repre-

sent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a

compare match occurs.

Figure 15-9. Phase and Frequency Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x

Registers are updat ed with the doub le buffer value ( at BOTTO M). Wh en either OCR1A o r ICR1

is used for defining the TO P value, the OC1A or ICF1 Flag set when TCNT1 has reached TOP.

The Interrupt Flags can then be used to generate an int er rup t ea ch ti me t he count er re aches the

TOP or BOTTOM value.

When changing the TOP value the prog ram must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.

As Figure 15-9 shows the output generated is, in contrast to the phase correct mode, symmetri-

cal in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising

and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore

frequency correct.

RPFCPWM TOP 1+()log 2()log

-------------------------------

----

OCRnx/TOP Updateand

TOVn Interrupt Flag Set

(Interrupt on Bottom)

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Se

(Interrupt on TOP)

1 2 3 4

CNTn

eriod

Cnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

133

8025D–AVR–03/08

ATmega48P/88P/168P/328P

Using the ICR1 Regis ter for defining TOP work s well when using fixed TOP values. By using

ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,

if the base PWM frequency is a ctively changed by chang ing the TOP value, using t he OCR1A as

TOP is clearly a better choice due to its double buffer feature.

In phase and frequency correct PWM mode, the compare units allow generation of PWM wave-

forms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and

an inverted PWM output can be generated by setting the COM1x1:0 to three (See Table on

page 136). The actual OC1x value will only be visible on the port pin if the data direction for the

port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing)

the OC1x Register at the compare match between OCR1x and TCNT1 when the counter incre-

ments, and clearing (or setting) the OC1x Register at compare match between OCR1x and

TCNT1 when the counter decrements. The PWM frequency for the output when using phase

and frequency correct PWM can be calculated by the following equation:

The N variable re pr esents the pres cale r divider (1, 8, 64, 25 6, or 10 24 ).

The extreme values for the OCR1x Register represents special cases when generating a PWM

waveform output in the phas e correct PWM mode. If the OCR1x is set equal to BOTTOM the

output will be continuously low and if set equal to TOP the output will be set to high for non-

inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A

is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle

with a 50% duty cycle.

15.10 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a

clock enable sign al in the following figures. Th e figures include information on whe n Interrupt

Flags are set, and when the OCR1x Register is up dated with the OCR1x buffer value (only for

modes utilizing double buffering). Figure 15-10 shows a timing diagra m for the se tting of OCF1x.

Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling

Figure 15-11 shows the same timing data, but with th e prescaler enabled.

fOCnxPFCPWM fclk_I/O

2NTOP⋅⋅

----------------------------=

clk

(

clkI/O/1)

CFnx

clk

I/O

CRnx

CNTn

OCRnx V alue

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

134 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 15-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8)

Figure 15-12 shows the count sequen ce close to TOP in var iou s mod es. When using ph ase and

frequency correct PWM mode t he OCR1x Register is updated at BOTTOM. The timin g diagrams

will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTO M+1 and so on.

The same renaming applies for modes that set the TOV1 Flag at BOTTOM.

Figure 15-12. Timer/Counter Timing Diagram, no Prescaling

CFnx

CRnx

CNTn

OCRnx V alue

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

clk

I/O

clk

(

clk

I/O

/8)

TOVn (FPWM)

and ICFn (if used

as T OP)

OCRnx

(Update at TOP)

TCNTn

(CTC and FPWM)

TCNTn

(

PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2

Old OCRnx Value New OCRnx Value

TOP - 1 TOP BOTTOM BOTTOM + 1

clk

(clk

I/O

/1)

clkI/O

135

8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 15-13 shows the same timing data, but with th e prescaler enabled.

Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

15.11 Register Description

15.11.1 TCCR1A – Timer/Counter1 Control Register A

• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A

• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B

The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respec-

tively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output

overrides the normal port functionality of the I/O pin it is connected to. If one or both of the

COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the

I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-

ing to the OC1A or OC 1B pin mu st be set in or de r to ena ble the out put dr ive r.

When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen-

dent of the WGM13:0 bits setting. Table 15-1 shows the COM1x1:0 bit functionality when the

WGM13:0 bits are set t o a Normal or a CTC mode (non-PWM).

TOVn (FPWM)

nd ICFn (if used

as T OP)

OCRnx

(Update at TOP)

TCNTn

(CTC and FPWM)

TCNTn

(PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2

Old OCRnx Value New OCRnx Value

TOP - 1 TOP BOTTOM BOTTOM + 1

clk

I/O

clk

(clk

I/O

/8)

Bit 76543210

(0x80) COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 TCCR1A

Read/Write R/W R/W R/W R/W R R R/W R/W

Initial Value00000000

Table 15-1. Compare Output Mode, non-PWM

COM1A1/COM1B1 COM1A0/COM1B0 Description

0 0 Norm al port operation, OC1A/OC1B disconnected.

0 1 Toggle OC1A/OC1B on Compare Match.

Clear OC1A/OC1B on Compare Match (Set output to

low level).

Set OC1A/OC1B on Compare Match (Set output to

high level).

136 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Table 15-2 shows the COM1x1 :0 bit functionality when the WGM13:0 bits are set to the fast

PWM mode.

Note: 1. A speci al case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In

this case the co mp a re match is ignored, but the set or clear is done at BOTTOM. See Section

“15.9.3” on page 127. for more details.

Table 15-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase

correct or the ph as e an d freq u en cy co rr ect , PW M m od e.

Note: 1. A speci al case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See

Section “15.9.4” on page 129. for more details.

• Bit 1:0 – WGM11:0: Waveform Generation Mode

Combined with the WGM13: 2 bit s found in t he TCCR1B Register, these bit s contr ol the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 15-4. Modes of operation supported by th e Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types

of Pulse Width Modulation (PWM) modes. (See Section “15.9” on page 126.).

Table 15-2. Compare Output Mode, Fast PWM(1)

COM1A1/COM1B1 COM1A0/COM1B0 Description

0 0 Normal port operation, OC1A/OC1B disconnected.

WGM13:0 = 14 or 15: To ggle OC1A on Compare

Match, OC1B disconnected (normal port operation).

For all other WGM1 settings, normal port op eration,

OC1A/OC1B disconnected.

Clear OC1A/OC1B on Compare Match, set

OC1A/OC1B at BOTTOM (non-inverting mode)

Set OC1A/OC1B on Compare Match, clear

OC1A/OC1B at BOTTOM (inverting mode )

Table 15-3. Compare Output Mode, Phase Correct an d Phase and Frequency Correct

PWM(1)

COM1A1/COM1B1 COM1A0/COM1B0 Description

0 0 Norm al port operation, OC1A/OC1B disconnected.

WGM13:0 = 9 or 11: Toggle OC1A on Compare

Match, OC1B disconnected (normal port operation) .

For all other WGM1 settings, normal port op eration,

OC1A/OC1B disconnected.

Clear OC1A/OC1B on Compare Match when up-

counting. Set OC1A/OC1B on Compare Match when

downcounting.

Set OC1A/OC1B on Compare Match wh en up -

counting. Clear OC1A/OC1B on Compare Match

when downcounting.

137

8025D–AVR–03/08

ATmega48P/88P/168P/328P

Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and

location of these bits are compatible with previous versions of the timer.

15.11.2 TCCR1B – Timer/Counter1 Control Register B

• Bit 7 – ICNC1: Input Capture Noise Canceler

Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is

activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four

successive equal va lued samples of the ICP1 pin for changing its output. The Input Capture is

therefore delayed by four Oscillator cycles when the noise canceler is enabled.

• Bit 6 – ICES1: Input Capture Edge Select

This bit selects wh ich edge on the Input Captur e pin (ICP1) that is used to trigg er a capture

event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and

when the ICES1 bit is written to one, a rising (pos itive) edge will trigger the capture.

When a capture is triggered according to the ICES1 setting, the counter value is copied into the

Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this

can be used to cause an Input Capture Interrupt, if this int errupt is enabled.

Table 15-4. Waveform Generation Mode Bit Description(1)

Mode WGM13 WGM12

(CTC1) WGM11

(PWM11) WGM10

(PWM10) Timer/Counter Mode of

Operation TOP Update of

OCR1x at TOV1 Flag

Set on

0 0 0 0 0 Normal 0xFFFF Immediate MAX

1 0 0 0 1 PWM, Pha s e Correct, 8-bit 0x00FF TOP BOTTOM

2 0 0 1 0 PWM, Pha s e Correct, 9-bit 0x01FF TOP BOTTOM

3 0 0 1 1 PWM, Pha s e Correct, 10-bit 0x0 3FF TOP BOTTOM

4 0 1 0 0 CTC OCR1A Immediate MAX

5 0 1 0 1 F ast PWM, 8-bit 0x00FF BOT TOM T OP

6 0 1 1 0 F ast PWM, 9-bit 0x01FF BOT TOM T OP

7 0 1 1 1 F ast PWM, 10-bit 0x03FF BOTT O M TOP

81000

PWM, Phase and Frequency

Correct ICR1 BOTTOM BOTTOM

91001

PWM, Phase and Frequency

Correct OCR1A BOTTOM BOTTOM

10 1 0 1 0 PWM, Phase Correct ICR1 TOP BOTTOM

11 1 0 1 1 PWM, Phase Correct OCR1A TOP BOTTOM

12 1 1 0 0 CTC ICR1 Immediate MAX

13 1 1 0 1 (Reserved) – – –

14 1 1 1 0 Fast PWM ICR1 BOTTOM TOP

15 1 1 1 1 Fast PWM OCR1A BOTTOM TOP

Bit 7 6 5 4 3 2 1 0

(0x81) ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the

TCCR1A and the TCCR1B Re gister), the ICP1 is disconnected and consequen tly the Input Ca p-

ture function is disabled.

• Bit 5 – Reserved Bit

This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be

written to zero when TCCR1B is written.

• Bit 4:3 – WGM13:2: Waveform Generation Mode

See TCCR1A Register description.

• Bit 2:0 – CS12:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure

15-10 and Figure 15-11.

If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

15.11.3 TCCR1C – Timer/Counter1 Control Register C

• Bit 7 – FOC1A: Force Output Compare for Channel A

• Bit 6 – FOC1B: Force Output Compare for Channel B

The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode.

When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on

the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0

bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the

value present in the COM1x1:0 bits that dete rmine the effect of the forced compare.

A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer

on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always

read as zero.

Table 15-5. Clock Select Bit Description

CS12 CS11 CS10 Description

0 0 0 No clock source (Timer/Counter stopped).

001clk

I/O/1 (No prescal i ng)

010clk

I/O/8 (From prescaler)

011clk

I/O/64 (From prescaler)

100clk

I/O/256 (From prescaler)

101clk

I/O/1024 (From prescaler)

1 1 0 External clock source on T1 pin. Clock on falling edge.

1 1 1 External clock source on T1 pin. Clock on rising edge.

Bit 7 6 5 4 3 2 1 0

(0x82) FOC1A FOC1B – – – – – – TCCR1C

Read/Write R/W R/W R R R R R R

Initial Value 0 0 0 0 0 0 0 0

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15.11.4 TCNT1H and TCNT1L – Timer/Counter1

The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct

access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To

ensure that both the high and low bytes are read and written simultaneously when the CPU

accesses these registers, the access is performed using an 8-bit temporary High Byte Register

(TEMP). This tempor ary register is shared b y all the ot her 1 6-bit r egister s. See Section “1 5.3” on

page 116.

Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a com-

pare match between TCNT1 and one of the OCR1x Registers.

Writing to the TCNT1 Register blocks ( rem oves) the comp ar e matc h on the followin g timer clock

for all compare units.

15.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A

15.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B

The Output Compare Registers contain a 16-bit value that is continuously compared with the

counter value (TCNT1 ). A match can be used to generate an Output Com pare interrupt, or to

generate a waveform output on the OC1x pin.

The Output Compa re Register s are 16-b it in size. To ensure t hat both the high and low bytes are

written simultaneously when th e CPU writes to these registers, the access is performed using an

8-bit temporary High Byte Register (TEM P). This temporary register is shared by all the other

16-bit register s. See Section “15.3” on page 116.

Bit 76543210

(0x85) TCNT1[15:8] TCNT1H

(0x84) TCNT1[7:0] TCNT1L

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

(0x89) OCR1A[15:8] OCR1AH

(0x88) OCR1A[7:0] OCR1AL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

(0x8B) OCR1B[15:8] OCR1BH

(0x8A) OCR1B[7:0] OCR1BL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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15.11.7 ICR1H and ICR1L – Input Capture Register 1

The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the

ICP1 pin (or opt ionally on t he Analo g Comparat or o utput f or Timer/ Counter 1). The Input Capture

can be used for defining the counter TOP value.

The Input Captur e Registe r is 16-bit in size . To en sure tha t both the high and low byt es are read

simultaneously when the CPU accesses these registers, the access is performed using an 8-bit

temporary High Byte Register (TEMP). Th is temporary register is shared by all the other 16-bit

registers. See Section “15.3” on page 116.

15.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register

• Bit 7, 6 – Res: Reserved Bits

These bits are unused bits in the ATmega48P/88P/168P/328P, and will always read as zero.

• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), th e Timer/Counter1 I nput Capture interru pt is enabled. The co rresponding Interru pt

Vector (see “Interrupts” on page 58) is executed when the ICF1 Flag, located in TIFR1, is set.

• Bit 4, 3 – Res: Reserved Bits

These bits are unused bits in the ATmega48P/88P/168P/328P, and will always read as zero.

• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), th e Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 58) is executed when the OCF1B Flag, located in

TIFR1, is set.

• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), th e Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 58) is executed when the OCF1A Flag, located in

TIFR1, is set.

• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector

(See ”Interrupts” on page 58) is executed when the TOV1 Flag, located in TIFR1, is set.

Bit 76543210

(0x87) ICR1[15:8] ICR1H

(0x86) ICR1[7:0] ICR1L

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

(0x6F) – – ICIE1 – – OCIE1B OCIE1A TOIE1 TIMSK1

Read/Write R R R/W R R R/W R/W R/W

Initial Value00000000

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15.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register

• Bit 7, 6 – Res: Reserved Bits

These bits are unused bits in the ATmega48P/88P/168P/328P, and will always read as zero.

• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag

This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register

(ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the

counter reaches the TOP value.

ICF1 is automatically cleared when the Input Ca pture Interrupt Vector is executed. Alternatively,

ICF1 can be cleared by wr iting a logic one to its bit location.

• Bit 4, 3 – Res: Reserved Bits

These bits are unused bits in the ATmega48P/88P/168P/328P, and will always read as zero.

• Bit 2 – OCF1B: Timer/Counter1, Output Compare B Matc h Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output

Compare Register B (OCR1B).

Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.

OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is exe-

cuted. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.

• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Matc h Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output

Compare Register A (OCR1A).

Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.

OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is exe-

cuted. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.

• Bit 0 – TOV1: Timer/Counter1, Overflow Flag

The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC modes,

the TOV1 Flag is set when the timer overflows. Refer to Table 15-4 on pag e 137 for the TOV1

Flag behavior when using another WGM13:0 bit setting.

TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed.

Alternatively, TOV1 can be cleared by writing a logic one to its bit location.

Bit 76543210

0x16 (0x36) – – ICF1 – – OCF1B OCF1A TOV1 TIFR1

Read/Write R R R/W R R R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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16. Timer/Counter0 and Timer/Counter1 Prescalers

”8-bit Timer/Counter0 with PWM” on page 95 and ”16-bit Timer/Counter1 with PWM” o n page

114 share the same prescale r module , but the Timer/C ounter s can hav e differe nt presca ler set-

tings. The description below applies to both Timer/Counter1 and Timer/Counter0.

16.1 Internal Clock Source

The Timer/Counter can be clocked d ire ctly by the system clock ( by se ttin g the CSn2 :0 = 1). This

provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system

clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a

clock source. The prescaled clock has a frequency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or

fCLK_I/O/1024.

16.2 Prescaler Reset

The prescaler is free running, i.e., oper ates independently of the Clock Select logic of the

Timer/Counter, and it is shared b y Timer/Counter1 and Time r/Counter0. Since the prescale r is

not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications

for situations where a prescaled clock is used. One example of prescaling artifacts occurs when

the timer is enabled a nd clo cked by th e prescale r ( 6 > CSn2: 0 > 1). The numb er of syst em clock

cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system

clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).

It is possible to use the prescaler reset for synchron izing the Timer/Counter to program execu-

tion. However, care must be taken if the other Timer/Counter that shares the same prescaler

also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is

connected to.

16.3 External Clock Source

An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock

(clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the p in syn chro nization

logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 16-1

shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector

logic. The regist ers are clocked at the p ositive edge of the internal system clock (clkI/O). The latch

is transparent in the hig h period of the internal system clock.

The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative

(CSn2:0 = 6) edge it detects.

Figure 16-1. T1/T0 Pin Sampling

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been app lied to the T1/T0 pin to the counter is updated.

Tn_sync

(To Clock

Select Logic)

Edge DetectorSynchronization

DQDQ

clkI/O

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Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least

one system clock cycle, otherwise it is a ri sk that a false Tim er/Counter clo ck pulse is gene rated.

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (fExtClk < fclk_I/O/2) give n a 50/50% duty cycle. Since th e edge detecto r uses

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, du e to variation of the system clock frequency

and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximum frequency of an exter nal clock source is less than fclk_I/O/2.5.

An external clock source can not be presca le d.

Figure 16-2. Prescaler for Timer/Counter0 and Timer/ Counter1(1)

Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 16-1.

PSRSYNC

Clear

clk

I/O

Synchronization

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16.4 Register Description

16.4.1 GTCCR – General Timer/Counter Control Register

• Bit 7 – TSM: Timer/Counte r Synchronization Mode

Writing the TSM b i t to on e a ctiva te s the Tim er/Counter Synch r on iza tio n mo d e. In th is m o de , th e

value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the correspond-

ing prescaler reset signals asserted. This ensures that the corresponding Timer/Coun ters are

halted and ca n be conf igured to the same value without the risk of one of t hem adva ncing dur ing

configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared

by hardware, and the Timer/Counters start counting simultaneously.

• Bit 0 – PSRSYNC: Prescaler Reset

When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor-

mally cleared im mediately by har dware, except if the TSM bit is set. Note tha t Timer/Counter1

and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both

timers.

Bit 765432 1 0

0x23 (0x43) TSM –––––PSRASY PSRSYNC GTCCR

Read/WriteR/WRRRRRR/WR/W

Initial Value000000 0 0

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17. 8-bit Timer/Counter2 with PWM and Asynchronous Operation

17.1 Features •Single Channel Counter

•Clear Timer on Compare Match (Auto Reload)

•Glitch-free, Phase Correct Pulse Width Modulator (PWM)

•Frequency Generator

•10-bit Clock Prescaler

•Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B)

•Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock

17.2 Overview Timer/Counter2 is a general purpose, single channel, 8-b it Timer/Counter module. A simplified

block diagram of the 8-bit Timer/Counter is shown in Figure 17-1. For the actual placement of

I/O pins, refer to ”Pinout ATmega48P/88P/168P/328P” on page 2. CP U accessible I/O Regis-

ters, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit

locations are liste d in th e ”Register Description” on page 159.

The PRTIM2 bit in ”Minimizing Power Consumption” on page 43 must be written to zero to

enable Timer/Counter2 module.

Figure 17-1. 8-bit Timer/Counter Block Diagram

Clock Select

Timer/Counter

DATA BUS

OCRnA

OCRnB

TCNTn

Waveform

Generation

Waveform

Generation

OCnA

OCnB

Fixed

TOP

Value

Control Logic

TOP BOTTOM

Count

Clear

Direction

TOVn

(Int.Req.)

OCnA

(Int.Req.)

OCnB

(Int.Req.)

TCCRnA TCCRnB

Edge

Detector

( From Prescaler )

clkTn

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17.2.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg-

isters. Interrupt request (sho rten as Int.Req.) signals are all visible in the Timer Interrupt F lag

(TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from

the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by

the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock

source he Timer/Counter uses to incr eme nt (or decreme nt ) its valu e. The Tim er/ Count er is inac-

tive when no clo ck source is selected. The out put from th e Clock Select logic is referre d to as the

timer clock (clkT2).

The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the

Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-

erator to generate a PWM or variable frequency output on the Output Compare pins (OC2A and

OC2B). See Section “17.5” on page 147. for details. The compare match event will also set the

Compare Flag (OCF2A or OCF2B) which can be used to generate an Output Compare interrupt

request.

17.2.2 Definitions Many register and bit refere nces in this document are written in general form. A lower case “n”

replaces the Timer/Counter number, in this case 2. However, when using the register or bit

defines in a program, the precise form must be used, i.e., TCNT2 for accessing Timer/Counter2

counter value and so on.

The definitions in Table 17-1 are also used extensively throughout the section.

17.3 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal synchronous or an external asynchronous

clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O. W hen the A S2

bit in the ASSR Register is written to logic one, th e clock sour ce is taken fr om the Timer /Counter

Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see ”ASSR

– Asynchronous Status Register” on page 165. For details on clock sources and prescaler, see

”Timer/Counter Prescaler” on page 157.

17.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

17-2 on page 147 shows a block diagram of the counter and its surrounding environment.

Table 17-1. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes zero (0 x00).

MAX The counter reache s its MAXimum when it becomes 0xFF (decimal 255).

TOP The counter reaches the TOP whe n it becom es equal to the high est value in the

count sequence. The TOP value can be assigned to be the fixed value 0xFF

(MAX) or the value stored in the OCR2A Register. The assignment is depen-

dent on the mode of operation.

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Figure 17-2. Counter Unit Block Diagram

Signal description (internal signals):

count Increment or de cre m en t TCNT2 by 1.

direction Selects between increment and decrement.

clear Clear TCNT2 (set all bits to zero).

clkTn Timer/Co un te r clo ck, re fe rr ed to as clk T2 in the following.

top Signalizes that TCNT2 has reached maximum value.

bottom Signalizes that TCNT2 has reached minimum value (zero).

Depending on the mo de o f oper at ion us ed, the cou nt er is cleared , in cr eme nted , o r decr em ent ed

at each timer clock (clkT2). clkT2 can be generated from an external or inte rnal clock source,

selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the

timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of

whether clkT2 is present or not. A CPU write overrides (has priority over ) all counter clear or

count operations.

The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in

the Timer/Counter Control Register (TCCR2A) and the WGM22 located in the Timer/Counter

Control Register B (TCCR2B). There are close connections between how the counter behaves

(counts) and how waveforms are generated on the Output Compare outputs OC2A and OC2B.

For more details about advanced counting sequences and waveform generation, see ”Modes of

Operation” on page 150.

The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by

the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt.

17.5 Output Compare Unit

The 8-bit comparator continuously compares TCNT2 with the Output Compare Register

(OCR2A and OCR2B). Whenever TCNT2 equa ls OCR2A or OCR2B, the comparator signals a

match. A match will set the Output Compar e Flag (OCF2A or OCF2 B) at the next timer clock

cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output

Compare interrupt . Th e Outp ut Co mpare Flag is aut om atica lly cleare d wh en the int errup t is exe-

cuted. Alternatively, the Output Com pare Flag can be cleared by software by writing a logical

one to its I/O bit location. The Waveform G enerator uses the match signal to generate an output

according to operating mode set by the WGM22:0 bits and Compare Output mode (COM2x1:0)

bits. The max and bottom signals are used by the Waveform Generator for handling the special

cases of the extreme values in some modes of operation (”Modes of Operation” on page 150).

Figure 17-3 shows a block diagram of the Output Compare unit.

DATA BUS

TCNTn Control Logic

count

TOVn

(Int.Req.)

topbottom

direction

clear

TOSC1

T/C

Oscillator

TOSC2

Prescaler

clk

I/O

clk Tn

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Figure 17-3. Output Compare Unit, Block Diagram

The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM)

modes. For the Nor mal and Clear Timer on Compare (CTC ) modes of operation, the double

buffering is di sabled. The double buffering sync hronizes the update of the OCR2x Compare

occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR2x Register access may seem co mplex, but this is not case. Wh en the double buff ering

is enabled, the CPU has access to the OC R2x Buffer Register, and if double buffering is dis-

abled the CPU will access the OCR2x directly.

17.5.1 Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC2x) bit. Forcing compare match will not set the

OCF2x Flag or reload/clear the timer, but the OC2x pin will be updated as if a real compare

match had occurred (the COM2x1:0 bits settings define whether the OC2x pin is set, cleared or

toggled).

17.5.2 Compare Match Blocking by TCNT2 Write

All CPU write operations to the TCNT2 Register will block any compare match that occurs in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR2x to be initial-

ized to the same value as TCNT2 wit hout trigg ering an inte rrupt when t he Timer/Coun ter clock is

enabled.

17.5.3 Using the Output Compare Unit

Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock

cycle, there are r isks involved when changing TCNT 2 when using the Output Compare channel,

independently of whether the Timer/Counter is running or not. If the value written to TCNT2

equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform

generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is

downcounting.

OCFnx (Int.Req.)

= (8-bit Comparator )

OCRnx

OCnx

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMnX1:0

bottom

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The setup of the OC2x should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OC2x value is to use the Force Output Com-

pare (FOC2x) strobe bit in Normal mode. The OC2x Register keeps its value even when

changing between Wa veform Generation modes.

Be aware that the COM2x1:0 bits are not double buffered together with the compare value.

Changing the COM2x1:0 bits will take effect immediately.

17.6 Compare Match Output Unit

The Compare Outpu t mode (COM2x1: 0) bits ha ve two funct ions. The Wavef orm Genera tor uses

the COM2x1:0 bits for defining the Output Compare (OC2x) state at the next compare match.

Also, the COM2x1:0 bits control the OC2x pin output source. Figure 17-4 shows a simplified

schematic of th e logic affecte d by the COM2x1: 0 bit setting. The I/O Registers, I/O bits, and I/O

pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers

(DDR and PORT) that are affected by the COM2x1:0 bits are shown. When referring to the

OC2x state, the reference is for the internal OC2x Register, not the OC2x pin.

Figure 17-4. Compare Match Output Unit, Schematic

The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform

Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

ble on the pin. The port override function is independent of the Waveform Generation mode.

The design of the Output Compare pin logic allows initializat ion of the OC2x state before t he out-

put is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of

operation. See Sectio n “17.11” on page 159 .

PORT

DDR

OCn

OCnx

Waveform

Generator

OMnx1

OMnx0

DATA BUS

OCnx

clk

I/O

150 8025D–AVR–03/08

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17.6.1 Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes.

For all modes, setting the COM2x1:0 = 0 tells the Waveform Generator that no action on the

OC2x Register is t o be performed on the next com pare match. F or compare output actions in t he

non-PWM modes refer to Table 17-5 on page 160. For fast PWM mode, refer to Table 17-6 on

page 160, and for phase correct PWM refer to Table 17-7 on page 161 .

A change of the COM2x1:0 bits state will have effect at the first compare match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC2x strobe bits.

17.7 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the comb ination of the Wave form Generati on mode (WGM22: 0) and Compare Ou tput

mode (COM2x1:0) bits. T he Compare Output mode bits do no t affect the counting sequence,

while the Waveform Gener ation mode bits do . The COM2x1:0 bi ts control whether th e PWM out-

put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes

the COM2x1:0 bits control whether the output should be set, cleared, or toggled at a compare

match (See Section “17.6” on page 149.).

For detailed timing information refer to ” T imer/Counter Timing Diagrams” on page 154.

17.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM22:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-

tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same

timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth

bit, except that it is only set, not cleared. However, combined with the timer overflo w interrupt

that automatically clears the TOV2 Flag, the timer resolution can be increased by software.

There are no special cases to consider in the Normal mode, a new counter value can be written

anytime.

The Output Compar e u nit can be used to ge nerat e int errup t s at so me given time . Usin g the Ou t-

put Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time.

17.7.2 Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM22:0 = 2), the OCR2A Register is used to

manipulate the count er resolut io n. In CTC mode the counter is clear ed to zero wh en the counter

value (TCNT2) matches the OCR2A. The OCR2A de fines the top value for the counter, hence

also its resolution. This m ode allows greater control of the compare ma tch output frequency. It

also simplifies the op e ra tio n of coun tin g exte rn al ev en ts.

The timing diagram for the CTC mode is shown in Figure 17-5. The counter value (TCNT2)

increases until a compare match occurs between TCNT2 and OCR2A, and then counter

(TCNT2) is cleared.

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Figure 17-5. CTC Mode, Timing Diagram

An interrupt can be generated each time the counter value reaches the TOP value by using the

OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-

ning with none or a low pres caler value must be done with care since the CTC mode does not

have the double buffering feature. If the new value written to OCR2A is lower than the current

value of TCNT2, the counter will miss the compare match. The counter will then have to count to

its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can

occur.

For generatin g a wavefor m out put in CT C mod e, t he OC2A ou tput can be se t to toggle it s logica l

level on each compare match by setting the Compare Output mode bits to toggle mode

(COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for

the pin is set to output. The waveform generated will have a maximum frequency of fOC2A =

fclk_I/O/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following

equation:

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the

counter counts from MAX to 0x00.

17.7.3 Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM22 :0 = 3 or 7) provides a high fre-

quency PWM waveform generation option. The fast PWM differs from the other PWM option by

its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOT-

TOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. In non-

inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match

between TCNT2 and OCR2x, and set at BOTTOM. In inverting Compare Output mode, the out-

put is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the

operating fr equency of the fast PWM mode can be twice as high as the phase correct PWM

mode that uses dual-slop e operation. This hig h frequency makes the fast PWM mode well suited

for power regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

CNTn

Cnx

(

Toggle)

OCnx Interrupt Flag Set

1 4

eriod 2 3

(COMnx1:0 = 1)

fOCnx fclk_I/O

2N1OCRnx+()⋅⋅

----------------------------------------------

----

152 8025D–AVR–03/08

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In fast PWM mode, the counter is incremented until the counter value matches the TOP value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

PWM mode is shown in Figure 17-6. The TCNT2 value is in the timing diagram shown as a his-

togram for illustrating the single-slope operation. The diagram includes non-inverted and

inverted PWM outputs. Th e small horizo ntal line marks on th e TCNT2 slopes represe nt compare

matches between OCR2x and TCNT2.

Figure 17-6. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveform s on the OC2x pin.

Setting the COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generate d by setting the COM2x1:0 to three. TOP is de fined as 0xFF whe n WGM2:0 = 3,

and OCR2A when MGM2:0 = 7. (See Table 17-3 on page 159). The actual OC2x value will only

be visible on the port pin if the data direction for the port pin is set as output. The PWM wave-

form is generated by setting (o r clearing) the OC2x Reg ister at the compare match between

OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the timer clock cycle the

counter is cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR2A Register represent special cases wh en generating a PWM

waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will

be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result

in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0

bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform

CNTn

OCRnx Update and

TOVn Interrupt Flag Set

eriod

2 3

Cnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Interrupt Flag Se

4 5 6 7

fOCnxPWM fclk_I/O

N256⋅

------------------=

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generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero. This fea-

ture is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output

Compare unit is enabled in the fast PWM mode.

17.7.4 Phase Correct PWM Mode

The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct

PWM waveform generation option. The phase correct PWM mode is based on a dual-slope

operation. The coun ter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-

TOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. In non-

inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match

between TCNT2 and OCR2 x while upco unting, and set on the compar e match while do wncoun t-

ing. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has

lower maximum operation frequency than single slope operation. However, due to the symmet-

ric feature of the dual-slope PWM modes, these modes are preferred for motor control

applications.

In phase correc t PWM mode the counter is increm ented until the counte r value matches TOP.

When the counter reaches TOP, it changes the count direction. The TCNT2 value will be equal

to TOP for one timer clo ck cycle. The tim ing dia gram fo r th e pha se correct PWM mode is shown

on F igure 17- 7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating

the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The

small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x

and TCNT2.

Figure 17-7. Phase Correct PWM Mode , Tim in g Dia gr am

The Timer/Counter Over flow Flag (TOV2) is set each time the counter reache s BOTTOM. The

Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM

TOVn Interrupt Flag Set

OCnx Interrupt Flag Set

1 2 3

CNTn

eriod

Cnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Update

154 8025D–AVR–03/08

ATmega48P/88P/168P/328P

output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when

WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (See Table 17-4 on page 160). The actual OC2x

value will only be visible on the port pin if the data direction for the port pin is set as output. The

PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match

between OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x

PWM frequency for the output when using phase correct PWM can be calculated by the follow-

ing equation :

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR2A Register represent special cases wh en generating a PWM

waveform output in the phase correct PWM mo de. If the OCR2A is set equal to BO TTOM, the

output will be continuously low and if set equal to MAX the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of period 2 in Figure 17-7 O Cnx has a transition from high to low even though

there is no Compare Match. The point of this transition is to guarantee sym metry around BOT-

TOM. There are two cases that give a transition without Compare Match.

• OCR2A changes its value from MAX, lik e in Figure 17-7. When the OCR2A value is MAX the

OCn pin value is the same as the result of a down-counting compare match. To ensure

symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-

counting Compare Match.

• The timer starts counting from a v alue higher than the one in OCR2A, and for that reason

misses the Compare Match and hence th e OCn change that w ould ha v e happe ned on the w a y

up.

17.8 Timer/Counter Timing Diagrams

The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2)

is therefore shown as a clock en able signal. In asynchronous mode, clkI/O should be replaced by

the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are

set. Figure 17-8 contains timing data for basic Timer/Counter operation. The figure shows the

count sequence close to the MAX value in all modes other than phase correct PWM mode.

Figure 17-8. Timer/Counter Timing Diagram, no Prescaling

Figure 17-9 shows the same timing data, but with the prescaler enabled.

fOCnxPCPWM fclk_I/O

N510⋅

------------------=

clk

(

clk

I/O

/1)

TOVn

clk

I/O

CNTn MAX - 1 MAX BOTTOM BOTTOM + 1

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Figure 17-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

Figure 17-10 shows the setting of OCF2A in all modes except CTC mode.

Figure 17-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8)

Figure 17-11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.

Figure 17-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (fclk_I/O/8)

TOVn

CNTn MAX - 1 MAX BOTTOM BOTTOM + 1

clkI/O

clkTn

(

clk

I/O

/8)

OCFnx

OCRnx

CNTn

OCRnx V alue

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

clk

I/O

clk

(

clk

I/O

/8)

OCFnx

OCRnx

CNTn

(CTC)

TOP

TOP - 1 TOP BOTTOM BOTTOM + 1

clk

I/O

clk

(

clk

I/O

/8)

156 8025D–AVR–03/08

ATmega48P/88P/168P/328P

17.9 Asynchronous Operation of Timer/Counter2

When Timer/Coun ter2 operates asynchronously, some considerations must be taken.

• Warning: When switching between asynchronous and synchronous clocking of

Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A saf e

procedure for switching clock source is:

a. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2.

b. Select clock source by setti ng AS2 as appropriate.

c. Write new values to TCNT2, OCR2x, and TCCR2x.

d. To switch to asynchronous operation : Wait for TCN2xUB, OCR2xUB, and TCR2xUB.

e. Clear the Timer/Counter2 Interrupt Flags.

f. Enable interrupts, if needed.

• The CPU main clock frequency must be more than four times the Oscillator frequency.

• When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is transferred to a

tempora ry register, and latched after two positive edges on TOSC1. The user should not write

a new value before the contents of the temporary register have been transferred to its

destination. Each of the five mentioned re gisters hav e their individual tempor ary register , which

means that e .g. writing to TCNT2 does not distur b an OCR2x write in progress. To detect that a

transf er to the destination register has tak en place, the Asynchronous Status Register – ASSR

has been implemented.

• When entering Power-save or ADC Noise Reduction mode after having written to TCNT2,

OCR2x, or TCCR2x, the user must wait until the written register has been updated if

Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode

before the changes are effective. This is particularly important if any of the Output Compare2

interrupt is used to wake up the device, since the Output Compare function is disabled during

writing to OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode

before the corresponding OCR2xUB bit returns to zero, the device will never receive a

compare match interrupt, and the MCU will not wake up.

• If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction

mode, precautions must be taken if the user wants to re-enter one of these modes: If re-

entering sleep mode within the TOSC1 cycle, the interrupt will immidiately occur and the

device wake up again. The result is multiple interrupts and wake-ups within one TOSC1 cycle

from the first in terrupt. If the user is in doubt whether the time bef or e re-entering Po wer- sav e or

ADC Noise Reduction mode is suffi cient, the following algorithm can be used to ensure that

one TOSC1 cycle has elapsed :

a. Write a value to TCCR2x, TCNT2, or OCR2x.

b. Wait until the corresponding Update Busy Flag in ASSR returns to zero.

c. Enter Power-save or ADC Noise Reduction mode.

• When the asynchronous operation is selected, the 32.768 kHz Oscillator f or Timer/Counter2 is

always running, except in Power-down and Standby modes. After a Power-up Reset or wake-

up from Po wer-do wn or Standb y mode , the user should be a w are of the fact that this Oscillator

might take as long as one second to stabilize. The user is advised to wait for at least one

second before using Timer/Counter2 after power-up or wake-u p from Power-down or Standby

mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up

from Power-down or Standby mode due to unstable clock signal upon start-up, no matter

whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.

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• Description of wake up from Power-save or ADC Noise Reduction mode when the timer is

clocked asynchrono usly: When the interrupt condition is met, the wake up process is started

on the following cycle of the timer clock, that is, the timer is always advanced by at least one

before the processor can read the counte r value. After wake-up, the MCU is halted for four

cycles, it executes the interrupt routine, and resumes execution from the instruction following

SLEEP.

• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect

result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be

done through a register synchronized to the internal I/O clock domain. Synchronization takes

place f or e v ery rising T OSC1 edge. When waking up from Power-sa v e mode , and the I /O clock

(clkI/O) again becomes active, TCNT2 will read as the previous v alue (before entering sleep)

until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-

sav e mode is essentially unpr edictab le, as it depends on the w ak e-up time. The recommended

procedure for reading TCNT2 is thus as follows:

a. Write any value to either of the registers OCR2x or TCCR2x.

b. Wait for the corr esponding Update Busy Flag to be cleared.

c. Read TCNT2.

During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous

timer takes 3 p rocessor cycles plus one t imer cycle. The timer is therefore advanced by at least

one before the processor can read the timer value causing the setting of the Interrupt Flag. The

Output Compare pin is changed on the time r clock and is not synchron ized to the processor

clock.

17.10 Timer/Counter Prescaler

Figure 17-12. Prescaler for Timer /Counter2

The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main

system I/O clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously

clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter

10-BIT T/C PRESCALER

TIMER/COUNTER2 CLOCK SOURCE

clkI/O clkT2S

TOSC1

AS2

CS20

CS21

CS22

clkT2S

/64

clkT2S

/128

clkT2S

/1024

clkT2S

/256

clkT2S

/32

SRASY

Clear

clkT2

158 8025D–AVR–03/08

ATmega48P/88P/168P/328P

(RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can

then be conne cted between the TOSC1 and TOSC2 pins to serve as an independent clock

source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal.

For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64,

clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected.

Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a

predictable prescaler.

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17.11 Register Description

17.11.1 TCCR2A – Timer/ Co un t er Cont rol Register A

• Bits 7:6 – COM2A1:0 : Compare Match Output A Mode

These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0

bits are set, the OC2A outpu t overr ides the no rmal por t functi onality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin

must be set in order to enable the output dr iver.

When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the

WGM22:0 bit setting. Table 17- 2 shows the COM2A1:0 bit functionality when the WGM22:0 bits

are set to a normal or CTC mode (non-PWM).

Table 17-3 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM

mode.

Note: 1. A speci al case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at BOTTOM. See ”Fast PWM Mode” on

page 151 for more details.

Bit 7 6 5 4 3210

(0xB0) COM2A1 COM2A0 COM2B1 COM2B0 – – WGM21 WGM20 TCCR2A

Read/Write R/W R/W R/W R/W R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 17-2. Compare Output Mode, non-PWM Mode

COM2A1 COM2A0 Description

0 0 Normal port operation, OC0A disconnected.

0 1 Toggle OC2A on Compare Match

1 0 Clear OC2A on Compare Match

1 1 Set OC2A on Compare Match

Table 17-3. Compare Output Mode, Fast PWM Mode(1)

COM2A1 COM2A0 Description

0 0 Normal port operation, OC2A disconnected.

WGM22 = 0: Norm al Port Operation, OC0A Disconnected.

WGM22 = 1: Toggle OC2A on Compare Match.

Clear OC2A on Compare Match, set OC2A at BOTT OM,

(non-inverti ng mode).

Set OC2A on Compare Match, clear OC2A at BOTTOM,

(inverting mode).

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Table 17-4 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase cor-

rect PWM mode.

Note: 1. A speci al case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at T OP. See ”Phase Correct PWM Mode” on

page 153 for more details.

• Bits 5:4 – COM2B1:0 : Compare Match Output B Mode

These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0

bits are set, the OC2B outpu t overr ides the no rmal por t functi onality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2B pin

must be set in order to enable the output dr iver.

When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the

WGM22:0 bit setting. Table 17- 5 shows the COM2B1:0 bit functionality when the WGM22:0 bits

are set to a normal or CTC mode (non-PWM).

Table 17-6 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM

mode.

Table 17-4. Compare Output Mode, Phase Correct PWM Mod e(1)

COM2A1 COM2A0 Description

0 0 Normal port operation, OC2A disconnected.

WGM22 = 0: Normal Port Operation, OC2A Disconnecte d.

WGM22 = 1: Toggle OC2A on Compare Match.

Clear OC2A on Compare Match when up-counting . Set OC2A on

Compare Match when down-counting.

Set OC2A on Compare Match when up-counting. Clear OC2A on

Compare Match when down-counting.

Table 17-5. Compare Output Mode, non-PWM Mode

COM2B1 COM2B0 Description

0 0 Normal port operation, OC2B disconnected.

0 1 Toggle OC2B on Compare Match

1 0 Clear OC2B on Compare Match

1 1 Set OC2B on Compare Match

Table 17-6. Compare Output Mode, Fast PWM Mode(1)

COM2B1 COM2B0 Description

0 0 Normal port operation, OC2B disconnected.

01Reserved

Clear OC2B on Compare Match, set OC2B at BOTT OM,

(non-inverti ng mode).

Set OC2B on Compare Match, clear OC2B at BOTTOM,

(inverting mode).

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Note: 1. A speci al case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at BOTTOM. See ”Phase Correct PWM

Mode” on page 153 for more details.

Table 17-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase cor-

rect PWM mode.

Note: 1. A speci al case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at T OP. See ”Phase Correct PWM Mode” on

page 153 for more details.

• Bits 3, 2 – Res: Reserved Bits

These bits are reserved bits in the ATmega48P/88P/168P/328P and will always read as zero.

• Bits 1:0 – WGM21: 0: Waveform Generation Mode

Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 17-8. Modes of operation supported by th e Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of

Pulse Width Modulation (PWM) mod es (s ee ”Modes of Operation” on page 150).

Notes: 1. MAX= 0xFF

2. BOTTOM= 0x00

Table 17-7. Compare Output Mode, Phase Correct PWM Mod e(1)

COM2B1 COM2B0 Description

0 0 Normal port operation, OC2B disconnected.

01Reserved

Clear OC2B on Compare Match when up-counting . Set OC2B on

Compare Match when down-counting.

Set OC2B on Compare Match when up-counting. Clear OC2B on

Compare Match when down-counting.

Table 17-8. Wa ve fo rm Ge ne ra tion Mo d e Bit Des crip tio n

Mode WGM2 WGM1 WGM0

Timer/Counter

Mode of

Operation TOP Update of

OCRx at TOV Flag

Set on(1)(2)

0 0 0 0 Normal 0xFF Immediate MAX

10 0 1

PWM, Phase

Correct 0xFF TOP BOTTOM

2 0 1 0 CTC OCRA Immediate MAX

3 0 1 1 Fast PWM 0xFF BOTTOM MAX

4 1 0 0 Reserved – – –

51 0 1

PWM, Phase

Correct OCRA TOP BOTTOM

6 1 1 0 Reserved – – –

71 1 1Fast PWM OCRABOTTOMTOP

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17.11.2 TCCR2B – Timer/ Co un t er Cont rol Register B

• Bit 7 – FOC2A: Force Output Compare A

The FOC2A bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2A bit,

an immediate Compare Match is forced on the Waveform Generation unit. The OC2A output is

changed according to its COM2A1:0 bits setting. Note th at the FOC2A bit is implemented as a

strobe. Therefore it is the value present in the COM2A1:0 bits that determines the effect of the

forced compare.

A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR2A as TOP.

The FOC2A bit is always read as zero.

• Bit 6 – FOC2B: Force Output Compare B

The FOC2B bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2B bit,

an immediate Compare Match is forced on the Waveform Generation unit. The OC2B output is

changed according to its COM2B1:0 bits setting. Note th at the FOC2B bit is implemented as a

strobe. Therefore it is the value present in the COM2B1:0 bits that determines the effect of the

forced compare.

A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR2B as TOP.

The FOC2B bit is always read as zero.

• Bits 5:4 – Res: Reserved Bits

These bits are reserved bits in the ATmega48P/88P/168P/328P and will always read as zero.

• Bit 3 – WGM22: Waveform Generation Mode

See the descript ion in the ”TCCR2A – Timer/Counter Control Register A” on page 159.

• Bit 2:0 – CS22:0: Clock Select

The three Clock Se lect bits select the cl ock source to be use d by the Timer/Co unter, see Table

17-9 on page 163.

Bit 7 6 5 4 3 2 1 0

(0xB1) FOC2A FOC2B – – WGM22 CS22 CS21 CS20 TCCR2B

Read/Write W W R R R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

17.11.3 TCNT2 – Timer/Counter Register

The Timer/Counter Register gives direct access, both for read and write operations, to the

Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare

Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,

introduces a risk of missing a Compare Match between TCNT2 and the OCR2x Registers.

17.11.4 OCR2A – Output Compare Register A

The Output Compare Register A contains an 8-bit value that is continuously compared with the

counter value (TCNT2). A match can be used to generate an Outp ut Compare interrupt, or to

generate a waveform output on the OC2A pin.

17.11.5 OCR2B – Output Compare Register B

The Output Compare Register B contains an 8-bit value that is continuously compared with the

counter value (TCNT2). A match can be used to generate an Outp ut Compare interrupt, or to

generate a waveform output on the OC2B pin.

Table 17-9. Clock Select Bit Description

CS22 CS21 CS20 Description

0 0 0 No clock source (Timer/Counter stopped).

001clk

T2S/(No prescaling)

010clk

T2S/8 (From prescaler)

011clk

T2S/32 (From prescaler)

100clk

T2S/64 (From prescaler)

101clk

T2S/128 (From prescaler)

110clk

T2S/256 (From prescaler)

111clk

T2S/1024 (From prescaler)

Bit 76543210

(0xB2) TCNT2[7:0] TCNT2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

(0xB3) OCR2A[7:0] OCR2A

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

(0xB4) OCR2B[7:0] OCR2B

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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17.11.6 TIMSK2 – Timer/Counter2 Interrupt Mask Register

• Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable

When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counte r2 Compare M a tch B interrup t is en ab le d. T h e co rr esponding int er rup t is execute d

if a compare match in Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the

Timer/Counter 2 Interrupt Flag Register – TIFR2.

• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable

When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counte r2 Compare M a tch A interrup t is en ab le d. T h e co rr esponding int er rup t is execute d

if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the

Timer/Counter 2 Interrupt Flag Register – TIFR2.

• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable

When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Cou nter2 occur s, i.e., when the TOV2 bit is se t in the Tim er/Count er2 Int errupt

Flag Register – TIFR2.

17.11.7 TIFR2 – Timer/Counter2 Interrupt Flag Register

• Bit 2 – OCF2B: Out put Compare Flag 2 B

The OCF2B bit is set ( one) when a compare match occurs between the Timer/Counter2 and the

data in OCR2B – Output Compare Register2. OCF2B is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic

one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counte r2 Compare match Interrupt

Enable), and OCF2B are set (one), the Timer/Counter2 Compare match Interrupt is executed.

• Bit 1 – OCF2A: Out put Compare Flag 2 A

The OCF2A bit is set ( one) when a compare match occurs between the Timer/Counter2 and the

data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic

one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counte r2 Compare match Interrupt

Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed.

• Bit 0 – TOV2: Timer/Counter2 Overflow Flag

The TOV2 bit is set (one) when an overflo w occurs in Time r/Coun te r2 . TO V2 is clear ed by har d-

ware when executing the corre spon ding int erru pt han dling vecto r. Alt ernat ively, TOV2 is clear ed

by writing a logic one to th e flag. When t he SREG I- bit, TO IE2 A (Timer /Co unte r2 Ove rfl ow Inte r-

rupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In

PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.

Bit 76543 2 1 0

(0x70) –––––OCIE2BOCIE2ATOIE2TIMSK2

Read/Write RRRRR R/WR/WR/W

Initial Value 00000 0 0 0

Bit 76543210

0x17 (0x37) –––––OCF2BOCF2ATOV2TIFR2

Read/Write R R R R R R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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17.11.8 ASSR – Asynchronous Status Register

• Bit 7 – RES: Reserved bit

This bit is reserved and will always read as zero.

• Bit 6 – EXCLK: Enable External Clock Input

When EXCLK is written to one, and asynchronous clock is selected, the external clock input

buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead

of a 32 kHz crystal. Writing to EXCLK should be done before asynchronous operation is

selected. Note that the crystal Oscillator will only run when this bit is zero.

• Bit 5 – AS2: Asynchronous Timer/Counter2

When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is

written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscil-

lator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A,

OCR2B, TCCR2A and TCCR2B might be corrupted.

• Bit 4 – TCN2UB: Timer/Counter2 Update Busy

When Timer/Counter2 operates asynchrono usly and TCNT2 is written, this bit becomes set.

When TCNT2 has been updated from the temporary storage register, this bit is cleared by hard-

ware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.

• Bit 3 – OCR2AUB: Output Compare Register2 Update Busy

When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set.

When OCR2A has been updated f rom the tem porary st orage register, this bit is cleared by hard-

ware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value.

• Bit 2 – OCR2BUB: Output Compare Register2 Update Busy

When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set.

When OCR2B has been updated f rom the tem porary st orage register, this bit is cleared by hard-

ware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value.

• Bit 1 – TCR2AUB: Timer/Counter Control Register2 Update Busy

When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set.

When TCCR2A has been updated from the temporary storage register, this bit is cleared by

hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new

value.

• Bit 0 – TCR2BUB: Timer/Counter Control Register2 Update Busy

When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set.

When TCCR2B has been updated from the temporary storage register, this bit is cleared by

hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new

value.

If a write is performed to any of the five Time r/Counter2 Registers while its update busy fla g is

set, the updated value might get corrupted and cause an unintentional interrupt to occur.

Bit 7 6 5 4 3 2 1 0

(0xB6) – EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB ASSR

Read/Write R R/W R/W R R R R R

Initial Value 0 0 0 0 0 0 0 0

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The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different.

When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A

and TCCR2B the value in the temporary storage register is read.

17.11.9 GTCCR – General Timer/Counter Control Register

• Bit 1 – PSRASY: Prescaler Reset Timer/Counter2

When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared

immediately by hardware. If the bit is writ ten when Timer/Counter2 is operating in asynchronous

mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by

hardware if the TSM bit is set. Refer to the description of the ”Bit 7 – TSM: Timer/Counter Syn-

chronization Mode” on pag e 144 for a description of the Timer/Counter Synchronization mode.

Bit 7 6 5 4 3 2 1 0

0x23 (0x4 3 ) TSM – – – – – PSRASY PSRSYNC GTCCR

Read/Write R/W R R R R R R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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18. SPI – Serial Peripheral Interface

18.1 Features •Full-duplex, Three-wire Synchronous Data Transfer

•Master or Slave Operation

•LSB Fir st or MSB First Data Transfer

•Seven Programmable Bit Rates

•End of Transmission Inte rrupt Flag

•Write Collision Flag Protection

•Wake-up from Idle Mode

•Double Speed (CK/2) Master SPI Mode

18.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the

ATmega48P/88P/168P/328P and peripheral devices or bet we en several AVR devices.

The USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 205. The

PRSPI bit in ”Minimizing Power Consumption” on page 43 must be written to zero to enable SPI

module.

Figure 18-1. SPI Block Diagram(1)

Note: 1. Refer to Figure 1-1 on page 2, and Table 13-3 on page 83 for SPI pin placement.

SPI2X

DIVIDER

/2/4/8/16/32/64/128

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The interconnection between Master and Slave CPUs with SPI is shown in Figure 18-2 on page

168. The system consists of two shift Registers, and a Master clock generator. The SPI Master

initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave.

Master and Slave prepare the data to be sent in their respective shift Registers, and the Master

generates th e requ ired cloc k pulses on the S CK line to interchange data. Data is always shifted

from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the

Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave

by pulling high the Slave Select, SS, line.

When configured as a Master, the SPI interface has no automatic control of the SS line. This

must be handled by user software before communication can start. When this is done, writing a

byte to the SPI Data Register starts the SPI clock generator, an d the hardware shifts the eight

bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of

Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an

interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or

signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be

kept in the Buffer Register for later use.

When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long

as the SS pin is driven high. In this sta te, software may update the contents of the SPI Data

until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission

Flag, SPIF is set. If the SPI Inte rrupt Enable bit, SPIE , in the SPCR Register is set, an interrupt

is requested. The Slave may continue to place new data to be sent into SPDR before reading

the incoming data. The last incoming byte will be kept in the Buffer Register for later use.

Figure 18-2. SPI Master-slave Interconnection

The system is single buffered in the transmit direction and double buffered in the receive direc-

tion. This means that bytes to be transmitted cannot be written to the SPI Data Register before

the entire shift cycle is completed. When receiving data, however, a received character must be

read from the SPI Data Register before the next character has been completely shifted in. Oth-

erwise, the first byte is lost.

In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure

correct sampling of the clock signal, the minimum low and high periods should be:

Low periods: Longer than 2 CPU clock cycles.

High periods: Longer than 2 CPU clock cycles.

SHIFT

ENABLE

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When the SPI is enab led, th e data di rection of the MO SI, MISO , SCK, and SS pins is overrid den

according to Table 18-1 on page 169. For more details on automatic port overrides, refer to

”Alternate Port Functions” on page 81 .

Note: See ”Alternate Functions of Port B” on page 83 for a detailed description of how to define the

direction of the user defined SPI pins.

The following code examples show how to initialize the SPI as a Master and how to perform a

simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction

actual data direction bits for these pins. E.g. if M OSI is placed on pin PB5, replace DD_MOSI

with DDB5 and DDR_SPI with DDRB.

Table 18-1. SPI Pin Overrides(Note:)

Pin Direction, Master SPI Direction, Slave SPI

MOSI User Defined Input

MISO Input User Defined

SCK User Defined Input

SS User Defined Input

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Note: 1. See ”About Code Examples” on page 8.

Assembly Code Example(1)

SPI_MasterInit:

; Set MOSI and SCK output, all others input

ldi r17,(1<<DD_MOSI)|(1<<DD_SCK)

out DDR_SPI,r17

; Enable SPI, Master, set clock rate fck/16

ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)

out SPCR,r17

ret

SPI_MasterTransmit:

; Start transmission of data (r16)

out SPDR,r16

Wait_Transmit:

; Wait for transmission complete

in r16, SPSR

sbrsr16, SPIF

rjmp Wait_Transmit

ret

C Code Example(1)

void SPI_MasterInit(void)

{

/* Set MOSI and SCK output, all others input */

DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);

/* Enable SPI, Master, set clock rate fck/16 */

SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);

}

void SPI_MasterTransmit(char cData)

{

/* Start transmission */

SPDR = cData;

/* Wait for transmission complete */

while(!(SPSR & (1<<SPIF)))

;

}

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The following code examples show how to initialize the SPI as a Slave and how to perform a

simple reception.

Note: 1. See ”About Code Examples” on page 8.

Assembly Code Example(1)

SPI_SlaveInit:

; Set MISO output, all others input

ldi r17,(1<<DD_MISO)

out DDR_SPI,r17

; Enable SPI

ldi r17,(1<<SPE)

out SPCR,r17

ret

SPI_SlaveReceive:

; Wait for reception complete

sbis SPSR,SPIF

rjmp SPI_SlaveReceive

; Read received data and return

in r16,SPDR

ret

C Code Example(1)

void SPI_SlaveInit(void)

{

/* Set MISO output, all others input */

DDR_SPI = (1<<DD_MISO);

/* Enable SPI */

SPCR = (1<<SPE);

}

char SPI_SlaveReceive(void)

{

/* Wait for reception complete */

while(!(SPSR & (1<<SPIF)))

;

/* Return Data Register */

return SPDR;

}

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18.3 SS Pin Functionality

18.3.1 Slave Mode When the SPI is configured as a Slave , the Slave Select (SS) pin is always input. When SS is

held low, the SPI is activated, and MISO becomes an output if configured so by the user. All

other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which

means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin

is driven high.

The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous

with the master clock generator. When the SS pin is driven high, the SPI slave will immediately

reset the send and receive logic, and drop any partially received data in th e Shift Register.

18.3.2 Master Mode When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the

direction of the SS pin.

If SS is configured as an output, the pin is a general output pin which does not affect the SPI

system. Typically, the pin will be driving the SS pin of the SPI Slave.

If SS is configured a s an inpu t, it m ust be held h igh to ensu re Mast er SPI operat ion. If the SS pin

is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin

defined as an input, the SPI system interprets this as another master selecting the SPI as a

slave and starti ng to se nd data t o it. To avoid bus con t ention , th e SPI syst em takes t he fo llowing

actions:

1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of

the SPI becoming a Slave, the MOSI and SCK pins become inputs.

2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enab led, and t he I-bit in SREG is

set, the interrupt routine will be executed.

Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi-

bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the

MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master

mode.

18.4 Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are

determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure

18-3 and Figure 18-4 on page 173. Data bits are shifted o ut and latched in on opposite edges of

the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by sum-

marizing Table 18-3 on page 174 and Table 18-4 on page 174, as done in Table 18-2.

Table 18-2. SPI Modes

SPI Mode Conditions Leading Edge Trailing eDge

0 CPOL=0, CPHA=0 Sample (Rising) Setup (Falling)

1 CPOL=0, CPHA=1 Setup (Rising) Sample (Falling)

2 CPOL=1, CP HA=0 Sample (Falling) Setup (Rising )

3 CPOL=1, CPHA=1 Setup (Falling) Sample (Rising)

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Figure 18-3. SPI Transfer Format with CPHA = 0

Figure 18-4. SPI Transfer Format with CPHA = 1

Bit 1

Bit 6

LSB

MSB

SCK (CPOL = 0)

mode 0

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SCK (CPOL = 1)

mode 2

MSB

LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

MSB first (DORD = 0)

LSB first (DORD = 1)

SCK (CPOL = 0)

mode 1

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SCK (CPOL = 1)

mode 3

MSB

LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

LSB

MSB

MSB first (DORD = 0)

LSB first (DORD = 1)

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18.5 Register Description

18.5.1 SPCR – SPI Control Register

• Bit 7 – SPIE: SPI Interrupt Enable

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if

the Global Interrupt Enable bit in SREG is set.

• Bit 6 – SPE: SPI Enable

When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI

operations.

• Bit 5 – DORD: Data Order

When the DORD bit is written to one, the LSB of the data word is transmitted first.

When the DORD bit is written to zero, the MSB of the data word is transmitted first.

• Bit 4 – MSTR: Master/Slave Select

This bit selects Master SPI mode when written to on e, and Slave SPI mode when written logic

zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,

and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable S PI Mas-

ter mode.

• Bit 3 – CPOL: Clock Polarity

When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low

when idle. Refer to Figure 18-3 and Figure 18-4 for an example. The CPOL functionality is sum-

marized below:

• Bit 2 – CPHA: Clock Phase

The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or

trailing (last) edge of SCK. Refer to Figure 18-3 and Figure 18-4 for an example. The CPOL

functionality is summarized below:

Bit 76543210

0x2C (0x4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 18-3. CPOL Functionality

CPOL Leading Edge Trailing Edge

0 Rising Falling

1 Falling Rising

Table 18-4. CPHA Functionality

CPHA Leading Edge Trailing Edge

0 Sample Setup

1 Setup Sample

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• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits contr ol the SCK ra te of t he dev ice configur ed as a Mast er. SPR1 and SPR0 ha ve

no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is

shown in the following table:

18.5.2 SPSR – SPI Status Register

• Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF Flag is set. An interrupt is generate d if SPIE in

SPCR is set and global interru pts are enabled. If SS is an input and is driven low when the SPI is

in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the

corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the

SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).

• Bit 6 – WCOL: Write COLlision Flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The

WCOL bit (and t he SPI F b it) ar e cleare d b y fi r st r eading t h e SPI Stat u s Regi ste r wit h WCOL set ,

and then accessing the SPI Data Register.

• Bit 5..1 – Res: Reserved Bits

These bits are reserved bits in the ATmega48P/88P/168P/328P and will always read as zero.

• Bit 0 – SPI2X: Double SPI Speed Bit

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI

is in Master mode (see Table 18-5). This means that the minimum SCK period will be two CPU

clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at fosc/4

or lower.

The SPI interface on the ATmega48P/88P/168P/328P is also used for program memory and

EEPROM downloading or uploading. See page 308 for serial programming and verification.

Table 18-5. Relationship Between SCK and the Oscillator Frequency

SPI2X SPR1 SPR0 SCK Frequency

000

fosc/4

001

fosc/16

010fosc/64

011fosc/128

100

fosc/2

101fosc/8

110fosc/32

111

fosc/64

Bit 76543210

0x2D (0x4D) SPIF WCOL – – – – – SPI2X SPSR

Read/Write RRRRRRRR/W

Initial Value 0 0 0 0 0 0 0 0

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18.5.3 SPDR – SPI Data Register

The SPI Data Register is a read/write register used for data transfer between the Register File

and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-

ter causes the Shif t Reg i ste r Rece ive bu ffer to be read.

Bit 76543210

0x2E (0x4E) MSB LSB SPDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial ValueXXXXXXXXUndefined

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19. USART0

19.1 Features •Full Duplex Operation (Independent Serial Receive and Transmit Registers)

•Asynchronous or Synchronous Op eration

•Master or Slave Clocked Synchronous Operation

•High Resolution Baud Rate Generator

•Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

•Odd or Even Parity Generation and Parity Check Supported by Hardware

•Data OverRun Detection

•Framing Error Detection

•Noise Filterin g Includes False Start Bit Detection and Digital Low Pass Filter

•Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

•Multi-processor Communication Mode

•Double Speed Asynchronous Communication Mode

19.2 Overview The Universal Syn chronous and Asynchronous serial Re ceiver and Transmitter (USART) is a

highly flexible serial communication device.

The USART0 can also be used in Master SPI mode, see “USART in SPI Mode” on page 205.

The Power Reduction USART bit, PRUSART0, in ”Minimizing Power Consumptio n” on pag e 43

must be disabled by writing a logical zero to it.

A simplified block diagram of the USART Tr ansm itter is shown in Fi gure 19 -1 on pag e 178. CPU

accessible I/O Registers and I/O pins are shown in bold.

The dashed boxe s in the blo ck diagr am se parat e th e thr ee main pa rts of the USART ( list ed fro m

the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.

The Clock Generation logic consists of synchronization logic for external clock input used by

synchronous slave operation, and the baud rate generator. The XCKn (Transfer Clock) pin is

only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a

serial Shift Register, Parity Generator and Control logic for handling different serial frame for-

mats. The write buffer allows a continuous transfer of data without any delay between frames.

The Receiver is the most complex part of the USART module due to its clock and data recovery

units. The recovery units are used for asynchronous data reception . In addition to the recovery

units, the Receiver includes a Parity Che cker, Control logic, a Shift Register and a two level

receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and

can detect Frame Error, Data OverRun and Parity Errors.

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Figure 19-1. USART Block Diagram(1)

Note: 1. Refer to Figure 1-1 on page 2 an d Table 13-9 on page 89 for USART0 pin placement.

19.3 Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver. The

USART supports four modes of clock operation: Normal asynchrono us, Double Speed asyn-

chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART

Control and Status Register C (UCSRnC) selects between asynchronous and synchronous

operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the

UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register

for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or

external (Slave mode). The XCKn pin is only active when using synchronous mode.

PARITY

GENERATOR

UBRRn [H:L]

UDRn(Transmit)

UCSRnA UCSRnB UCSRnC

BAUD RATE GENERATOR

TRANSMIT SHIFT REGISTER

RECEIVE SHIFT REGISTER RxDn

TxDn

CONTROL

UDRn (Receive)

CONTROL

XCKn

DATA

RECOVERY

CLOCK

RECOVERY

CONTROL

PARITY

CHECKER

DATA BUS

OSC

SYNC LOGIC

Clock Generator

Transmitter

Receiver

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Figure 19-2 shows a block diagram of the clock generation logic.

Figure 19-2. Clock Generation Logic, Block Diagram

Signal description:

txclk Transmitter clock (Internal Signal).

rxclk Receiver base clock (Internal Signal).

xcki Input from XCK pin (internal Signal). Used for synchronous slave

operation.

xcko Clock output to XCK pin (Internal Signal). Used for synchronous master

operation.

fosc XTAL pin frequency (System Clock).

19.3.1 Internal Clock Generation – The Baud Rate Generator

Internal clock generation is used for the asynchronous and the synchronous master modes of

operation. The descrip tion in this section refers to Figure 19-2.

The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a

programmable prescaler or bau d rate generator. The down-counter, running at system clock

(fosc), is loaded with the UBRRn value each time the counter has counted down to zero or when

the UBRRnL Register is written. A clock is generated each time the counter reaches zero. This

clock is the baud rate generator clock output (= fosc/(UBRRn+1)). The Transmitter divides th e

baud rate g enerato r clock outpu t by 2, 8 or 16 d epending on mode. Th e baud r ate genera tor ou t-

put is used directly by the Re ceiver’s clo c k and data recovery units. Howe ver, th e re co very unit s

use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the

UMSELn, U2Xn and DDR_XCKn bits.

Prescaling

Down-Counter /2

UBRRn

/4 /2

foscn

UBRRn+1

Sync

OSC

XCKn

txclk

U2Xn

UMSELn

DDR_XCKn

xcki

xcko

DDR_XCKn rxclk

Edge

Detector

UCPOLn

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Table 19-1 contains equations for calculating the baud rate (in bits per second) and for calculat-

ing the UBRRn value for each mode of operation using an internally gen erated clock source.

Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)

BAUD Baud rate (in bits per second, bps)

fOSC System Oscillator clock frequency

UBRRn Contents of the UBRRnH and UBRRnL Regi sters, (0-4095)

Some examples of UBRRn values for some system clock frequencies are found in Table 19-9

(see page 201).

19.3.2 Double Speed Operation (U2Xn)

The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has

effect for the asynchronous operation. Set this bit to zero when using synchronous operation.

Setting this bit will red uce the divisor of the baud rate divider from 16 to 8, effectively doubling

the transfer rate for asynchro nous communication. Note however that the Receiver will in this

case only use half the number of samples (reduced from 16 to 8) for data sampling and clock

recovery, and therefore a more accurate baud rate setting and system clock are required when

this mode is used. For the Transmitter, there are no downsides.

Table 19-1. Equations for Calculating Baud Rate Register Setting

Operating Mode Equation for Calculating Baud

Rate(1) Equation for Calculating

UBRRn Value

Asynchronous Normal mode

(U2Xn = 0)

Asynchronous Double Speed

mode (U2Xn = 1)

Synchronous Master mode

BAUD fOSC

16 UBRRn1+()

------------------------------------------=

UBRRnfOSC

16BAUD

------------------------

–=

BAUD fOSC

8UBRRn1+()

---------------------------------------=

UBRRnfOSC

8BAUD

--------------------

–=

BAUD fOSC

2UBRRn1+()

---------------------------------------=

UBRRnfOSC

2BAUD

--------------------

–=

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19.3.3 Exte rna l ClockExternal clocking is used by the synchronous slave modes of operation. The description in this

section refers to Figure 19-2 for details.

External clock input from the XCKn pin is sampled by a synchronizat ion re giste r to m inimize the

chance of meta-stability. The output from the synchronization register must then pass through

an edge detector b efore it can be used by the Transmitter and Rece iver. This process intro-

duces a two CPU clo ck peri od delay and t here fore the maximu m ext ernal XCKn clock fre quency

is limited by the following equation:

Note that fosc depends on the stability of the system clock source. It is therefore recommended to

add some margin to avoid possible loss of data due to frequency variations.

19.3.4 Synchronous Clock Operation

When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input

(Slave) or clock output (Master). The dependency between the clock edges and data sampling

or data change is the same. The basic principle is that data input (on RxDn) is sampled at the

opposite XCKn clock edge of the edge the data output (TxDn) is changed.

Figure 19-3. Synchronous Mode XCKn Timing.

The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is

used for data change. As Figure 19-3 shows, when UCPOLn is zero the data will be changed at

rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is set, the data will be changed

at falling XCKn edge and sampled at rising XCKn edge.

19.4 Frame Formats

A serial frame is define d to be o ne char acter of da ta bits with synchronization bits (start and stop

bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of

the following as va lid frame formats:

• 1 start bit

• 5, 6, 7, 8, or 9 data bits

• no, ev en or odd parity bit

• 1 or 2 stop bits

XCK fOSC

--------

---

RxD / TxD

XCK

RxD / TxD

XCK

UCPOL = 0

UCPOL = 1

Sample

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A frame starts w ith the s tart bit f ollowe d by t he leas t signif icant da ta b it. Then the next da ta bit s,

up to a total of nin e, are succeed ing, endin g with t he most sig nificant bit. If enab led, the pa rity bit

is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can

be directly followed by a new frame, or the communication line can be set to an idle (high) state.

Figure 19-4 illustrates the possible combinations of the frame formats. Bits inside brackets are

optional.

Figure 19-4. Frame Formats

St Start bit, always low.

(n) Data bits (0 to 8).

PParity bit. Can be odd or even.

Sp Stop bit, always high.

IDLE No transfers on the communication line (RxDn or TxDn). An IDLE line

must be high.

The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in

UCSRnB and UCSRnC. The Receiver and Transmitt er use t he same se tting. Not e that changing

the setting of any of these bits will corrupt all ongoing communication for both the Receiver and

Transmitter.

The USART Character SiZe (UCSZn 2:0) bits select the number of data bits in the frame. The

USART Parity mode (UPMn1:0) bits enable and set the type of parity bit. The selection between

one or two stop bits is done by the USART Stop Bit Select (USBSn) bit. The Receiver ignores

the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the

first stop bit is zero.

19.4.1 Parity Bit Calculation

The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the

result of the exclusive or is inverted. The relation between the parity bit and data bits is as

follows:

Peven Parity bit using even parity

Podd Parity bit using odd parity

dnData bit n of the character

If used, the parity bit is located between the last data bit and first stop bit of a serial frame.

10 2 3 4 [5] [6] [7] [8] [P]St Sp1 [Sp2] (St / IDLE)(IDLE)

FRAME

Peven dn1–…d3d2d1d00

Podd

⊕⊕⊕⊕⊕⊕

dn1–…d3d2d1d01⊕⊕⊕⊕⊕⊕

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19.5 USART Initialization

The USART has to be initialized bef ore any communication can take place. The init ialization pro-

cess normally consists of setting the baud rate, setting frame format and enabling the

Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the

Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the

initialization.

Before doing a re -in itia liza tio n with cha ng ed bau d rat e o r fr ame form at , be sure th at ther e are no

ongoing transmissions dur ing the per iod the reg ist ers are ch ang ed. Th e TXCn Flag can be used

to check that the Transmitter has completed all transfers, and the RXC Flag can be used to

check that there are no unread data in the receive buffer. Note that the TXCn Flag must be

cleared befo re eac h tra n s m issio n (b ef or e UDRn is written) if it is used for this purpose.

The following simple USART initializatio n code examples show one assembly and one C func-

tion that are equal in functionality. The examples assume asynchronous operation using polling

(no interru pts enable d) and a fixed fr ame format . The bau d rate is given as a funct ion paramet er.

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For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16

Registers.

Note: 1. See ”Abou t Code Examples” on page 8.

More advanced initialization ro ut ines can be mad e th at include fr ame forma t a s para met ers , dis-

able interrupts and so on. However, many applications use a fixed setting of the baud and

control registers, and for these types of applications the initialization code can be placed directly

in the main routine, or be combined with initialization code for other I/O modules.

19.6 Data Transmission – The USART Transmitter

The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UC SRnB

den by the USART and given the function as the Transmitter’s serial output. The baud rate,

mode of operation and fram e format must be set up once befor e doing any tran smissions. I f syn-

Assembly Code Example(1)

USART_Init:

; Set baud rate

out UBRRnH, r17

out UBRRnL, r16

; Enable receiver and transmitter

ldi r16, (1<<RXENn)|(1<<TXENn)

out UCSRnB,r16

; Set frame format: 8data, 2stop bit

ldi r16, (1<<USBSn)|(3<<UCSZn0)

out UCSRnC,r16

ret

C Code Example(1)

#define FOSC 1843200 // Clock Speed

#define BAUD 9600

#define MYUBRR FOSC/16/BAUD-1

void main( void )

{

...

USART_Init(MYUBRR)

...

}

void USART_Init( unsigned int ubrr)

{

/*Set baud rate */

UBRR0H = (unsigned char)(ubrr>>8);

UBRR0L = (unsigned char)ubrr;

Enable receiver and transmitter */

UCSR0B = (1<<RXEN0)|(1<<TXEN0);

/* Set frame format: 8data, 2stop bit */

UCSR0C = (1<<USBS0)|(3<<UCSZ00);

}

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chronous operation is used, the clock on the XCKn pin will be overridden and used as

transmission clock.

19.6.1 Sending Frames with 5 to 8 Data Bit

A data transmission is in itiated by loa ding the transmit buffer with t he data to be t ransmitted. The

CPU can load the transmit buffer by writing to the UDRn I/O location. The buffered data in the

transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new

frame. The Shif t Regi ster is loaded wit h new dat a if it is in id le stat e ( no ongoin g tr ansmission ) or

immediately after the last sto p bit of the pr evious frame is transmitte d. When th e Shift Register is

loaded with new data, it will transfer one complete frame at the rate given by the Baud Register,

U2Xn bit or by XCKn depending on mode of operation.

The following code examples show a simple USART transmit function based on polling of the

Data Register Empty (UDREn) Flag. When using frames with less than eight bits, the most sig-

nificant bits written to the UDRn are ignored. The USART has to be initialized before the function

can be used. For the assembly code, the data to be sen t is assumed to be store d in Register

R16

Note: 1. See ”Abou t Code Examples” on page 8.

The function simply waits for the transmit buffer to be empty by checking the UDREn Flag,

before loading it with new data to be transmitted. If the Data Register Empty interrupt is utilized,

the interrupt routine writes the data into the buffer.

19.6.2 Sending Frames with 9 Data Bit

If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in UCS-

RnB before the low byte of the character is written to UDRn. The following code examples show

Assembly Code Example (1)

USART_Transmit:

; Wait for empty transmit buffer

sbis UCSRnA,UDREn

rjmp USART_Transmit

; Put data (r16) into buffer, sends the data

out UDRn,r16

ret

C Code Example(1)

void USART_Transmit( unsigned char data )

{

/* Wait for empty transmit buffer */

while ( !( UCSRnA & (1<<UDREn)) )

;

/* Put data into buffer, sends the data */

UDRn = data;

}

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a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is

assumed to be stored in regist ers R17:R16.

Notes: 1. These transmit functions are written to be general functions. They can be optimized if the con-

tents of th e UCSRn B is static . F or exam ple , only the TXB8 bit of the UCSRnB Register is used

after initialization.

2. See ”About Code Examples” on page 8.

The ninth bit can be used for indicating an address frame when using multi processor communi-

cation mode or for ot he r pr ot oc ol ha nd lin g as fo r ex a m ple syn chr o niza tio n.

19.6.3 Transmitter Flags and Interrupts

The USART Transmitter has two flags that indicate its state: USART Data Register Empty

(UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts.

The Data Register Empty (U DREn) Flag indicates whether the tran smit buffer is ready to re ceive

new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer

contains data to be transmitted that has not yet been moved into the Shift Re gister. For compat-

ibility with future devices, always write this bit to zero when writing the UCSRnA Register.

When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the

USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that

global interrupts are enabled). UDREn is cleared by writing UDRn. When interrupt-driven data

transmission is used, the Data Register Empty interrupt routine must either write new data to

Assembly Code Example(1)(2)

USART_Transmit:

; Wait for empty transmit buffer

sbis UCSRnA,UDREn

rjmp USART_Transmit

; Copy 9th bit from r17 to TXB8

cbi UCSRnB,TXB8

sbrc r17,0

sbi UCSRnB,TXB8

; Put LSB data (r16) into buffer, sends the data

out UDRn,r16

ret

C Code Example(1)(2)

void USART_Transmit( unsigned int data )

{

/* Wait for empty transmit buffer */

while ( !( UCSRnA & (1<<UDREn))) )

;

/* Copy 9th bit to TXB8 */

UCSRnB &= ~(1<<TXB8);

if ( data & 0x0100 )

UCSRnB |= (1<<TXB8);

/* Put data into buffer, sends the data */

UDRn = data;

}

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UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new

interrupt will occur once the interrupt routine terminates.

The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift

The TXCn Flag bit is automatically cleared when a transmit complete interrupt is executed, or it

can be cleared by writin g a one to its b it locatio n. The TXCn Flag is useful in half-duplex commu-

nication interfaces (like the RS-485 standard), where a transmitting application must enter

receive mode and free the communication bus immediately after completing the tra nsmission.

When the Transmit Compete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the USART

Transmit Complete Interrupt will be executed when the TXCn Flag becomes set (provided that

global interrupts are enabled). When the transmit complete interrupt is used, the interrupt han-

dling routine does not have to clear the TXCn Flag, this is done automatically when the interrupt

is executed.

19.6.4 Parity Generator

The Parity Gene rator calculat es the par ity bit f or the serial frame data. When parity bit is enabled

(UPMn1 = 1), the transmitter control logic inserts the parity bit between the last data bit and the

first stop bit of the frame that is sent.

19.6.5 Disabling the Transmitter

The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongo-

ing and pending transmissions are completed, i.e., when the Transmit Shift Register and

Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter

will no longer override the TxDn pin.

19.7 Data Reception – The USART Receiver

The USART Receiver is enabled by writing the Receive Enable (RXENn) bit in the

UCSRnB Register to one. When th e Receiver is enabled, the normal pin operation of the RxDn

pin is overridden by the USART and given the function as the Rec eiver’s ser ial input. The bau d

rate, mode of operation and frame format must be set up once before an y serial reception can

be done. If synchronous operation is used, the clock on the XCKn pin will be used as transfer

clock.

19.7.1 Receiving Frames with 5 to 8 Data Bits

The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start

bit will be sampled at the baud rate or XCKn clock, and shifted into the Re ceive Shift Register

until the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver.

When the first stop bit is received, i.e., a complete serial frame is present in the Receive Shift

buffer can then be read by reading the UDRn I/O location.

The following code example shows a simple USART receive function based on polling of the

Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant

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bits of the data read from the UDRn will be masked to zero. The USART has to be initi alized

before the function can be used.

Note: 1. See ”About Code Examples” on page 8.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions th at allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “C BR”.

The function simply waits for data to be present in the receive buffer by checking the RXCn Flag,

before readin g the buffer and returning the value.

19.7.2 Receiving Frames with 9 Data Bits

If 9-bit chara cters are used (UCSZ n=7) the ninth b it must be read fr om the RXB8n bit in UC S-

RnB before reading the low bits from the UDRn. This rule applies to the FEn, DORn and UPEn

Status Flags as well. Read status from UCSRnA, then data from UDRn. Reading the UDRn I/O

location will change the state of the receive buffer FIFO and consequently the TXB8n, FEn,

DORn and UPEn bits, which all are stored in the FIFO, will change.

The following code example shows a simple USART receive function that handles both nine bit

characters and the status bits.

Assembly Code Example(1)

USART_Receive:

; Wait for data to be received

sbis UCSRnA, RXCn

rjmp USART_Receive

; Get and return received data from buffer

in r16, UDRn

ret

C Code Example(1)

unsigned char USART_Receive( void )

{

/* Wait for data to be received */

while ( !(UCSRnA & (1<<RXCn)) )

;

/* Get and return received data from buffer */

return UDRn;

}

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Note: 1. See ”About Code Examples” on page 8.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions th at allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “C BR”.

The rece ive function example r eads all th e I/O Registers into the Register File before any com-

putation is done. This gives an optimal receive buffer utilization since the buffer location read will

be free to accept new data as early as possible.

Assembly Code Example(1)

USART_Receive:

; Wait for data to be received

sbis UCSRnA, RXCn

rjmp USART_Receive

; Get status and 9th bit, then data from buffer

in r18, UCSRnA

in r17, UCSRnB

in r16, UDRn

; If error, return -1

andi r18,(1<<FEn)|(1<<DORn)|(1<<UPEn)

breq USART_ReceiveNoError

ldi r17, HIGH(-1)

ldi r16, LOW(-1)

USART_ReceiveNoError:

; Filter the 9th bit, then return

lsr r17

andi r17, 0x01

ret

C Code Example(1)

unsigned int USART_Receive( void )

{

unsigned char status, resh, resl;

/* Wait for data to be received */

while ( !(UCSRnA & (1<<RXCn)) )

;

/* Get status and 9th bit, then data */

/* from buffer */

status = UCSRnA;

resh = UCSRnB;

resl = UDRn;

/* If error, return -1 */

if ( status & (1<<FEn)|(1<<DORn)|(1<<UPEn) )

return -1;

/* Filter the 9th bit, then return */

resh = (resh >> 1) & 0x01;

return ((resh << 8) | resl);

}

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19.7.3 Receive Compete Flag and Interrupt

The USART Receiver has one flag that indicates the Receiver state.

The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive

buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive

buffer is empty (i.e., doe s not co ntain any unr ead data) . If the Receive r is disabled (RXENn = 0),

the receive buffer will be flushed and consequently the RXCn bit will become zero.

When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receiv e

Complete interrupt will be executed as long as the RXCn Flag is se t (provided that global inter-

rupts are enabled). When interrupt-driven data reception is used, the receive complete routine

must read the received data from UDRn in order to clear the RXCn Flag, otherwise a new inter-

rupt will occur once the interrupt routine terminates.

19.7.4 Rece iv er Error Flags

The USART Receiver has three Error Flag s: Frame Er ror (FEn), Data OverRun (DORn) and

Parity Error (UPEn). All can be accessed by reading UCSRnA. Common for the Error Flags is

that they are located in the receive buffer together with the frame for which they indicate the

error status. Due to the buffering of the Error Flags, the UCSRnA must be read before the

receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read location.

Another equality for the Error Flags is that they can not be alte red by software doing a write to

the flag location. However, all flags must be set to zero when the UCSRnA is written for upward

compatibility of future USART implementations. None of the Error Flags can generate interrupts.

The Frame Error (FEn ) Flag indicates the state of the first stop bit of the next read able frame

stored in th e rec eive b uffer. The FEn Flag is zero when t he st op b it was c orre ctly re ad ( as on e),

and the FEn Flag will be one when the stop bit was incorrect (zero). This flag can be used for

detecting out-of -sync conditions, detecting br eak conditions and protocol h andling. The FEn

Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all,

except for the first, stop bits. For com patibility with future devices, always set this bit to zero

when writing to UCSRnA.

The Data OverRun (DORn) Flag indicates data loss due to a receiver bu ffer full condition. A

Data OverRun occurs when the receive buffer is full (two characters), it is a new character wait-

ing in the Receive Shift Register, and a new start bit is detected. If the DORn Flag is set there

was one or more serial frame lost between the frame last read from UDRn, and the next frame

read from UDRn. For compatibility with future devices, alway s write this bit to zero when writing

to UCSRnA. The DORn Flag is cleared when the frame received was successfully moved from

the Shift Register to the receive buffer.

The Parity Error (UPEn) Flag indicates tha t the next frame in the receive buffer had a Parity

Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For

compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more

details see ”Parity Bit Calculation” on pa ge 182 and ”Parity Checker” on page 190.

19.7.5 Parity CheckerThe Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of Par-

ity Check to be performed (odd or even) is selected by the UPMn0 bit. When en abled, the Parity

Checker calculates the parity of the data bits in incoming frames and compares the result with

the parity bit f rom the serial fr ame. The resu lt of the ch eck is stored in the rece ive buffe r together

with the rece ive d da ta an d sto p bit s. T h e Par i ty E rr or (UPEn) Flag ca n th en b e r ea d by so ftware

to check if the frame had a Parity Error.

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The UPEn bit is set if the next character that can be read from the receive buffer had a Parity

Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is

valid until the receive buffer (UDRn) is read.

19.7.6 Disabling the Receiver

In contrast to the Transmitter, disabling of the Receiver will be immed iate. Data from ongoing

receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will

no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be

flushed when the Receiver is disabled. Remaining data in the buffer will be lost

19.7.7 Flushing the Receive Buffer

The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be

emptied of its contents. Unrea d data will be lost. If the buffer has to be flushed during normal

operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag

is cleared. The following code example shows how to flush the receive buffer.

Note: 1. See ”About Code Examples” on page 8.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions th at allow access to extended I/O. Typically

“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “C BR”.

19.8 Asynchronous Data Reception

The USART includes a clock recovery and a data recovery unit for handling asynchronous data

reception. The clock recovery logic is used for synchronizing the internally generated baud rate

clock to the incoming asyn ch ronou s se rial fram es at t he RxDn pin . T he data re co very lo gic sam-

ples and low pass filters each incoming bit, thereby improving the noise immunity of the

Receiver. The asynchronous reception operational range depends on the accuracy of the inter-

nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.

19.8.1 Asynchronous Clock Recovery

The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 19-5

illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times

the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The hor-

izontal arrows illustrate the synchronization variation due to the sampling process. Note the

larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples

denoted zero are samples done when the RxDn line is idle (i.e., no communication activity).

Assembly Code Example(1)

USART_Flush:

sbis UCSRnA, RXCn

ret

in r16, UDRn

rjmp USART_Flush

C Code Example(1)

void USART_Flush( void )

{

unsigned char dummy;

while ( UCSRnA & (1<<RXCn) ) dummy = UDRn;

}

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Figure 19-5. Start Bit Sampling

When the cl ock recove ry logic detects a high ( idle) to low (start) transition on the Rx Dn line, the

start bit detection sequence is initiated. Let sample 1 denote the first zero-sampl e as shown in

the figure. T he clock re covery logic then uses sam ples 8 , 9, and 1 0 for Nor mal mod e, and sam -

ples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the

figure), t o decide if a valid start bit is re ceive d. If two or m ore o f these thre e samples have log ical

high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts

looking for the next high to low-transition. If however, a valid start bit is detected, the clock recov-

ery logic is synchronized and the data recovery can begin. The synchronization process is

repeated for each start bit.

19.8.2 Asynchronous Data Reco very

When the receiver clock is synchronized to the start bit, the data recovery can begin. The data

recovery unit uses a state machine that has 16 states for each bit in Normal mode and eight

states for each bit in Double Spee d mode. Figure 19-6 shows the sampling of the data bits and

the parity bit. Each of the samples is given a number that is equal to the state of the recovery

unit.

Figure 19-6. Sampling of Data and Parity Bit

The decision of the logic level of the received bit is taken by doing a majority voting of the logic

value to the three samples in the center of the received bit. The center samples ar e emphasized

on the figure by ha ving th e samp le num ber inside boxes. The majority vo t ing pr ocess is done as

follows: If two or all three samples have high levels, the received bit is registered to be a logic 1.

If two or all three samples have low levels, the received bit is registered to be a logic 0. This

majority voting process acts as a low pass filter for the incoming signal on the RxDn pin. The

recovery process is then repeated until a complete frame is received. Including the first stop bit.

Note that the Receiver only uses the first stop bit of a frame.

Figure 19-7 on page 193 shows the sampling of the stop bit and the earliest possible beginning

of the start bit of the next frame.

12345678 9 10 11 12 13 14 15 16 12

STARTIDLE

BIT 0

1234 5 678120

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

12345678 9 10 11 12 13 14 15 16 1

BIT n

1234 5 6781

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

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Figure 19-7. Stop Bit Sampling and Next Start Bit Sampling

The same majority voting is done to the stop bit as done fo r the other bits in the fr ame. If the stop

bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.

A new high to low tr ansit ion ind i cating the start bit of a n ew fra me can com e r igh t aft er the last of

the bits used for majority voting. For Normal Speed mode, the first low level sample can be at

point marked (A) in Figure 19-7. For Double Speed mode the first low level must be delayed to

(B). (C) marks a stop bit of full length. The early start bit detection influences the operational

range of the Receiver.

19.8.3 Asynchronous Operational Range

The operational ra nge of the Receiver is dependent on the mism atch between the received bit

rate and the inter nally gene rated baud ra te. If the Tra nsmitter is sending f rames at too fast or too

slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see

Table 19-2 on page 194) base frequency, the Receiver will not be able to synchronize the

frames to the start bit.

The following equations can be used to calculate the ratio of the incoming data rate and internal

receiver baud rate.

DSum of character size and parity size (D = 5 to 10 bit)

SSamples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed

mode.

SFFirst sample number used for majority voting. SF = 8 for normal speed and SF = 4

for Double Speed mode.

SMMiddle sample number used for majority voting. SM = 9 for normal speed and

SM= 5 for Double Speed mode.

Rslow is the ratio of the slowe st incoming da ta rate that can be accepted in relation t o the

receiver baud rate. Rfast is the ratio of the fastest incoming data rate that can be

accepted in relation to the receiver baud rate.

Table 19-2 on page 194 and Table 19-3 on page 194 list the maximu m receiver baud rate er ror

that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate

variations.

12345678 9 10 0/1 0/1 0/1

STOP 1

1234 5 6 0/1

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

(A) (B) (C)

Rslow D

+()S

S1–DS⋅SF

---------------------------------------

----

=Rfast D

+()S

D1+()SS

--------------------------------

---

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The recommendations of the maximum receiver baud rate error was made under the assump-

tion that the Receiver and Transmitter equally divides the maximum total err or.

There are two possible sources for the receivers baud rate error. The Receiver’s system clock

(XTAL) will always have some minor instability over the supply voltage range and the tempera-

ture range. When using a crystal to generate the system clock, this is rarely a problem, but for a

resonator th e syste m clock ma y diff er more t han 2% dep en ding o f th e reson ator s t oler ance . The

second source for the error is more controllable. The baud rate generator can not always do an

exact division of t he system fr equency to get th e b aud rate wan ted. I n this case an UBRRn value

that gives an acceptable low error can be used if possible.

19.9 Multi-processor Communication Mode

Setting the Multi-processor Communication mode (MPCMn) bit in UCSRnA enables a filtering

function of incoming frames received b y the USART Receiver. Frames that do not contain

address information will be ignored and not put into the receive buffer. This effectively reduces

the number of incoming frames that has to be handled by the CPU, in a system with multiple

MCUs that communicate via the same serial bus. The Transmitter is unaffected by the MPCMn

setting, but has to be used differently when it is a part of a system utilizing the Multi-processor

Communication mode.

If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indi-

cates if the frame contains data or address information. If the Receiver is set up for frames with

Table 19-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode

(U2Xn = 0)

# (Data+Pa rity Bit) Rslow (%) Rfast (%) Max Total Err o r (%) Recommended Max

Receiver Error (%)

5 93.20 106.67 +6.67/-6.8 ± 3.0

6 94.12 105.79 +5.79/-5.88 ± 2.5

7 94.81 105.11 +5.11/-5.19 ± 2.0

8 95.36 104.58 +4.58/-4.54 ± 2.0

9 95.81 104.14 +4.14/-4.19 ± 1.5

10 96.17 103.78 +3.78/-3.83 ± 1.5

Table 19-3. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode

(U2Xn = 1)

# (Data+Pa rity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max

Receiver Error (%)

5 94.12 105.66 +5.66/-5.88 ± 2.5

6 94.92 104.92 +4.92/-5.08 ± 2.0

7 95.52 104,35 +4.35/-4.48 ± 1.5

8 96.00 103.90 +3.90/-4.00 ± 1.5

9 96.39 103.53 +3.53/-3.61 ± 1.5

10 96.70 103.23 +3.23/-3.30 ± 1.0

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nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When

the frame type bit (the first sto p or t he ninth b it) is o ne, th e f rame con tai ns a n add ress. When t he

frame type bit is zero the frame is a data frame.

The Multi-processor Communication mode enables several slave MCUs to receive data from a

master MCU. This is done by first decoding an address frame to find out which MCU has been

addressed. If a particular slave MCU has been addressed, it will receive the following data

frames as normal, while the other slave MCUs will ignore the received frames until another

address frame is received.

19.9.1 Using MPCMn For an MCU to act as a master MCU, it can use a 9-bit char acter frame format ( UCSZn = 7). The

ninth bit (TXB8n) must be set when an a ddress frame (TXB8n = 1) or cle ared when a data frame

(TXB = 0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit character

frame format.

The following proce dure should be used to exchang e data in Multi-processor Communicatio n

mode:

1. All Slave MCUs are in Multi-processor Communication mode (MPCMn in

UCSRnA is set).

2. The Master MCU sends an address frame, and all slave s rece ive and read this fr a me. In

the Slave MCUs, the RXCn Flag in UCSRnA will be set as normal.

3. Each Slave MCU reads the UDRn Register and determines if it has been selected. If so,

it clears the MPCMn bit in UCSRnA, otherwise it waits for the next address byte and

keeps the MPCMn setting.

4. The addressed MCU will receive all data frames until a new address frame is received.

The other Slave MCUs, which still have the MPCMn bit set, will ignore the data frames.

5. When the last data frame is received by the addressed MCU, the addressed MCU sets

the MPCMn bit and waits for a new address frame from master. The process then

repeats from 2.

Using any of the 5- to 8-bit character frame formats is possible, but impractical since the

Receiver must change between using n and n+1 character frame formats. This makes full-

duplex operation difficult since the Transmitter and Receiver uses the same character size set-

ting. If 5- to 8-bit character frames ar e used, the Transmitter must be set to use two sto p bit

(USBSn = 1) since the first stop bit is used for indicating the frame type.

Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The

MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be

cleared when using SBI or CBI instructions.

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19.10 Register Description

19.10.1 UDRn – USART I/O Data Register n

The USART Transmit Data Buffer Regist er and USART Receive Data Buffer Regist ers share t he

same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Reg-

ister (TXB) will be the destination for data written to the UDRn Register location. Reading the

UDRn Register location will return the contents of the Receive Data Buffer Register (RXB).

For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to

zero by the Receiver.

The transmit buffer can only be written when the UDREn Flag in the UCSRnA Register is set.

Data written to UDRn when the UDREn Flag is not set, will be ignored by the USART Transmit-

ter. When data is written to the transmit buffer, and the Transmitter is en abled, the Transmitter

will load the data into the Transmit Shift Register when the Shift Register is empty. Then the

data will be serially transmitted on the TxDn pin.

The receive buffer consists of a two level FIFO. The FIFO w ill change its state whenever the

receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Modify-

Write instructions (SBI and CBI) on this location. Be careful when using bit test in structions

(SBIC and SBIS), since these also will change the state of the FIFO.

19.10.2 UCSRnA – USART Control and Status Register n A

• Bit 7 – RXCn: USART Receive Complete

This flag bit is set when th ere are unr ead data in the rece ive buffer a nd cleared whe n the rece ive

buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive

buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag can be

used to generate a Receive Complete int errupt (see description of the RXCIEn bit).

• Bit 6 – TXCn: USART Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and

there are no new data currently present in the transmit buff er (UDRn). The TXCn Fl ag bit is auto-

matically cleared when a transmit comple te interrup t is execut ed, or it can be clea red by writin g

a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see

description of the TXCI En bit).

• Bit 5 – UDREn: USART Data Register Empty

The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDR En

is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a

Bit 76543210

RXB[7:0] UDRn (Read)

TXB[7:0] UDRn (Write)

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

RXCn TXCn UDREn FEn DORn UPEn U2Xn MPCMn UCSRnA

Read/Write R R/W R R R R R/W R/W

Initial Value00100000

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Data Register Empty interrupt (see description of the UDRIEn bit). UDREn is set after a reset to

indicate that the Transmitter is ready.

• Bit 4 – FEn: Frame Error

This bit is set if the next character in the re ceive buffer had a Frame Error when received. I.e.,

when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the

receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one.

Always set this bit to zero when writing to UCSRnA.

• Bit 3 – DORn: Data OverRun

This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive

buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a

new start bit is detected. This bit is valid until the receive buffer (UDRn) is read . Always set this

bit to zero when writing to UCSRnA.

• Bit 2 – UPEn: USART Parity Error

This bit is set if the next character in the receive buffer h ad a Parity Error when received and the

Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer

(UDRn) is read. Always set this bit to zero when writing to UCSRnA.

• Bit 1 – U2Xn: Double the USART Transmission Speed

This bit only has effect for the asynchronous ope ration. Write this bit to zero when using syn-

chronous operatio n.

Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou-

bling the transfer r ate for asynchronous communication.

• Bit 0 – MPCMn: Multi-processor Communication Mode

This bit enables the Multi-processor Communication mod e. When the MPCMn bit is written to

one, all the incoming fra mes received by the USART Receiver that do not contain address infor-

mation will be ignored. The Transmitter is unaffected by the MPCMn setting. For more detailed

information see ”Multi-processor Communication Mode” on page 194.

19.10.3 UCSRnB – USART Control and Status Register n B

• Bit 7 – RXCIEn: RX Complete Interrupt Enable n

Writing this bit t o one e nables in terrup t on the RXCn Flag. A USART Receive Complete interrupt

will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is

written to one and the RXCn bit in UCSRnA is set.

• Bit 6 – TXCIEn: TX Complete Interrupt Enable n

Writing this bit to one enables in terrupt on the TXCn Flag. A USART Transmit Complete interrupt

will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is

written to one and the TXCn bit in UCSRnA is set.

Bit 7 6 5 4 3 2 1 0

RXCIEn TXCIEn UDRIEn RXENn TXENn UCSZn2 RXB8n TXB8n UCSRnB

Read/Write R/W R/W R/W R/W R/W R/W R R/W

Initial Value 0 0 0 0 0 0 0 0

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• Bit 5 – UDRIEn: USART Data Register Empty Inte rrupt Enable n

Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will

be generated on ly if the UDRIEn bit is written to one, the Global Inter rupt Flag in SREG is written

to one and the UDREn bit in UCSRnA is set .

• Bit 4 – RXENn: Receiver Enable n

Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper-

ation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer

invalidating the FEn, DORn, and UPEn Flags.

• Bit 3 – TXENn: Transmitter Enable n

Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port

operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to

zero) will not become effective until ongoing and pending transmissions are completed, i.e.,

when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-

mitted. When disabled, the Transmitter will no longer override the TxDn port.

• Bit 2 – UCSZn2: Character Size n

The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits

(Character SiZe) in a frame the Receiver and Transmitter use.

• Bit 1 – RXB8n: Receive Data Bit 8 n

RXB8n is the ninth data bit of the rece ived char acter when op erating wit h serial frames with nine

data bits. Must be read before reading the low bits from UDRn.

• Bit 0 – TXB8n: Transmit Data Bit 8 n

TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames

with nine data bits. Must be written before writing the low bits to UDRn.

19.10.4 UCSRnC – USART Control and Status Register n C

• Bits 7:6 – UMSELn1:0 USART Mode Select

These bits select the mode of operation of the USARTn as shown in Table 19-4.

Note: 1. See ”USART in SPI Mode” on page 205 for full description of the Master SPI Mode (MSPIM)

operation

Bit 7 6 5 4 3 2 1 0

UMSELn1 UMSELn0 UPMn1 UPMn0 USBSn UCSZn1 UCSZn0 UCPOLn UCSRnC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 1 1 0

Table 19-4. UMSELn Bits Settings

UMSELn1 UMSELn0 Mode

0 0 Asynchronous USART

0 1 Synchronous USART

1 0 (Reserved)

1 1 Master SPI (MSPIM)(1)

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• Bits 5:4 – UPMn1:0: Parity Mode

These bits enable and set type of parity generation and check. If enabled, the Transmitter will

automatically generate and send the parity of the transmitted data bits within each frame. The

Receiver will generate a parity value for the incoming data and compare it to the UPMn setting.

If a mismatch is detected, the UPEn Flag in UCSRnA will be set.

• Bit 3 – USBSn: Stop Bit Select

This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores

this setting.

• Bit 2:1 – UCSZn1:0: Character Size

The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits

(Character SiZe) in a frame the Receiver and Transmitter use.

• Bit 0 – UCPOLn: Clock Polarity

This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is

used. The UCPOLn bi t sets the relat ionship be tween dat a output change an d dat a input samp le,

and the synchronous clock (XCKn).

Table 19-5. UPMn Bits Settings

UPMn1 UPMn0 Parity Mode

00Disabled

01Reserved

1 0 Enabled, Even Parity

1 1 Enabled, Odd P arity

Table 19-6. USBS Bit Settings

USBSn Stop Bit(s)

01-bit

12-bit

Table 19-7. UCSZn Bits Settings

UCSZn2 UCSZn1 UCSZn0 Character Size

0005-bit

0016-bit

0107-bit

0118-bit

1 0 0 Reserved

1 0 1 Reserved

1 1 0 Reserved

1119-bit

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19.10.5 UBRRnL and UBRRnH – USART Baud Rate Registers

• Bit 15:12 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, these bit must be

written to zero when UBRRnH is written.

• Bit 11:0 – UBRR11:0: USART Baud Rate Register

This is a 12-bit register which contains the USART baud rate. T he UBRRnH contains the four

most significant bits , and the UBRRnL contains the eig ht least significant bits of the USART

baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud

rate is changed. Writing UBRRnL will trigger an immediate update of the baud rate prescaler.

19.11 Examples of Baud Rate Setting

For standard crystal and resona tor frequencies, the most commonly us ed baud rates for asyn-

chronous operation can be generated by using the UBRRn settings in Table 19-9. UBRRn

values which yield an ac tual baud rate differing less than 0.5% fr om the target baud rate, are

bold in the table. Higher error ratings are acceptable, but the Receiver will have less noise resis-

tance when the error ratings are high, especially for large serial frames (see ”Asynchronous

Operational Range” on page 193). The error values are calculated using the following equation:

Table 19-8. UCPOLn Bit Settings

UCPOLn Transmitted Data Changed (Output of

TxDn Pin) Received Data Sampled (Input on RxDn

Pin)

0 Rising XCKn Edge Fa lling XCKn Edge

1 Falling XCKn Edge Rising XCKn Edge

Bit 151413121110 9 8

– – – – UBRRn[11:8] UBRRnH

UBRRn[7:0] UBRRnL

76543210

Read/Write R R R R R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

00000000

Error[%] BaudRateClosest Match

BaudRate

-------------------------------------------------- 1–

⎝⎠

⎛⎞

100%•=

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Note: 1. UBR Rn = 0, Error = 0.0%

Table 19-9. Examples of UBRR n Settings for Commonly Used Oscillator Frequencies

Baud

Rate

(bps)

fosc = 1.0000 MHz fosc = 1.8432 MHz fosc = 2.0000 MHz

U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U 2Xn = 1

UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error

2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2%

4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2%

9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2%

14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1%

19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2%

28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5%

38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0%

57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5%

76.8k – – 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5%

115.2k – – 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5%

230.4k––––––00.0%––––

250k––––––––––00.0%

Max.(1) 62.5 kbps 125 kbps 115.2 kbps 230.4 kbps 125 kbps 250 kbps

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Table 19-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)

Baud

Rate

(bps)

fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz

U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1

UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error

2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0%

4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0%

9600 230.0%470.0%250.2%510.2%470.0%950.0%

14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0%

19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0%

28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0%

38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0%

57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0%

76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0%

115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0%

230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0%

250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8%

0.5M – – 0 -7.8% – – 0 0.0% 0 -7.8% 1 -7.8%

1M ––––––––––0-7.8%

Max. (1) 230.4 kbps 460.8 kbps 250 kbps 0.5 Mbps 460.8 kbps 921.6 kbps

1. UBRRn = 0, Error = 0. 0%

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Table 19-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)

Baud

Rate

(bps)

fosc = 8.0000 MHz fosc = 11.0592 MHz fosc = 14.7456 MHz

U2Xn = 0 U2Xn = 1 U2 Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1

UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error

2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0%

4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0%

9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0%

14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0%

19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.0% 95 0.0%

28.8k 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0%

38.4k 12 0.2% 25 0.2% 17 0.0% 35 0.0% 23 0.0% 47 0.0%

57.6k 8 -3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0%

76.8k 6 -7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0%

115.2k 3 8.5% 8 -3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0%

230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0%

250k 1 0.0% 3 0.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3%

0.5M 0 0.0% 1 0.0% – – 2 -7.8% 1 -7.8% 3 -7.8%

1M ––00.0%––––0-7.8%1-7.8%

Max. (1) 0.5 Mbps 1 Mbps 691.2 kbps 1.3824 Mbps 921.6 kb ps 1.8432 Mbps

1. UBRRn = 0, Error = 0. 0%

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Table 19-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued)

Baud

Rate

(bps)

fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz

U2Xn = 0 U2Xn = 1 U2 Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1

UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error

2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0%

4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0%

9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2%

14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2%

19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2%

28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2%

38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.0% 32 -1.4% 64 0.2%

57.6k 16 2.1% 34 -0.8% 19 0.0% 39 0.0% 21 -1.4% 42 0.9%

76.8k 12 0.2% 25 0.2% 14 0.0% 29 0.0% 15 1.7% 32 -1.4%

115.2k 8 -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1.4% 21 -1.4%

230.4k 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1.4%

250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0%

0.5M 1 0.0% 3 0.0% – – 4 -7.8% – – 4 0.0%

1M 00.0%10.0%––––––––

Max. (1) 1 Mbps 2 Mbps 1.152 Mbps 2.304 Mbps 1.25 Mbps 2.5 Mbps

1. UBRRn = 0, Error = 0. 0%

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20. USART in SPI Mode

20.1 Features •Full Duplex, Three-wire Synchronous Data Transfer

•Master Operation

•Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3)

•LSB First or MSB First Data Transfer (Configurable Data Order)

•Queued Operation (Double Buffered)

•High Resolution Baud Rate Generator

•High Speed Operation (fXCKmax = fCK/2)

•Flexible Interrupt Generation

20.2 Overview The Universal Synchronous and Asynchronous serial Receiver an d Transmitter (U SART) can be

set to a master SPI compliant mode of operation.

Setting both UMSELn1:0 bits to one enables the USART in MSPIM logic. In this mode of opera-

tion the SPI master control logic takes direct control over the USART resources. These

resources include the transmitter and receiver shift register and buffers, and the baud rate gen-

erator. The parity generator and checker, the data and clock recovery logic, and the RX and TX

control logic is disabled. The USART RX and TX control logic is replaced by a common SPI

transfer control logic. However, the pin control logic and interrupt generation logic is identical in

both modes of operation.

The I/O register locati ons ar e t he sa me in b oth mo des. However , so me of the f u nctionalit y of t he

control registers changes when using MSPIM.

20.3 Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver. For

USART MSPIM mode of operation only internal clock generation (i.e. master operation) is sup-

ported. The Da ta Directi on Register for the XCKn pin (D DR_XCKn) must the refo re be set t o one

(i.e. as output) for the USART in MSPIM to operate correctly. Preferably the DDR_XCKn should

be set up before the USART in MSPIM is enabled (i.e. TXENn and RXENn bit set to one).

The internal cloc k genera tion use d in MSPIM mode is identical t o the USART synchr onous mas-

ter mode. The baud rate or UBRRn setting can therefore be calculated using the same

equations, see Table 20-1:

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Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)

BAUD Baud rate (in bits per second, bps)

fOSC System Oscillator clock frequency

UBRRn Contents of the UBRRnH and UBRRnL Regi sters, (0-4095)

20.4 SPI Data Modes and Timing

There are four combinations of XCKn (SCK) phase and polar ity with respect to seria l data, which

are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are

shown in Figure 20-1. Data bits are shifted out and latched in on opposite edges of the XCKn

signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn function-

ality is summarized in Table 20-2. Note that changing the setting of any of these bits will corrupt

all ongoing communication for both the Receiver and Transmitter.

Table 20-1. Equations for Calculating Baud Rate Register Setting

Operating Mode Equation for Calculating Baud

Rate(1) Equation for Calculating UBRRn

Value

Synchronous Master

mode BAUD fOSC

2UBRRn1+()

---------------------------------------= UBRRnfOSC

2BAUD

-------------------- 1–=

Table 20-2. UCPOLn and UCPHAn Functionality-

UCPOLn UCPHAn SPI Mode Leading Edge Trailing Edge

0 0 0 Sample (Rising) Setup (Falling)

0 1 1 Setup (Rising) Sample (Falling)

1 0 2 Sample (Falling) Setup (Rising)

1 1 3 Setup (Falling) Sample (Rising)

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Figure 20-1. UCPHAn and UCPOLn data transfer timing diagrams.

20.5 Frame Formats

A serial frame f or the MSPIM is def ined to be one character of 8 da ta bits. The USART in MSPIM

mode has two valid frame formats:

• 8-bit data with MSB first

• 8-bit data with LSB first

A frame starts with the least or most significant data bit. Then the next data bits, up to a total of

eight, are succeeding, ending with the most or least significant bit accordingly. When a complete

frame is transmitted, a new frame can directly follow it, or the communication line can be set to

an idle (high) state.

The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The

Receiver and Transmitter use the same setting. Note that changing the setting of any of these

bits will corrupt all ongoing communication for both the Receiver and Transmitter.

16-bit data transfer can be achieved by writing two data bytes to UDRn. A UART transmit com-

plete interrupt will then signal that the 16-bit value has been shifted out.

20.5.1 USART MSPIM Initialization

The USART in MSPIM mode has to be initialized before any communication can take place. The

initialization process nor mally consists of sett ing the baud r ate, setting ma ster mode of o peration

(by setting DDR_XCKn to one), setting frame format and enabling the Transmitter and the

Receiver. Only the transmitter can operate independ ently. For interrupt driven USART opera-

tion, the Global Interrupt Flag should be cleared (and thus interrupts globally disabled) when

doing the initialization.

Note: To ensure immediate initialization of the XCKn output the baud-rate register (UBRRn) must be

zero at the time the transmitter is enabled. Contrary to the normal mode USART operation the

UBRRn must then be written to the desired value after the transmitter is enabled, but before the

first transmission is started. Setting UBRRn to zero before enab ling the transmitter is not neces-

sary if the initialization is done immediately after a reset since UBRRn is reset to zero.

Before doing a re-initialization with changed baud rate, data mode, or frame format, be sure that

there is no ongoing transmissions during the period the registers are changed. The TXCn Flag

can be used to check that the Transmitter has completed all transfers, and the RXCn Flag can

XCK

Data setup (TXD)

Data sample (RXD)

XCK

Data setup (TXD)

Data sample (RXD)

XCK

Data setup (TXD)

Data sample (RXD)

XCK

Data setup (TXD)

Data sample (RXD)

UCPOL=0 UCPOL=1

UCPHA=0 UCPHA=1

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be used to check that there are no unread data in the receive buffer. Note that the TXCn Flag

must be cleared before each transmission (before UDRn is written) if it is used for this purpose.

The following simple USART initializatio n code examples show one assembly and one C func-

tion that are equal in functionality. The exam ples assume polling (no interrupts enabled). Th e

baud rate is given as a function parameter. For the assembly code, the baud rate parameter is

assumed to be stored in the r17:r16 registers.

Note: 1. See ”Abou t Code Examples” on page 8.

Assembly Code Example(1)

USART_Init:

clr r18

out UBRRnH,r18

out UBRRnL,r18

; Setting the XCKn port pin as output, enables master mode.

sbi XCKn_DDR, XCKn

; Set MSPI mode of operation and SPI data mode 0.

ldi r18, (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn)

out UCSRnC,r18

; Enable receiver and transmitter.

ldi r18, (1<<RXENn)|(1<<TXENn)

out UCSRnB,r18

; Set baud rate.

; IMPORTANT: The Baud Rate must be set after the transmitter is enabled!

out UBRRnH, r17

out UBRRnL, r18

ret

C Code Example(1)

void USART_Init( unsigned int baud )

{

UBRRn = 0;

/* Setting the XCKn port pin as output, enables master mode. */

XCKn_DDR |= (1<<XCKn);

/* Set MSPI mode of operation and SPI data mode 0. */

UCSRnC = (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn);

/* Enable receiver and transmitter. */

UCSRnB = (1<<RXENn)|(1<<TXENn);

/* Set baud rate. */

/* IMPORTANT: The Baud Rate must be set after the transmitter is enabled

UBRRn = baud;

}

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20.6 Data Transfer Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn bit in

the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation

of the TxDn pin is overridden and given the function as the Transmitter's serial output. Enabling

the receiver is optional and is done by setting the RXENn bit in the UCSRnB register to one.

When the receiver is enabled, the normal pin operation of the RxDn pin is overridden and given

the function as the Receiver's serial input. The XCKn will in both cases be used as the transfer

clock.

After initialization the USART is ready for doing dat a tran sfers. A data transfer is init iated by wr it-

ing to the UDRn I/O location. This is the case for both sending and receiving data since the

transmitter controls the transfer clock. The data written to UDRn is moved from the transmit

buffer to the shift register when the shift r egister is ready to send a new frame.

Note: To keep the input buff er in sync with the number of data bytes transmitted, the UDRn register must

be read once for each byte transmitted. Th e input buffer operation is identi cal to normal USART

mode, i.e. if an overflow occurs the character last received will be lost, not the first data in the

buffer. This means that if four bytes are transferred, byte 1 first, then byte 2, 3, and 4, and the

UDRn is not read before all transf ers are completed, then byte 3 to be received will be lost, and not

byte 1.

The following code examples show a sim ple U SART in MSPIM mode t ransfe r fu ncti on based on

polling of the Data Register Empty (UDREn) Flag and the Receive Complete (RXCn) Flag. The

USART has to be initialize d befor e t he funct ion can be used. For the assembly code, the dat a to

be sent is assumed to be stored in Register R16 and the data received will be available in the

same register (R16) after the function returns.

The function simply waits for the transmit buffer to be empty by checking the UDREn Flag,

before loadin g it with new da ta to be transm itted. The func tion then waits for data to be pr esent

in the receive buffer by checking the RXCn Flag, before reading the buffer and returning the

value.

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Note: 1. See ”Abou t Code Examples” on page 8.

20.6.1 Transmitter and Receiver Flags and Interrupts

The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode

are identi cal in fu nct ion to the no rma l USART op erat ion. Howe ver, t he r eceiver er ror st at us fla gs

(FE, DOR, and PE) are not in use and is always read as zero.

20.6.2 Disabling the Transmitter or Receiver

The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to

the normal USART oper ation.

Assembly Code Example (1)

USART_MSPIM_Transfer:

; Wait for empty transmit buffer

sbis UCSRnA, UDREn

rjmp USART_MSPIM_Transfer

; Put data (r16) into buffer, sends the data

out UDRn,r16

; Wait for data to be received

USART_MSPIM_Wait_RXCn:

sbis UCSRnA, RXCn

rjmp USART_MSPIM_Wait_RXCn

; Get and return received data from buffer

in r16, UDRn

ret

C Code Example(1)

unsigned char USART_Receive( void )

{

/* Wait for empty transmit buffer */

while ( !( UCSRnA & (1<<UDREn)) );

/* Put data into buffer, sends the data */

UDRn = data;

/* Wait for data to be received */

while ( !(UCSRnA & (1<<RXCn)) );

/* Get and return received data from buffer */

return UDRn;

}

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20.7 AVR USART MSPIM vs. AVR SPI

The USART in MSPIM mode is fully compatible with the AVR SPI regarding:

• Master mode timing diagram.

• The UCPOLn bit functionality is identical to the SPI CPOL bit.

• The UCPHAn bit functionality is identical to the SPI CPHA bit.

• The UDORDn bit functionality is identical to the SPI DORD bit.

However, since the USART in MSPIM mode reuses the USART resources, the use of the

USART in MSPIM mode is some what d iff er ent co mpa re d to th e SPI . In ad dit ion t o d iff er ence s of

the control register bits, and that only master operation is supported by the USART in MSPIM

mode, the following features differ between the two modules:

• The USART in MSPIM mode includes (double) buffering of the transmitter. The SPI has no

buffer.

• The USART in MSPIM mode receiver includes an additional buffer lev el.

• The SPI WCOL (Write Collision) bit is not included in USART in MSPIM mode.

• The SPI double speed mode (SPI2X) bit is not included. However, the same effect is achieved

by setting UBRRn accordingly.

• Interrupt timing is not compatible.

• Pin control differs due to the master only operation of the USART in MSPIM mode.

A comparison of the USART in MSPIM mode and the SPI pins is shown in Tabl e 20-3 on page

211.

Table 20-3. Comparison of USART in MSPIM mode and SPI pins.

USART_MSPIM SPI Comment

TxDn MOSI Master Out only

RxDn MISO Master In only

XCKn SCK (Functionally identical)

(N/A) SS Not supported by USART in

MSPIM

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20.8 Register Description

The following section de scr ib es th e re gis te rs us ed for SPI op er a tion usin g the USART .

20.8.1 UDRn – USART MSPIM I/O Data Register

The function an d b it d escript io n of t he USART dat a r egi ster ( UDRn) in M SPI mode is iden tica l to

normal USART operat ion. See “UDRn – USART I/O Data Register n” on page 196.

20.8.2 UCSRnA – USART MSPIM Control and Status Register n A

• Bit 7 - RXCn: USART Receive Complete

This flag bit is set when th ere are unr ead data in the rece ive buffer a nd cleared whe n the rece ive

buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive

buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag can be

used to generate a Receive Complete int errupt (see description of the RXCIEn bit).

• Bit 6 - TXCn: USART Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and

there are no new data currently present in the transmit buff er (UDRn). The TXCn Fl ag bit is auto-

matically cleared when a transmit comple te interrup t is execut ed, or it can be clea red by writin g

a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see

description of the TXCI En bit).

• Bit 5 - UDREn: USART Data Register Empty

The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDR En

is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a

Data Register Empty interrupt (see description of the UDRIE bit). UDREn is set after a reset to

indicate that the Transmitter is ready.

• Bit 4:0 - Reserved Bits in MSPI mode

When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,

these bits must be written to zero when UCSRnA is written.

20.8.3 UCSRnB – USART MSPIM Control and Status Register n B

• Bit 7 - RXCIEn: RX Complete Interrupt Enable

Writing this bit t o one e nables in terrup t on the RXCn Flag. A USART Receive Complete interrupt

will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is

written to one and the RXCn bit in UCSRnA is set.

Bit 7 6 5 4 3 2 1 0

RXCn TXCn UDREn - - - - - UCSRnA

Read/Write R R/W R R R R R R

Initial Value 0 0 0 0 0 1 1 0

Bit 7 6543210

RXCIEn TXCIEn UDRIE RXENn TXENn - - - UCSRnB

Read/Write R/W R/W R/W R/W R/W R R R

Initial Value 0 0 0 0 0 1 1 0

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• Bit 6 - TXCIEn: TX Complete Interrupt Enable

Writing this bit to one enables in terrupt on the TXCn Flag. A USART Transmit Complete interrupt

will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is

written to one and the TXCn bit in UCSRnA is set.

• Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable

Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will

be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written

to one and the UDREn bit in UCSRnA is set .

• Bit 4 - RXENn: Receiver Enable

Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will override

normal port operation for the RxDn pin when enabled. Disabling the Receiver will flush the

receive buffer. Only enabling the receiver in MSPI mode (i.e. setting RXENn=1 and TXENn=0)

has no meaning since it is the transmitter that controls the transfer clock and since only master

mode is supported.

• Bit 3 - TXENn: Transmitter Enable

Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port

operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to

zero) will not become effective until ongoing and pending transmissions are completed, i.e.,

when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-

mitted. When disabled, the Transmitter will no longer override the TxDn port.

• Bit 2:0 - Reserved Bits in MSPI mode

When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,

these bits must be written to zero when UCSRnB is written.

20.8.4 UCSRnC – USART MSPIM Control and Status Register n C

• Bit 7:6 - UMSELn1:0: USART Mode Select

These bits select the m ode of op erat ion of th e USART as shown in Ta ble 2 0-4. See ”UCSRnC –

USART Control and Status Register n C” on page 198 for full description of the normal USART

operation. The MSPIM is enabled when both UMSELn bits are set to one. The UDORDn,

UCPHAn, and UCPOLn can be set in the same write operation where the MSPIM is enabled.

Bit 7 6 5 4 3 2 1 0

UMSELn1 UMSELn0 - - - UDORDn UCPHAn UCPOLn UCSRnC

Read/Write R/W R/W R R R R/W R/W R/W

Initial Value 0 0 0 0 0 1 1 0

Table 20-4. UMSELn Bits Settings

UMSELn1 UMSELn0 Mode

0 0 Asynchronous USART

0 1 Synchronous USART

1 0 Reserved

1 1 Master SPI (MSPIM)

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• Bit 5:3 - Reserved Bits in MSPI mode

When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,

these bits must be written to zero when UCSRnC is written.

• Bit 2 - UDORDn: Data Order

When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the

data word is transmitted first. Refer to the Frame Formats section page 4 for details.

• Bit 1 - UCPHAn: Clock Phase

The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last)

edge of XCKn. Refer to the SPI Data Modes and Timing section page 4 for details.

• Bit 0 - UCPOLn: Clock Polarity

The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and

UCPHAn bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and

Timing section page 4 for det ails.

20.8.5 USART MSPIM Baud Rate Registers - UBRRnL and UBRRnH

The function and bit description of the baud rate registers in MSPI mode is identical to normal

USART operation. See “UBRRnL and UBRRnH – USART Baud Rate Registers” on page 200.

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21. 2-wire Serial Interface

21.1 Features •Simple Yet Powerful and Flexible Communica ti on Interface , only two Bus Lines Needed

•Both Master and Slave Operation Supported

•Device can Operate as Transmitter or Receiver

•7-bit Address Space Allows up to 128 Different Slave Addresses

•Multi-master Arbitration Support

•Up to 400 kHz Data Transfer Speed

•Slew-rate Limited Output Drivers

•Noise Suppression Circuitry Rejects Spikes on Bus Lines

•Fully Programmable Slave Address with General Call Support

•Address Recognition Causes Wake-up When AVR is in Sleep Mode

•Compatible with Philips’ I2C pr otocol

21.2 2-wire Serial Interface Bus Definition

The 2-wire Se rial Interface ( TWI) is ideally suite d for typical micr ocontroller applications. The

TWI protoc ol allows t he syste ms desig ner to interconnect up to 128 different devices using only

two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hard-

ware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All

devices connec ted to the bus have individual add resses, and mechanisms for reso lving bus

contention are inh erent in the TWI protocol.

Figure 21-1. TWI Bus Interconne ct ion

Device 1 Device 2 Device 3 Device n

SDA

SCL

........ R1 R2

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21.2.1 TWI Terminology

The following definit ions are frequently encount ered in this section.

The PRTWI bit in ”Minimizin g Power Consum ption” on page 43 must b e written to zero to en able

the 2-wire Serial Interface.

21.2.2 Electrical Inter connection

As depicted in Figure 21- 1, both bus lines are connected to the positive supply voltage through

pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector.

This implements a wired-AND function which is essential to the operation of the interface. A low

level on a TWI bus line is generated when one or more TWI devices output a zero. A high level

is output when all TWI devices tri-state their outputs, allowing the pull-up resistors to pull the line

high. Note that all AVR devices conne cted to the TWI bus must be powered in orde r to allow any

bus operation.

The number of devices that can be connected to the bus is only limited by the bus capacitance

limit of 400 pF and the 7-bit slave address space. A detailed specification of the electrical char-

acteristics of the TWI is given in ”2-wire Serial Interface Characteristics” on page 322. Two

different sets of specifications are presented there, one relevant for bus speeds below 100 kHz,

and one valid for bus speeds up to 400 kHz.

Table 21-1. TWI Terminology

Term Description

Master The device that initiates and terminates a transmission. The Master also generates the

SCL clock.

Slave The device addressed by a Master.

Transmitter The device placing data on the bus.

Receiver The device reading data from the bus.

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21.3 Data Transfer and Frame Format

21.3.1 Transferring Bits

Each data b it tran sfer red o n the T WI bus is acco mpa nied by a p ulse on th e cloc k line. The lev el

of the data line must be stable when the clock line is high. The only exception to this rule is for

generating st art and stop conditions.

Figure 21-2. Data Validity

21.3.2 START and STOP Conditions

The Master initiates and terminates a data transmission. The transmission is initiated when the

Master issues a START condition on the bus, and it is terminated when the Master issues a

STOP condition. Between a START and a STOP condition, the bus is considered busy, and no

other master should try to seize control of the bus. A special case occurs when a new START

condition is issued between a START and STOP condition. This is referred to as a REPEATED

START condition, and is used when the Master wishes to initiate a new transfer without relin-

quishing control of the bus. After a REPEATED START, the bus is considered busy until the next

STOP. This is identical to the START behavior, and therefore START is used to describe both

START and REPEATED START for the r emainde r of t his datashe et, un less oth erwise note d. As

depicted below, START an d STOP conditions are signalled by cha nging the level of the SDA

line when the SCL line is high.

Figure 21-3. START, REPEATED START and STOP conditions

SDA

SCL

Data Stable Data Stable

Data Change

SDA

SCL

START STOPREPEATED STARTSTOP START

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21.3.3 Address Packet Format

All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 addre ss bits, one

READ/WRITE control bit and an acknowledge bit. If the READ/WRIT E bit is set, a read opera-

tion is to be performed, otherwise a write operation should be performed. When a Slave

recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL

(ACK) cycle. If the addressed Slave is busy, or for some other reason can not service the Mas-

ter’s request, the SDA line should be left high in the ACK clock cycle. The Master can then

transmit a STOP condition, or a REPEATED START condition to initiate a new transmission. An

address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or

SLA+W, respectively.

The MSB of the add ress b yte is tra nsm it ted firs t. Slave addresses can freely be allocated by the

designer, but the address 0000 000 is reserved for a general call.

When a general call is issued, all slaves should respond by pulling the SDA line low in the ACK

cycle. A general call is used when a Master wishes to transmit the same message to several

slaves in the system. When the general call addre ss followed by a Write bit is transmitted on t he

bus, all slaves set up to ackn owledge the general call will pull the SDA line low in the ack cycle.

The following data packets will then be received by al l the slaves that acknowledged the general

call. Note that transmitting the general call address followed by a Read bit is meaningless, as

this would cause contention if several slaves started transmitting different data.

All addresses of the format 1111 xxx should be reserved for future purposes.

Figure 21-4. Address Packet Format

21.3.4 Data Packet Format

All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and

an acknowledge bit. During a data transfer, the Master generates the clock and the START and

STOP conditions, while the Receiver is responsible for acknowledging the reception. An

Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL

cycle. If the Rece iver leaves the SDA line high, a NACK is signalled. When th e Receiver has

received the last byte, or for some reason cannot receive any more bytes, it should inform the

Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first.

SDA

SCL

START

12 789

Addr MSB Addr LSB R/W ACK

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Figure 21-5. Data Packet Format

21.3.5 Combining Address and Data Packets into a Transmission

A transmission basically consists of a START condition, a SLA+R/W, one or more data packets

and a STOP condition. An emp ty message, consisting of a START followed by a STOP cond i-

tion, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement

handshaking between the Master and the Slave. The Slave can extend the SCL low period by

pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the

Slave, or the Slave needs extra time for processing between the data transmissions. The Slave

extending the SCL low period will not affect the SCL high period, which is determined by the

Master. As a conseq uence , t he Slave can red uce t he TWI dat a tr an sfe r sp ee d by prol ong ing the

SCL duty cycle.

Figure 21-6 shows a typical data transmission. Note that several data bytes can be transmitted

between the SLA+R/W and the STOP con dition, depending on the software protocol imple-

mented by the application software.

Figure 21-6. Typical Data Transmission

21.4 Multi-master Bus Systems, Arbitration and Synchronization

The TWI protocol allows bus systems with several masters. Special concerns have been taken

in order to ensure that transmissions will proceed as normal, even if two or more masters initiate

a transmission at the same time. Two problems arise in multi-master systems:

• An algorithm must be impleme nted allowing only one of the masters to complete the

transmission. All other masters should cease transmission when they discover that they have

lost the selection process. This selection process is called arbitration. When a contending

master discovers that it has lost the arbitration process, it should immediately switch to Slave

mode to check whether it is being addr essed by the winni ng master. The fact that multiple

12 789

Data MSB Data LSB ACK

Aggregate

SDA

SDA from

Transmitter

SDA from

Receiver

SCL from

Master

SLA+R/W Data Byte

STOP, REPEATED

START or Next

Data Byte

12 789

Data Byte

Data MSB Data LSB ACK

SDA

SCL

START

12 789

Addr MSB Addr LSB R/W ACK

SLA+R/W STOP

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masters ha v e started transmission at the same time shou ld not be detect able t o the sla v es , i.e .

the data being transferred on the bus must not be corrupted.

• Different masters may use different SCL frequencies. A scheme must be devised to

synchronize the serial clocks from all masters, in order to let the transmission proceed in a

lockstep fashion. This will facilitate the arbitration process.

The wired-ANDing of the bus lines is us ed to solve both these problems. The serial clocks from

all masters will be wired-ANDed, yielding a co mbined clock with a high period equal to the one

from the Master with the shortest high period. The low period of the combined clock is equal to

the low period of the Master with the longest low period. Note that all masters listen to the SCL

line, effectively starting to count their SCL high and low time-out periods when the combined

SCL line goes high or low, respectively.

Figure 21-7. SCL Synchronization Between Multiple Masters

Arbitration is carried out by all masters continuously monitoring the SDA line after outputting

data. If the value read from the SDA line does not match the value the Master had output, it has

lost the arbitra tion. Not e that a Ma ster can only lo se arbitr ation wh en it outputs a high SDA value

while another Master outputs a low value. The losing Master should immediately go to Slave

mode, checking if it is being addressed by the winning Master. The SDA line should be left high,

but losing masters are allowed to generate a clock signal until the end of the current data or

address packet. Arbitration will continue until only one Mas ter remains, and this may take many

bits. If several masters are trying to address the same Slave, arbitration will continue into the

data packet.

low

high

SCL from

Master A

SCL from

Master B

SCL Bus

Line

low

high

Masters Start

Counting Low Period

Masters Start

Counting High Period

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Figure 21-8. Arbitration Between Two Masters

Note that arbitration is not allowed between:

• A REPEATED START condition and a data bit.

• A STOP conditio n an d a da ta bit.

• A REPEATED START and a STOP condition.

It is the user software’s responsibility to ensure that these illegal arbitration cond itions never

occur. This implies that in multi-master systems, all data transfers must use the same composi-

tion of SLA+R/W and data packets. In other words: All transmissions must contain the same

number of data packets, otherwise the result of the arbitration is undefined.

SDA from

Master A

SDA from

Master B

SDA Line

Synchronized

SCL Line

START Master A Loses

Arbitration, SDAA SDA

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21.5 Overview of the TWI Module

The TWI module is comprised of several submodule s, as shown in Figure 21-9. All registers

drawn in a thick line are accessible through the AVR data bus.

Figure 21-9. Overview of the TWI Module

21.5.1 SCL and SDA Pins

These pins interface the AVR TWI with the rest of the MCU system. The outpu t drivers contain a

slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike

suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR

pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as

explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need

for external on es.

21.5.2 Bit Rate Generator Unit

This unit controls the period of SCL when operating in a Master mode. The SCL period is con-

trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status

CPU clock frequency in the Slave must be at least 16 time s higher than the SCL frequen cy. Note

TWI Unit

Address Register

(TWAR)

Address Match Unit

Address Comparator

Control Unit

Control Register

(TWCR)

Status Register

(TWSR)

State Machine and

Status control

SCL

Slew-rate

Control

Spike

Filter

SDA

Slew-rate

Control

Spike

Filter

Bit Rate Generator

Bit Rate Register

(TWBR)

Prescaler

Bus Interface Unit

START / STOP

Control

Arbitration detection Ack

Spike Suppression

Address/Data Shift

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that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock

period. The SCL frequency is generated according to the following equation:

• TWBR = Value of the TWI Bit Rate Register.

•PrescalerValue = Value of the prescaler, see Table 21-7 on page 244.

Note: Pull-up resistor values should be selected according to the SCL frequency and the capacitive b us

line load. See Table 28-6 on page 322 for value of pull-up resistor.

21.5.3 Bus Interface Unit

This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and

Arbitration det ection ha rdwa re . The TWDR con ta ins the a ddress or dat a byt es to be t ransmit ted,

or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also

contains a register containing the (N)ACK bit to be transmitt ed or receiv ed. This (N)ACK Regis-

ter is not directly accessible by the application software. Howeve r, whe n rec eiving, it can be set

or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter mode, the

value of the received (N)ACK bit can be determined by the value in the TWSR.

The START/STOP Controller is responsible for generation and detection of START, REPEATED

START, and STOP conditions. The START/STOP controller is able to detect START and STOP

conditions even when the AVR MCU is in one of the sle ep mode s, e nabling th e MCU to wa ke up

if addressed by a Mast er .

If the TWI has initiated a transmission as Master, the Arbitration Detection hardware continu-

ously monitor s the transmissio n trying to dete rmine if arbitrat ion is in pr ocess. If the TWI ha s lost

an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate

status codes generated.

21.5.4 Address Match Unit

The Address Match unit checks if received address bytes match the seven-bit address in the

TWI Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the

TWAR is written to one, all incoming address bits will also be compared against the General Call

address. Upon an address match, the Control Unit is informed, allowing correct action to be

taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR.

The Address Match unit is able to compare addresses even when the AVR MCU is in sleep

mode, enabling the MCU to wake up if addressed by a Master. If anothe r interrupt (e.g., INT0)

occurs during TWI Power-down address match and wakes up the CPU, the TWI aborts opera-

tion and retu rn to it’s idle stat e. If this cause any p roblems, ensure that TWI Address Match is the

only enabled interrupt when entering Power-down.

21.5.5 Control Unit The Control unit monitors t he TWI bus an d generates r esponses correspond ing to set tings in the

TWI Control Register (TWCR). When an event requirin g the attention of the application occurs

on the TWI bus, t he TWI Interr upt Flag (TWINT) is asse rted. In the ne xt clock cycle, the TWI Sta-

tus Register (TWSR) is updated with a status code identifying the event. The TWSR only

contains relevant status information when the TWI Interrupt Flag is asserted. At all other times,

the TWSR contains a special status code indicating that no relevant status information is avail-

able. As long as the TW INT Flag is s et, the SCL line is held low. This allows the application

software to complete its tasks before allowing the TWI transmission to continue.

SCL frequency CPU Clock frequency

16 2(TWBR) PrescalerValue()⋅+

-----------------------------------------------------------------------------------------=

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The TWINT Flag is set in the following situations:

• After the TWI has transmitted a START/REPEATED START condition.

• After the TWI has transmitted SLA+R/W.

• After the TWI has transmitted an address byte.

• After the TWI has lost arbitration.

• After the TWI has been addressed by own slave address or general call.

• After the TWI has received a data byte.

• After a STOP or REPEATED START has been received while still addressed as a Slave.

• When a bus error has occurred due to an illegal START or STOP condition.

21.6 Using the TWIThe AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like

reception of a b yte or transmission of a ST ART condition. Because the TWI is interrupt-based,

the application soft war e is fre e to car ry o n oth er oper at ions dur ing a TWI byte t ransf er. Not e that

the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in

SREG allow the applica tio n to de cide wh et he r or no t as se rtio n of th e T WINT F lag sho u ld ge n er -

ate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT Flag in

order to detect actio ns on the TWI bus.

When the TWINT Flag is asserted, the TWI has finished an operation and awaits application

response. In this case, the TWI Status Register (TWSR) contains a value indicating the current

state of the TWI bus. The application software can then decide how the TWI should behave in

the next TWI bus cycle by manipulating the TWCR and TWDR Registers.

Figure 21-10 is a simple example of how th e application can interfa ce to the TWI hardware. In

this example, a Mast er wish es to tr ansm it a sing le data byte to a Slave. T his des cription is q uite

abstract, a more detailed explanation follows later in this section. A simple code example imple-

menting the desired be havior is also presented.

Figure 21-10. Interfacing the Application to the TWI in a Typical Transmission

START SLA+W A Data A STOP

1. Application

writes to TWCR to

initiate

transmission of

START

2. TWINT set.

Status code indicates

START condition sent

4. TWINT set.

Status code indicates

SLA+W sent, ACK

received

6. TWINT set.

Status code indicates

data sent, ACK received

3. Check TWSR to see if START was

sent. Application loads SLA+W into

TWDR, and loads appropriate control

signals into TWCR, makin sure that

TWINT is written to one,

and TWSTA is written to zero.

5. Check TWSR to see if SLA+W was

sent and ACK received.

Application loads data into TWDR, and

loads appropriate control signals into

TWCR, making sure that TWINT is

written to one

7. Check TWSR to see if data was sent

and ACK received.

Application loads appropriate control

signals to send STOP into TWCR,

making sure that TWINT is written to one

TWI bus

Indicates

TWINT set

Application

Action

TWI

Hardware

Action

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1. The first step in a TWI transmission is to transmit a START condition. This is done by

writing a specific value into TWCR, instru cting the TWI hardware to transmit a START

condition. Which value to write is described later on. However, it is important that the

TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will

not start any operation as long as the TWINT bit in TWCR is set. Immediately after the

application has cleared TWINT, the TWI will initiate transmission of the START condition.

2. When the START condition has been transmitted, the TWINT Flag in TWCR is set, and

TWSR is updated with a status code indicating that the START condition has success-

fully been sent.

3. The application software should now examine the value of TWSR, to make sure that the

STAR T conditio n was successfully transmitted. I f TWSR indicates o ther wise, the applica-

tion software might take some special action, like calling an error routine. Assuming that

the status code is as e xpected, the application m ust load SLA+W into TWDR. Remember

that TWDR is used both for address and data. After TWDR has been loaded with the

desired SLA+W, a specific value m ust be written to TWCR, instructing the TWI hardw are

to transmit the SLA+W present in TWDR. Which value to write is described later on.

However, it is important that the TW INT bi t is set in the value written. Writing a one to

TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in

TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate

transmission of the address packet.

4. When the address packet has been transmitted, the TWINT Flag in TWCR is set, and

TWSR is updated with a status code indicating that the address packet has successfully

been sent. The status code will also reflect whether a Slave ackno wledged the packet or

not.

5. The application software should now examine the value of TWSR, to make sure that the

address packet was successfully transmitted, and that the value of the ACK bit was as

e xpected. If TWSR indicates otherwise , the application softw are might tak e some special

action, like calling an error routine. Assuming that the status code is as expected, the

application must load a data packet into TWDR. Subsequently, a specific value must be

written to TWCR, instructing the TWI hardware to transmit the data packet present in

TWDR. Which value to write is described later on. However, it is important that the

TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will

not start any operation as long as the TWINT bit in TWCR is set. Immediately after the

application has cleared TWINT, the TWI will initiate transmission of the data packet.

6. When the data pac k et has been tr ansmitted, the TWINT Fla g in TWCR is set, and TWSR

is updated with a stat us code indica tin g that the data pack et has successf ull y been sent .

The status code will also reflect whether a Slave acknowledged the packet or not.

7. The application software should now examine the value of TWSR, to make sure that the

data packet was successfully transmitted, and that the value of the ACK bit was as

e xpected. If TWSR indicates otherwise , the application softw are might tak e some special

action, like calling an error routine. Assuming that the status code is as expected, the

application must write a specific value to TWCR, instructing the TWI hardw are to transmit

a ST OP condition. Which v alue to write is described later on. Ho we ve r , it is important that

the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI

will not start any operation as long as the TWINT bit in TWCR is set. Immediately after

the application has cleared TWINT, the TWI will initiate transmission of the STOP condi-

tion. Note that TWINT is NOT set after a STOP condition has been sent.

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Even though this example is sim ple, it shows the principles involved in all TWI transmissions.

These can be summarized as follows:

• When the TWI has finished an operation and expects applicat ion re sponse , the TWINT F lag is

set. The SCL line is pulled low until TWINT is cleared.

• When the TWINT F lag is set, the user must upd ate all TWI Re gisters with the v alu e rele v ant f or

the ne xt TWI b us cycle . As an e xample , TWDR must be load ed with the v alue to be transmit ted

in the next bus cycle.

• After all TWI Register updates and other pending application software tasks have been

completed, TWCR is written. When writing TWCR, the TWIN T bit shou ld be set. Writing a one

to TWINT clears the flag. The TWI will then commence executing whatever operation was

specified by the TWCR setting.

In the following an assembly and C implementation of the example is given. Note that the code

below assumes that several definitions have been made, for example by using include-files.

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Assembly Code Example C Example Comments

ldi r16,

(1<<TWINT)|(1<<TWSTA)|

(1<<TWEN)

out TWCR, r16

TWCR = (1<<TWINT)|(1<<TWSTA)|

(1<<TWEN) Send START condition

wait1:

in r16,TWCR

sbrs r16,TWINT

rjmp wait1

while (!(TWCR & (1<<TWINT)))

;Wait fo r TW INT Flag set . This

indicates that the START

condition ha s be e n transmitted

in r16,TWSR

andi r16, 0xF8

cpi r16, START

brne ERROR

if ((TWSR & 0xF8) != START)

ERROR(); Check v alue of TWI Status

status diff erent from STAR T go to

ERROR

ldi r16, SLA_W

out TWDR, r16

ldi r16, (1<<TWINT) |

(1<<TWEN)

out TWCR, r16

TWDR = SLA_W;

TWCR = (1<<TWINT) |

(1<<TWEN);

Load SLA_W into TWDR

TWCR to start transmission of

address

wait2:

in r16,TWCR

sbrs r16,TWINT

rjmp wait2

while (!(TWCR & (1<<TWINT)))

;Wait fo r TW INT Flag set . This

indicates that the SLA+W has

been transmitted, and

ACK/NACK has been received.

in r16,TWSR

andi r16, 0xF8

cpi r16, MT_SLA_ACK

brne ERROR

if ((TWSR & 0xF8) !=

MT_SLA_ACK)

ERROR();

Check v alue of TWI Status

status different from

MT_SLA_ACK go to ERR OR

ldi r16, DATA

out TWDR, r16

ldi r16, (1<<TWINT) |

(1<<TWEN)

out TWCR, r16

TWDR = DATA;

TWCR = (1<<TWINT) |

(1<<TWEN); Load DATA into TWDR Register.

Clear TWINT bit in TWCR to

start transmission of data

wait3:

in r16,TWCR

sbrs r16,TWINT

rjmp wait3

while (!(TWCR & (1<<TWINT)))

;Wait fo r TW INT Flag set . This

indicates that the DATA has been

transmitted, and ACK/NACK has

been received.

in r16,TWSR

andi r16, 0xF8

cpi r16, MT_DATA_ACK

brne ERROR

if ((TWSR & 0xF8) !=

MT_DATA_ACK)

ERROR();

Check v alue of TWI Status

status different from

MT_DATA_ACK go to ERROR

ldi r16,

(1<<TWINT)|(1<<TWEN)|

(1<<TWSTO)

out TWCR, r16

TWCR = (1<<TWINT)|(1<<TWEN)|

(1<<TWSTO); Transmit STOP condition

228 8025D–AVR–03/08

ATmega48P/88P/168P/328P

21.7 Transmission Modes

The TWI can operate in one of four major modes. These are named Master Transmitter (MT),

Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these

modes can be us ed in th e s am e ap p lication. As an example, the TWI can use MT mode to write

data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters

are present in the system, some of these might transmit data to the TWI, and then SR mode

would be used. It is the application software that decides which modes are legal.

The following sections describe each of these modes. Possible status codes a re described

along with figures detailing data transmission in each of the modes. These figures contain the

following abbrevia tions:

S: START condition

Rs: REPEATED START condition

R: Read bit (high level at SDA)

W: Write bit (low level at SDA)

A: Acknowledge bit (low level at SDA)

A: Not acknowledge bit (high level at SDA)

Data: 8-bit data byte

P: STOP condition

SLA: Slave Address

In F igure 21-12 to Figure 21-18, circles are used to indicate that the TWINT Flag is set. The

numbers in the circles show the status code held in TWSR, with the prescaler bits masked to

zero. At these points, actions must be taken by the application to continue or complete the TWI

transfer. The TWI transfer is suspended until the TWINT Flag is cleared by software.

When the TWINT Flag is set, the status code in TWSR is used to dete rmine the ap propriat e soft-

ware action. F or each stat us code, the required software a ction and d etails of the following se rial

transfer are given in Table 21-2 to Table 21-5. Note t hat the p re scal er bi ts a re masked t o zer o in

these tables.

21.7.1 Master Transmitter Mode

In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver

(see Figure 21-11). In order to enter a Master mode, a START condition must be transmitted.

The format of the following address packet determines whether Master Transmitter or Master

Receiver mode is to be enter ed. If SLA+W is tra nsmitted, MT mode is enter ed, if SLA+R is trans-

mitted, MR mode is entered. All the status codes mentioned in this section assume that the

prescaler bits are zero or are masked to zero.

229

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ATmega48P/88P/168P/328P

Figure 21-11. Data Transfer in Master Transmitter Mode

A START condition is sent by writing the following value to TWCR:

TWEN must be set to en able t he 2-wire Ser ial In terface, TWSTA must be wr itten t o one to trans-

mit a START condition and TWINT must be written to one to clear the TWINT Flag. The TWI will

then test the 2-wire Serial Bus and generate a START condition as soon as the bus becomes

free. After a START condition has be en tr ansmitt ed, the TWIN T Flag is se t by h ardware, and t he

status code in TWSR will be 0x08 (see Table 21-2). In order to enter MT mode, SLA+W must be

transmitted. This is done by writing SLA+W to TWDR. Thereafter the TWINT bit should be

cleared (by writing it to one) to continue th e transfer. This is ac complished by writing the follow-

ing value to TWCR:

When SLA+W have been transmitte d and an acknowledgemen t bit has been received, T WINT is

set again and a number of status codes in TWSR are possible. Possible status codes in Master

mode are 0x18, 0x20, or 0 x38. The a ppropriate action to b e taken for each of t hese status cod es

is detailed in Table 21-2.

When SLA+W has been successfully transmitted, a data packet should be transmitted. This is

done by writing the data byte to TWDR. TWDR must only be written when TWINT is high. If not,

the access will be discarded, and the Write Collision bit (TWWC) will be set in the TWCR Regis-

ter. After updating TWDR, the TWINT bit should be cleared (by writing it to one) to continue the

transfer. This is accomplished by writing the following value to TWCR:

This scheme is repeated until the last byte has been sent and the transfer is ended by generat-

ing a STOP condition or a repeated START condition. A STOP condition is generated by writing

the following value to TWCR:

A REPEATED START condition is generated by writing the following value to TWCR:

TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE

value 1 X10X10 X

TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE

value 1 X00X10 X

TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE

value 1 X00X10 X

TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE

value 1 X01X10 X

TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE

value 1 X10X10 X

Device 1

MASTER

TRANSMITTER

Device 2

SLAVE

RECEIVER

Device 3 Device n

SDA

SCL

........ R1 R2

VCC

230 8025D–AVR–03/08

ATmega48P/88P/168P/328P

After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same

Slave again, or a ne w Slave without transmitting a STOP condition. Repeated START en ables

the Master to switch betwee n Slaves, Master Transmitte r mode and Master Receiver mode with-

out losing control of the bus.

Table 21-2. Status codes for Master Transmitter Mode

Status Code

(TWSR)

Prescaler Bits

are 0

Status of the 2-wire Serial Bus

and 2-wire Serial Interface

Hardware

Application Software Response

Next Action Taken by TWI Hardware

To/from TWDR To TWCR

STA STO TWIN

TTWE

0x08 A START condition has been

transmitted Load SLA+W 0 0 1 X SLA+W will be transmitted;

ACK or NOT ACK will be received

0x10 A repeated START condition

has been transmitted Load SLA+W or

Load SLA+R

SLA+W will be transmitted;

ACK or NOT ACK will be received

SLA+R will be transmitted;

Logic will switch to Master Receiver mode

0x18 SLA+W has been transmitted;

ACK has been received Load data byte or

No TWDR action or

No TWDR action

Data byte will be transmitted and A CK or NOT ACK will

be received

Repeated START will be transmitted

STOP condition will be transmitted and

TWSTO Flag will be reset

STOP condition followed by a START conditio n will be

transmitted and TWSTO Flag will be reset

0x20 SLA+W has been transmitted;

NOT ACK has been received Load data byte or

No TWDR action or

No TWDR action

Data byte will be transmitted and A CK or NOT ACK will

be received

Repeated START will be transmitted

STOP condition will be transmitted and

TWSTO Flag will be reset

STOP condition followed by a START conditio n will be

transmitted and TWSTO Flag will be reset

0x28 Data byte has been transmit-

ted;

ACK has been received

Load data byte or

No TWDR action or

No TWDR action

Data byte will be transmitted and A CK or NOT ACK will

be received

Repeated START will be transmitted

STOP condition will be transmitted and

TWSTO Flag will be reset

STOP condition followed by a START conditio n will be

transmitted and TWSTO Flag will be reset

0x30 Data byte has been transmit-

ted;

NOT ACK has been received

Load data byte or

No TWDR action or

No TWDR action

Data byte will be transmitted and A CK or NOT ACK will

be received

Repeated START will be transmitted

STOP condition will be transmitted and

TWSTO Flag will be reset

STOP condition followed by a START conditio n will be

transmitted and TWSTO Flag will be reset

0x38 Arbitration lost in SLA+W or

data bytes No TWDR action or

No TWDR action

2-wire Serial Bus will be released and not addressed

Slave mode entered

A START condition will be transmitted when the bus

becomes free

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ATmega48P/88P/168P/328P

Figure 21-12. Formats and States in the Master Transmitter Mode

21.7.2 Master Receiver Mode

In the Master Receiver mode, a number of data bytes are rece ived from a Slave Transmitter

(Slave see Figure 21-13). In order to enter a Master mode, a START condit ion must be tran smit-

ted. The format of the following address packet determines whether Master Transmitter or

Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R

is transmitted, MR mode is entered. All the status codes mentioned in this section assume that

the prescaler bits are zero or are masked to zero.

S SLA W A DATA A P

$08 $18 $28

R SLA W

$10

$20

$30

A or A

$38

Other master

continues

A or A

$38

Other master

continues

$68

Other master

continues

$78 $B0

To corresponding

states in slave mode

Successfull

transmission

to a slave

receiver

Next transfer

started with a

repeated start

condition

Not acknowledge

received after the

slave address

Not acknowledge

received after a data

byte

Arbitration lost in slave

address or data byte

Arbitration lost and

addressed as slave

DATA A

From master to slave

From slave to master

Any number of data bytes

and their associated acknowledge bits

This number (contained in TWSR) corresponds

to a defined state of the 2-Wire Serial Bus. The

rescaler bits are zero or masked to zero

232 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 21-13. Data Transfer in Ma ster Receiver Mode

A START condition is sent by writing the following value to TWCR:

TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written to

one to transmit a START co ndition and TWINT must b e set to clear the TWINT Flag . The TWI

will then test the 2-wire Serial Bus and generate a START condition as soon as the bus

becomes free. After a START condition has been transmitted, the TWINT Flag is set by hard-

ware, and the status code in TWSR will be 0x08 (See Table 21-2). In order to enter MR mode,

SLA+R must be transmitted. This is done by writing SLA+R to TW DR. Therea fter the T WIN T b it

should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing

the following value to TWCR:

When SLA+R have been tr ansmitt ed and an acknowle dgemen t bi t has b een re ceived, TWI NT is

set again and a number of status codes in TWSR are possible. Possible status codes in Master

mode are 0x38, 0x40, or 0 x48. The a ppropriate action to b e taken for each of t hese status cod es

is detailed in Table 21-3. Received data can be read from the TWDR Register when the TWINT

Flag is set high by hardware. This scheme is repeated until the last byte has been received.

After the last by te has been re ce ived, th e MR sho uld inf orm th e ST b y sendin g a NACK af ter t he

last received data byte. The transfer is ended by generating a STOP condition or a repeated

START condition. A STOP condition is generated by writing the following value to TWCR:

A REPEATED START condition is generated by writing the following value to TWCR:

After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same

Slave again, or a ne w Slave without transmitting a STOP condition. Repeated START en ables

TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE

value 1 X10X10 X

TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE

value 1 X00X10 X

TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE

value 1 X01X10 X

TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE

value 1 X10X10 X

Device 1

MASTER

RECEIVER

Device 2

SLAVE

TRANSMITTER

Device 3 Device n

SDA

SCL

........

R1 R2

233

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ATmega48P/88P/168P/328P

the Master to switch betwee n Slaves, Master Transmitte r mode and Master Receiver mode with-

out losing control over the bus.

Table 21-3. Status codes for Master Receiver Mode

Status Code

(TWSR)

Prescaler Bits

are 0

Status of the 2-wire Serial Bus

and 2-wire Serial Interface

Hardware

Application Software Response

Next Action Taken by TWI Hardware

To/from TWDR To TWCR

STA STO TWIN

TTWE

0x08 A START condition has been

transmitted Load SLA+R 0 0 1 X SLA+R will be transmitted

ACK or NOT ACK will be received

0x10 A repeated START condition

has been transmitted Load SLA+R or

Load SLA+W

SLA+R will be transmitted

ACK or NOT ACK will be received

SLA+W will be transmitted

Logic will switch to Master Transmitter mode

0x38 Arbitration lost in SLA+R or

NOT ACK bit No TWDR action or

No TWDR action

2-wire Serial Bus will be released and not addressed

Slave mode will be entered

A START condition will be transmitted when the bus

becomes free

0x40 SLA+R has been transmitted;

ACK has been received No TWDR action or

No TWDR action

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

0x48 SLA+R has been transmitted;

NOT ACK has been received No TWDR action or

No TWDR action or

No TWDR action

Repeated START will be transmitted

STOP condition will be transmitted and TWSTO Flag

will be reset

STOP condition followed by a START conditio n will be

transmitted and TWSTO Flag will be reset

0x50 Data byte has been received;

ACK has been returned Read data byte or

Read data byte

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

0x58 Data byte has been received;

NOT ACK has been returned Read data byte or

Read data byte or

Read data byte

Repeated START will be transmitted

STOP condition will be transmitted and TWSTO Flag

will be reset

STOP condition followed by a START conditio n will be

transmitted and TWSTO Flag will be reset

234 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 21-14. Formats and States in the Master Receiver Mode

21.7.3 Slave Receiver Mode

In the Slave Receiver mode, a number of data bytes are received from a Master Transmitter

(see Figure 21-15). All the status codes mentioned in this section assume that the prescaler bits

are zero or are masked to zero.

Figure 21-15. Data transfer in Slave Receiver mode

S SLA R A DATA A

$08 $40 $50

SLA R

$10

$48

A or A

$38

Other master

continues

$38

Other master

continues

$68

Other master

continues

$78 $B0

To corresponding

states in slave mode

Successfull

reception

from a slave

receiver

Next transfer

started with a

repeated start

condition

Not acknowledge

received after the

slave address

Arbitration lost in slave

address or data byte

Arbitration lost and

addressed as slave

DATA A

From master to slave

From slave to master

Any number of data bytes

and their associated acknowledge bits

This number (contained in TWSR) corresponds

to a defined state of the 2-Wire Serial Bus. The

rescaler bits are zero or masked to zero

PDATA A

$58

Device 3 Device n

SDA

SCL

........

R1 R2

Device 2

MASTER

TRANSMITTER

Device 1

SLAVE

RECEIVER

235

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ATmega48P/88P/168P/328P

To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:

The upper 7 bits are the address to which the 2-wire Serial Interface will respond when

addressed by a Master. If the LSB is set, the TWI will respon d to the general ca ll address (0x00 ),

otherwise it will ignore the general call address.

TWEN must be wr itte n t o one t o en able t he TWI . The TWEA b it mu st be wr itt e n to on e to en able

the acknowledgement of the device’s own slave addr ess or the general call addre ss. TWSTA

and TWSTO must be written to zero.

When TWAR and TWCR have been initialized, the TWI waits until it is addre ssed by its own

slave address (or the gen eral call address if enabled) follo wed by the data direction bit. If the

direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered. A fter

its own slave address and the write bit have been received, the TWINT Flag is set and a valid

status code can be read from TWSR. The status code is used to determine the appropriate soft-

ware action. The appropriate action to be taken for each status code is detailed in Table 21-4.

The Slave Receiver mode may also b e entere d if arbit ration is lost wh ile the TWI is in t he Master

mode (see states 0x68 and 0x78).

If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”) to SDA

after the next received data byte. This can be used to indicate that the Slave is not able to

receive any more bytes. While T WEA is zero, the TWI does not acknowledge its own slave

address. However, the 2-wire Serial Bus is s till monitored and address recognition may resume

at any time by sett ing TWEA. T his implies that the TW EA bit may be us ed to tem porarily iso late

the TWI from the 2-wire Serial Bus.

In all sleep mo des other than Id le mode, the clo ck system to the TWI is t urned off. If the TWEA

bit is set, the interface can still acknowledge its own slave address or the general call address by

using the 2-wire Serial Bus clock as a clock source. The pa rt will then wake up from slee p and

the TWI will hold the SCL cloc k low during the wake up and until the TWIN T Flag is cleared (by

writing it to one). Further data reception will be carried out as normal, with the AVR clocks run-

ning as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be

held low for a long time, blocking other data transmissions.

Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present

on the bus when waking up from these Sleep modes.

TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE

value Device’s Own Slave Address

TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE

value 0100010 X

236 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Table 21-4. Status Codes for Slave Receiver Mode

Status Code

(TWSR)

Prescaler Bits

are 0

Status of the 2-wire Serial Bus

and 2-wire Serial Interface Hard-

ware

Application Software Respon se

Next Action Taken by TWI Hardware

To/from TWDR To TWCR

STA STO TWIN

TTWE

0x60 Own SLA+W has been received;

ACK has been returned No TWDR actio n or

No TWDR action

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

0x68 Arbitration lost in SLA+R/W as

Master; own SLA+W has been

received; ACK has been returned

No TWDR action or

No TWDR action

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

0x70 General call address has been

received; ACK has been returned No TWDR action or

No TWDR action

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

0x78 Arbitration lost in SLA+R/W as

Master; General call address has

been received; ACK has been

returned

No TWDR action or

No TWDR action

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

0x80 Previously addressed with own

SLA+W; data has been received;

ACK has been returned

Read data byte or

Read data byte

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

0x88 Previously addressed with own

SLA+W; data has been received;

NOT ACK has been returned

Read data byte or

Read data byte

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitt ed when the bus

becomes free

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitt ed when the bus

becomes free

0x90 Previously addressed with

general call; data has been re-

ceived; ACK has been returned

Read data byte or

Read data byte

Data byte will be received and NOT ACK will be

returned

Data byte will be received and ACK will be returned

0x98 Previously addressed with

general call; data has been

received; NOT ACK has been

returned

Read data byte or

Read data byte

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitt ed when the bus

becomes free

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitt ed when the bus

becomes free

0xA0 A STOP condition or repeated

START condition has been

received while still addressed as

Slave

No action 0

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”

Switched to the not addressed Slave mode;

no recognition of own SLA or GCA;

a START condition will be transmitt ed when the bus

becomes free

Switched to the not addressed Slave mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitt ed when the bus

becomes free

237

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ATmega48P/88P/168P/328P

Figure 21-16. Formats and States in the Slave Receiver Mode

21.7.4 Slave Transmitter Mode

In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver

(see Figure 21-17). All the status codes mentioned in this section assume that the prescaler bits

are zero or are masked to zero.

Figure 21-17. Data Transfer in Slave Transmitter Mode

S SLA W A DATA A

$60 $80

$88

$68

Reception of the own

slave address and one or

more data bytes. All are

acknowledged

Last data byte received

is not acknowledged

Arbitration lost as master

and addressed as slave

Reception of the general call

address and one or more data

bytes

Last data byte received is

not acknowledged

From master to slave

From slave to master

Any number of data bytes

and their associated acknowledge bits

This number (contained in TWSR) corresponds

to a defined state of the 2-Wire Serial Bus. The

prescaler bits are zero or masked to zero

P or SDATA A

$80 $A0

P or SA

ADATAA

$70 $90

$98

$78

P or SDATA A

$90 $A0

P or SA

General Call

Arbitration lost as master and

addressed as slave by general call

DATA A

Device 3 Device n

SDA

SCL

........ R1 R2

Device 2

MASTER

RECEIVER

Device 1

SLAVE

TRANSMITTER

238 8025D–AVR–03/08

ATmega48P/88P/168P/328P

To initiate the Slave Transmit ter mode, TWAR and TWCR must be initialized as follows:

The upper seven bits are the addre ss to which the 2-wire Serial Interface will respond when

addressed by a Master. If the LSB is set, the TWI will respon d to the general ca ll address (0x00 ),

otherwise it will ignore the general call address.

TWEN must be wr itte n t o one t o en able t he TWI . The TWEA b it mu st be wr itt e n to on e to en able

the acknowledgement of the device’s own slave addr ess or the general call addre ss. TWSTA

and TWSTO must be written to zero.

When TWAR and TWCR have been initialized, the TWI waits until it is addre ssed by its own

slave address (or the gen eral call address if enabled) follo wed by the data direction bit. If the

direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR mode is entered. A fter

its own slave address and the write bit have been received, the TWINT Flag is set and a valid

status code can be read from TWSR. The status code is used to determine the appropriate soft-

ware action. The appropriate action to be taken for each status code is detailed in Table 21-5.

The Slave Transmitte r mode may also be entered if arbitration is lost while the TWI is in the

Master mode (see state 0xB0).

If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the trans-

fer. State 0xC0 or state 0xC8 will be entered, depending on whether the Master Receiver

transmits a NACK or ACK after the final b yte. The TWI is switched to the not addre ssed Slave

mode, and will ignore the Master if it continues the transfer. Thus the Master Receiver receives

all “1” as serial data. State 0xC8 is entered if the Master demands additional data bytes (by

transmitting ACK), even though the Slave has transmitted the last byte (TWEA zero and expect-

ing NACK from the Master).

While TWEA is zero, the TWI does not respond to its own slave address. However, the 2-wire

Serial Bus is still monitored and address recognition may resume at any time by setting TWEA.

This implies that the TWEA b i t may be used to te mpo rarily isolat e th e TWI fr om th e 2- wire Seria l

Bus.

In all sleep mo des other than Id le mode, the clo ck system to the TWI is t urned off. If the TWEA

bit is set, the interface can still acknowledge its own slave address or the general call address by

using the 2-wire Serial Bus clock as a clock source. The pa rt will then wake up from slee p and

the TWI will hold the SCL clock will low during th e wake up and until the TWINT Flag is cleared

(by writing it to one). Further data tr ansmission will be carried out as normal, with the AVR clocks

running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may

be held low for a long time, blocking other data transmissions.

Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present

on the bus when waking up from these sleep modes.

TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE

value Device’s Own Slave Address

TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE

value 0100010 X

239

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ATmega48P/88P/168P/328P

Table 21-5. Status Codes for Slave Transmitter Mode

Status Code

(TWSR)

Prescaler

Bits

are 0

Status of the 2-wire Serial Bus

and 2-wire Serial Interface Hard-

ware

Application Software Response

Next Action Taken by TWI Hardware

To/from TWDR To TWCR

STA STO TWIN

TTWE

0xA8 Own SLA+R has been received;

ACK has been returned Load data byte or

Load data byte

Last data byte will be transmitted and NOT ACK should

be received

Data byte will be transmitted and ACK should be re-

ceived

0xB0 Arbitration lost in SLA+R/W as

Master; own SLA+R has been

received; ACK has been ret urned

Load data byte or

Load data byte

Last data byte will be transmitted and NOT ACK should

be received

Data byte will be transmitted and ACK should be re-

ceived

0xB8 Data byte in TWDR has been

transmitted; ACK has been

received

Load data byte or

Load data byte

Last data byte will be transmitted and NOT ACK should

be received

Data byte will be transmitted and ACK should be re-

ceived

0xC0 Data byte in TWDR has been

transmitted; NOT ACK has been

received

No TWDR action or

No TWDR action

Switched to the not addressed Sla ve mode;

no recognition of own SLA or GCA

Switched to the not addressed Sla ve mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”

Switched to the not addressed Sla ve mode;

no recognition of own SLA or GCA;

a START condition will be transmitt ed when the bus

becomes free

Switched to the not addressed Sla ve mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitt ed when the bus

becomes free

0xC8 Last data byte in TWDR has been

transmitted (TWEA = “0”); ACK

has been received

No TWDR action or

No TWDR action

Switched to the not addressed Sla ve mode;

no recognition of own SLA or GCA

Switched to the not addressed Sla ve mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”

Switched to the not addressed Sla ve mode;

no recognition of own SLA or GCA;

a START condition will be transmitt ed when the bus

becomes free

Switched to the not addressed Sla ve mode;

own SLA will be recognized;

GCA will be recognized if TWGCE = “1”;

a START condition will be transmitt ed when the bus

becomes free

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Figure 21-18. Formats and States in the Slave Transmitter Mode

21.7.5 Miscellaneous States

There are two stat us codes that do not correspond to a defined TWI state, see Table 21-6.

Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not

set. This occurs between other states, and when the TWI is not involved in a serial transfer.

Status 0x00 indicates that a bus error has occurred during a 2-wire Serial Bus transfer. A bus

error occurs when a START or STOP condition occurs at an illegal position in the format frame.

Examples of such illegal positions are during the serial transfer of an address byte, a data byte,

or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the

TWSTO Flag must set and TWINT must be cleared by writing a logic one to it. This causes the

TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in

TWCR are affected). The SDA and SCL lines are released, and no STOP condition is

transmitted.

21.7.6 Combining Several TWI Modes

In some cases, several TWI modes must be combined in order to complete the desired action.

Consider for example reading data from a serial EEPROM. Typically, such a transfer involves

the following steps:

1. The transfer must be initiated.

2. The EEPROM must be instructed what locat ion should be read.

3. The reading must be performed.

4. The tr ansfer must be finished.

S SLA R A DATA A

$A8 $B8

$B0

Reception of the own

slave address and one or

more data bytes

Last data byte transmitted.

Switched to not addressed

slave (TWEA = '0')

Arbitration lost as master

and addressed as slave

From master to slave

From slave to master

Any number of data bytes

and their associated acknowledge bits

This number (contained in TWSR) corresponds

to a defined state of the 2-Wire Serial Bus. The

prescaler bits are zero or masked to zero

P or SDATA

$C0

DATA A

$C8

P or SAll 1's

Table 21-6. Miscellaneous States

Status Code

(TWSR)

Prescaler Bits

are 0

Status of the 2-wire Serial Bus

and 2-wire Serial Interface

Hardware

Application Software Response

Next Action Taken by TWI Hardware

To/from TWDR To TWCR

STA STO TWIN

TTWE

0xF8 No relevant state information

available; TWINT = “0” No TWDR action No TWCR action Wait or proceed current transfer

0x00 Bus error due to an illegal

START or STOP condition No TWDR action 0 1 1 X Only the int ernal ha rdware is affect ed, no STOP condi-

tion is sent on the bus. In all cases, the bus is released

and TWSTO is cleared.

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Note that data is tran smitted both fro m Master to Slave and vice versa. The Maste r must instr uct

the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data

must be read fr om the Slave, impl ying the use of the MR mode. Thus, the transf er direction must

be changed. The Master must keep control of the bus during all these steps, and the steps

should be carried out as an atomical operation. If this principle is violated in a multi master sys-

tem, another Master can alter the data pointer in the EEPROM between steps 2 and 3, and the

Master will read the wrong data location. Such a change in transfer direction is accomplished by

transmitting a REPEATED START between the transmission of the address byte and reception

of the data. After a REPEATED START, the Master keeps owne rship of the bus. The following

figure shows the flow in this transfer.

Figure 21-19. Combining Several TWI Modes to Access a Serial EEPROM

21.8 Multi-master Systems and Arbitration

If multiple masters are connected to the same bus, transmissions may be initiated simulta-

neously by one or more of them. The TWI standard ensures that such situations are handled in

such a way that one of the masters will be allowed to proceed with the transfer, and that no data

will be lost in the process. An example of an arbitration situation is depicted below, where two

masters are trying to transmit data to a Slave Receiver.

Figure 21-20. An Arbitration Example

Several different scenarios may arise during arbitration, as described below:

• Two or more masters are performing identical communication with the same Slave. In this

case, neither the Slave nor any of the masters will know about the bus contention.

• Two or more masters are accessin g the same Slave with different data or direction bit. In this

case, arbitr ation will occur , either in the READ/WRITE bit or in the data bits . The masters trying

to output a one on SDA while another Master outputs a zero will lose the arbitration. Losing

masters will switch to not addressed Sla v e mode or wait until the b us is free and transmit a new

START condition, depending on application softw are action.

Master Transmitter Master Receiver

S = START Rs = REPEATED START P = STOP

Transmitted from master to slave Transmitted from slave to master

S SLA+W A ADDRESS A Rs SLA+R A DATA A P

Device 1

MASTER

TRANSMITTER

Device 2

MASTER

TRANSMITTER

Device 3

SLAVE

RECEIVER

Device n

SDA

SCL

........ R1 R2

VCC

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• Two or more masters are accessing different slaves. In this case, arbitration will occur in the

SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose

the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are

being addressed by the winning Master. If addressed, they will switch to SR or ST mode,

depending on the value of the READ/WRITE bit. If they are not being addressed, they will

switch to not addressed Slave mode or wait until the bus is free and transmit a new START

condition, depending on application software action.

This is summarized in Figure 21-21. Possible status values are given in circles.

Figure 21-21. Possible Status Codes Caused by Arbitration

21.9 Register Description

21.9.1 TWBR – TWI Bit Rate Register

• Bits 7..0 – TWI Bit Rate Register

TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency

divider which generates the SCL clock frequency in the Master modes. See ”Bit Rate Generator

Unit” on page 222 fo r calculating bit rates.

21.9.2 TWCR – TWI Control Register

The TWCR is used to contr ol the operat ion of the TWI . It is us ed to enable the T WI, to in itiate a

Master access by applying a START condition to the bus, to generate a Receiver acknowledge,

to generate a stop condition, and to control halting of the bus while the data to be written to the

bus are written to the TWDR. It also indicates a write collision if data is attempted written to

TWDR while the register is inaccessible.

Own

Address / General Call

received

Arbitration lost in SLA

TWI bus will be released and not addressed slave mode will be entered

A START condition will be transmitted when the bus becomes free

Arbitration lost in Data

Direction

Ye s

Write

Data byte will be received and NOT ACK will be returned

Data byte will be received and ACK will be returned

Last data byte will be transmitted and NOT ACK should be received

Data byte will be transmitted and ACK should be received

Read

68/78

SLASTART Data STOP

Bit 76543210

(0xB8) TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 TWBR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

(0xBC) TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE TWCR

Read/Write R/W R/W R/W R/W R R/W R R/W

Initial Value 0 0 0 0 0 0 0 0

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• Bit 7 – TWINT: TWI Interrupt Flag

This bit is set by hardware when the TWI has finished its current job and expects application

software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the

TWI Interrupt V ector . While the TWI NT Flag is se t, the SCL lo w perio d is stretch ed. The TWINT

Flag must be cleared by software by writing a logic one to it. Note that this flag is not automati-

cally cleared by hardware when executing the interr upt routine. Also note that clearing this flag

starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Sta-

tus Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this

flag.

• Bit 6 – TWEA: TWI Enable Acknowledge Bit

The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to

one, the ACK pulse is generated on the TWI bus if the following conditions are met:

1. The device’s own slave address has been received.

2. A general call has been received, while the TWGCE bit in the TWAR is set.

3. A data byte has been received in Master Receiver or Slave Receiver mode.

By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial

Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one

again.

• Bit 5 – TWSTA: TWI START Condition Bit

The application writes the TWSTA bit to one when it desires to become a Master on the 2-wire

Serial Bus. T he TWI hard ware checks if the bu s is available, and generates a START condition

on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is

detected, and then generates a new START condition to claim the bus Master status. TWSTA

must be cleared by soft ware when the START condition has b een transmitted.

• Bit 4 – TWSTO: TWI STOP Condition Bit

Writing the TWSTO bit to one in Master mode will generate a STOP condition on the 2-wire

Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared auto-

matically. In Slave mode, setting the TWST O bit can be used to recover from an error condition.

This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed

Slave mode and releases the SCL and SDA lines to a high impedance state.

• Bit 3 – TWWC: TWI Write Collision Flag

The TWWC bit is set whe n attempting to write to the TWI Dat a Register – TWDR when TWINT is

low. This flag is cleared by writing the TWDR Register when TWINT is high.

• Bit 2 – TWEN: TWI Enab le Bit

The TWEN bit enables TWI operat ion an d acti va te s t he TWI interf ace. When TWEN is writte n to

one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the

slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI

transmissions are terminated, regardless of any ongoing operation.

• Bit 1 – Res: Reserved Bit

This bit is a reserved bit and will always read as zero.

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• Bit 0 – TWIE: TWI Interrupt Enable

When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be acti-

vated for as long as the TWINT Flag is high.

21.9.3 TWSR – TWI Status Regist er

• Bits 7..3 – TWS: TWI Status

These 5 bits reflect the status of the TWI logic and the 2 -wire Serial Bus. The different status

codes are descr ibed later in this sec tion. N ote that the va lue re ad from TW SR cont ains bo th the

5-bit status value and the 2-bit prescaler value. The application designer should mask the pres-

caler bits to zero when checking the Status bits. This makes status checking independent of

prescaler setting. This approach is used in this datasheet, unless otherwise noted.

• Bit 2 – Res: Reserved Bit

This bit is reserved and will always read as zero.

• Bits 1..0 – TWPS: TWI Prescaler Bits

These bits can be read and writ ten, and control the bit rate prescaler.

To calculate bit rates, se e ”Bit Rate Generator Unit” on page 222. The value of TWPS1..0 is

used in the equation.

21.9.4 TWDR – TWI Data Register

In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR

contains the last byte received. It is writable while the TWI is not in t he process of shifting a byte.

This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Regis-

ter cannot be initialized b y the user before the first interrup t occurs. Th e data in TWD R remains

stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously

shifted in. TWDR always contains the last byte present on the bus, except after a wake up from

a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case

Bit 76543210

(0xB9) TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 TWSR

Read/Write RRRRRRR/WR/W

Initial Value 1 1 1 1 1 0 0 0

Table 21-7. TWI Bit Rat e Presca le r

TWPS1 TWPS0 Prescaler Value

001

014

1016

1164

Bit 76543210

(0xBB) TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 TWDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 1 1 1 1 1 1 1 1

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of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the

ACK bit is controlled automatica lly by the TWI lo gic, the CPU cannot access the ACK bit dir ectly.

• Bits 7..0 – TWD: TWI Data Register

These eight bits constitute the next data byte to be transmitted, or the latest data byte received

on the 2-wire Serial Bus.

21.9.5 TWAR – TWI (Slave) Address Register

The TWAR should be loaded with the 7-bit Slave address (in the seven most significan t bits of

TWAR) to which the TWI will resp ond when programmed as a Slave T ransmitter or Receiver,

and not needed in the Master modes. In multi master systems, TWAR must be set in masters

which can be addressed as Slaves by other Masters.

The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an

associated address comparator that looks for the slave address (or general call address if

enabled) in the received serial address. If a match is found, an interrupt request is generated.

• Bits 7..1 – TWA: TWI (Slave) Address Register

These seven bits constitute the slave address of the TW I un i t.

• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit

If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.

21.9.6 TWAMR – TWI (Slave) Address Mask Register

• Bits 7..1 – TWAM: TWI Address Mask

The TWAMR can be loaded with a 7-bit Salve Address mask. Each of the bits in TWAMR can

mask (disable) th e correspondin g address bit s in the TWI Address Registe r (TWAR). If the mask

bit is set to one then the address match logic ignores the compare between the incoming

address bit and the corresponding bit in TWAR. Figure 21-22 shown the address match logic in

detail.

Bit 76543210

(0xBA) TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE TWAR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 1 1 1 1 1 1 1 0

Bit 76543210

(0xBD) TWAM[6:0] – TWAMR

Read/Write R/W R/W R/W R/W R/W R/W R/W R

Initial Value 0 0 0 0 0 0 0 0

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Figure 21-22. TWI Address Match Logic, Block Diagram

• Bit 0 – Res: Reserved Bit

This bit is an unused bit in the ATmega48P/88P/168P/328P, and will always read as zero.

Addre

Match

Address Bit Comparator 0

Address Bit Comparator 6..1

TWAR0

TWAMR0

Address

Bit 0

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22. Analog Comparator

22.1 Overview The Analog Comparat or compares the input values on the positive pin AIN0 and negative pin

AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin

AIN1, the Analog Comparator output, ACO, is set. The comparator’s ou tput can be set to trigger

the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate

interrupt, exclusive to the Analog Comparator. Th e user can select Interrupt triggering on com-

parator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is

shown in Figure 22-1.

The Power Reduction ADC bit, PRADC, in ”Minimizing Power Consumption” on page 43 must

be disabled by writing a logical zero to be able to use the ADC input MUX.

Figure 22-1. Analog Comparator Block Diagram(2)

Notes: 1. See Table 22-1 on page 248.

2. Refer to Figure 1-1 on page 2 and Table 13-9 on page 89 for Analog Comparator pin

placement.

22.2 Analog Comparator Multiplexed Input

It is possible to select any of the ADC7..0 pins to replace the negative input to the Analog Com-

parator. The ADC multiplexer is used to select this input, and consequently, the ADC must be

switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in

ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX2..0 in ADMUX

select the input pin to replace the negative input to the Analog Comparator, as shown in Table

22-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog

Comparator

ACBG

BANDGAP

REFERENCE

ADC MULTIPLEXER

OUTPUT

ACME

ADEN

(1)

248 8025D–AVR–03/08

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22.3 Register Description

22.3.1 ADCSRB – ADC Control and Status Register B

• Bit 6 – ACME: Analog Compar ator Multiplexer Enable

When this bit is written logic one and the ADC is switched off (A DEN in ADCSRA is zero), the

ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written

logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed

description of this bit, see ”Analog Comparator Multiplexed Input” on page 247.

22.3.2 ACSR – Analog Comparato r Cont rol and Status Re gi st er

• Bit 7 – ACD: Analog Comparat or Disable

When this bit is written logic one, the power to the Ana log Comparator is swit ched off. This bit

can be set at any time to turn off the Analog Comparator. This will reduce power consumption in

Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be

disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is

changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Select

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog

Comparator. When this bit is cleared, AI N0 is ap plied to the positive input of the Analog Compar-

ator. When the bandgap referance is used as input to the Analog Comparator, it will take a

Table 22-1. Analog Comparator Multiplexed In put

ACME ADEN MUX2..0 Analog Comparator Negative Input

0 x xxx AIN1

1 1 xxx AIN1

1 0 000 ADC0

1 0 001 ADC1

1 0 010 ADC2

1 0 011 ADC3

1 0 100 ADC4

1 0 101 ADC5

1 0 110 ADC6

1 0 111 ADC7

Bit 76543210

(0x7B) –ACME–––ADTS2 ADTS1 ADTS0 ADCSRB

Read/Write R R/W R R R R/W R/W R/W

Initial Value00000000

Bit 76543210

0x30 (0x50) ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial Value 0 0 N/A 0 0 0 0 0

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certain time for the voltage to stabilize. If not stabilized, the first conversion may give a wrong

value. See ”Internal Voltage Reference” on page 50

• Bit 5 – ACO: Analog Comparator Output

The output of the Analog Comparator is synchronized and then directly connected to ACO. The

synchronization introduces a delay of 1 - 2 clock cycles.

• Bit 4 – ACI: Analog Comparator Interrupt Fla g

This bit is set by hardware when a comparator output event triggers the interrupt mode defined

by ACIS1 and ACIS0. The Analog Comparator interrupt routine is ex ecut ed if the ACIE bit is se t

and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-

rupt handling ve ctor. Alternatively, ACI is cleared by writing a logic one to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is writte n logic one and t he I-bit in the Status Register is set, the Analog Com-

parator interrupt is activated. When written logic zero, the interrupt is disabled.

• Bit 2 – ACIC: Analog Comparator Input Capture Enable

When written logic one, this bit enables the input ca pture function in Timer/Cou nter1 to be trig-

gered by the Ana log Comp arat or. The compar ator o utput is in this case directly connecte d to the

input capture front-end logic, making the comparator utilize the noise canceler and edge select

features of the Timer/Cou nter1 Input Capture interru pt. When written logic zero, no connection

between the Analog Comparator and the input capture function exists. To make the comparator

trigger the Time r/Counter1 Input Ca pture interrupt, the IC IE1 bit in the Timer Interrup t Mask

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determin e which comparator even ts that trigger the Analog Compa rator interr upt. The

different settings are shown in Table 22 -2.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by

clearing its Inte rrupt Enable bit in the ACSR Reg ister. Ot herwise an inter rupt can occu r when the

bits are changed.

Table 22-2. ACIS1/ACIS0 Settings

ACIS1 ACIS0 Interrupt Mode

0 0 Comparator Interrupt on Output Toggle.

01Reserved

1 0 Comparator Interrupt on Falling Output Edge.

1 1 Comparator Interrupt on Rising Output Edge.

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22.3.3 DIDR1 – Digital Input Disable Register 1

• Bit 7..2 – Res: Reserved Bits

These bits are unused bits in the ATmega48P/88P/168P/328P, and will always read as zero.

• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disa ble

When this bit is writte n logic one , the digita l input buf fer on the AI N1/0 pin is disa bled. The corr e-

sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is

applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ-

ten logic one to reduce power consumption in the digital input buffer.

Bit 76543210

(0x7F) ––––––AIN1DAIN0DDIDR1

Read/Write RRRRRRR/WR/W

Initial Value 00000000

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23. Analog-to-Digital Converter

23.1 Features •10-bit Resolution

•0.5 LSB Integral Non-linearity

•± 2 LSB Absolute Accuracy

•13 - 260 µs Conversion Time

•Up to 76.9 kSPS (Up to 15 kSPS at Maximum Resolution)

•6 Multiplexed Single Ended Input Channels

•2 Additional Multiplexed Single Ended Input Channels (TQFP and QFN/MLF Package only)

•Temperature Sensor Input Channel

•Optional Left Adjust men t for ADC Result Readout

•0 - VCC ADC Input Voltage Range

•Selectable 1.1V ADC Reference Voltage

•Free Running or Single Conversion Mode

•Interrupt on ADC Conversion Complete

•Sleep Mode Noise Canceler

23.2 Overview The ATmega48P/88P/168P/328P features a 10-bit successive approximation ADC. The ADC is

connected to an 8-chann el Analog Multiplexer which allows eight single-ended volta ge inputs

constructed from the pins of Port A. The single-ended voltage inputs refer to 0V (GND).

The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is

held at a constant level during conversion. A block diagram of the ADC is shown in Figure 23-1

on page 252.

The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than ±

0.3V from VCC. See the paragraph ”ADC Noise Canceler” on page 257 on how to connect this

pin.

Internal reference voltages of nominally 1.1V or AVCC are provided On-chip. Th e voltage refer-

ence may be externally decoupled at the AREF pin by a capacitor for bett er noise performance.

The Power Reduction ADC bit, PRADC, in ”Minimizing Power Consumption” on page 43 must

be disabled by writing a logical zero to enable the ADC.

The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-

mation. The minimum value represents GND and the maximum value represents the voltage on

the AREF pin minus 1 LSB. Optionally, AVCC or an internal 1.1V reference voltage may be con-

nected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal

voltage reference may thus be deco upled by an external capacitor at the AREF pin to im prove

noise immunity.

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Figure 23-1. Analog to Digital Converter Block Schema tic Operation,

The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input

pins, as well as GND and a fixed bandgap voltage reference, ca n be selected as single ended

inputs to the ADC. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Volt-

age reference and input channel selections will not go into effect until ADEN is set. The ADC

does not consume power when ADEN is cleared, so it is recommended to switch off the ADC

before enterin g po we r sa ving s lee p m od es .

The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and

ADCL. By default, the result is presented right ad justed, but can optionally be presented left

adjusted by setting the ADLAR bit in ADMUX.

If the result is left ad justed and no more than 8-bit precision is requ ired, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data

Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers

is blocked. This means that if ADCL has been read, an d a conversion completes b efore ADCH is

ADC CONVERSION

COMPLETE IRQ

8-BIT DATA BUS

15 0

ADC MULTIPLEXER

SELECT (ADMUX) ADC CTRL. & STATUS

(ADCH/ADCL)

MUX2

ADIE

ADFR

ADSC

ADEN

ADIF ADIF

MUX1

MUX0

ADPS0

ADPS1

ADPS2

MUX3

CONVERSION LOGIC

10-BIT DAC

SAMPLE & HOLD

COMPARATOR

INTERNAL 1.1V

REFERENCE

MUX DECODER

AVCC

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

REFS0

REFS1

ADLAR

CHANNEL SELECTION

ADC[9:0]

ADC MULTIPLEXER

OUTPUT

AREF

BANDGAP

REFERENCE

PRESCALER

GND

INPUT

MUX

TEMPERATURE

SENSOR

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read, neither register is updated and the result from the conversion is lost. When ADCH is read,

ADC access to the ADCH and ADCL Registers is re-enabled.

The ADC has its own interr upt which can be trigge red when a conversion co mpletes. When ADC

access to the Data Registers is prohibited be tween reading of ADCH and ADCL, the interrupt

will trigger even if the result is lost.

23.3 Starting a Conversion

A single conversion is started by disabli ng the Power Reduct ion ADC bit, PRADC, in ”Minimizing

Power Consumption” on page 43 by writing a logical zero to it and writing a logical one to the

ADC Start Conversion bit, ADSC. This bit stays high as long as the conve rsion is in progress

and will be cleared by hardware when the conversion is completed. If a different data channel is

selected while a conversion is in progress, the ADC will finish the current conversion before per-

forming the channel change.

Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is

enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is

selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (See description of the ADTS

bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal,

the ADC prescaler is reset and a conversion is started. This provides a method of starting con-

versions at fixed intervals. If the trigger signal still is set when the conversion completes, a new

conversion will not be started. If another positive edge occurs on the trigger signal during con-

version, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific

interrupt is di sabled or t he Global In terr upt Enable b it in SREG is cleared. A conversion can th us

be triggered with out causing an interr upt. However, the Interrup t Flag must be cleare d in order to

trigger a new conversion at the next interrupt event.

Figure 23-2. ADC Auto Trigger Logic

Using the ADC Interrupt Flag as a trigger source make s the ADC start a new conver sion as soon

as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-

stantly sampling and up dating the ADC Data Register . The first conversion must be started by

writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive

conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.

DSC

ADIF

SOURCE 1

SOURCE n

ADTS[2:0]

CONVERSION

LOGIC

PRESCALER

START CLKADC

.EDGE

DETECTOR

ADATE

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If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to

one. ADSC can also be us ed to determine if a conversion is in pr ogress. The ADSC bit will be

read as one during a conversion, independently of how the conversio n was started.

23.4 Prescaling and Conversion Timing

Figure 23-3. ADC Prescaler

By default, the successive approximation circuitry requires an input clock frequency between 50

kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the

input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.

The ADC module contains a prescaler, which generates an acceptable ADC clock frequency

from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.

The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit

in ADCSRA. The prescaler keeps runnin g for as long as the ADEN bit is set, and is continuously

reset when ADEN is low.

When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion

starts at the following rising edge of the ADC clock cycle.

A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched

on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.

When the bandgap reference volta ge is used as input to the ADC, it will take a certain time for

the voltage to stabilize. If not stabilized, the first value read after the first conversion may be

wrong.

The actual sample- and-h old ta kes pla ce 1. 5 ADC clock cycles aft er t he sta rt of a norma l con ver-

sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is

complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conver sion

mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new

conversion will be initiated on the first rising ADC clock edge.

When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures

a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold

takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi-

tional CPU clock cycles are used for synchr onization logic.

7-BIT ADC PRESCALER

ADC CLOCK SOURCE

ADPS0

ADPS1

ADPS2

CK/128

CK/2

CK/4

CK/8

CK/16

CK/32

CK/64

Reset

DEN

TART

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In Free Running mode, a new conversion will be started immediately after the conversion com-

pletes, while ADSC remains high. For a summary of conversion times, see Table 23-1 on page

256.

Figure 23-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)

Figure 23-5. ADC Timing Diagram, Single Conversion

Figure 23-6. ADC Timing Diagram, Auto Triggered Conversion

Sign and MSB of Result

LSB of Result

ADC Clock

ADSC

Sample & Hold

ADIF

ADCH

ADCL

Cycle Number

ADEN

1212

13 14 15 16 17 18 19 20 21 22 23 24 25 1 2

First Conversion Next

Conversion

MUX and REFS

Update

MUX and REFS

Update

Conversion

Complete

123456789 10 11 12 13

Sign and MSB of Result

LSB of Result

ADC Clock

ADSC

ADIF

ADCH

ADCL

Cycle Number 12

One Conversion Next Conversion

Sample & Hold

MUX and REFS

Update

Conversion

Complete MUX and REFS

Update

1 2 3 4 5 6 7 8 910 11 12 13

Sign and MSB of Result

LSB of Result

ADC Clock

Trigger

Source

ADIF

ADCH

ADCL

Cycle Number 12

One Conversion Next Conversion

Conversion

Complete

Prescaler

Reset

ADATE

Prescaler

Reset

Sample &

Hold

MUX and REFS

Update

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Figure 23-7. ADC Timing Diagram, Free Running Conversion

23.5 Changing Channel or Reference Selection

The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary

selection only takes place at a safe point during the conversion. The channel and reference

selection is continu ously updated until a conve rsion is started. Once the conver sion starts, the

channel and reference se lection is locked to e nsure a sufficient sampling t ime for the ADC. Co n-

tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in

ADCSRA is set). Note tha t the conversion starts on the following rising ADC clock edge after

ADSC is written. The user is thus advised not to write new channel or refe rence select ion values

to ADMUX until one ADC clock cycle after ADSC is written.

If Auto Triggering is used, the exact tim e of the triggering event can be indeterministic. Special

care must be taken when updating the ADMUX Register, in order to control which conversion

will be affected by the new settings.

If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the

ADMUX Register is changed in this period, the user cannot te ll if the next conversion is based

on the old or the new settings. ADMUX can be safely updated in the following ways:

a. When ADATE or ADEN is cleared.

b. During conversion, min imum one ADC clock cycle after the trigger event.

c. After a conversion, before the I nterrupt Flag used as trigger source is cleared.

When updating ADMUX in one of these conditions, the new settings will affect the next ADC

conversion.

Table 23-1. ADC Conversion Time

Condition Sample & Hold

(Cycles from Start of Conversion) Conversion Time

(Cycles)

First conversion 13.5 25

Normal conv ersions, single ended 1.5 13

Auto Triggered conver si o ns 2 13.5

11 12 13

Sign and MSB of Result

LSB of Result

DC Clock

DSC

DIF

DCH

DCL

ycle Number 12

One Conversion Next Conversion

Conversion

Complete Sample & Ho

MUX and REFS

Update

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23.5.1 ADC Input Channels

When changing channel selections, the user should observe the following guidelines to ensure

that the correct channel is selected:

In Single Conversion mode, always select the chann el before sta rting the conversion. The chan-

nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the

simplest method is t o wa it for the co nversio n to complete b efore cha nging the ch annel sele ction.

In Free Running mode, always select the channel before starting the first conversion. The chan-

nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the

simplest method is to wait for the first conversion to complete, and then change the cha nnel

selection. Since the next conversion has already started automatically, the next result will reflect

the previous channel selection. Subsequent conversions will reflect the new channel selection.

23.5.2 ADC Voltage Reference

The referenc e voltage for the ADC (VREF) indicates the conversion range for the ADC. Single

ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as

either AVCC, internal 1.1V reference, or external AREF pin.

AVCC is connected to the ADC thro ugh a passive switch. The internal 1.1V refe rence is gener-

ated from the internal bandgap reference (VBG) through an internal amplifier. In either case, the

external AREF pin is directly connected to the ADC, and the reference voltage can be made

more immune to noise by connecting a capacitor between the AREF pin and gro und. VREF can

also be measured at th e AREF pin with a high impedance vo ltmeter. Note that VREF is a high

impedance source, and only a capacitive load should be connected in a system.

If the user has a fixed volt age source connect ed to the AREF pin, the user ma y not use the oth er

reference voltage options in the application, as they will be shorted to the external voltage. If no

external voltage is applied to the AREF pin, the user may switch between AVCC and 1.1V as ref-

erence selection. The first ADC conversion result after switching reference voltage source may

be inaccurate, an d th e user is advised to discard this resu lt.

23.6 ADC Noise Canceler

The ADC features a noise canceler that enables conversion during sleep mode to reduce noise

induced from the CPU core and o ther I/O pe ripherals. The noise ca nceler can be used with ADC

Noise Reduc tion an d Id le m ode. To m ake use of th is fe atur e, th e fo llowing proce dur e sh ould b e

used:

a. Make sure that the ADC is enabled and is not busy converting. Single Conversion

mode must be select ed and the ADC conv ersion complete interrupt must be enab led.

b. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion

once the CPU has been halted.

c. If no other interrupts occur before the ADC conversion completes, the ADC interrupt

will wak e up the CPU and e x ecute the ADC Con v ersion Complete interrupt routine. If

another interrupt wakes up the CPU before the ADC conversion is complete, that

interrupt will be ex ecuted, and an ADC Conv ersion Complete interrupt request will be

generated when the ADC conv ersion completes. The CPU will remain in active mode

until a new sleep command is executed.

Note that the ADC will not be automatically turned off when entering other sleep modes than Idle

mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter-

ing such sleep modes to avoid excessive power consumption.

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23.6.1 Analog Input Circuitry

The analog input circuitry for single ended channels is illustrated in Figure 23-8. An ana log

source applied to ADCn is subjecte d to the pin ca pacitance and inp ut leakage of that pin, re gard-

less of whether that channel is selected as input for the ADC. When the channel is selected, the

source must dr ive the S/H capacitor th rough the series re sistance (combined resistance in the

input path).

The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or

less. If such a source is used, the samp ling time wi ll be n egligible . I f a sour ce with higher impe d-

ance is used, the sampling time will depend on how long time the source needs to charge the

S/H capacitor, with can vary widely. The user is recommended to only use low impedance

sources with slowly varying signals, since this minimizes t he r equ i re d ch ar ge t ra ns fe r t o th e S/H

capacitor.

Signal components higher than the Nyquist frequency (fADC/2) should not be present for either

kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised

to remove high frequency components with a low-pass filter before applying the signals as

inputs to the ADC.

Figure 23-8. Analog Input Circuitry

23.6.2 Analog Noise Canceling Techniques

Digital circuitry inside and outside the device generates EMI which might affect the accuracy of

analog measurements. If conversion accuracy is critical, the noise level can be reduced by

applying the following techniques:

a. Keep analog sig nal paths as short as possible. M ak e sure analog t racks run ov er the

analog ground plane, and keep them well away from high-speed switching digital

tracks.

b. The AVCC pin on the device should be connected to the digita l VCC supply v oltage via

an LC network as shown in Figu re 23-9.

c. Us e the ADC no ise ca nc ele r fu nct i on to re du ce indu ce d no ise from th e CPU.

d. If an y ADC [3..0] p ort pins are used as digital out puts , it is essential that the se do no t

switch while a conversion is in progress. However, using the 2-wire Interface (ADC4

ADCn

IIH

1..100 kΩ

CS/H= 14 pF

VCC/2

IIL

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and ADC5) will only affe ct the conv ersion on ADC4 and ADC5 and not the other ADC

channels.

Figure 23-9. ADC Power Connections

23.6.3 ADC Accuracy Definitions

An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps

(LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.

Several parameters describe the deviation from the ideal behavior:

• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at

0.5 LSB). Ideal value: 0 LSB.

GND

VCC

PC5 (ADC5/SCL)

PC4 (ADC4/SDA)

PC3 (ADC3)

PC2 (ADC2)

PC1 (ADC1)

PC0 (ADC0)

ADC7

GND

AREF

AVCC

ADC6

PB5

10µH

100nF Analog Ground Plane

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Figure 23-10. Offset Error

• Gain error: After adjusting fo r offset, the gain error is f ound as the devia tion of the last transition

(0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0

LSB

Figure 23-11. Gain Error

• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum

deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0

LSB.

Output Code

REF

Input Voltage

Ideal ADC

Actual ADC

Offset

Error

Output Code

VREF Input Voltage

Ideal ADC

Actual ADC

Gain

Error

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Figure 23-12. Integral Non-linearity (INL)

• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval

between two adjacent tr ansitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.

Figure 23-13. Differential Non-linearity (DNL)

• Quantization Error: Due to the quantization of the inp ut v olta ge into a finite n umber of co des , a

range of input voltages (1 LSB wide) will code to the same value. Always ±0.5 LSB.

• Absolute accuracy: Th e maximum deviation of an actual (unadjusted) transition compared to

an ideal transition for any code. This is the compound effect of offset, gain error, diff erential

error, non-linearity, and quantization error. Ideal value: ±0.5 LSB.

Output Code

REF

Input Voltage

Ideal ADC

Actual ADC

INL

Output Code

0x3FF

0x000

0VREF Input Voltage

DNL

1 LSB

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23.7 ADC Conversion Result

After the conversion is complete (ADIF is high), the conversion result can be found in the ADC

Result Registers (ADCL, ADCH).

For single ended conversion, the result is

where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see

Table 23-3 on page 263 an d Table 23-4 on page 264). 0x 000 represents analog ground, and

0x3FF represents the selected reference voltage minus one LSB.

23.8 Temperature Measurement

The temperature measurement is based on an on-chip temperature sensor that is coupled to a

single ended ADC8 chann el. Selecting t he ADC8 ch annel by writ ing the MUX3..0 bits in ADMUX

also be selected for the ADC voltage reference source in the temperature sensor measurement.

When the temperature sensor is en abled, the ADC converter can be used in single conversion

mode to measure the voltage over the temperature sensor .

The measured voltage has a linear relation ship to the temperature as described in Table 23-2.

The voltage sensitivity is approximately 1 mV/°C and the accuracy of the temperature measure-

ment is +/- 10°C.

The values described in Ta ble 23-2 are typical values. However, due to the process variation the

temperature sensor output voltage varies from one chip to another. To be capable of achieving

more accurate results the temperature measurement can be calibrated in the application soft-

ware. The software calibration requires that a calibration value is measured and stored in a

be done utilizing the formula:

T = { [(ADCH << 8) | ADCL] - TOS} / k

where ADCn are the ADC data registers, k is a fixed coefficient and TOS is the temperature sen-

sor offset value determined and stored into EEPROM as a part of the production test.

ADC VIN 1024⋅

VREF

--------------------------=

Table 23-2. Temperature vs. Sensor Output Voltage (Typical Case)

Temperature / °C-45°C+25°C+85°C

Voltage / mV 242 mV 314 mV 380 mV

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23.9 Register Description

23.9.1 ADMUX – ADC Multiplexer Selection Register

• Bit 7:6 – REFS1:0 : Reference Selection Bits

These bits select the voltage reference for the ADC, as shown in Table 23-3. If these b its are

changed during a conversion, the change will not go in effect until this conversion is complete

(ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external

reference voltage is being applied to the AREF pin.

• Bit 5 – ADLAR: ADC Left Adjust Result

The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.

Write one to ADL AR to left adjust the resu lt. Oth erwise, the r esult is ri ght adju sted. Changing t he

ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-

sions. For a complet e description of this bit, see ”ADCL and ADCH – The ADC Data Register” on

page 266.

• Bit 4 – Res: Reserved Bit

This bit is an unused bit in the ATmega48P/88P/168P/328P, and will always read as zero.

• Bits 3:0 – MUX3:0: Analog Channel Selection Bits

The value of these bits selects which analog inputs are connected to the ADC. See Table 23-4

for details. If these bits are changed during a conversion, the change will not go in effect until this

conversion is complete (ADIF in ADCSRA is set).

Bit 76543210

(0x7C) REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 ADMUX

Read/Write R/W R/W R/W R R/W R/W R/W R/W

Initial Value00000000

Table 23-3. Voltage Reference Selections for ADC

REFS1 REFS0 Voltage Reference Selection

0 0 AREF, Inter nal Vref turned off

AVCC with external capacitor at AREF pin

10Reserved

1 1 Inte rnal 1.1V Voltage Reference with external capacitor at AREF pin

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Note: 1. For Temperature Sensor.

23.9.2 ADCSRA – ADC Control and Status Register A

• Bit 7 – ADEN: ADC Enable

Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the

ADC off while a conversion is in progress, will terminate this conversion.

• Bit 6 – ADSC: ADC Start Conversion

In Single Conversion mod e, write this bit t o one to start ea ch conversion. In Free Running mode,

write this bit to one to st art th e first conversion. Th e first conversion af ter ADSC ha s been writt en

after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,

will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-

tion of the ADC.

ADSC will read as one as long as a conversion is in progress. When the conversion is complete,

it returns to zero. Writing zero to this bit has no effect.

Table 23-4. Input Channel Selections

MUX3..0 Single Ende d Inp ut

0000 ADC0

0001 ADC1

0010 ADC2

0011 ADC3

0100 ADC4

0101 ADC5

0110 ADC6

0111 ADC7

1000 ADC8(1)

1001 (reserved)

1010 (reserved)

1011 (reserved)

1100 (reserved)

1101 (reserved)

1110 1.1V (VBG)

1111 0V (GND)

Bit 76543210

(0x7A) ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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• Bit 5 – ADATE: ADC A uto Trigger Enable

When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-

version on a positive e dge of the select ed trigger signal. The trigger sou rce is selected by setting

the ADC Trigger Select bits, ADTS in ADCSRB.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set when an ADC conversion completes and the Data Re gisters are updated. The

ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.

ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alter-

natively, ADIF is cleared by writing a logical one to the fl ag. Beware that if doing a Read-Modify-

Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI

instructions ar e used.

• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is wr itte n to on e a n d t he I- bit in SREG is set, the ADC Conversion Complete Inter-

rupt is activated.

• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

These bits determine the division f actor be twee n the syst em clock frequen cy and th e inpu t clock

to the ADC.

Table 23-5. ADC Prescaler Selections

ADPS2 ADPS1 ADPS0 Division Factor

000 2

001 2

010 4

011 8

100 16

101 32

110 64

111 128

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23.9.3 ADCL and ADCH – The ADC Data Register

23.9.3.1 ADLAR = 0

23.9.3.2 ADLAR = 1

When an ADC conversion is complete, the result is found in these two registers.

When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if

the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH.

The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from

the registers. If ADLA R is set, the result is left adjusted. If ADLAR is cleared (default), th e result

is right adjusted.

• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in ”ADC Conversion Result” on

page 262.

23.9.4 ADCSRB – ADC Control and Status Register B

• Bit 7, 5:3 – Res: Rese rved Bits

These bits are reser ved for future use. To ensure compatib ility with future devices, these bist

must be written to zero when ADCSRB is written.

• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source

If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger

an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion

will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trig-

ger source that is cleared to a trigger source that is set, will generate a positive edge on the

Bit 151413121110 9 8

(0x79) ––––––ADC9 ADC8 ADCH

(0x78) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL

76543210

Read/WriteRRRRRRRR

RRRRRRRR

Initial Value00000000

00000000

Bit 151413121110 9 8

(0x79) ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH

(0x78) ADC1 ADC0 – – ––––ADCL

76543210

Read/WriteRRRRRRRR

RRRRRRRR

Initial Value00000000

00000000

Bit 76543210

(0x7B) – ACME – – – ADTS2 ADTS1 ADTS0 ADCSRB

Read/Write R R/W R R R R/W R/W R/W

Initial Value00000000

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trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running

mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.

23.9.5 DIDR0 – Digital Input Disable Register 0

• Bits 7:6 – Res: Reserved Bits

These bits are reser ved for future use. To ensure compatib ility with future devices, these bits

must be written to zero when DIDR0 is written.

• Bit 5:0 – ADC5D ..ADC0D: ADC5..0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-

abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an

analog signal is applied to the ADC5..0 pin and the digital input from this pin is not needed, this

bit should be written logic one to r educe power consumption in the digital input buffer.

Note that ADC pins ADC7 and ADC6 do not have digital input buffers, and therefore do not

require Digital Input Disable bits.

Table 23-6. ADC Auto Trigger Source Selections

ADTS2 ADTS1 ADTS0 Trigger Source

0 0 0 Free Running mode

0 0 1 Analog Comparator

0 1 0 External Interrupt Request 0

0 1 1 Timer/Counter0 Compare Match A

1 0 0 Timer/Counter0 Overflow

1 0 1 Timer/Counter1 Compare Match B

1 1 0 Timer/Counter1 Overflow

1 1 1 Timer/Counter1 Capture Event

Bit 76543210

(0x7E) – – ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D DIDR0

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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24. debugWIRE On-chip Debug System

24.1 Features •Complete Program Flow Control

•Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin

•Real-time Operation

•Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs)

•Unlimited Number of Program Break Points (Using Software Break Points)

•Non-intrusive Operation

•Electrical Characteristics Identical to Real Device

•A u tomatic Configuration System

•High-Speed Oper ation

•Programming of Non-volatile Memories

24.2 Overview The debugWIRE On-chip debug system uses a One-wire, bi-directiona l interface to control the

program flow, execute AVR instructions in the CPU and to program the different non-volatile

memories.

24.3 Physical Interface

When the deb ugWIRE Enable (DW EN) Fuse is progr ammed and Loc k bits are unprog rammed,

the debugWIRE system within the target device is activated. The RESET port pin is configured

as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the commu-

nication gateway between target and emulator.

Figure 24-1. The debugWIRE Setup

Figure 24-1 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator

connector. The system clock is not affected by debugWIRE and will always be the clock source

selected by the CKSEL Fuses.

GND

dW(RESET)

VCC

1.8 - 5.5

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When designing a system where debugWIRE will be used, the following observations must be

made for correct operation:

• Pull-up resistors on the dW/(RESET) line must not be smaller than 10kΩ. The pull-up resistor

is not required for debugWIRE functionality.

• Connecting the RESET pin directly to VCC will not work.

• Capacitors connected to the RESET pin must be disconnected when using debugWire.

• All external reset sources must be disconnected.

24.4 Software Break Points

debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a

Break Point in AVR Studio® will insert a BREAK instruction in the Program memory. The instruc-

tion replaced by the BREAK instruction will be stored. When program execution is continued, the

stored instruction will be executed before continuing from the Program memory. A break can be

inserted manually by putting the BREAK instruction in the program.

The Flash must be re-prog rammed each time a Break Point is changed. This is automatically

handled by AVR Studio through the debugWIRE interface. The use of Break Points will therefore

reduce the Fl ash Data ret ention. Devices used for d ebugging p urposes sho uld not b e shipped to

end customers.

24.5 Limitations of debugWIRE

The debugWIRE communication pin (dW) is physically located on the same pin as External

Reset (RESET). An External Reset source is therefore not supported when the debugWIRE is

enabled.

A programmed DWEN Fuse enables some parts of the clock syst em to be running in all sleep

modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse should

be disabled when debugWir e is not used.

24.6 Register Description

The following sectio n descr ib es th e re gisters used with the de bu g Wire .

24.6.1 DWDR – debugWire Data Register

The DWDR Register provides a communicatio n channel from the running program in the MCU

to the debugger. This register is only acce ssible by the debugWIRE and can therefore not be

used as a general purpo se register in the norma l operations.

Bit 76543210

DWDR[7:0] DWDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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25. Self-Programming the Flash, ATmega48P

25.1 Overview In ATmega48P, there is no Read- While-Write support, and no separate Boot Loader Section.

The SPM instruction can be executed from the entire Flash.

The device provides a Self-Programming mechanism for downloading and uploading program

code by the MCU itself. The Self-Programming can use any available data interface and associ-

ated protocol to read code and write (program) that code into the Program memory.

The Program memory is updated in a page by page fashion. Before programming a page with

the data stored in the temporary page buffer, the page must be erased. The temporary page

buffer is filled one word at a time using SPM and the buffer can be filled either before the Page

Erase command or between a Page Erase and a Page Writ e operation:

Alternative 1, fill the buffer before a Page Erase

• Fill temporary page buffer

• Perform a P age Erase

• Perform a Page Write

Alternative 2, fill the buffer after Page Erase

• Perform a P age Erase

• Fill temporary page buffer

• Perform a Page Write

If only a part of t he page needs to be changed, the rest of the page must be stored (for example

in the temporary page buf fer) befo re the erase, and then be re-written . When using alternat ive 1,

the Boot Loader pr ovides an effe ctive Rea d- Modify- Wr ite fe at ure which allo ws t he use r soft ware

to first read the page, do the necessary changes, and then write back the modified data. If alter-

native 2 is used, it is not p ossible to read the old data while loading since the page is already

erased. The temporary page buffer can be accessed in a random sequence. It is essential that

the page addre ss used in both the Page Er ase and Page Write operation is ad dressing the same

page.

25.1.1 Performing Page Erase by SPM

To execute Page Erase, set up the address in the Z-pointer, write “00000011” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

The page address must be written to PCPAGE in the Z-register. Othe r bits in the Z-pointer will

be ignored during this operation.

• The CPU is halted during the Page Erase operation.

25.1.2 Filling the Temporary Buff er (Page Loading)

To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write

“00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The

content of PCWORD in the Z-register is used to address the data in the temporary buffer. The

temporary buffer will auto-erase after a Page Write operation or by writing the RWWSRE bit in

SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than

one time to each addr ess without erasing the temporary buffer.

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If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be

lost.

25.1.3 Performing a Page Write

To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPM CSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to

zero during this operation.

• The CPU is halted during the Page Write operation.

25.2 Addressing the Flash During Self-Programming

The Z-pointer is used to address the SPM commands.

Since the Flash is organized in pages (see Table 27-11 on page 299), the Program Counter can

be treated as havin g two different sections. One sect ion, consisting of the least signif icant bits, is

addressing the words within a page, while the most significant bits are addressing the pages.

This is shown in Figure 26-3 on page 283. Note that the Page Erase and Page Write operations

are addressed independently. Therefore it is of major importance that the software addresses

the same page in both the Page Erase and Page Write operation.

The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the

Flash byte-b y-b yte, also the LSB (bit Z0) of th e Z- po in te r is used .

Figure 25-1. Addressing the Flash During SPM(1)

Note: 1. The different variables used in Figure 26-3 are listed in Table 27-11 on page 299.

Bit 151413121110 9 8

ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8

ZL (R30) Z7Z6Z5Z4Z3Z2Z1Z0

76543210

PROGRAM MEMORY

0115

Z - REGISTER

BIT

ZPAGEMSB

WORD ADDRESS

WITHIN A PAGE

PAGE ADDRESS

WITHIN THE FLASH

ZPCMSB

INSTRUCTION WORD

PAGE PCWORD[PAGEMSB:0]:

PAGEEND

PAGE

PCWORDPCPAGE

PCMSB PAGEMSB

PROGRAM

COUNTER

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25.2.1 EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the

Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It

is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies

that the bit is cleare d before writing to the SPMCSR Register.

25.2.2 Reading the Fuse and Lock Bits from Software

It is possib le to read bo th the Fuse and Loc k bits from so ftware. To read t he Lock bits, lo ad the

Z-pointer with 0x0001 and set the BL BSET and SELFPRGEN bits in SPMCSR. When an LPM

instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are set

in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET

and SELFPRGEN bits will auto-clear upon comple tion of reading the Lock bits or if no LPM

instruction is executed within three CPU cycles or no SPM instruction is executed within four

CPU cycles. When BLBSET and SELFPRGEN are cleared, LPM will work as described in the

Instruction set Manual.

The algorithm for reading the Fuse Low byte is similar to the one described above for reading

the Lock bits. To read th e Fuse Low byte, load the Z-pointer with 0 x0000 and set the BLBSET

and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles

after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low byte

(FLB) will be loaded in the destination register as shown below.See Table 27-5 on page 296 for

a detailed description and mapping of the Fuse Low byte.

Similarly, when reading the Fuse High byte (FHB), load 0x0003 in the Z-pointer. When an LPM

instruction is executed within thre e cycles after the BLBSET and SELFPRGEN bits are set in the

SPMCSR, the value of the Fuse High byte will be loaded in the destination register as sho wn

below. See Table 27-4 on page 295 for detailed description an d mapping of the Extended F use

byte.

Similarly, when reading the Extended Fuse byte (EFB), load 0x0002 in the Z-pointer. Wh en an

LPM instruction is executed within three cycles after the BLBSET and SELFPRGEN bits are set

in the SPMCSR, the value of the Extended Fuse byte will be loaded in the destination register as

shown below. See Table 2 7-5 on page 296 for detailed description and mapping of the Extended

Fuse byte.

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are

unprogrammed, will be read as one.

Bit 76543210

Rd ––––––LB2LB1

Bit 76543210

Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0

Bit 76543210

Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0

Bit 76543210

Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0

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25.2.3 Preventing Flash Corruption

During periods of low VCC, the Flash program can be corrupted because the supply voltage is

too low for the CPU and the Flash to operate properly. These issues are the same as for board

level systems using the Flash, and th e same design solutions should be applied.

A Flash program co rr up tion can be cau sed b y two situ a tions when th e voltag e is too low. F irst , a

regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,

the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions

is too low.

Flash corruption can easily be avoided by following these design recommendations (one is

sufficient):

1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done b y e nab ling the int ernal Brown-out Detecto r (BOD) if the op era ting volt-

age matches the de tection le v el. If not, an e xternal low VCC rese t protection circuit can be

used. If a reset occurs while a write operation is in progress, the write operation will be

completed provided that the power supply voltage is sufficient.

2. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will pre-

vent the CPU from attempting to decod e and execute instructions, effectively protecting

the SPMCSR Register and thus the Flash from unintentional writes .

25.2.4 Programming Time for Flash when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 26-5 shows the typical pro-

gramming time for Flash accesses fr om the CPU.

Note: 1. Minimum and maximum programming time is per individual operation.

Table 25-1. SPM Programming Time(1)

Symbol Min Programming Time Max Programming Time

Flash write (Page Erase, Page Write, and

write Lock bits by SPM) 3.7 ms 4.5 ms

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25.2.5 Simple Assembly Code Example for a Boot Loader

Note that the RWWSB bit will always be read as zero in ATmega48P. Nevertheless, it is recom-

mended to check this bit as shown in the code example, to ensure compatibility with devices

supporting Read-While-Write.

;-the routine writes one page of data from RAM to Flash

; the first data location in RAM is pointed to by the Y pointer

; the first data location in Flash is pointed to by the Z-pointer

;-error handling is not included

;-the routine must be placed inside the Boot space

; (at least the Do_spm sub routine). Only code inside NRWW section can

; be read during Self-Programming (Page Erase and Page Write).

;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),

; loophi (r25), spmcrval (r20)

; storing and restoring of registers is not included in the routine

; register usage can be optimized at the expense of code size

;-It is assumed that either the interrupt table is moved to the Boot

; loader section or that the interrupts are disabled.

.equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words

.org SMALLBOOTSTART

Write_page:

; Page Erase

ldi spmcrval, (1<<PGERS) | (1<<SELFPRGEN)

rcallDo_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN)

rcallDo_spm

; transfer data from RAM to Flash page buffer

ldi looplo, low(PAGESIZEB) ;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

Wrloop:

ld r0, Y+

ld r1, Y+

ldi spmcrval, (1<<SELFPRGEN)

rcallDo_spm

adiw ZH:ZL, 2

sbiw loophi:looplo, 2 ;use subi for PAGESIZEB<=256

brne Wrloop

; execute Page Write

subi ZL, low(PAGESIZEB) ;restore pointer

sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256

ldi spmcrval, (1<<PGWRT) | (1<<SELFPRGEN)

rcallDo_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN)

rcallDo_spm

; read back and check, optional

ldi looplo, low(PAGESIZEB) ;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

subi YL, low(PAGESIZEB) ;restore pointer

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sbci YH, high(PAGESIZEB)

Rdloop:

lpm r0, Z+

ld r1, Y+

cpse r0, r1

rjmp Error

sbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256

brne Rdloop

; return to RWW section

; verify that RWW section is safe to read

Return:

in temp1, SPMCSR

sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet

ret

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN)

rcallDo_spm

rjmp Return

Do_spm:

; check for previous SPM complete

Wait_spm:

in temp1, SPMCSR

sbrc temp1, SELFPRGEN

rjmp Wait_spm

; input: spmcrval determines SPM action

; disable interrupts if enabled, store status

in temp2, SREG

cli

; check that no EEPROM write access is present

Wait_ee:

sbic EECR, EEPE

rjmp Wait_ee

; SPM timed sequence

out SPMCSR, spmcrval

spm

; restore SREG (to enable interrupts if originally enabled)

out SREG, temp2

ret

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25.3 Register Description’

25.3.1 SPMCSR – Store Progra m Memory Control and Status Register

The Store Progr am Memory Contro l and Status Regist er contains the co ntrol bits nee ded to con-

trol the Program memory operations.

• Bit 7 – SPMIE: SPM Interrupt Enable

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM

ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SELF-

PRGEN bit in the SPMCSR Register is cleared. The interrupt will not be generated during

EEPROM write or SPM.

• Bit 6 – RWWSB: Read-While-Write Section Busy

This bit is for compatibility with devices supporting R ead-While-Write. It will alw ays read as zero

in ATmega48P.

• Bit 5 – Res: Reserved Bit

This bit is a reserved bit in the ATmega48P/88P/168P/328P and will always read as zero.

• Bit 4 – RWWSRE: Read-While-Write Section Read Enable

The functionality of t his bit in AT meg a48P is a su bset of t he f uncti on ality in AT mega88 P/1 68P. I f

the RWWSRE bit is written while filling the temporary page buffer, the temporary page buffer will

be cleared and the data will be lost.

• Bit 3 – BLBSET: Boot Lock Bit Set

The functionality of this bit in ATmega48P is a subset of the functionality in ATmega88P/168P.

An LPM instruction within three cycles after BLBSET and SE LFPRGEN are set in the SPMCSR

destination register. See ”Reading the Fuse and Lock Bits from Software” on page 272 for

details.

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four

clock cycles executes Page Write, with the data stored in the temporary buffer. The page

address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The

PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed

within four clock cycles. The CPU is halt ed during the entire Page Write operat ion.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four

clock cycles executes Page Erase. The page address is taken from the high part of the Z-

pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a

Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted dur-

ing the entire Page Write operation.

Bit 7 6 5 4 3 2 1 0

0x37 (0x57) SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SELFPRGEN SPMCSR

Read/Write R/W R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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• Bit 0 – SELFPRGEN: Self Programming Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one together with

either RWWSRE, BLBSET, PGWRT, or PGE RS, the following SPM instruction will have a spe-

cial meaning, see description above. If only SELFPRGEN is written, the following SPM

instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer.

The LSB of the Z-pointer is ignored. The SELFPRGEN bit will auto-clear upon completion of an

SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase

and Page Write, the SELFPRGEN bit remains high until the operation is completed.

Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower

five bits will have no effect.

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26. Boot Loader Support – Read-While-Write Self-Programming, ATmega88P,

ATmega168P and ATmega328P

26.1 Features •Read-While-Write Self-Programming

•Flexible Boot Memory Size

•High Security (Separate Boot Lock Bits for a Flexible Protection)

•Separate Fuse to Select Reset Vector

•Optimized P age(1) Size

•Code Efficient Algorithm

•Efficient Read-Modify-Write Support

Note: 1. A page is a section in the Flash consisting of several bytes (see Table 27-11 on page 299)

used during pr ogramming. The page organ ization does not affect normal operation.

26.2 Overview In ATmega88P, ATmega168P and ATmega328P, the Boot Loader Support provides a real

Read-While-Write Self-Programming mechanism for downloading and uploading program code

by the MCU itself. This featur e allows flexible application software updates controlled by the

MCU using a Flash-reside nt Boo t Loade r p rogr am. T he Boot Load er pr ogra m can use any avail-

able data interface and associated protocol to read code and write (program) that code into the

Flash memory, or read the code from the program memory. T he program code within the Boot

Loader section has the capability to write into the entire Flash, including the Boot Loader mem-

ory. The Boot Loader can thus ev en modi fy itself, and it can also erase itself fr om t he code if the

feature is not needed anymore. The size of the Boot Loader memory is configurable with fuses

and the Boot Loader has two separate sets of Boot Lock bits which can be set independently.

This gives the user a unique flexibility to select different levels of protection.

26.3 Application and Boot Loader Flash Sections

The Flash memory is organized in two main sections, the Application section and the Boot

Loader section (see Figure 26-2). The size of the different sections is configured by the

BOOTSZ Fuses as shown in Table 26- 6 on page 289 and Figure 26-2. These two sections can

have different level of protection since they have different sets of Lock bits.

26.3.1 Application Section

The Application section is the section of the Flash that is used for storing the application code.

The protection level for the Application section can be selected by the applicat ion Boot Lock bits

(Boot Lock bits 0), see Table 26-2 on page 282. The Application section can never store any

Boot Loader code sin ce the SPM instruction is disab led when executed from the Application

section.

26.3.2 BLS – Boot Loader Section

While the Application section is used for storing the application code, the The Boot Loader soft-

ware must be located in the BLS since the SPM instruction can initiate a programming when

executing from the BLS only. The SPM instruction can access the entire Flash, including the

BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader

Lock bits (Boot Lock bits 1), see Table 26-3 on page 282.

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26.4 Read-While-Write and No Read-While-Write Flash Sections

Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader soft-

ware update is depende nt on which address that is being progr ammed. In addition to the two

sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also

divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-

Write (NRWW) section. The limit between the RWW- and NRWW sections is given in Table 26-

7 on page 289 and Figure 26-2 on page 281. The main difference between the two sections is:

• When erasing or writing a page located inside the RWW section, the NRWW section can be

read during the operation.

• When erasing or writing a page located inside the NR WW section , the CPU is halted during the

entire operation.

Note that the user software ca n never read any code th at is located in side the RWW section dur-

ing a Boot Loader software operation. The syntax “Read-While-Write section” refers to which

section that is being programmed (erased or written), not which section that actually is being

read during a Boot Loader software update.

26.4.1 RWW – Read-While-Write Section

If a Boot Loader software update is programming a page inside the RWW section, it is possible

to read code from the Flash, but only code that is located in the NRWW section. During an on-

going programming, the software must ensure that the RWW section never is being read. If the

user software is trying to read code that is located inside the RWW section (i.e., by a

call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown

state. To avoid this, the interrupts should either be disabled or moved to the Boot Loader sec-

tion. The Boot Loader section is always located in the NRWW section. The RWW Section Busy

bit (RWWSB) in the Store Program Memory Control and Status Register (SPMCSR) will be read

as logical one as long as the RWW section is blocked for reading. After a programming is com-

pleted, the RWWSB must be cleared by software before reading code located in the RWW

section. See Section “26.9.1 ” on page 292. for details on how to clear RWWSB.

26.4.2 NRWW – No Read-While-Write Section

The code located in the NRWW section can be read when the Boot Loader software is updating

a page in the RWW section. When the Boot Loader code updates the NRWW section, the CPU

is halted during the entire Page Erase or Page Write operation.

Table 26-1. Read-While-Write Features

Which Section does the Z-

pointer Address during

the Programming?

Which Section can be

read during

Programming? CPU Halted? Read-While-Write

Supported?

RWW Section NRWW Section No Yes

NRWW Section None Yes No

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Figure 26-1. Read-While-Write vs. No Read-While-Write

Read-While-Write

(RWW) Section

No Read-While-Write

(NRWW) Section

Z-pointer

Addresses RWW

Section

Z-pointer

Addresses NRWW

Section

CPU is Halted

During the Operation

Code Located in

NRWW Section

Can be Read During

the Operation

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Figure 26-2. Memory Sections

Note: 1. The parameters in the figure abov e are given in Table 26-6 on page 289.

26.5 Boot Loader Lock Bits

If no Boot Loader capability is needed, the entire Flash is available for application code. The

Boot Loader has two separ at e sets of Boot Lock bits which ca n be set indepen de ntly. This gives

the user a unique flexibility to select different levels of protection.

The user can select:

• To protect the entire Flash from a software update by the MCU.

• To protect onl y the Boot Loader Flash section from a software update by the MCU.

• To protect only the Application Flash section from a software update by the MCU.

• Allow software update in the entire Flash.

See Table 26-2 and Table 26-3 for further details. The Boot Lock bits can be set in software and

in Serial or Parallel Programming mode, but they can be cleared by a Chip Erase command

only. The general Write Lock (Lock Bit mod e 2) does not control the programming of the Flash

memory by SPM instruction. Similarly, the general Read/Write Lock (Lock Bit mode 1) does not

control reading nor writing by LPM/SPM, if it is attempted.

0x0000

Flashend

Program Memory

BOOTSZ = '11'

Application Flash Section

Boot Loader Flash Section Flashend

Program Memory

BOOTSZ = '10'

0x0000

Program Memory

BOOTSZ = '01'

Program Memory

BOOTSZ = '00'

Application Flash Section

Boot Loader Flash Section

0x0000

Flashend

Application Flash Section

Flashend

End RWW

Start NRWW

Application Flash Section

Boot Loader Flash Section

End RWW

Start NRWW

End RWW

Start NRWW

0x0000

End RWW, End Application

Start NRWW, Start Boot Loader

Application Flash SectionApplication Flash Section

Application Flash Section

Read-While-Write SectionNo Read-While-Write Section Read-While-Write SectionNo Read-While-Write Section

Read-While-Write SectionNo Read-While-Write SectionRead-While-Write SectionNo Read-While-Write Section

End Application

Start Boot Loader

End Application

Start Boot Loader

End Application

Start Boot Loader

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Note: 1. “1 ” means unprogrammed, “0” means programmed

26.6 Entering the Boot Loader Program

Entering the Boot Loader takes place by a jump or call from the application program. This may

be initiated by a trigge r such as a command received via USART, or SPI interface. Alternatively,

the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash

start address afte r a reset. In th is case, the Boot Loader is star ted after a reset. After the applica-

tion code is loaded, the program can start execut ing the application code. Note that the fuses

cannot be changed by the MCU itself. This means that once the Boot Reset Fuse is pro-

grammed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be

changed through the serial or parallel programming interface.

Note: 1. “1 ” means unprogrammed, “0” means programmed

Table 26-2. Boot Lock Bit0 Protection Modes (Ap plication Section)(1)

BLB0 Mode BLB02 BLB01 Protection

111

No restrictions for SPM or LPM accessing the Applic ation

section.

2 1 0 SPM is not allowed to write to the Application section.

300

SPM is not allowed to write to the Application section, and LPM

executing from the Boot Loader section is not allowed to read

from the Application section. If Interrupt Vectors are placed in

the Boot Loader section, interrupts are disabled while executing

from the Application section.

401

LPM executing from the Boot Loader section is not allowed to

read from the Application section. If Interrupt Vectors are placed

in the Boot Loader section, interrupts are disabled while

executing from the Application section.

Table 26-3. Boot Lock Bit1 Protection Modes ( Boot Loader Section)(1)

BLB1 Mode BLB12 BLB11 Protection

111

No restrictions for SPM or LPM accessing the Boot Loader

section.

2 1 0 SPM is not allowed to write to the Boot Loader section.

300

SPM is not allowed to write to the Boot Loader section, and LPM

executing from the Application section is not allowed to read

from the Boot Loader section. If Interrupt Vectors are placed in

the Application section, interrupts are disabled while executing

from the Boot Loader section.

401

LPM executing from the Application section is not allowed to

read from the Boot Loader section. If Interrupt Vectors are

placed in the Application section, interrupts are disabled while

executing from the Boot Loader section.

Table 26-4. Boot Reset Fuse(1)

BOOTRST Reset Address

1 Reset Vector = Application Reset (address 0x0000)

0 Reset Vector = Boot Loader Reset (see Table 26-6 on pa ge 289)

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26.7 Addressing the Flash During Self-Programming

The Z-pointer is used to address the SPM commands.

Since the Flash is organized in pages (see Table 27-11 on page 299), the Program Counter can

be treated as havin g two different sections. One sect ion, consisting of the least signif icant bits, is

addressing the words within a page, while the most significant bits are addressing the pages.

This is1 shown in Figure 26-3. Note that the Page Erase and Page Write operations are

addressed independently. Therefore it is of major importance that the Boot Loader software

addresses the same page in both the Page Erase and Pa ge Write operation. Once a program-

ming operation is initiated, the address is latched and the Z-pointer can be used for other

operations.

The only SPM operation that does no t use the Z-pointer is Setting the Boot Loader Lock bits.

The content of the Z-pointer is ignored and will have no effect on the operation. The LPM

instruction does also use the Z-pointer to store the address. Since this instruction addresses the

Flash byte-b y-b yte, also the LSB (bit Z0) of th e Z- po in te r is used .

Figure 26-3. Addressing the Flash During SPM(1)

Note: 1. The different variables used in Figure 26-3 are listed in Table 26-8 on page 289.

26.8 Self-Programming the Flash

The program memory is updated in a page by page fashion. Before programming a page with

the data stored in the temporary page buffer, the page must be erased. The temporary page

buffer is filled one word at a time using SPM and the buffer can be filled either before the Page

Erase command or between a Page Erase and a Page Writ e operation:

Bit 151413121110 9 8

ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8

ZL (R30) Z7Z6Z5Z4Z3Z2Z1Z0

76543210

PROGRAM MEMORY

0115

Z - REGISTER

BIT

ZPAGEMSB

WORD ADDRESS

WITHIN A PAGE

PAGE ADDRESS

WITHIN THE FLASH

ZPCMSB

INSTRUCTION WORD

PAGE PCWORD[PAGEMSB:0]:

PAGEEND

PAGE

PCWORDPCPAGE

PCMSB PAGEMSB

PROGRAM

COUNTER

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Alternative 1, fill the buffer before a Page Erase

• Fill temporary page buffer

• Perform a P age Erase

• Perform a Page Write

Alternative 2, fill the buffer after Page Erase

• Perform a P age Erase

• Fill temporary page buffer

• Perform a Page Write

If only a part of t he page needs to be changed, the rest of the page must be stored (for example

in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1,

the Boot Loader pr ovides an effe ctive Rea d- Modify- Wr ite fe at ure which allo ws t he use r soft ware

to first read the page, do the necessary changes, and then write back the modified data. If alter-

native 2 is used, it is not p ossible to read the old data while loading since the page is already

erased. The temporary page buffer can be accessed in a random sequence. It is essential that

the page addre ss used in both the Page Er ase and Page Write operation is ad dressing the same

page. See ”Simple Assembly Code Example for a Boot Loader” on page 287 for an assembly

code example.

26.8.1 Performing Page Erase by SPM

To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

The page address must be written to PCPAGE in the Z-register. Othe r bits in the Z-pointer will

be ignored during this operation.

• Page Erase to the RWW section: The NRWW section can be read during the Page Erase.

• Page Erase to the NRWW section: The CPU is halted during the operation.

26.8.2 Filling the Temporary Buff er (Page Loading)

To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write

“00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The

content of PCWORD in the Z-register is used to address the data in the temporary buffer. The

temporary buffer will auto-erase after a Page Write operation or by writing the RWWSRE bit in

SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than

one time to each addr ess without erasing the temporary buffer.

If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be

lost.

26.8.3 Performing a Page Write

To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to

zero during this operation.

• Page Write to the RWW section: The NRWW section can be read during the Page Write.

• Page Write to the NRWW section: The CPU is halted during the operation.

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26.8.4 Using the SPM Interrupt

If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the

SELFPRGEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of

polling the SPMCSR Register in software. When using the SPM interrupt, the Interrupt Vectors

should be moved to the BLS section to avoid that an interrupt is accessing the RWW section

when it is blocked for reading. How to move the interrupts is described in ”Interrupts” on page

58.

26.8.5 Consideration While Updating BLS

Special care must be taken if the user allows the Boot Loader section to be updated by leaving

Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the

entire Boot Loader, and further software updates might be impossible. If it is not necessary to

change the Boot Loader software itself, it is r ecommended to progra m the Boot Lock bit11 to

protect the Boot Loader software from any internal software changes.

26.8.6 Prevent Reading the RWW Section During Self-Programming

During Self-Programming (either Page Erase or Page Write), the RWW section is always

blocked for reading. The user software itself must prevent that this section is addressed during

the self programming operation. The RWWSB in the SPMCSR will be set as long as the RWW

section is busy. During Se lf-Pro grammin g the In terr upt Vect or t able should b e move d to the BLS

as described in ”Watchdog Timer” on page 51, or the interrupts must be disabled. Before

addressing the RWW section after the programming is completed, the user software must clear

the RWWSB by writing the RWWSRE. See ”Simple Assembly Code Example fo r a Boot Lo ader”

on page 287 for an example.

26.8.7 Setting the Boot Loader Lock Bits by SPM

To set the Boot Loader Lock bits and general Lock Bits, write the desired data to R0, write

“X0001001” to SPMCSR and execu te SPM within four clock cycles after writing SPMCSR.

See Table 26-2 and Table 26-3 for how the different settings of the Boot Loader bits affect the

Flash acces s .

If bits 5..0 in R0 are cleared (zero), the corresponding Lock bit will be programmed if an SPM

instruction is executed within four cycles after BLBSET and SELFPRGEN are set in SPMCSR.

The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to

load the Z-pointer with 0x0001 (same as used fo r reading t he lOck bits). For future compatibility it

is also recommended to set bits 7 and 6 in R0 to “1” when writing the Lock bits. When program-

ming the Lock bits the entire Flash can be read during the ope ration.

26.8.8 EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the

Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It

is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies

that the bit is cleare d before writing to the SPMCSR Register.

26.8.9 Reading the Fuse and Lock Bits from Software

It is possib le to read bo th the Fuse and Loc k bits from so ftware. To read t he Lock bits, lo ad the

Z-pointer with 0x0001 and set the BL BSET and SELFPRGEN bits in SPMCSR. When an LPM

Bit 76543210

R0 1 1 BLB12 BLB11 BLB02 BLB01 LB2 LB1

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instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are set

in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET

and SELFPRGEN bits will auto-clear upon comple tion of reading the Lock bits or if no LPM

instruction is executed within three CPU cycles or no SPM instruction is executed within four

CPU cycles. When BLBSET and SELFPRGEN are cleared, LPM will work as described in the

Instruction set Manual.

The algorithm for reading the Fuse Low byte is similar to the one described above for reading

the Lock bits. To read th e Fuse Low byte, load the Z-pointer with 0 x0000 and set the BLBSET

and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles

after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low byte

(FLB) will be loaded in the destination register as shown below. Refer to Table 27-5 on page 296

for a detailed description and mapping of the Fuse Low byte.

Similarly, when read ing the Fu se High byte, load 0 x000 3 in t he Z-p ointer . When an LPM instruc-

tion is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the

SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as

shown below. Refe r t o Tab le 2 7- 7 o n pa ge 297 for detailed description and mapping of the Fuse

High byte.

When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction

is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the SPMCSR,

the value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown

below. Refer to Table 27-4 on page 295 for detailed description and mapping of the Extended

Fuse byte.

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are

unprogrammed, will be read as one.

26.8.10 Preventi n g Fl as h Cor ru pt io n

During periods of low VCC, the Flash program can be corrupted because the supply voltage is

too low for the CPU and the Flash to operate properly. These issues are the same as for board

level systems using the Flash, and th e same design solutions should be applied.

A Flash program co rr up tion can be cau sed b y two situ a tions when th e voltag e is too low. F irst , a

regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,

the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions

is too low.

Flash corruption can easily be avoided by following these design recommendations (one is

sufficient):

Bit 76543210

Rd – – BLB12 BLB11 BLB02 BLB01 LB2 LB1

Bit 76543210

Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0

Bit 76543210

Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0

Bit 76543210

Rd – – – – EFB3 EFB2 EFB1 EFB0

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1. If there is no need f or a Boot Loader update in the system, progra m the Boot Loader Lock

bits to prevent any Boot Loader software updates.

2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done b y e nab ling the int ernal Brown-out Detecto r (BOD) if the op era ting volt-

age matches the de tection le v el. If not, an e xternal low VCC rese t protection circuit can be

used. If a reset occurs while a write operation is in progress, the write operation will be

completed provided that the power supply voltage is sufficient.

3. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will pre-

vent the CPU from attempting to decod e and execute instructions, effectively protecting

the SPMCSR Register and thus the Flash from unintentional writes .

26.8.11 Programming Time for Flash when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 26-5 shows the typical pro-

gramming time for Flash accesses fr om the CPU.

Note: 1. Minimum and maximum programming time is per individual operation.

26.8.12 Simple Assembly Code Example for a Boot Loader

;-the routine writes one page of data from RAM to Flash

; the first data location in RAM is pointed to by the Y pointer

; the first data location in Flash is pointed to by the Z-pointer

;-error handling is not included

;-the routine must be placed inside the Boot space

; (at least the Do_spm sub routine). Only code inside NRWW section can

; be read during Self-Programming (Page Erase and Page Write).

;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),

; loophi (r25), spmcrval (r20)

; storing and restoring of registers is not included in the routine

; register usage can be optimized at the expense of code size

;-It is assumed that either the interrupt table is moved to the Boot

; loader section or that the interrupts are disabled.

.equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words

.org SMALLBOOTSTART

Write_page:

; Page Erase

ldi spmcrval, (1<<PGERS) | (1<<SELFPRGEN)

call Do_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN)

call Do_spm

; transfer data from RAM to Flash page buffer

ldi looplo, low(PAGESIZEB) ;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

Wrloop:

ld r0, Y+

ld r1, Y+

ldi spmcrval, (1<<SELFPRGEN)

call Do_spm

Table 26-5. SPM Programming Time(1)

Symbol Min Programming Time Max Programming Time

Flash write (Page Erase, P age Write, and

write Lock bits by SPM) 3.7 ms 4.5 ms

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adiw ZH:ZL, 2

sbiw loophi:looplo, 2 ;use subi for PAGESIZEB<=256

brne Wrloop

; execute Page Write

subi ZL, low(PAGESIZEB) ;restore pointer

sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256

ldi spmcrval, (1<<PGWRT) | (1<<SELFPRGEN)

call Do_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN)

call Do_spm

; read back and check, optional

ldi looplo, low(PAGESIZEB) ;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

subi YL, low(PAGESIZEB) ;restore pointer

sbci YH, high(PAGESIZEB)

Rdloop:

lpm r0, Z+

ld r1, Y+

cpse r0, r1

jmp Error

sbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256

brne Rdloop

; return to RWW section

; verify that RWW section is safe to read

Return:

in temp1, SPMCSR

sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet

ret

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SELFPRGEN)

call Do_spm

rjmp Return

Do_spm:

; check for previous SPM complete

Wait_spm:

in temp1, SPMCSR

sbrc temp1, SELFPRGEN

rjmp Wait_spm

; input: spmcrval determines SPM action

; disable interrupts if enabled, store status

in temp2, SREG

cli

; check that no EEPROM write access is present

Wait_ee:

sbic EECR, EEPE

rjmp Wait_ee

; SPM timed sequence

out SPMCSR, spmcrval

spm

; restore SREG (to enable interrupts if originally enabled)

out SREG, temp2

ret

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26.8.13 ATmega88P Boot Loader Parameters

In Table 26-6 through Table 26-8, the parameters used in the description of the self programming are given.

Note: The different BOOTSZ Fuse configurations are shown in Figure 26-2 on page 281.

For details about these two section, see ”NRWW – No Read-While-Write Section” on page 279 and ”RWW – Read-While-

Write Section” on page 279

Note: 1. Z15:Z13: always ignored

Z0: should be zero for all SPM commands, byte select for the LPM instr uction.

See ”Addressing the Flash During Self-Programming” on page 283 for details about the use of Z-pointer during Self-

Programming.

Table 26-6. Boot Size Configuration, ATmega88P

BOOTSZ1 BOOTSZ0 Boot

Size Pages

Application

Flash

Section

Boot

Loader

Flash

Section

End

Application

Section Boot Reset Address (Start Boot Loader

Section)

1 1 128 words 4 0x000 - 0xF7F 0xF80 - 0xFFF 0xF7F 0xF80

1 0 256 words 8 0x000 - 0xEFF 0xF00 - 0xFFF 0xEFF 0xF00

0 1 512 words 16 0x000 - 0xDFF 0xE00 - 0xFFF 0xDFF 0xE00

0 0 1024 words 32 0x000 - 0xBFF 0xC00 - 0xFFF 0xBFF 0xC00

Table 26-7. Read-While-Write Limit, ATmega88P

Section Pages Address

Read-While-Write section (RWW) 96 0x000 - 0xBFF

No Read-While-Write section (NRWW) 32 0xC00 - 0xFFF

Table 26-8. Explanation of Different Variables used in Figure 26-3 and the Mapping to the Z- pointer, ATmega88P

Variable Corresponding

Z-value(1) Description

PCMSB 11 Most significant bit in the Program Counter . (The Prog ram Counter is

12 bits PC[11:0])

PAGEMSB 4 Most significant bit which is used to address the words within one

page (32 words in a page requires 5 bits PC [4:0]).

ZPCMSB Z12 Bit in Z-register that is mapped to PCMSB. Because Z0 is not used,

the ZPCMSB equals PCMSB + 1.

ZPAGEMSB Z5 Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not

used, the ZPAGEMSB equals PAGEMSB + 1.

PCPAGE PC[11:5] Z12:Z6 Program counter page address: Page select, for page erase and

page write

PCWORD PC[4:0] Z5:Z1 Program counter word address: Word select, for filling temporary

buffer (must be zero during page write operation)

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26.8.14 ATmega168P Boot Loader Parameters

In Table 26-9 through Table 26-11, the parameters used in the description of the self progr amming are given.

Note: The different BOOTSZ Fuse configurations are shown in Figure 26-2 on page 281.

For details about these two section, see ”NRWW – No Read-While-Write Section” on page 279 and ”RWW – Read-While-

Write Section” on page 279

Note: 1. Z15:Z14: always ignored

Z0: should be zero for all SPM commands, byte select for the LPM instr uction.

See ”Addressing the Flash During Self-Programming” on page 283 for details about the use of Z-pointer during Self-

Programming.

Table 26-9. Boot Size Configuration, ATmega168P

BOOTSZ1 BOOTSZ0 Boot

Size Pages

Application

Flash

Section

Boot

Loader

Flash

Section

End

Application

Section Boot Reset Address (Start Boot

Loader Section)

1 1 128 words 2 0x0000 - 0x1F7F 0x1F80 - 0x1FFF 0x1F7F 0x1F80

1 0 256 words 4 0x0000 - 0x1EFF 0x1F00 - 0x1FFF 0x1EFF 0x1F00

0 1 512 words 8 0x0000 - 0x1DFF 0x1E00 - 0x1FFF 0x1DFF 0x1E00

0 0 1024 words 16 0x0000 - 0x1BFF 0x1C00 - 0x1FFF 0x1BFF 0x1C00

Table 26-10. Read-While-Write Limit, ATmega168P

Section Pages Address

Read-While-Write section (RWW) 112 0x0000 - 0x1BFF

No Read-While-Wr ite section (NRWW) 16 0x1C00 - 0x1FFF

Table 26-11. Explanation of Different Variables used in Figure 26-3 and the Mapping to the Z-pointer, ATmega168P

Variable Corresponding

Z-value(1) Description

PCMSB 12 Most significant bit in the Program Counter. (The Program Counter

is 13 bits PC[12:0])

PAGEMSB 5 Most significant bit which is used to address the words within

one page (64 words in a page requires 6 bits PC [5:0])

ZPCMSB Z13 Bit in Z-regist er th at is ma ppe d to PCM SB. Because Z 0 is not u se d,

the ZPCMSB equals PCMSB + 1.

ZPAGEMSB Z6 Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not

used, the ZPAGEMSB equals PAGEMSB + 1.

PCPAGE PC[12:6] Z13:Z7 Program counter page address: Page select, for page erase and

page write

PCWORD PC[5:0] Z6:Z1 Program counter word address: Word select, for filling temporary

buffer (must be zero during page write operation)

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26.8.15 ATmega328P Boot Loader Parameters

In Table 26-12 through Table 26-14, the parameters used in the description of the self programming are given.

Note: The different BOOTSZ Fuse configurations are shown in Figure 26-2 on page 281.

For details about these two section, see ”NRWW – No Read-While-Write Section” on page 279 and ”RWW – Read-While-

Write Section” on page 279

Note: 1. Z15: always ignored

Z0: should be zero for all SPM commands, byte select for the LPM instr uction.

See ”Addressing the Flash During Self-Programming” on page 283 for details about the use of Z-pointer during Self-

Programming.

Table 26-12. Boot Size Configuration, ATmega328P

BOOTSZ1 BOOTSZ0 Boot

Size Pages

Application

Flash

Section

Boot

Loader

Flash

Section

End

Application

Section Boot Reset Address (Start Boot

Loader Section)

1 1 256 words 4 0x0000 - 0x3EFF 0x3F00 - 0x3FFF 0x3EFF 0x3F00

1 0 512 words 8 0x0000 - 0x3DFF 0x3E00 - 0x3FFF 0x3DFF 0x3E00

0 1 1024 words 16 0x0000 - 0x3BFF 0x3C00 - 0x3FFF 0x3BFF 0x3C00

0 0 2048 words 32 0x0000 - 0x37FF 0x3800 - 0x3FFF 0x37FF 0x3800

Table 26-13. Read-While-Write Limit, ATmega328P

Section Pages Address

Read-While-Write section (RWW) 224 0x0000 - 0x37FF

No Read-While-Wr ite section (NRWW) 32 0x3800 - 0x3FFF

Table 26-14. Explanation of Different Variables used in Figure 26-3 and the Mapping to the Z-pointer, ATmega328P

Variable Corresponding

Z-value(1) Description

PCMSB 13 Most significant bit in the Program Counter. (The Program Counter

is 14 bits PC[13:0])

PAGEMSB 5 Most significant bit which is used to address the words within

one page (64 words in a page requires 6 bits PC [5:0])

ZPCMSB Z14 Bit in Z-regist er th at is ma ppe d to PCM SB. Because Z 0 is not u se d,

the ZPCMSB equals PCMSB + 1.

ZPAGEMSB Z6 Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not

used, the ZPAGEMSB equals PAGEMSB + 1.

PCPAGE PC[13:6] Z14:Z7 Program counter page address: Page select, for page erase and

page write

PCWORD PC[5:0] Z6:Z1 Program counter word address: Word select, for filling temporary

buffer (must be zero during page write operation)

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26.9 Register Description

26.9.1 SPMCSR – Store Progra m Memory Control and Status Register

The Store Progr am Memory Contro l and Status Regist er contains the co ntrol bits nee ded to con-

trol the Boot Load e r oper at i on s.

• Bit 7 – SPMIE: SPM Interrupt Enable

When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM

ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SELF-

PRGEN bit in the SPMCSR Register is cleared.

• Bit 6 – RWWSB: Read-While-Write Section Busy

When a Self-Programming (Page Eras e or Page Write) operation to the RWW section is initi-

ated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section

cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a

Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be

cleared if a page load operation is initiated.

• Bit 5 – Res: Reserved Bit

This bit is a reserved bit in the ATmega48P/88P/168P/328P and always read as zero.

• Bit 4 – RWWSRE: Read-While-Write Section Read Enable

When programming (Page Erase or Page Write) to the RWW section, the RWW section is

blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the

user software must wait until the programming is completed (SELFPRGEN will be cleared).

Then, if the RWWSRE bit is written to one at the same time as SELFPRGEN, the next SPM

instruction within four clock cycles re-enables the RWW section. The RWW section cannot be

re-enabled while the Flash is busy with a Page Erase or a Page Write (SELFPRGEN is set). If

the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort

and the data loaded will be lost.

• Bit 3 – BLBSET: Boot Lock Bit Set

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four

clock cycles sets Boot Lock bit s and Memory Lo ck bits, according to the data in R0. The data in

R1 and the address in the Z-pointer are ig nored. The BLBSET bit will automatically be cleare d

upon completio n of the Lock bit set, or if n o SPM instruction is execute d within four clock cycles.

An LPM instruction within three cycles after BLBSET and SE LFPRGEN are set in the SPMCSR

destination register. See ”Reading the Fuse and Lock Bits from Software” on page 285 for

details.

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four

clock cycles executes Page Write, with the data stored in the temporary buffer. The page

address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The

Bit 7 6 5 4 3 2 1 0

0x37 (0x57) SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SELFPRGEN SPMCSR

Read/Write R/W R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed

within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW

section is addressed.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four

clock cycles executes Page Erase. The page address is taken from the high part of the Z-

pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a

Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted dur-

ing the entire Page Write ope ration if the NRWW section is addressed.

• Bit 0 – SELFPRGEN: Self Programming Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one together with

either RWWSRE, BLBSET, PGWRT or PGERS, the following SPM instruction will have a spe-

cial meaning, see description above. If only SELFPRGEN is written, the following SPM

instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer.

The LSB of the Z-pointer is ignored. The SELFPRGEN bit will auto-clear upon completion of an

SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase

and Page Write, the SELFPRGEN bit remains high until the operation is completed.

Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower

five bits will have no effect.

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27. Memory Programming

27.1 Program And Data Memory Lock Bits

The ATmega88P/168P provides six Lock bits which can be left unprogrammed (“1”) or can be

programmed ( “0”) to obtain th e additio nal featur es listed in Table 27-2 . The Lock bits can only be

erased to “1” with the Chip Erase co mmand.The ATmega48P ha s no sepa rate Boot Loa der sec-

tion. The SPM instr uction is enabled for the wh ole Flash if t he SELFPRGEN fuse is program med

(“0”), otherwise it is disabled.

Notes: 1. “1” means unprogrammed, “0” means programmed

2. Only on ATmega88P/168P.

Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.

2. “1” means unprogrammed, “0” means programmed

Table 27-1. Lock Bit Byte(1)

Lock Bit Byte Bit No Description Default Value

7 – 1 (unprogrammed)

6 – 1 (unprogrammed)

BLB12(2) 5 Boot Lock bit 1 (unprogrammed)

BLB11(2) 4 Boot Lock bit 1 (unprogrammed)

BLB02(2) 3 Boot Lock bit 1 (unprogrammed)

BLB01(2) 2 Boot Lock bit 1 (unprogrammed)

LB2 1 Lock bit 1 (unprogrammed)

LB1 0 Lock bit 1 (unprogrammed)

Table 27-2. Lock Bit Protection Modes(1)(2)

Memory Lock Bits Protection Type

LB Mode LB2 LB1

1 1 1 No memory lock features enabled.

210

Further programming of the Flash and EEPROM is disabled in

Parallel and Serial Programming mode. The Fuse bits are

locked in both Serial and Parallel Programming mode.(1)

300

Further programming and verification of the Flash and EEPROM

is disabled in Parallel and Serial Programming mode. The Boot

Lock bits and Fuse bits are locked in both Ser ial and Parallel

Programming mode.(1)

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Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.

2. “1” means unprogrammed, “0” means programmed

27.2 Fuse Bits The ATmega48P/88P/168P/328P has t hree Fuse byt es. Ta ble 27-4 - Table 27-9 de scribe br iefly

the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the

fuses are read as logical zero, “0”, if they are programmed.

Table 27-3. Lock Bit Protection Modes(1)(2). Only ATmega88P/168P.

BLB0 Mode BLB02 BLB01

111

No restrictions for SPM or LPM accessing the Applic ation

section.

2 1 0 SPM is not allowed to write to the Application section.

300

SPM is not allowed to write to the Application section, and LPM

executing from the Boot Loader section is not allowed to read

from the Application section. If Interrupt Vectors are placed in

the Boot Loader section, interrupts are disabled while executing

from the Application section.

401

LPM executing from the Boot Loader section is not allowed to

read from the Application section. If Interrupt Vectors are placed

in the Boot Loader section, interrupts are disabled while

executing from the Application section.

BLB1 Mode BLB12 BLB11

111

No restrictions for SPM or LPM accessing the Boot Loader

section.

2 1 0 SPM is not allowed to write to the Boot Loader section.

300

SPM is not allowed to write to the Boot Loader section, and LPM

executing from the Application section is not allowed to read

from the Boot Loader section. If Interrupt Vectors are placed in

the Application section, interrupts are disabled while executing

from the Boot Loader section.

401

LPM executing from the Application section is not allowed to

read from the Boot Loader section. If Interrupt Vectors are

placed in the Application section, interrupts are disabled while

executing from the Boot Loader section.

Table 27-4. Extended Fuse Byte for ATmega48P

Extended Fuse Byte Bit No Description Default Value

–7– 1

–6– 1

–5– 1

–4– 1

–3– 1

–2– 1

–1– 1

SELFPRGEN 0 Self Prog ramming Enab le 1 (unprogrammed)

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Note: 1. The default v alue of BOOTSZ[1:0] results in maximum Boot Siz e. See ”Pin Name Mapping” on

page 300.

Note: 1. See Table 28-4 on page 319 for BODLEVEL Fuse decoding..

Table 27-5. Extended Fuse Byte for ATmega88P/168P

Extended Fuse Byte Bit No Description Default Value

–7– 1

–6– 1

–5– 1

–4– 1

–3– 1

BOOTSZ1 2

Select Boot Size

(see

Table 26-6 on page 289 ,

Table 26-9 on page 290 and

Table 26-12 on page 291

for details)

0 (programmed)(1)

BOOTSZ0 1

Select Boot Size

(see

Table 26-6 on page 289 ,

Table 26-9 on page 290 and

Table 26-12 on page 291

for details)

0 (programmed)(1)

BOOTRST 0 Select Reset Vector 1 (unprogrammed)

Table 27-6. Extended Fuse Byte for ATmega328P

Extended Fuse Byte Bit No Description Default Value

–7– 1

–6– 1

–5– 1

–4– 1

–3– 1

BODLEVEL2(1) 2Brown-out Detector trigger

level 1 (unprogrammed)

BODLEVEL1(1) 1Brown-out Detector trigger

level 1 (unprogrammed)

BODLEVEL0(1) 0Brown-out Detector trigger

level 1 (unprogrammed)

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Notes: 1. See ”Alternate Functions of Port C” on page 86 fo r de scripti on of RSTD I SBL Fu se.

2. The SPIEN Fuse is not accessible in serial programming mode.

3. See ”WDTCSR – Watchdog Timer Control Register” on page 55 for details.

4. See Table 28-4 on page 319 for BODLEVEL Fuse decoding.

Notes: 1. See ”Alternate Functions of Port C” on page 86 fo r de scripti on of RSTD I SBL Fu se.

Table 27-7. Fuse High Byte f or ATmega48P/88P/168P

High Fuse Byte Bit No Description Default Value

RSTDISBL(1) 7 External Reset Disable 1 (unprogrammed)

DWEN 6 debugWIRE Enable 1 (unprogrammed)

SPIEN(2) 5Enable Serial Program and

Data Downloading 0 (programmed, SPI

programming enabled)

WDTON(3) 4 Watchdog Timer Always On 1 (unprogrammed)

EESAVE 3 EEPROM mem ory is

preserved through the Chip

Erase

1 (unprogrammed), EEPR OM

not reserved

BODLEVEL2(4) 2Brown-out Detector trigger

level 1 (unprogrammed)

BODLEVEL1(4) 1Brown-out Detector trigger

level 1 (unprogrammed)

BODLEVEL0(4) 0Brown-out Detector trigger

level 1 (unprogrammed)

Table 27-8. Fuse High Byte f or ATmega328P

High Fuse Byte Bit No Description Default Value

RSTDISBL(1) 7 External Reset Disable 1 (unprogrammed)

DWEN 6 debugWIRE Enable 1 (unprogrammed)

SPIEN(2) 5Enable Serial Program and

Data Downloading 0 (programmed, SPI

programming enabled)

WDTON(3) 4 Watchdog Timer Always On 1 (unprogrammed)

EESAVE 3 EEPROM mem ory is

preserved through the Chip

Erase

1 (unprogrammed), EEPR OM

not reserved

BOOTSZ1 2

Select Boot Size

(see

Table 26-6 on page 289 ,

Table 26-9 on page 290 and

Table 26-12 on page 291

for details)

0 (programmed)(4)

BOOTSZ0 1

Select Boot Size

(see

Table 26-6 on page 289 ,

Table 26-9 on page 290 and

Table 26-12 on page 291

for details)

0 (programmed)(4)

BOOTRST 0 Select Reset Vector 1 (unprogrammed)

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2. The SPIEN Fuse is not accessible in serial programming mode.

3. See ”WDTCSR – Watchdog Timer Control Register” on page 55 for details.

4. The default v alue of BOO T SZ[1:0] results in maximum Boot Size . See ”Pin Name Mapping” on

page 300.

Note: 1. The default value of SUT1..0 results in maximum start-up time for the default clock source.

See Table 8-11 on page 34 for details.

2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See Table 8-10 on

page 34 for details.

3. The CK OUT Fuse allo ws the system cloc k to be output on PORTB0. See ”Clock Output Buffer”

on page 36 for details.

4. See ”System Clock Prescaler” on page 36 for details.

The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if

Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.

27.2.1 Latching of Fuses

The fuse values are latched when the device enters programming mode and chang es of the

fuse values will have no effect until the part leaves Programming mode. This does not apply to

the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on

Power-up in Normal mode.

27.3 Signature Bytes

All Atmel microcontrollers have a three- byte signature code which identifies the device. This

code can be read in both serial and parallel mode, also when the device is locked. The three

bytes reside in a separate address space . For the ATmega48P/88P/168P/328P the signature

bytes are given in Table 27-10.

Table 27-9. Fuse Low Byte

Low Fuse Byte Bit No Description Default Value

CKDIV8(4) 7 Divide clock by 8 0 (progr ammed)

CKOUT(3) 6 Clock output 1 (unprogrammed)

SUT1 5 Select start-up time 1 (unprogrammed)(1)

SUT0 4 Select start-up time 0 (programmed)(1)

CKSEL3 3 Select Clock source 0 (programmed)(2)

CKSEL2 2 Select Clock source 0 (programmed)(2)

CKSEL1 1 Select Clock source 1 (unprogrammed)(2)

CKSEL0 0 Select Clock source 0 (programmed)(2)

Table 27-10. Device ID

Part

Signature Bytes Address

0x000 0x001 0x002

ATmega48P 0x1E 0x92 0x0A

ATmega88P 0x1E 0x93 0x0F

ATmega168P 0x1E 0x94 0x0B

ATmega328P 0x1E 0x95 0x0F

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27.4 Calibration Byte

The ATmega48P/88P/1 68P/328P has a byte calibration value for th e Interna l RC Oscillat or. This

byte resides in the high byte of add re ss 0x000 in th e sig natu re ad dress space . During re set , this

byte is automatically written into the OSCCAL Reg ister to ensure correct frequency of the cali-

brated RC Oscillator.

27.5 Page Size

27.6 Parallel Programming Parameters, Pin Mapping, and Commands

This section describes how to parallel program and verify Flash Program memory, EEPROM

Data memory, Memory Lock bits, and Fuse bits in the ATmega48P/88P/168P/328P. Pulses are

assumed to be at least 250 ns unless ot herwise noted.

27.6.1 Signal Names In this section, some pins of the ATmega48P/88P/168P/328P are referenced by signal names

describing their functionality during pa rallel program ming, see Figure 27-1 and Table 27-13.

Pins not described in th e following table are referenced by pin names.

The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.

The bit coding is shown in Table 27-15.

When pulsing WR or OE, the com mand loaded determines the action executed. The different

Commands are shown in Table 27-16.

Table 27-11. No. of Words in a Page and No. of Pages in the Flash

Device Flash Size Page Size PCWORD No. of

Pages PCPAGE PCMSB

ATmega48P 2K words

(4K bytes) 32 words PC[4:0] 64 PC[10:5] 10

ATmega88P 4K words

(8K bytes) 32 words PC[4:0] 128 PC[11:5] 11

ATmega168P 8K words

(16K bytes) 64 words PC[5:0] 128 PC[12 :6 ] 12

ATmega328P 16K words

(32K bytes) 64 words PC[5:0] 256 PC[13:6] 13

Table 27-12. No. of Words in a Page and No. of Pages in the EEPROM

Device EEPROM

Size Page

Size PCWORD No. of

Pages PCPAGE EEAMSB

ATmega48P 256 bytes 4 bytes EEA[1:0] 64 EEA[7:2] 7

ATmega88P 512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8

ATmega168P 512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8

ATmega328P 1K bytes 4 bytes EEA[1:0] 256 EEA[9:2] 9

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Figure 27-1. Parallel Programming

Note: VCC - 0.3V < AVCC < VCC + 0.3V, ho we ver, AVCC should always be within 4.5 - 5.5V

Table 27-13. Pin Name Mapping

Signal Name in

Programming Mode Pin Name I/O Function

RDY/BSY PD1 O 0: Device is busy programming, 1: Device is

ready for new command

OE PD2 I Output Enable (Activ e low)

WR PD3 I Write Pulse (Active low)

BS1 PD4 I Byte Select 1 (“0” selects Low byte, “1” selects

High byte)

XA0 PD5 I XTAL Action Bit 0

XA1 PD6 I XTAL Action Bit 1

PAGEL PD7 I Program memory and EEPROM Data Page

Load

BS2 PC2 I Byte Select 2 (“0” selects Low byte, “1” selects

2’nd High byte)

DATA {PC[1:0]: PB[5:0]} I/O Bi-directional Data b us (Output when OE is low)

Table 27-14. Pin Values Used to Enter Programming Mode

Pin Symbol Value

PAGEL Prog_enable[3] 0

XA1 Prog_enable[2] 0

XA0 Prog_enable[1] 0

BS1 Prog_enable[0] 0

VCC

GND

XTAL1

PD1

PD2

PD3

PD4

PD5

PD6

PC[1:0]:PB[5:0]

DATA

RESET

PD7

+12 V

BS1

XA0

XA1

RDY/BSY

PAGEL

PC2

BS2

AVCC

+4.5 - 5.5V

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27.7 Parallel Programming

27.7.1 Enter Programming Mode

The following algorithm puts the device in Parallel (High-voltage) Programming mode:

1. Set Prog_enable pins listed in Ta ble 27-1 4 on page 300 to “0000”, RESET pin to 0V and

VCC to 0V.

2. Apply 4.5 - 5.5 V be twee n VCC and GND.

Ensure that VCC reaches at least 1.8V within the next 20 µs.

3. Wait 20 - 60 µs, and apply 11.5 - 12.5V to RESET.

4. Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has been

applied to ensure the Prog _e n able Signatur e ha s be en latc he d.

5. Wait at least 300 µs before giving any parallel programming commands.

6. Exit Programming mode by power the device down or by bringing RESET pin to 0V.

If the rise time of t he VCC is unable to fulfill the requirements listed above, the following alterna-

tive algorithm can be used.

1. Set Prog_enable pins listed in Ta ble 27-1 4 on page 300 to “0000”, RESET pin to 0V and

VCC to 0V.

2. Apply 4.5 - 5.5 V be twee n VCC and GND.

3. Monitor VCC, and as soon as VCC reaches 0.9 - 1.1V, apply 11.5 - 12.5V to RESET.

Table 27-15. XA1 and XA0 Coding

XA1 XA0 Action when XTAL1 is Pulsed

0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1).

0 1 Load Data (High or Low data byte for Flash determined by BS1).

1 0 Load Command

1 1 No Action, Idle

Table 27-16. Command Byte Bit Coding

Command Byte Command Executed

1000 0000 Chip Erase

0100 0000 Write Fuse bits

0010 0000 Write Lock bits

0001 0000 Write Flash

0001 0001 Write EEPROM

0000 1000 Read Signature Bytes and Calibration byte

0000 0100 Read Fuse and Lock bits

0000 0010 Read Flash

0000 0011 Read EEPROM

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ATmega48P/88P/168P/328P

4. Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has been

applied to ensure the Prog _e n able Signatur e ha s be en latc he d.

5. Wait until VCC actually reaches 4.5 -5. 5V before giving any parallel programming

commands.

6. Exit Programming mode by power the device down or by bringing RESET pin to 0V.

27.7.2 Considerations for Efficient Programming

The loaded command and address are retained in the device during programming. For efficient

programming, the following should be considered.

• The command need s only be loaded once when writing or reading mult iple memory locations.

• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the

EESAVE Fuse is programmed) and Flash after a Chip Erase.

• Address high byte needs only be loaded before programming or reading a new 256 word

window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes

reading.

27.7.3 Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits . The Lo ck bits are

not reset until the program memory has been completely erased. The Fuse bits are not

changed. A Chip Erase must be performed before the Flash and/or EEPROM are

reprogrammed.

Note: 1. The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.

Load Command “Chip Erase”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “1000 0000”. This is the command for Chip Erase.

4. Give XTAL1 a positive pulse. This loads the command.

5. Give WR a negative pulse. This st arts the Chip Erase. RDY/BSY goes low.

6. Wait until RDY/BSY goes high befor e loading a new command.

27.7.4 Programming the Flash

The Flash is organized in pages, see Table 27-11 on page 299. When programming the Flash,

the program data is latched into a page buffer. This allows one page of program data to be pro-

grammed simultaneously. The following procedure describes how to program the entire Flash

memory:

A. Load Command “Write Flash”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “0001 0000”. This is the command f or Write Flash.

4. Give XTAL1 a positive pulse. This loads the command.

B. Load Address Low byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “0”. This selects low address.

3. Set DATA = Address low byte (0x00 - 0xFF).

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4. Give XTAL1 a positive pulse. This loads the address lo w byte.

C. Load Data Low Byte

1. Set XA1, XA0 to “01”. This enables data loading.

2. Set D ATA = Data low byte (0x00 - 0xFF).

3. Give XTAL1 a positive pulse. This loads the data byte.

D. Load Data High Byte

1. Set BS1 to “1”. This selects high data byte.

2. Set XA1, XA0 to “01”. This enables data loading.

3. Set DATA = Data high byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the data byte.

E. Latch Data

1. Set BS1 to “1”. This selects high data byte.

2. Give PAGEL a positive pulse. This latches the data bytes. (See Figure 27-3 for signal

waveforms)

F. Repeat B through E unt il the entire buffer is filled or until all data within the page is loaded.

While the lower bits in t he addre ss are mapped t o words within the pa ge, th e higher b its addr ess

the pages within the FLASH. This is illustrated in Figure 27-2 on page 304. Note that if less than

eight bits are required to address words in the page (pagesize < 256), the most significant bit(s)

in the address low byte are used to address the page when performing a Page Write.

G. Load Address High byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “1”. This selects high address.

3. Set DATA = Address high byte (0x00 - 0xFF).

4. Give XTAL1 a positive pulse. This loads the address high byte.

H. Program Page

1. Giv e WR a negative pulse . This starts programming of the ent ire page of d ata. RDY/BSY

goes low.

2. Wait until RDY/BSY goes high ( See Figure 27-3 for signal waveforms).

I. Repeat B through H until the entire Flash is programmed or until all data has been

programmed.

J. End Page Programming

1. 1. Set XA1, XA0 to “10”. This en ables command loading.

2. Set DATA to “0000 0000”. This is the command for No Operation.

3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are

reset.

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Figure 27-2. Addressing the Flash Which is Organized in Pages(1)

Note: 1. PCPAGE and PCWORD are listed in Table 27-11 on page 299.

Figure 27-3. Programming the Flash Waveforms(1)

Note: 1. “XX” is don’t care. The letters refer to the programming description above.

27.7.5 Programming the EEPROM

The EEPROM is organized in pages, see Table 27-12 on page 299. When programming the

EEPROM, the program data is latched into a page buffer. This allows one page of data to be

programmed simultaneously. The programming algorithm for the EEPROM data memory is as

follows (refer to ”Programming the F lash” on page 302 for details on Com mand, Address and

Data loading):

1. A: Load Command “0001 0001”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. C: Load Data (0x00 - 0xFF).

PROGRAM MEMORY

WORD ADDRESS

WITHIN A PAGE

PAGE ADDRESS

WITHIN THE FLASH

INSTRUCTION WORD

PAGE PCWORD[PAGEMSB:0]:

PAGEEND

PAGE

PCWORDPCPAGE

PCMSB PAGEMSB

PROGRAM

COUNTER

RDY/BSY

ESET +12V

PAGEL

BS2

0x10 ADDR. LOW ADDR. HIGH

DATA DATA LOW DATA HIGH ADDR. LOW DATA LOW DATA HIGH

XA1

XA0

BS1

XTAL1

XX XX XX

ABCDEBCDEGH

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5. E: Latch data (give PAGEL a positive pulse).

K: Repeat 3 through 5 until the entire buffer is filled.

L: Program EEPROM page

1. Set BS1 to “0”.

2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY

goes low.

3. W ait until to RDY/BSY goes high bef or e prog ramm ing the next page (See Figure 27-4 for

signal waveforms).

Figure 27-4. Programming the EEPROM Waveforms

27.7.6 Reading the Flash

The algorithm for reading the Flash m emory is as follows (refer to ”Programming the Flash” on

page 302 for details on Command and Address loading):

1. A: Load Command “0000 0010”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.

5. Set BS1 to “1”. The Flash word high byte can now be read at DATA.

6. Set OE to “1”.

27.7.7 Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to ”Programming the Flash”

on page 302 for details on Command and Address loading):

1. A: Load Command “0000 0011”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.

5. Set OE to “1”.

RDY/BSY

ESET +12V

PAGEL

BS2

0x11 ADDR. HIGH

DATA ADDR. LOW DATA ADDR. LOW DATA XX

XA1

XA0

BS1

XTAL1

AGBCEBC EL

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27.7.8 Programming the Fuse Low Bits

The algorith m for progr amming th e Fuse Lo w bits is as follows (ref er to ” Programmin g the Flash”

on page 302 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Give WR a negative pulse and wa it for RDY/BSY to go high.

27.7.9 Programming the Fuse High Bits

The algorithm for programming the Fuse High bits is as follows (refer to ”Programming the

Flash” on page 302 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Set BS1 to “1” and BS2 to “0”. This selects high data byte .

4. Give WR a negative pulse and wa it for RDY/BSY to go high.

5. Set BS1 to “0”. This selects low data byte.

27.7.10 Programming the Extended Fuse Bits

The algorithm for programming the Extended Fuse bits is as follows (refer to ”Progr amming th e

Flash” on page 302 for details on Command and Data loading):

1. 1. A: Load Command “0100 0000”.

2. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. 3. Set BS1 to “0” and BS2 to “1”. This selects extended data byte.

4. 4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. 5. Set BS2 to “0”. This selects low data byte.

Figure 27-5. Programming the FUSES Waveforms

27.7.11 Programming the Lock Bits

The algorithm for programming the Lock bits is as follows (refer to ”Programming the Flash” on

page 302 for details on Command and Data loading):

RDY/BSY

RESET +12V

PAGEL

0x40

DATA

DATA XX

XA1

XA0

BS1

XTAL1

0x40 DATA XX

Write Fuse Low byte Write Fuse high byte

0x40 DATA XX

Write Extended Fuse byte

BS2

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1. A: Load Command “0010 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs the Lo ck bit. If LB mode 3 is programmed

(LB1 and LB2 is programmed), it is not po ssible to program the Boot Lock bits by any

External Programming mode.

3. Give WR a negative pulse and wa it for RDY/BSY to go high.

The Lock bits can only be cleared by executing Chip Erase.

27.7.12 Reading the Fuse and Lock Bits

The algorithm for reading the Fuse and Lock bits is as follows (refer to ”Programming the Flash”

on page 302 for details on Command loading):

1. A: Load Command “0000 0100”.

2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Lo w bits can now be

read at DATA (“0” means programmed).

3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be

read at DATA (“0” means programmed).

4. Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits can now

be read at DATA (“0” means programmed).

5. Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be read at

DATA (“0” means programmed).

6. Set OE to “1”.

Figure 27-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read

27.7.13 Reading the Signature Bytes

The algorithm for reading the Signature bytes is as follows (refer to ”Programming t he F l as h” on

page 302 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte (0x00 - 0x02).

3. Set OE to “0”, and BS1 to “0”. The selected Signatu re byte can now be read at DATA.

4. Set OE to “1”.

Lock Bits 0

BS2

Fuse High Byte

BS1

DATA

Fuse Low Byte 0

BS2

Extended Fuse Byte

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27.7.14 Reading the Calibration Byte

The algorithm for reading the Calibration byte is as follows (refer to ”Programming th e F lash” on

page 302 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte, 0x00.

3. Set OE to “0”, and BS1 to “1”. The Calibrati on byte can now be read at DATA.

4. Set OE to “1”.

27.7.15 Parallel Programmi ng Characteristics

For chracteristics of the Parallel Programming, see ”Parallel Programming Characteristics” on

page 325.

27.8 Serial Downloading

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while

RESET is pulled to GND. The se rial interface co nsists of pins SCK, MOSI (i nput) and MI SO (out-

put). After RESET is set low, the Programming Enable instruction needs to be executed first

before program/erase operations can be executed. NOTE, in Table 27-17 on page 309, the pin

mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal

SPI interface.

Figure 27-7. Serial Programming and Verify(1)

Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the

XTAL1 pin.

2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 - 5.5V

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase

instruction. The Chip Erase operation turns the content of every memory location in both the

Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods

for the serial clock (SCK) input are defined as follows:

Low: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

VCC

GND

XTAL1

SCK

MISO

MOSI

RESET

+1.8 - 5.5V

AVCC

+1.8 - 5.5V

(2)

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27.8.1 Serial Programming Pin Mapping

27.8.2 Serial Programming Algorithm

When writing ser ial data to the ATm ega48P/88P/1 68P/328P, data is clocked on the ris ing edge

of SCK.

When reading data from the ATmega48P/88P/168P/328P, data is clocked on the falling edge of

SCK. See Figure 27-9 for timing details .

To program a nd verify the ATme ga48P/88 P/168P/ 328P in t he seri al progr amming mode, t he fol-

lowing sequence is reco mmended (See Serial Programming Instruction set in Table 27-19 on

page 310):

1. Power-up sequence:

Apply power between VCC and GN D while RESET and SCK are set to “0”. In some sys-

tems, the programmer can not guarantee that SCK is held low during power-up. In this

case, RESET must be given a positive pulse of at least two CPU clock cycles duration

after SCK has been set to “0”.

2. Wait for at least 20 ms and enable serial programming by sending the Programming

Enable serial instruction to pin MOSI.

3. The serial programming instructions will not work if the communication is out of synchro-

nization. When in sync. the second byte (0x53), will echo back when issuing the third

byte of the Programming Enable instruction. Whether the echo is correct or not, all four

bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a

positive pulse and issue a new Programming Enable command.

4. The Flash is programmed one page at a time. The memory page is loaded one byte at a

time by supplying the 6 LSB of the address and data together with the Load Program

Memory Page instruction. To ensure correct loading of the page, the data low byte must

be loaded before data high byte is applied for a given address. The Program Memory

Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of

the address. If polling (RDY/BSY) is not used, the user must wait at least t WD_FLASH before

issuing the next page (See Table 27-18). Accessing the serial programming interface

before the Flash write operation completes can result in incorrect programming.

5. A: The EEPROM array is programmed one byte at a time by supplying the address and

data together with the appropriate Write instruction. An EEPROM memory location is first

automatically erased before new data is written. If polling (RDY/BSY) is not used, the

user must wait at least tWD_EEPROM before issuing the next byte (See Table 27-18). In a

chip erased device, no 0xFF s in the da ta file(s) need to be programmed .

B: The EEPROM array is programmed one page at a time. The Memory page is loaded

one b yte a t a time by supplying the 6 LSB of the a ddress and data toget her with t he Load

EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading

the Write EEPROM Memory P age Instruction with the 7 MSB of the address. When using

EEPROM page access only b yte locations loaded with the Load EEPROM Memory Page

instruction is altered. The remaining location s r emain u nchange d. If po lling (R DY/BSY) is

Table 27-17. Pin Mapping Serial Programming

Symbol Pins I/O Description

MOSI PB3 I Serial Data in

MISO PB4 O Serial Data out

SCK PB5 I Serial Clock

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not used, the used must wait at least tWD_EEPROM before issuing the next byte (See Table

27-18). In a chip erased device, no 0xFF in the data file(s) need to be programmed.

6. Any memo ry location can be v erified b y using the Read instruction which returns the con-

tent at the selected address at serial output MISO.

7. At the end of the programming session, RESET can be set high to commence normal

operation.

8. Power-off sequence (if needed):

Set RESET to “1”.

Turn VCC power off.

27.8.3 Serial Programming Instruction set

Table 27-19 on page 310 and Figure 27-8 on page 312 describes the Instruction set.

Table 27-18. Typical Wait Delay Before Writing the Next Flash or EEPROM Location

Symbol Minimum Wait Delay

tWD_FLASH 4.5 ms

tWD_EEPROM 3.6 ms

tWD_ERASE 9.0 ms

Table 27-19. Serial Programming Instruction Set (Hexadecimal values)

Instruction/Operation

Instruction Format

Byte 1 Byte 2 Byte 3 Byte4

Programming Enab le $AC $53 $00 $00

Chip Erase (Program Memory/EEPROM) $AC $80 $00 $00

Poll RDY/BSY $F0 $00 $00 data byte out

Load Instructions

Load Extended Address byte(1) $4D $00 Extended adr $0 0

Load Program Memory Page, High byte $48 $00 adr LSB high data byte in

Load Program Memor y Page, Low byte $40 $00 adr LSB low data byte in

Load EEPROM Memory Page (page access) $C1 $00 0000 000aa data byte in

Read Instructions

Read Program Memory, High byte $28 adr MSB adr LSB high data byte out

Read Program Memory, Low byte $20 adr MSB adr LSB low data b y t e ou t

Read EEPROM Memory $A0 0000 00aa aaaa aaaa data byte out

Read Lock bits $58 $00 $00 data byte out

Read Signature Byte $30 $00 0000 000aa data byte out

Read Fuse bits $50 $00 $00 data byte out

Read Fuse High bits $58 $08 $00 data byte out

Read Extended Fuse Bits $50 $08 $00 data byte out

Read Calibration Byte $38 $00 $00 data byte out

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Notes: 1. Not all instructions are applicable for all parts.

2. a = address.

3. Bits are programmed ‘0’, unprogrammed ‘1’.

4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) .

5. Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size.

6. Instructions accessing program memory use a word address. This address may be random within the page range.

7. See htt://www.atmel.com/a vr for Application Notes regarding programming and programmers.

If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until

this bit returns ‘0’ before the next instruction is carried out.

Within the same page, the low data byte must be loaded prior to the high data byte.

After data is loaded to the page buffer, program the EEPROM page, see Figure 27-8 on page

312.

Write Instructions(6)

Write Progra m Me mo ry Page $4C adr MSB adr LSB $00

Write EEPROM Memory $C0 0000 00aa aaaa aaaa data byte in

Write EEPROM Memory Page (page access) $C2 0000 00aa aaaa aa00 $00

Write Lock bits $AC $E0 $00 data byte in

Write Fuse bits $AC $A0 $00 data byte in

Write Fuse High bits $AC $A8 $00 data byte in

Write Extended Fuse Bits $AC $A4 $00 data byte in

Table 27-19. Serial Programming Instruction Set (Hexadecimal values) (Continued)

Instruction/Operation

Instruction Format

Byte 1 Byte 2 Byte 3 Byte4

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Figure 27-8. Serial Programming Instruction example

27.8.4 SPI Se ri al Programming Chara ct e ri st ic s

Figure 27-9. Serial Programming Waveforms

For characteristics of the SPI module see “SPI Timing Characteristics” on page 320.

Byte 1 Byte 2 Byte 3 Byte 4

Adr MSB Adr LSB

Bit 15 B 0

Serial Programming Instruction

Program Memory/

EEPROM Memory

Page 0

Page 1

Page 2

Page N-1

Page Buffer

Write Program Memory Page/

Write EEPROM Memory Page

Load Program Memory Page (High/Low Byte)/

Load EEPROM Memory Page (page access)

Byte 1 Byte 2 Byte 3 Byte 4

Bit 15 B 0

Adr MSB Adr LSB

Page Offset

Page Number

Adr

dr M

r MS

Adr

dr LS

LSB

MSB

LSB

SERIAL CLOCK INPUT

(SCK)

SERIAL DATA INPUT

(MOSI)

(MISO)

SAMPLE

ERIAL DATA OUTPUT

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28. Electrical Characteristics

28.1 Absolute Maximum Ratings*

28.2 DC Characteristics

Operating Te mperature.................................. -55°C to +125°C*NOTICE: S tresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Storage Temperature..................................... -65°C to +150°C

Voltage on any Pin except RESET

with respect to Ground ................................-0.5V to VCC+0.5V

Voltage on RESET with respect to Ground......-0.5V to +13.0V

Maximum Operating Voltage ............................................ 6.0V

DC Current per I/O Pin............................................... 40.0 mA

DC Current VCC and GND Pins................................ 200.0 mA

TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)

Symbol Parameter Condition Min. Typ. Max. Units

VIL Input Low Voltage, except

XTAL1 and RESET pin VCC = 1.8V - 2.4V

VCC = 2.4V - 5.5V -0.5

-0.5 0.2VCC(1)

0.3VCC(1) V

VIH Input High Voltage, except

XTAL1 and RESET pins VCC = 1.8V - 2.4V

VCC = 2.4V - 5.5V 0.7VCC(2)

0.6VCC(2) VCC + 0.5

VCC + 0.5 V

VIL1 Input Low Voltage,

XTAL1 pin VCC = 1.8V - 5.5V -0.5 0.1VCC(1) V

VIH1 Input High Voltage,

XTAL1 pin VCC = 1.8V - 2.4V

VCC = 2.4V - 5.5V 0.8VCC(2)

0.7VCC(2) VCC + 0.5

VCC + 0.5 V

VIL2 Input Low Voltage,

RESET pin VCC = 1.8V - 5.5V -0 .5 0.1VCC(1) V

VIH2 Input High Voltage,

RESET pin VCC = 1.8V - 5.5V 0.9VCC(2) VCC + 0.5 V

VIL3 Input Low Voltage,

RESET pin as I/O VCC = 1.8V - 2.4V

VCC = 2.4V - 5.5V -0.5

-0.5 0.2VCC(1)

0.3VCC(1) V

VIH3 Input High Voltage,

RESET pin as I/O VCC = 1.8V - 2.4V

VCC = 2.4V - 5.5V 0.7VCC(2)

0.6VCC(2) VCC + 0.5

VCC + 0.5 V

VOL Output Low Voltage(3)

except RESET pin IOL = 20 mA, VCC = 5V

IOL = 10 mA, VCC = 3V 0.9

0.6 V

VOH Output High Voltage(4)

except Reset pin IOH = -20 mA, VCC = 5V

IOH = -10 mA, VCC = 3V 4.2

2.3 V

IIL Input Leakage

Current I/O Pin VCC = 5.5V, pin low

(absolute value) 1µA

IIH Input Leakage

Current I/O Pin VCC = 5.5V, pin high

(absolute value) 1µA

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Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low

2. “Min” means the lowest value where the pin is guaranteed to be read as high

3. Although each I/O port can sink more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V) under steady state

conditions (non-transient), the following must be obser ved:

ATmega48P/88P/168P/328P:

1] The sum of all IOL, f or ports C0 - C5, ADC7, ADC6 should not exceed 100 mA.

2] The sum of all IOL, for ports B0 - B5, D5 - D7, XTAL1, XTAL2 should not exceed 100 mA.

3] The sum of all IOL, for ports D0 - D4, RESET should not e xceed 100 mA.

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test condition.

4. Although each I/O port can source more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V) under steady state

conditions (non-transient), the following must be obser ved:

ATmega48P/88P/168P/328P:

1] The sum of all IOH, f or ports C0 - C5, D0- D4, ADC7, RESET should not exceed 150 mA.

2] The sum of all IOH, for ports B0 - B5, D5 - D7, ADC6, XTAL1, XTAL2 should not exceed 150 mA.

If IIOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current

greater than the listed test condition.

28.2.1 ATmega48P DC Characteristics

Notes: 1. Values with “Minimizing Power Consumption” enabled (0xFF).

2. Typical values at 25°C. Maximum values are characterized values and not test limits in production.

3. The current consumption values include input leakage current.

RRST Reset Pull-up Resistor 30 60 kΩ

RPU I/O Pin Pull-up Resistor 20 50 kΩ

VACIO Analog Comparator

Input Offset Voltage VCC = 5V

Vin = VCC/2 <10 40 mV

IACLK Analog Comparator

Input Leakage Current VCC = 5V

Vin = VCC/2 -50 50 nA

tACID Analog Comparator

Propagation Delay VCC = 2.7V

VCC = 4.0V 750

500 ns

TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) (Cont inued)

Symbol Parameter Condition Min. Typ. Max. Units

TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)

Symbol Parameter Condition Min. Typ.(2) Max. Units

ICC

Power Supply Current(1)

Active 1 MHz, VCC = 2V 0.3 0.5 mA

Active 4 MHz, VCC = 3V 1.9 2.5 mA

Active 8 MHz, VCC = 5V 6.8 9 mA

Idle 1 MHz, VCC = 2V 0.06 0.15 mA

Idle 4 MHz, VCC = 3V 0.4 0.7 mA

Idle 8 MHz, VCC = 5V 1.6 2.7 mA

Power-save mode(3)

32 kHz TOSC enabled,

VCC = 1.8V 0.75 TBD µA

32 kHz TOSC enabled,

VCC = 3V 0.85 TBD µA

Power-down mode(3) WDT enabled, VCC = 3V 4.2 8 µA

WDT disabled, VCC = 3V 0.18 2 µA

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28.2.2 ATmega88P DC Characteristics

Notes: 1. Values with “Minimizing Power Consumption” enabled (0xFF).

2. Typical values at 25°C. Maximum values are characterized values and not test limits in production.

3. The current consumption values include input leakage current.

28.2.3 ATmega168P DC Characteristics

Notes: 1. Values with “Minimizing Power Consumption” enabled (0xFF).

2. Typical values at 25°C. Maximum values are characterized values and not test limits in production.

3. The current consumption values include input leakage current.

TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)

Symbol Parameter Condition Min. Typ.(2) Max. Units

ICC

Power Supply Current(1)

Active 1 MHz, VCC = 2V 0.3 0.5 mA

Active 4 MHz, VCC = 3V 1.7 2.5 mA

Active 8 MHz, VCC = 5V 6.3 9 mA

Idle 1 MHz, VCC = 2V 0.05 0.15 mA

Idle 4 MHz, VCC = 3V 0.3 0.7 mA

Idle 8 MHz, VCC = 5V 1.4 2.7 mA

Power-save mode(3)

32 kHz TOSC enabled,

VCC = 1.8V 0.72 TBD µA

32 kHz TOSC enabled,

VCC = 3V 0.9 TBD µA

Power-down mode(3) WDT enabled, VCC = 3V 4.4 8 µA

WDT disabled, VCC = 3V 0.2 2 µA

TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)

Symbol Parameter Condition Min. Typ.(2) Max. Units

ICC

Power Supply Current(1)

Active 1 MHz, VCC = 2V 0.3 0.5 mA

Active 4 MHz, VCC = 3V 1.8 2.5 mA

Active 8 MHz, VCC = 5V 6.7 9 mA

Idle 1 MHz, VCC = 2V 0.06 0.15 mA

Idle 4 MHz, VCC = 3V 0.4 0.7 mA

Idle 8 MHz, VCC = 5V 1.7 2.7

Power-save mode(3)

32 kHz TOSC enabled,

VCC = 1.8V 0.8 TBD µA

32 kHz TOSC enabled,

VCC = 3V 0.9 TBD µA

Power-down mode(3) WDT enabled, VCC = 3V 4.6 8 µA

WDT disabled, VCC = 3V 0.1 2 µA

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28.3 Speed GradesMaximu m frequency is dependent on VCC. As shown in Figure 28-1 and Figure 28-2, the Ma xi-

mum Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC <

4.5V.

Figure 28-1. Maximum Frequency vs. VCC, ATmega48P/88P/168PV

Figure 28-2. Maximum Frequency vs. VCC, ATmega48P/88P/168P

4 MHz

1.8V 2.7V 4.5V

10 MHz

20 MHz

5.5V

Safe Operating Area

4 MHz

1.8V 2.7V 4.5V

10 MHz

20 MHz

5.5V

Safe Operating Area

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Figure 28-3. Maximum Frequency vs. VCC, ATmega328P

4 MHz

1.8V 2.7V 4.5V

10 MHz

20 MHz

5.5V

Safe Operating Area

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28.4 Clock Characteristics

28.4.1 Calibrated Internal RC Oscillator Accuracy

Notes: 1. Voltage range for ATmega48PV/88PV/168PV/328PV.

2. Voltage range for ATmega48P/88P/168P/328P.

28.4.2 External Clock Drive Waveforms

Figure 28-4. External Clock Drive Waveforms

28.4.3 External Clock Drive

Note: All DC Cha racteristics contained in this datasheet are based on simulation and characterization of other AVR microcontrollers

manufactured in the same process technology. These values are preliminary values representing design targets, and will be

updated after characterization of actual silicon.

Table 28-1. Calibration Accuracy of Internal RC Oscillator

Frequency VCC Temperature Calibration Accuracy

Factory

Calibration 8.0 MHz 3V 25°C±10%

User

Calibration 7.3 - 8.1 MHz 1.8V - 5.5V(1)

2.7V - 5.5V(2) -40°C - 85°C±1%

IL1

IH1

Table 28-2. External Clock Drive

Symbol Parameter

VCC=1.8-5.5V VCC=2.7-5.5V VCC=4.5-5.5V

UnitsMin. Max. Min. Max. Min. Max.

1/tCLCL Oscillator Frequency 0 4 0 10 0 20 MHz

tCLCL Clock Period 250 100 50 ns

tCHCX High Time 100 40 20 ns

tCLCX Low Time 100 40 20 ns

tCLCH Rise Time 2.0 1.6 0.5 μs

tCHCL Fall Time 2.0 1.6 0.5 μs

ΔtCLCL

Change in per iod from

one clock cycle to the

next 222%

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28.5 System and Reset Characteristics

Notes: 1. Values are gu i de l i ne s only. Actual values are TBD.

2. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling)

Notes: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is

tested down to VCC = VBOT during the production test. This guarantees that a Brown-Out Reset will occur before VCC drops to

a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using

BODLEVEL = 110 and BODLEVEL = 101 for ATmega48P/88P/168PV and ATmega328P, and BODLEVEL = 101 and

BODLEVEL = 1 00 for ATmega48 P/88P/168P/328P.

Table 28-3. Re se t, Brown-ou t an d In te rna l Voltage Characteristics (1)

Symbol Parameter Min Typ Max Units

VPOT Power-on Reset Threshold Voltage (rising) 1.1 1.4 1.6 V

Power-on Reset Threshold Voltage (falling)(2) 0.6 1.3 1.6 V

SRON Power-on Slope Rate 0.01 10 V/ms

VRST RESET Pin Threshold Voltage 0.2 VCC 0.9 VCC V

tRST Minimum pulse width on RESET Pin 2.5 µs

VHYST Brown-out Detector Hysteresis 50 mV

tBOD Min Pulse Width on Brown-out Reset 2 µs

VBG Bandgap reference voltage VCC=2.7

TA=25°C 1.0 1.1 1.2 V

tBG Bandgap reference start-up time VCC=2.7

TA=25°C 40 70 µs

IBG Bandgap reference current consumption VCC=2.7

TA=25°C 10 µA

Table 28-4. BODLEVEL Fuse Coding(1)

BODLEVEL 2:0 Fuses Min VBOT Typ VBOT Max VBOT Units

111 BOD Disabled

110 1.7 1.8 2.0

V101 2.5 2.7 2.9

100 4.1 4.3 4.5

011

Reserved

010

001

000

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28.6 SPI Timing Characteristics

See Figure 28-5 and Figure 28-6 for details.

Note: 1. I n SPI Programming mode the minimum SCK high/low period is:

- 2 tCLCL for fCK < 12 MHz

- 3 tCLCL for fCK > 12 MHz

2. All DC Characteristics contained in this datasheet are based on simulation and characteriza-

tion of other AVR microcontrollers manufactured in the same process technology. These

values are preliminary values representing design targets, and will be updated after character-

ization of actual silicon.

Table 28-5. SPI Timing Parameters

Description Mode Min Typ Max

1 SCK period Master See Table 18-5

2 SCK high/low Master 50% duty cycle

3 Rise/Fall time Master 3.6

4 Setup Master 10

5Hold Master 10

6 Out to SCK Master 0.5 • tsck

7 SCK to out Master 10

8 SCK to out high Master 10

9SS

low to out Slave 15

10 SCK period Slave 4 • tck

11 SCK high/low(1) Slav e 2 • tck

12 Rise/Fall time Slave 1600

13 Setup Slave 10

14 Hold Slave tck

15 SCK to out Sla ve 15

16 SCK to SS high Slave 20

17 SS high to tri-state Slave 10

18 SS low to SCK Slave 20

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Figure 28-5. SPI Interface Timing Requirements (Master Mode)

Figure 28-6. SPI Interface Timing Requirements (Slave Mode)

MOSI

(

Data Output)

SCK

(CPOL = 1)

MISO

(Data Input)

SCK

(CPOL = 0)

MSB LSB

LSBMSB

...

345

MISO

(

Data Output)

SCK

(CPOL = 1)

MOSI

(Data Input)

SCK

(CPOL = 0)

MSB LSB

LSBMSB

...

11 11

1213 14

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28.7 2-wire Serial Interface Characteristics

Table 28-6 describes th e requirement s for devices connecte d to the 2-wir e Serial Bus. The ATm ega48P/88P/1 68P/328P 2-

wire Serial Interface meets or exceeds these requirements under the noted conditions.

Timing symbols refer to Figure 28-7.

Notes: 1. In ATmega48P/88P/168P/328P, this parameter is characterized and not 100% tested.

2. Required only for fSCL > 100 kHz.

Table 28-6. 2-wire Serial Bus Requirements

Symbol Parameter Condition Min Max Units

VIL Input Low-voltage -0.5 0.3 VCC V

VIH Input High-voltage 0.7 VCC VCC + 0.5 V

Vhys(1) Hysteresis of Schmitt Trigger Inputs 0.05 VCC(2) –V

VOL(1) Output Low-voltage 3 mA sink current 0 0.4 V

tr(1) Rise Time for both SDA and SCL 20 + 0.1Cb(3)(2) 300 ns

tof(1) Output Fall Time from VIHmin to VILmax 10 pF < Cb < 400 pF(3) 20 + 0.1Cb(3)(2) 250 ns

tSP(1) Spikes Suppressed by Input Filter 0 50(2) ns

IiInput Current each I/O Pin 0.1VCC < Vi < 0.9VCC -10 10 µA

Ci(1) Capacitance for each I/O Pin – 10 pF

fSCL SCL Clock Frequency fCK(4) > max(16fSCL, 250kHz)(5) 0 400 kHz

Rp Value of Pull-up resistor

fSCL ≤ 100 kHz

fSCL > 100 kHz

tHD;STA Hold Time (repeated) START Condition fSCL ≤ 100 kHz 4.0 – µs

fSCL > 100 kHz 0.6 – µs

tLOW Low Period of the SCL Clock fSCL ≤ 100 kHz(6) 4.7 – µs

fSCL > 100 kHz(7) 1.3 – µs

tHIGH High period of the SCL clock fSCL ≤ 100 kHz 4.0 – µs

fSCL > 100 kHz 0.6 – µs

tSU;STA Set-up tim e for a repeated START condition fSCL ≤ 100 kHz 4.7 – µs

fSCL > 100 kHz 0.6 – µs

tHD;DAT Data hold time fSCL ≤ 100 kHz 0 3.45 µs

fSCL > 100 kHz 0 0.9 µs

tSU;DAT Data setup time fSCL ≤ 100 kHz 250 – ns

fSCL > 100 kHz 100 – ns

tSU;STO Setup time for STOP condition fSCL ≤ 100 kHz 4.0 – µs

fSCL > 100 kHz 0.6 – µs

tBUF Bus free time between a STOP and START

condition fSCL ≤ 100 kHz 4.7 – µs

fSCL > 100 kHz 1.3 – µs

VCC 0,4V

–

3mA

-----------------------

----

1000ns

-----------------Ω

VCC 0,4V

–

3mA

-----------------------

----

300ns

--------------Ω

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ATmega48P/88P/168P/328P

3. Cb = capacitance of one bus line in pF.

4. fCK = CPU clock frequency

5. This requirement applies to all ATmega48P/88P/168P/328P 2-wire Se rial Interface operation. Other devices connected to

the 2-wire Seri al Bus need only obey the general fSCL requirement.

6. The actual low period generated by the ATmega48P/88P/168P/328P 2-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must

be greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.

7. The actual low period generated by the ATmega48P/88P/168P/328P 2-wire Serial Interface is (1/fSCL - 2/fCK), thus the low

time requirement will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega48P/88P/168P/328P devices con-

nected to the bus may communicate at full speed (400 kHz) with other ATmega48P/88P/168P/328P devices, as well as any

other device with a proper tLOW acceptance margin.

Figure 28-7. 2-wire Serial Bus Timing

SU;STA

LOW

HIGH

LOW

HD;STA

HD;DAT

SU;DAT

SU;STO

BUF

SCL

SDA

324 8025D–AVR–03/08

ATmega48P/88P/168P/328P

28.8 ADC Characteristics – Preliminary Data

Note: 1. AVCC absolute min/max: 1.8V/5.5V

Table 28-7. ADC Characteristics

Symbol Parameter Condition Min Typ Max Units

Resolution 10 Bits

Absolute accuracy (Including

INL, DNL, quantization error ,

gain and offset error)

VREF = 4V, VCC = 4V,

ADC clock = 200 kHz 22.5LSB

VREF = 4V, VCC = 4V,

ADC clock = 1 MHz 4.5 LSB

VREF = 4V, VCC = 4V,

ADC clock = 200 kHz

Noise Reduction Mode 2LSB

VREF = 4V, VCC = 4V,

ADC clock = 1 MHz

Noise Reduction Mode 4.5 LSB

Integral Non-Linearity (INL) VREF = 4V, VCC = 4V,

ADC clock = 200 kHz 0.5 LSB

Differential Non-Line arity

(DNL) VREF = 4V, VCC = 4V,

ADC clock = 200 kHz 0.25 LSB

Gain Error VREF = 4V, VCC = 4V,

ADC clock = 200 kHz 2LSB

Offset Error VREF = 4V, VCC = 4V,

ADC clock = 200 kHz 2LSB

Conversion Time F ree Running Conversion 13 260 µs

Clock Frequency 50 1000 kHz

AVCC(1) Analog Supply Voltage VCC - 0.3 VCC + 0.3 V

VREF Reference Voltage 1.0 AVCC V

VIN Input Voltage GND VREF V

Input Bandwidth 38.5 kHz

VINT Internal Voltage Reference 1.0 1.1 1.2 V

RREF Reference Input Resistance 32 kΩ

RAIN Analog Input Resistance 100 MΩ

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28.9 Parallel Programming Characteristics

Notes: 1. tWLRH is valid for the Write Flash, Wr ite EEPROM, Wr ite Fuse bits and Write Lock bits

commands.

2. tWLRH_CE is valid for the Chip Erase command.

Table 28-8. Parallel Programming Charac teristics, VCC = 5V ± 10%

Symbol Parameter Min Typ Max Units

VPP Programming Enable Voltage 11.5 12.5 V

IPP Programming Enable Current 250 μA

tDVXH Data and Control Valid before XTAL1 High 67 ns

tXLXH XTAL1 Low to XTAL1 High 200 ns

tXHXL XTAL1 Pulse Width High 150 ns

tXLDX Data and Control Hold after XTAL1 Low 67 ns

tXLWL XTAL1 Low to WR Low 0 ns

tXLPH XTAL1 Low to PAGEL high 0 ns

tPLXH PAGEL low to XTAL1 high 150 ns

tBVPH BS1 Valid before PAGEL High 67 ns

tPHPL PAGEL Pulse Width High 150 ns

tPLBX BS1 Hold after PAGEL Low 67 ns

tWLBX BS2/1 H ol d after WR Low 67 ns

tPLWL PAG EL Low to WR Low 67 ns

tBVWL BS1 Valid to WR Low 67 ns

tWLWH WR Pulse Width Low 150 ns

tWLRL WR Low to RDY/BSY Low 0 1 μs

tWLRH WR Low to RDY/BSY High(1) 3.7 4.5 ms

tWLRH_CE WR Low to RDY/BSY High for Chip Erase(2) 7.5 9 ms

tXLOL XTAL1 Low to OE Low 0 ns

tBVDV BS1 Valid to DATA valid 0 250 ns

tOLDV OE Low to DATA Valid 250 ns

tOHDZ OE High to DATA Tri-stated 250 ns

326 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 28-8. Parallel Programming Timing, Including some General Timing Requirements

Figure 28-9. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)

Note: 1. The timing requirements shown in Figure 28-8 (i.e., tDVXH, tXHXL, and tXLDX) also apply to load-

ing operation.

Figure 28-10. Parallel Programming Timing, Reading Sequence (within the Same Page) with

Timing Requirements(1)

Note: 1. The timing requirements shown in Fi gure 28-8 (i.e., tDVXH, tXHXL, and tXLDX) also apply to read-

ing operation.

Data & Contol

(

DATA, XA0/1, BS1, BS2)

XTAL1

XHXL

WLWH

DVXH

XLDX

PLWL

WLRH

RDY/BSY

PAGEL

PHPL

PLBX

BVPH

XLWL

WLBX

BVWL

WLRL

XTAL1

AGEL

PLXH

XLXH

XLPH

ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)

DATA

BS1

XA0

XA1

LOAD ADDRESS

(LOW BYTE) LOAD DATA

(HIGH BYTE)

LOAD DATA

LOAD ADDRESS

(LOW BYTE)

TAL1

ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)

DATA

BS1

XA0

XA1

LOAD ADDRESS

(LOW BYTE) READ DATA

(HIGH BYTE) LOAD ADDRESS

(LOW BYTE)

BVDV

OLDV

XLOL

OHDZ

327

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ATmega48P/88P/168P/328P

29. Typical Characteristics

The following charts show typical behavior. These figures are not tested during m anufacturing.

All current consumption measurements are performed with all I/O pins configured as inputs and

with internal pull-ups enabled. A square wave generator with rail-to-rail outpu t is used as clock

source.

All Active- and Idle curr ent consump tion measurement s are done with all bits in t he PRR register

set and thus, the corresponding I/O modules are turned off. Also the Analog Comparator is dis-

abled during these measurements. The ”Supply Cu rrent of IO M odules” on page 333, page 357

and page 381 shows the additional current consumption compared to ICC Active and ICC Idle for

every I/O module controlled by the Power Reduction Register. See ”Power Reduction Register”

on page 43 for details.

The power consumption in Power-down mode is independent of clock selection.

The current consumption is a function of several factors such as: operating voltage, operating

frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient tempera-

ture. The dominating factors are operating voltage and frequency.

The current drawn fr om capacitive loaded pin s may be estimated (for on e pin) as CL*VCC*f where

CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to

function properly at frequencies higher than the ordering code indicates.

The difference between current consumption in Power-down mode with Watchdog Timer

enabled and Power-down mode with Watchdog Timer disabled represents the differential cur-

rent drawn by the Watchdog Timer.

328 8025D–AVR–03/08

ATmega48P/88P/168P/328P

29.1 ATmega48P Typical Characteristics

29.1.1 Active Supply Cu rrent

Figure 29-1. Active Supply Current vs. Low Frequency (0.1-1.0 MHz).

Figure 29-2. Active Supply Current vs. Frequency (1-20 MHz).

ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY

0.1-1.0 MHz

5.5 V

5.0 V

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

0.2

0.4

0.6

0.8

1.2

1.4

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (MHz)

(mA)

ACTIVE SUPPLY CURRENT vs. FREQUENCY

1-20MHz

02468101214161820

Frequency (MHz)

(mA)

1.8V

2.7V

3.3V

4.0V

4.5V

5.0V

5.5V

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ATmega48P/88P/168P/328P

Figure 29-3. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz).

Figure 29-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz).

ACTIVE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 128 KHz

85 °C

25 °C

-40 °C

0,02

0,04

0,06

0,08

0,1

0,12

0,14

0,16

0,18

1,5 2 2,5 3 3,5 4 4,5 5 5,5

(V)

(mA)

ACTIVE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 1 MHz

85 °C

25 °C

-40 °C

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

(mA)

330 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-5. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz).

29.1.2 Idle Supply Current

Figure 29-6. Idle Supply Current vs. Low Frequency (0.1-1.0 MHz).

ACTIVE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 8 MHz

85 °C

25 °C

-40 °C

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(mA)

IDLE SUPPLY CURRENT vs. LOW FREQUENCY

0.1-1.0 MHz

5.5 V

5.0 V

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (MHz)

(mA)

331

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ATmega48P/88P/168P/328P

Figure 29-7. Idle Supply Current vs. Frequen cy (1 -20 MHz).

Figure 29-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz).

IDLE SUPPLY CURRENT vs. FREQUENCY

1-20 MHz

5.5 V

5.0 V

4.5 V

0 2 4 6 8 101214161820

Frequency (MHz)

ICC (mA)

1.8V

2.7V

3.3V

4.0V

IDLE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 128 KHz

85 °C

25 °C

-40 °C

0.01

0.02

0.03

0.04

0.05

0.06

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(mA)

332 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz).

Figure 29-10. Idle Supply Current vs. Vcc (Internal RC Oscillator, 8 MHz).

IDLE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 1 MHz

85 °C

25 °C

-40 °C

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(mA)

IDLE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 8 MHz

85 °C

25 °C

-40 °C

0.5

1.5

2.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

(mA)

333

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ATmega48P/88P/168P/328P

29.1.3 Supply Current of IO Modules

The tables and formulas below can b e used to calculate the additional current consumption for

the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules

are controlled by the Powe r Reduction Regist er. See ”P ower Reduction Regist er” on pag e 43 for

details.

It is possible to calcu late t he typical cur rent co nsumption b ased on the n umber s from Tab le 29-2

on page 333 for other VCC and frequency settings than listed in Table 29-1 on page 333.

Example Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled

at VCC = 2.0V and F = 1MHz. From Table 29-2 on page 333, third column, we see that we need

to add 16.1% for the TIMER1, 15.5% for the ADC, and 13.4% for the SPI module. Reading from

Figure 29-6 on page 330, we find that the idle current consumption is ~0.055 mA at VCC = 2.0V

and F = 1MHz. The total cur rent consum ption in id le mode with TIMER1, ADC, and SPI en abled,

gives:

Table 29-1. Additional Current Consumption for the different I/O modules (absolute values)

PRR bit Typical numbers

VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz

PRUSART0 5.58 uA 35.6 uA 136.5 uA

PRTWI 8.97 uA 57.0 uA 231.5 uA

PRTIM2 9.84 uA 64.7 uA 263.5 uA

PRTIM1 9.80 uA 62.8 uA 247.9 uA

PRTIM0 2.31 uA 15.3 uA 60.9 uA

PRSPI 7.88 uA 51.9 uA 215.7 uA

PRADC 9.35 uA 60.5 uA 237.7 uA

Table 29-2. Additional Current Consumption (percentage) in Active and Idle mode

PRR bit

Additional Current consumption

compared to Active with external

clo ck (see Figure 29-1 on page

328 and Figure 29-2 on page 328)

Additional Current consumption

compared to Idle with external

clock (see Figure 29-6 on pa ge

330 and Figure 29-7 on page 331)

PRUSART0 1.9% 9.1%

PRTWI 3.1% 14.8%

PRTIM2 3.5% 16.6%

PRTIM1 3.4% 16.1%

PRTIM0 0.8% 3.9%

PRSPI 2.8% 13.4%

PRADC 3.3% 15.5%

ICCtotal 0.055 mA (1 + 0.161 + 0.155 + 0.134)⋅0.080 mA≈≈

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29.1.4 Power-down Supply Current

Figure 29-11. Power-Down Supply Current vs. VCC (Watchdog Timer Disabled).

Figure 29-12. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled).

POWER-DOWN SUPPLY CURRENT vs. VCC

WATCHDOG TIMER DISABLED

85 °C

25 °C

-40 °C

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(uA)

POWER-DOWN SUPPLY CURRENT vs. V

WATCHDOG TIMER ENABLED

85 °C

25 °C

-40 °C

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(uA)

335

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ATmega48P/88P/168P/328P

29.1.5 Power-save Supply Current

Figure 29-13. Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32 kHz Crys-

tal Oscillator Running).

29.1.6 Standby Supply Current

Figure 29-14. Standby Supply Current vs. Vcc (Watchdog Timer Disabled).

POWER-SAVE SUPPLY CURRENT vs. V

WATCHDOG TIMER DISABLED and 32 kHz CRYSTAL OSCILLATOR RUNNING

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.82.32.83.33.84.34.85.35.8

(V)

(uA)

25 °C

STANDBY SUPPLY CURRENT vs. V

WATCHDOG TIMER DISABLED

6MHz_xtal

6MHz_res

4MHz_xtal

4MHz_res

450kHz_res

2MHz_xtal

2MHz_res

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

0.2

1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8

(V)

(mA)

336 8025D–AVR–03/08

ATmega48P/88P/168P/328P

29.1.7 Pin Pull-Up

Figure 29-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V).

Figure 29-16. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V).

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

Vcc = 1.8 V

0 0.5 1 1.5 2 2.5 3

(V)

(uA)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

= 2.7 V

0 0.5 1 1.5 2 2.5 3

(V)

(uA)

337

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ATmega48P/88P/168P/328P

Figure 29-17. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5 V).

Figure 29-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8 V).

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

Vcc = 5 V

100

120

140

160

0123456

(V)

IOP (uA)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

VCC = 1.8 V

85 °C

25 °C

-40 °C

-5

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

VRESET (V)

IRESET (uA)

338 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V).

Figure 29-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5 V).

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

= 2.7 V

85 °C

25 °C

-40 °C

-10

0 0.5 1 1.5 2 2.5 3

VRESET (V)

IRESET (uA)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

= 5 V

85 °C

25 °C

-40 °C

-20

100

120

140

0123456

VRESET (V)

IRESET (uA)

339

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ATmega48P/88P/168P/328P

29.1.8 Pin Driver Strength

Figure 29-21. I/O Pin Output Voltage vs. Sink Current (VCC = 3 V).

Figure 29-22. I/O Pin Output Voltage vs. Sink Current (VCC = 5 V).

I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT

= 3 V

85 °C

25 °C

-40 °C

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

(mA)

(V)

I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT

= 5 V

85 °C

25 °C

-40 °C

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0 5 10 15 20 25

(mA)

(V)

340 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-23. I/O Pin Output Voltage vs. Source Current (Vcc = 3 V).

Figure 29-24. I/O Pin Output Voltage vs. Source Current(VCC = 5 V).

I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT

VCC = 3 V

85 °C

25 °C

-40 °C

0.5

1.5

2.5

3.5

0 5 10 15 20 25

(mA)

(V)

I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT

VCC = 5 V

85 °C

25 °C

-40 °C

4.3

4.4

4.5

4.6

4.7

4.8

4.9

5.1

0 5 10 15 20 25

IOH (mA)

(V)

341

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29.1.9 Pin Threshold and Hysteresis

Figure 29-25. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’).

Figure 29-26. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’).

I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC

VIH, IO PIN READ AS '1'

85 °C

25 °C

-40 °C

0.5

1.5

2.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

Threshold (V)

I/O PIN INPUT THRESHOLD VOLTAGE vs. V

VIL, IO PIN READ AS '0'

85 °C

25 °C

-40 °C

0.5

1.5

2.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Threshold (V)

342 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-27. I/O Pin Input Hysteresis vs. VCC.

Figure 29-28. Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’).

I/O PIN INPUT HYSTERESIS vs. V

85 °C

25 °C

-40 °C

0.1

0.2

0.3

0.4

0.5

0.6

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Input Hysteresis (mV)

RESET INPUT THRESHOLD VOLTAGE vs. V

VIH, IO PIN READ AS '1'

85 °C

25 °C

-40 °C

0.5

1.5

2.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

Threshold (V)

343

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ATmega48P/88P/168P/328P

Figure 29-29. Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’).

Figure 29-30. Reset Pin Input Hysteresis vs. VCC.

RESET INPUT THRESHOLD VOLTAGE vs. V

VIL, IO PIN READ AS '0'

85 °C

25 °C

-40 °C

0.5

1.5

2.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Threshold (V)

RESET PIN INPUT HYSTERESIS vs. V

85 °C

25 °C

-40 °C

0.1

0.2

0.3

0.4

0.5

0.6

0.7

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Input Hysteresis (mV)

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29.1.10 BOD Threshold

Figure 29-31. BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V).

Figure 29-32. BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V).

BOD THRESHOLDS vs. TEMPERATURE

Vcc = 1.8 V

1.7

1.72

1.74

1.76

1.78

1.8

1.82

1.84

1.86

1.88

1.9

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Temperature (C)

Threshold (V)

Rising Vcc

Falling Vcc

BOD THRESHOLDS vs. TEMPERATURE

Vcc = 2.7 V

2.6

2.65

2.7

2.75

2.8

2.85

2.9

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Temperature (C)

Threshold (V)

Rising Vcc

Falling Vcc

345

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Figure 29-33. BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V).

29.1.11 Internal Oscilllator Speed

Figure 29-34. Watchdog Oscillator Frequency vs. Temperature.

BOD THRESHOLDS vs. TEMPERATURE

Vcc = 4.3V

4.2

4.25

4.3

4.35

4.4

4.45

4.5

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Temperature (C)

Threshold (V)

Rising Vcc

Falling Vcc

WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE

5.5 V

4.5 V

4.0 V

3.3 V

2.7 V

103

104

105

106

107

108

109

110

111

112

113

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Temperature

(kHz)

346 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-35. Watchdog Oscillator Frequency vs. VCC.

Figure 29-36. Calibrated 8 MHz RC Oscillator Frequency vs. VCC.

WATCHDOG OSCILLATOR FREQUENCY vs. V

85 °C

25 °C

-40 °C

103

104

105

106

107

108

109

110

111

112

113

114

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(kHz)

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. V

85 °C

25 °C

-40 °C

7.6

7.7

7.8

7.9

8.1

8.2

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(MHz)

347

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Figure 29-37. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature.

Figure 29-38. Calibrated 8 MHz RC Oscillator Frequency vs. OSC CAL Value.

CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

5.0 V

3.0 V

7.8

7.85

7.9

7.95

8.05

8.1

8.15

8.2

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Temperature

FRC (MHz)

CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

85 °C

25 °C

-40 °C

0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240

OSCCAL (X1)

(MHz)

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ATmega48P/88P/168P/328P

29.1.12 Current Consumption of Peripheral Units

Figure 29-39. ADC Current vs. VCC (AREF = AVCC).

Figure 29-40. Analog Comparator Current vs. VCC.

ADC CURRENT vs. V

AREF = AV

85 °C

25 °C

-40 °C

100

150

200

250

300

350

400

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(uA)

ANALOG COMPARATOR CURRENT vs. VCC

85 °C

25 °C

-40 °C

100

1.522.533.544.555.5

(V)

(uA)

349

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Figure 29-41. AREF External Refe re nc e Cu rr en t vs. VCC.

Figure 29-42. Brownout Detector Current vs. VCC.

AREF EXTERNAL REFERENCE CURRENT vs. V

85 °C

25 °C

-40 °C

100

120

140

160

180

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

BROWNOUT DETECTOR CURRENT vs. VCC

85 °C

25 °C

-40 °C

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

350 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-43. Programming Current vs. VCC.

29.1.13 Current Consumption in Reset and Reset Pulsewidth

Figure 29-44. Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz).

PROGRAMMING CURRENT vs. V

85 °C

25 °C

-40 °C

1.5 2 2.5 3 3.5 4 4.5 5 5.5

CC (V)

ICC (mA)

RESET SUPPLY CURRENT vs. LOW FREQUENCY

0.1 - 1.0 MHz

5.5 V

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

0.05

0.1

0.15

0.2

0.25

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (MHz)

ICC (mA)

351

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Figure 29-45. Reset Supply Current vs. Frequency (1 - 20 MHz).

RESET SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz

5.5 V

4.5 V

0.5

1.5

2.5

3.5

4.5

02468101214161820

Frequency (MHz)

(mA)

4.0 V

3.3 V

2.7 V

1.8 V

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29.2 ATmega88P Typical Characteristics

29.2.1 Active Supply Cu rrent

Figure 29-46. Active Supply Current vs. Low Fr equency (0.1-1.0 MHz).

Figure 29-47. Active Supply Current vs. Frequency (1-20 MHz).

ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY

0.1 - 1.0 MHz

5.5 V

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

0.2

0.4

0.6

0.8

1.2

1.4

0 0.1 0.2 0.30.4 0.5 0.6 0.7 0.80.91

Frequency (MHz)

(mA)

ACTIVE SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz

5.5 V

4.5 V

02468101214161820

Frequency (MHz)

(mA)

4 V

3.3 V

2.7 V

1.8 V

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Figure 29-48. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz).

Figure 29-49. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz).

ACTIVE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 128 KHz

85 °C

25 °C

-40 °C

0.05

0.1

0.15

0.2

0.25

1.5 2 2.5 33.5 4 4.5 5 5.5

(V)

(mA)

ACTIVE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 1 MHz

85 °C

25 °C

-40 °C

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

1.5 2 2.5 33.5 4 4.5 5 5.5

(V)

(mA)

354 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-50. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz).

29.2.2 Idle Supply Current

Figure 29-51. Idle Supply Curren t vs. Low Frequency (0.1-1.0 MHz).

ACTIVE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 8 MHz

85 °C

25 °C

-40 °C

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(mA)

IDLE SUPPLY CURRENT vs. LOW FREQUENCY

0.1 - 1.0 MHz

5.5 V

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0 0.1 0.2 0.30.4 0.5 0.6 0.7 0.80.91

Frequency (MHz)

ICC (mA)

355

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Figure 29-52. Idle Supply Current vs. Freque n cy (1 -2 0 MH z).

Figure 29-53. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz).

IDLE SUPPLY CURRENT vs. FREQUENCY

1-20 MHz

5.5 V

4.5 V

0.5

1.5

2.5

3.5

4.5

02468101214161820

Frequency (MHz)

(mA)

4 V

3.3 V

2.7 V

1.8 V

IDLE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 128 KHz

85 °C

25 °C

-40 °C

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

0.045

0.05

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

(mA)

356 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-54. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz).

Figure 29-55. Idle Supply Current vs. Vcc (Internal RC Oscillator, 8 MHz).

IDLE SUPPLY CURRENT vs. VCC

INTERNAL RC OSCILLATOR, 1 MHz

85 °C

25 °C

-40 °C

0.1

0.2

0.3

0.4

0.5

0.6

1.5 2 2.5 33.5 4 4.5 5 5.5

(V)

(mA)

IDLE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 8 MHz

85 °C

25 °C

-40 °C

0.5

1.5

2.5

1.5 2 2.5 33.5 4 4.5 5 5.5

(V)

(mA)

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29.2.3 Supply Current of IO Modules

The tables and formulas below can b e used to calculate the additional current consumption for

the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules

are controlled by the Powe r Reduction Regist er. See ”P ower Reduction Regist er” on pag e 43 for

details.

It is possible to calcu late t he typical cur rent co nsumption b ased on the n umber s from Tab le 29-4

on page 357 for other VCC and frequency settings than listed in Table 29-3 on page 357.

Example Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled

at VCC = 2.0V and F = 1MHz. From Table 29-4 on page 357, third column, we see that we need

to add 17.0% for the TIMER1, 17.6% for the ADC, and 17.5% for the SPI module. Reading from

Figure 29-51 on page 354, we find that the idle current consumption is ~0.055 mA at VCC = 2.0V

and F = 1MHz. The total cur rent consum ption in id le mode with TIMER1, ADC, and SPI en abled,

gives:

Table 29-3. Additional Current Consumption for the different I/O modules (absolute values)

PRR bit Typical numbers

VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz

PRUSART0 4.12 uA 26.7 uA 108.3 uA

PRTWI 8.96 uA 58.6 uA 238.2 uA

PRTIM2 9.94 uA 64.1 uA 256.3 uA

PRTIM1 8.81 uA 56.9 uA 227.0 uA

PRTIM0 2.29 uA 15.5 uA 62.3 uA

PRSPI 8.31 uA 56.8 uA 260.4 uA

PRADC 9.27 uA 58.4 uA 230.8 uA

Table 29-4. Additional Current Consumption (percentage) in Active and Idle mode

PRR bit

Additional Current consumption

compared to Active with external

clo ck (see Figure 29-46 on page

352 and Figure 29-47 on page

352)

Additional Current consumption

compared to Idle with external

clock (see Figure 29-51 on page

354 and Figure 29-52 on page

355)

PRUSART0 1.3% 8.0%

PRTWI 2.9% 17.6%

PRTIM2 3.2% 19.2%

PRTIM1 2.8% 17.0%

PRTIM0 0.8% 4.6%

PRSPI 3.0% 17.5%

PRADC 2.9% 17.6%

ICCtotal 0.055 mA (1 + 0.170 + 0.176 + 0.175)⋅0.084 mA≈≈

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29.2.4 Power-down Supply Current

Figure 29-56. Power-Down Supply Current vs. VCC (Watchdog Timer Disabled).

Figure 29-57. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled).

POWER-DOWN SUPPLY CURRENT vs. VCC

WATCHDOG TIMER DISABLED

85 °C

25 °C

-40 °C

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

1.5 2 2.5 3 3.5 4 4.5 5 5.5

CC (V)

(uA)

POWER-DOWN SUPPLY CURRENT vs. V

WATCHDOG TIMER ENABLED

85 °C

25 °C

-40 °C

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(uA)

359

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29.2.5 Power-save Supply Current

Figure 29-58. Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32 kHz Crys-

tal Oscillator Running).

29.2.6 Standby Supply Current

Figure 29-59. Standby Supply Current vs. Vcc (Watchdog Timer Disabled).

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

(V)

(uA)

2.5 3.0 3.5 4.0 4.5 5.0 5.51.5 2.0

POWER-SAVE SUPPLY CURRENT vs. V

WATCHDOG TIMER DISABLED and 32 kHz CRYSTAL OSCILLATOR RUNNING

STANDBY SUPPLY CURRENT vs. VCC

WATCHDOG TIMER DISABLED

6MHz_xtal

6MHz_res

4MHz_xtal

4MHz_res

450kHz_res

2MHz_xtal

2MHz_res

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

1.5 2 2.5 33.5 4 4.5 5 5.5

VCC (V)

ICC (mA)

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29.2.7 Pin Pull-Up

Figure 29-60. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V).

Figure 29-61. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V).

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

VOP (V)

IOP (uA)

85 °C

25 °C

-40 °C

VCC = 1.8 V

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

0 0.5 1 1.5 2 2.5 3

(V)

(uA)

85 °C

25 °C

-40 °C

VCC = 2.7 V

361

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Figure 29-62. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5 V).

Figure 29-63. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8 V).

85 °C

25 °C

-40 °C

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

100

120

140

160

0123456

(V)

IOP (uA)

VCC = 5 V

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

= 1.8 V

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

RESET

(V)

RESET

(uA)

85 °C

25 °C

-40 °C

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ATmega48P/88P/168P/328P

Figure 29-64. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V).

Figure 29-65. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5 V).

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

VCC = 2.7 V

0 0.5 1 1.5 2 2.5 3

VRESET (V)

IRESET (uA)

85 °C

25 °C

-40 °C

IRESET (uA)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

VCC = 5 V

100

120

0123456

VRESET (V)

IRESET (uA)

85 °C

25 °C

-40 °C

363

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29.2.8 Pin Driver Strength

Figure 29-66. I/O Pin Output Voltage vs. Sink Current(VCC = 3 V).

Figure 29-67. I/O Pin Output Voltage vs. Sink Current(VCC = 5 V).

I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT

VCC = 3 V

85 °C

25 °C

-40 °C

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0 5 10 15 20 25

IOL (mA)

VOL (V)

I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT

= 5 V

85 °C

25 °C

-40 °C

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0 5 10 15 20 25

(mA)

(V)

364 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-68. I/O Pin Output Voltage vs. Source Current(Vcc = 3 V).

Figure 29-69. I/O Pin Output Voltage vs. Source Current(VCC = 5 V).

I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT

= 3 V

85 °C

25 °C

-40 °C

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

5.1

0 5 10 15 20 25

(mA)

(V)

I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT

= 5 V

85 °C

25 °C

-40 °C

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

0 5 10 15 20 25

(mA)

(V)

365

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29.2.9 Pin Threshold and Hysteresis

Figure 29-70. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’).

Figure 29-71. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’).

IRESET (uA)

I/O PIN INPUT THRESHOLD VOLTAGE vs. V

VIH, IO PIN READ AS '1'

85 °C

25 °C

-40 °C

0.5

1.5

2.5

3.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

Threshold (V)

IRESET (uA)

I/O PIN INPUT THRESHOLD VOLTAGE vs. V

VIL, IO PIN READ AS '0'

85 °C

25 °C

-40 °C

0.5

1.5

2.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

Threshold (V)

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Figure 29-72. I/O Pin Input Hysteresis vs. VCC.

Figure 29-73. Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’).

I/O PIN INPUT HYSTERESIS vs. V

85 °C

25 °C

-40 °C

0.1

0.2

0.3

0.4

0.5

0.6

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

Input Hysteresis (mV)

RESET INPUT THRESHOLD VOLTAGE vs. V

VIH, IO PIN READ AS '1'

85 °C

25 °C

-40 °C

0.5

1.5

2.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

Threshold (V)

367

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Figure 29-74. Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’).

Figure 29-75. Reset Pin Input Hysteresis vs. VCC.

RESET INPUT THRESHOLD VOLTAGE vs. VCC

VIL, IO PIN READ AS '0'

85 °C

25 °C

-40 °C

0.5

1.5

2.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

Threshold (V)

RESET PIN INPUT HYSTERESIS vs. V

85 °C

25 °C

-40 °C

0.1

0.2

0.3

0.4

0.5

0.6

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

Input Hysteresis (mV)

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29.2.10 BOD Threshold

Figure 29-76. BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V).

Figure 29-77. BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V).

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 1.8 V

Rising Vcc

Falling Vcc

1.5

1.6

1.7

1.8

1.9

2.1

2.2

2.3

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Temperature (C)

Threshold (V)

BOD THRESHOLDS vs. TEMPERATURE

Rising Vcc

Falling Vcc

2.5

2.55

2.6

2.65

2.7

2.75

2.8

2.85

2.9

2.95

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Temperature (C)

Threshold (V)

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Figure 29-78. BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V).

29.2.11 Internal Oscilllator Speed

Figure 29-79. Watchdog Oscillator Frequency vs. Temperature.

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 4.3 V

Rising Vcc

Falling Vcc

4.05

4.1

4.15

4.2

4.25

4.3

4.35

4.4

4.45

4.5

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Temperature (C)

Threshold (V)

5.5 V

4.0 V

3.3 V

2.7 V

WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE

100

102

104

106

108

110

112

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90

Temperature

(kHz)

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ATmega48P/88P/168P/328P

Figure 29-80. Watchdog Oscillator Frequency vs. VCC.

Figure 29-81. Calibrated 8 MHz RC Oscillator Frequency vs. VCC.

WATCHDOG OSCILLATOR FREQUENCY vs. V

85 °C

25 °C

-40 °C

102

103

104

105

106

107

108

109

110

111

112

2.5 3 3.5 4 4.5 5

(V)

(kHz)

CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. V

85 °C

25 °C

-40 °C

7.6

7.7

7.8

7.9

8.1

8.2

8.3

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

FRC (MHz)

371

8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-82. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature.

Figure 29-83. Calibrated 8 MHz RC Oscillator Frequency vs. OSC CAL Value.

CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

5.0 V

3.0 V

7.6

7.7

7.8

7.9

8.1

8.2

8.3

8.4

-50 -40 -30 -20 -10 0 10 20 30405060708090

Temperature

FRC (MHz)

CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

85 °C

25 °C

-40 °C

0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240

OSCCAL (X1)

(MHz)

372 8025D–AVR–03/08

ATmega48P/88P/168P/328P

29.2.12 Current Consumption of Peripheral Units

Figure 29-84. ADC Current vs. VCC (AREF = AVCC).

Figure 29-85. Analog Comparator Current vs. VCC.

ADC CURRENT vs. Vcc

AREF = AVCC

85 °C

25 °C

-40 °C

100

150

200

250

300

350

400

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

ANALOG COMPARATOR CURRENT vs. V

85 °C 25 °C

-40 °C

100

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(uA)

373

8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-86. AREF External Refe re nc e Cu rr en t vs. VCC.

Figure 29-87. Brownout Detector Current vs. VCC.

AREF EXTERNAL REFERENCE CURRENT vs. VCC

85 °C

25 °C

-40 °C

100

120

140

160

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(uA)

BROWNOUT DETECTOR CURRENT vs. V

85 °C

25 °C

-40 °C

100

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(uA)

374 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-88. Programming Current vs. VCC.

29.2.13 Current Consumption in Reset and Reset Pulsewidth

Figure 29-89. Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz).

PROGRAMMING CURRENT vs. VCC

85 °C

25 °C

-40 °C

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (mA)

RESET SUPPLY CURRENT vs. LOW FREQUENCY

0.1 - 1.0 MHz

5.5 V

5.0 V

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

0.05

0.1

0.15

0.2

0.25

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (MHz)

(mA)

375

8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-90. Reset Supply Current vs. Frequency (1 - 20 MHz).

RESET SUPPLY CURRENT vs. FREQUENCY

1-20 MHz

5.5 V

4.5 V

0.5

1.5

2.5

3.5

02468101214161820

Frequency (MHz)

ICC (mA)

4 V

3.3 V

2.7 V

1.8 V

376 8025D–AVR–03/08

ATmega48P/88P/168P/328P

29.3 ATmega168P Typical Characteristics

29.3.1 Active Supply Cu rrent

Figure 29-91. Active Supply Current vs. Low Fr equency (0.1-1.0 MHz).

Figure 29-92. Active Supply Current vs. Frequency (1-20 MHz).

ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY

0.1 - 1.0 MHz

5.5 V

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

0.2

0.4

0.6

0.8

1.2

1.4

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (MHz)

(mA)

ACTIVE SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz

5.5 V

4.5 V

0 2 4 6 8 10 12 14 16 18 20

Frequency (MHz)

(mA)

4.0 V

3.3 V

2.7 V

1.8 V

377

8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-93. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz).

Figure 29-94. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz).

ACTIVE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 128 KHz

85 °C

25 °C

-40 °C

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (mA)

ACTIVE SUPPLY CURRENT vs. VCC

INTERNAL RC OSCILLATOR, 1 MHz

85 °C

25 °C

-40 °C

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(mA)

378 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-95. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz).

29.3.2 Idle Supply Current

Figure 29-96. Idle Supply Curren t vs. Low Frequency (0.1-1.0 MHz).

ACTIVE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 8 MHz

85 °C

25 °C

-40 °C

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(mA)

IDLE SUPPLY CURRENT vs. LOW FREQUENCY

0.1 - 1.0 MHz

5.5 V

5.0 V

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

0.05

0.1

0.15

0.2

0.25

0.3

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (MHz)

(mA)

379

8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-97. Idle Supply Current vs. Freque n cy (1 -2 0 MH z).

Figure 29-98. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz).

IDLE SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz

5.5 V

5.0 V

4.5 V

0.5

1.5

2.5

3.5

4.5

0 2 4 6 8 10 12 14 16 18 20

Frequency (MHz)

ICC (mA)

4.0 V

3.3 V

2.7 V

1.8 V

IDLE SUPPLY CURRENT vs. VCC

INTERNAL RC OSCILLATOR, 128 KHz

85 °C

25 °C

-40 °C

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

0.045

0.05

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(mA)

380 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-99. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz).

Figure 29-100.Idle Supply Current vs. Vcc (Internal RC Oscillator, 8 MHz).

IDLE SUPPLY CURRENT vs. VCC

INTERNAL RC OSCILLATOR, 1 MHz

85 °C

25 °C

-40 °C

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(mA)

IDLE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 8 MHz

85 °C

25 °C

-40 °C

0.5

1.5

2.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(mA)

381

8025D–AVR–03/08

ATmega48P/88P/168P/328P

29.3.3 Supply Current of IO Modules

The tables and formulas below can b e used to calculate the additional current consumption for

the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules

are controlled by the Powe r Reduction Regist er. See ”P ower Reduction Regist er” on pag e 43 for

details.

It is possible to calcu late t he typical cur rent co nsumption b ased on the n umber s from Tab le 29-6

on page 381 for other VCC and frequency settings than listed in Table 29-5 on page 381.

Example Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled

at VCC = 2.0V and F = 1MHz. From Table 29-6 on page 381, third column, we see that we need

to add 15.2% for the TIMER1, 14.5% for the ADC, and 15.8% for the SPI module. Reading from

Figure 29-96 on pag e 378 , we fi nd t hat th e idle cur rent consumpt io n is ~0.055 mA at V CC = 2.0V

and F = 1MHz. The total cur rent consum ption in id le mode with TIMER1, ADC, and SPI en abled,

gives:

Table 29-5. Additional Current Consumption for the different I/O modules (absolute values)

PRR bit Typical numbers

VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz

PRUSART0 5.54 uA 34.8 uA 133.9 uA

PRTWI 10.1 uA 6 3.1 uA 250.6 uA

PRTIM2 10.4 uA 68.5 uA 269.4 uA

PRTIM1 9.66 uA 62.9 uA 248.1 uA

PRTIM0 2.45 uA 14.1 uA 60.8 uA

PRSPI 9.55 uA 63.8 uA 275.6 uA

PRADC 9.04 uA 58.6 uA 243.9 uA

Table 29-6. Additional Current Consumption (percentage) in Active and Idle mode

PRR bit

Additional Current consumption

compared to Active with external

clo ck (see Figure 29-91 on page

376 and Figure 29-92 on page

376)

Additional Current consumption

compared to Idle with external

clock (see Figure 29-96 on page

378 and Figure 29-97 on page

379)

PRUSART0 1.9% 8.5%

PRTWI 3.4% 15.6%

PRTIM2 3.6% 16.5%

PRTIM1 3.4% 15.2%

PRTIM0 0.8% 3.7%

PRSPI 3.5% 15.8%

PRADC 3.2% 14.5%

ICCtotal 0.065 mA (1 + 0.152 + 0.145 + 0.158)⋅0.095 mA≈≈

382 8025D–AVR–03/08

ATmega48P/88P/168P/328P

29.3.4 Power-down Supply Current

Figure 29-101.Power-Down Supply Current vs. VCC (Watchdog Timer Disa ble d ).

Figure 29-102.Power-Down Supply Current vs. VCC (Watchdog Time r Ena b led ).

POWER-DOWN SUPPLY CURRENT vs. VCC

WATCHDOG TIMER DISABLED

85 °C

25 °C

-40 °C

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(uA)

POWER-DOWN SUPPLY CURRENT vs. VCC

WATCHDOG TIMER ENABLED

85 °C

25 °C

-40 °C

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(uA)

383

8025D–AVR–03/08

ATmega48P/88P/168P/328P

29.3.5 Power-save Supply Current

Figure 29-103.Power-Save Supply Current vs. VCC (Watchdog Timer Disabl ed and 32 kHz

Crystal Oscillator Running).

29.3.6 Standby Supply Current

Figure 29-104.Standby Supply Current vs. Vcc (Watchd og Timer Disabled).

POWER-SAVE SUPPLY CURRENT vs. VCC

WATCHDOG TIMER DISABLED and 32 kHz CRYSTAL OSCILLATOR RUNNING

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.5 2 2.5 33.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

25 °C

STANDBY SUPPLY CURRENT vs. VCC

WATCHDOG TIMER DISABLED

6MHz_xtal

6MHz_res

4MHz_xtal

4MHz_res

2MHz_xtal

2MHz_res

1MHz_res

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

0.2

1.5 2 2.5 33.5 4 4.5 5 5.5

(V)

(mA)

384 8025D–AVR–03/08

ATmega48P/88P/168P/328P

29.3.7 Pin Pull-Up

Figure 29-105.I/O Pin Pull-u p Resistor Curren t vs. In pu t Volta g e (VCC = 1.8 V).

Figure 29-106.I/O Pin Pull-u p Resistor Curren t vs. In pu t Volta g e (VCC = 2.7 V).

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

= 1.8V

85 °C

25 °C

-40 °C

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

(V)

IOP (uA)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

= 2.7V

85 °C

25 °C

-40 °C

0 0.5 1 1.5 2 2.5 3

(V)

(uA)

385

8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-107.I/O Pin Pull-u p Resistor Curren t vs. In pu t Volta g e (VCC = 5 V).

Figure 29-108.Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8 V).

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

= 5V

85 °C

25 °C

-40 °C

100

120

140

160

0123456

(V)

IOP (uA)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

=1.8V

25 °C

85 °C

-40 °C

00.2

0.40.811.21.41.61.82

RESET

(V)

RESET

(uA)

0.6

386 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-109.Reset Pull-up Resistor Current vs. Reset Pin Voltage (V CC = 2.7 V).

Figure 29-110.Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5 V).

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

=2.7V

-40 °C

25 °C

85 °C

0 0.5 1 1.5 2 2.5 3

RESET

(V)

RESET

(uA)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

=5V

85 °C

25 °C

-40 °C

100

120

0123456

RESET

(V)

RESET

(uA)

387

8025D–AVR–03/08

ATmega48P/88P/168P/328P

29.3.8 Pin Driver Strength

Figure 29-111.I/O Pin Outpu t Volta ge vs. Sink Curr en t( V CC = 3 V).

Figure 29-112.I/O Pin Outpu t Volta ge vs. Sink Current(V CC = 5 V).

I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT

= 3V

85 °C

25 °C

-40 °C

0.2

0.4

0.6

0.8

1.2

0 5 10 15 20 25

(mA)

(V)

I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT

= 5V, NORMAL POWER PINS

85 °C

25 °C

-40 °C

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0 5 10 15 20 25

(mA)

VOL (V)

388 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-113.I/O Pin Output Voltage vs. Source Current(Vcc = 3 V).

Figure 29-114.I/O Pin Output Voltage vs. Source Current(VCC = 5 V).

I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT

= 3V, NORMAL POWER PINS

85 °C

25 °C

-40 °C

0.5

1.5

2.5

3.5

0 5 10 15 20 25

(mA)

VOH (V)

I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT

VCC = 5V, NORMAL POWER PINS

85 °C

25 °C

-40 °C

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

5.1

0 5 10 15 20 25

IOH (mA)

(V)

389

8025D–AVR–03/08

ATmega48P/88P/168P/328P

29.3.9 Pin Threshold and Hysteresis

Figure 29-115.I/O Pin Inpu t Th re sh o ld Volt ag e vs. VCC (V IH, I/O Pin read as ‘1’).

Figure 29-116.I/O Pin Inpu t Th re sh o ld Volt ag e vs. VCC (V IL, I/O Pin read as ‘0’).

I/O PIN INPUT THRESHOLD VOLTAGE vs. V

VIH, IO PIN READ AS '1'

85 °C

25 °C

-40 °C

0.5

1.5

2.5

3.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

Threshold (V)

I/O PIN INPUT THRESHOLD VOLTAGE vs. V

VIL, IO PIN READ AS '0'

85 °C

25 °C

-40 °C

0.5

1.5

2.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Threshold (V)

390 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-117.I/O Pin Input Hyst er esis vs. VCC.

Figure 29-118.Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’).

I/O PIN INPUT HYSTERESIS vs. V

85 °C

25 °C

-40 °C

0.1

0.2

0.3

0.4

0.5

0.6

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Input Hysteresis (mV)

RESET INPUT THRESHOLD VOLTAGE vs. V

VIH, IO PIN READ AS '1'

85 °C

25 °C

-40 °C

0.5

1.5

2.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

Threshold (V)

391

8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-119.Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’).

Figure 29-120.Reset Pin Input Hysteresis vs. VCC.

RESET INPUT THRESHOLD VOLTAGE vs. V

VIL, IO PIN READ AS '0'

85 °C

25 °C

-40 °C

0.5

1.5

2.5

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

Threshold (V)

RESET PIN INPUT HYSTERESIS vs. V

85°C

25°C

-40°C

0.1

0.2

0.3

0.4

0.5

0.6

1.522.533.544.555.5

(V)

Input Hysteresis (mV)

392 8025D–AVR–03/08

ATmega48P/88P/168P/328P

29.3.10 BOD Threshold

Figure 29-121.BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V).

Figure 29-122.BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V).

BOD THRESHOLDS vs. TEMPERATURE

Vcc =1.8V

1.7

1.72

1.74

1.76

1.78

1.8

1.82

1.84

1.86

1.88

1.9

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Temperature (C)

Threshold (V)

Rising Vcc

Falling Vcc

BOD THRESHOLDS vs. TEMPERATURE

Vcc = 2.7V

2,5

2.55

2.6

2.65

2.7

2.75

2.8

2.85

2.9

2.95

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Temperature (C)

Threshold (V)

Rising Vcc

Falling Vcc

393

8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-123.BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V).

29.3.11 Internal Oscilllator Speed

Figure 29-124.Watchdog Oscillator Frequency vs. Temperature.

BOD THRESHOLDS vs. TEMPERATURE

Vcc = 4.3V

4.05

4.1

4.15

4.2

4.25

4.3

4.35

4.4

4.45

4.5

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Temperature (C)

Threshold (V)

Rising Vcc

Falling Vcc

WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE

5.0 V

3.3 V

2.7 V

104

106

108

110

112

114

116

118

120

0 102030405060708090100110120

Temperature

FRC (kHz)

394 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-125.Watchdog Oscillator Frequency vs. VCC.

Figure 29-126.Calibrated 8 MHz RC Oscillator Frequency vs. VCC.

WATCHDOG OSCILLATOR FREQUENCY vs. VCC

85 °C

25 °C

109

110

111

112

113

114

115

116

117

118

119

120

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(kHz)

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE

85 °C

25 °C

7.8

7.85

7.9

7.95

8.05

8.1

2 2.5 3 3.5 4 4.5 5 5.5

(V)

FRC (MHz)

395

8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-127.Calibrated 8 MHz RC Oscillato r Frequency vs. Temperature.

Figure 29-128.Calibrated 8 MHz RC Oscillato r Frequency vs. OSCCAL Value.

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

5.5 V

2.7 V

1.8 V

7.8

7.85

7.9

7.95

8.05

8.1

8.15

0 102030405060708090100

Temperature

FRC (MHz)

CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

85 °C

25 °C

0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240

OSCCAL (X1)

(MHz)

396 8025D–AVR–03/08

ATmega48P/88P/168P/328P

29.3.12 Current Consumption of Peripheral Units

Figure 29-129.ADC Current vs. VCC (AREF = AV CC).

Figure 29-130.Analog Comparator Current vs. VCC.

ADC CURRENT vs. VCC

AREF = AVCC

85 °C

25 °C

-40 °C

100

150

200

250

300

350

400

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

ANALOG COMPARATOR CURRENT vs. V

85 °C

25 °C

-40 °C

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(uA)

397

8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-131.AREF External Reference Current vs. VCC.

Figure 29-132.Brownout Detector Current vs. VCC.

AREF CURRENT EXTERNAL REFERENCE CURRENT vs. V

85 °C

25 °C

-40 °C

100

120

140

160

180

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

ICC (uA)

BROWNOUT DETECTOR CURRENT vs. VCC

85 °C

25 °C

-40 °C

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(uA)

398 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-133.Programming Current vs. VCC.

29.3.13 Current Consumption in Reset and Reset Pulsewidth

Figure 29-134.Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz).

PROGRAMMING CURRENT vs. Vcc

85 °C

25 °C

-40 °C

1.5 2 2.5 3 3.5 4 4.5 5 5.5

(V)

(mA)

RESET SUPPLY CURRENT vs. V

0.1 - 1.0 MHz

5.5 V

5.0 V

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

0.2

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (MHz)

ICC (mA)

399

8025D–AVR–03/08

ATmega48P/88P/168P/328P

Figure 29-135.Reset Supply Current vs. Frequency (1 - 20 MHz).

RESET SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz

5.5 V

5.0 V

4.5 V

0.5

1.5

2.5

3.5

02468101214161820

Frequency (MHz)

ICC (mA)

4.0 V

3.3 V

2.7 V

1.8 V

400 8025D–AVR–03/08

ATmega48P/88P/168P/328P

30. Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0xFF) Reserved – – – – – – – –

(0xFE) Reserved – – – – – – – –

(0xFD) Reserved – – – – – – – –

(0xFC) Reserved – – – – – – – –

(0xFB) Reserved – – – – – – – –

(0xFA) Reserved – – – – – – – –

(0xF9) Reserved – – – – – – – –

(0xF8) Reserved – – – – – – – –

(0xF7) Reserved – – – – – – – –

(0xF6) Reserved – – – – – – – –

(0xF5) Reserved – – – – – – – –

(0xF4) Reserved – – – – – – – –

(0xF3) Reserved – – – – – – – –

(0xF2) Reserved – – – – – – – –

(0xF1) Reserved – – – – – – – –

(0xF0) Reserved – – – – – – – –

(0xEF) Reserved – – – – – – – –

(0xEE) Reserved – – – – – – – –

(0xED) Reserved – – – – – – – –

(0xEC) Reserved – – – – – – – –

(0xEB) Reserved – – – – – – – –

(0xEA) Reserved – – – – – – – –

(0xE9) Reserved – – – – – – – –

(0xE8) Reserved – – – – – – – –

(0xE7) Reserved – – – – – – – –

(0xE6) Reserved – – – – – – – –

(0xE5) Reserved – – – – – – – –

(0xE4) Reserved – – – – – – – –

(0xE3) Reserved – – – – – – – –

(0xE2) Reserved – – – – – – – –

(0xE1) Reserved – – – – – – – –

(0xE0) Reserved – – – – – – – –

(0xDF) Reserved – – – – – – – –

(0xDE) Reserved – – – – – – – –

(0xDD) Reserved – – – – – – – –

(0xDC) Reserved – – – – – – – –

(0xDB) Reserved – – – – – – – –

(0xDA) Reserved – – – – – – – –

(0xD9) Reserved – – – – – – – –

(0xD8) Reserved – – – – – – – –

(0xD7) Reserved – – – – – – – –

(0xD6) Reserved – – – – – – – –

(0xD5) Reserved – – – – – – – –

(0xD4) Reserved – – – – – – – –

(0xD3) Reserved – – – – – – – –

(0xD2) Reserved – – – – – – – –

(0xD1) Reserved – – – – – – – –

(0xD0) Reserved – – – – – – – –

(0xCF) Reserved – – – – – – – –

(0xCE) Reserved – – – – – – – –

(0xCD) Reserved – – – – – – – –

(0xCC) Reserved – – – – – – – –

(0xCB) Reserved – – – – – – – –

(0xCA) Reserved – – – – – – – –

(0xC9) Reserved – – – – – – – –

(0xC8) Reserved – – – – – – – –

(0xC7) Reserved – – – – – – – –

(0xC6) UDR0 USART I/O Data Register 196

(0xC5) UBRR0H USART Baud Rate Register High 200

(0xC4) UBRR0L USART Baud Rate Registe r Low 200

(0xC3) Reserved – – – – – – – –

(0xC2) UCSR0C UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 /UDORD0 UCSZ00 / UCPHA0 UCPOL0 198/213

(0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 197

(0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 196

401

8025D–AVR–03/08

ATmega48P/88P/168P/328P

(0xBF) Reserved – – – – – – – –

(0xBE) Reserved – – – – – – – –

(0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 –245

(0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –TWIE 242

(0xBB) TWDR 2-wire Serial Interface Data Register 244

(0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 245

(0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 –TWPS1TWPS0 244

(0xB8) TWBR 2-wire Serial Interface Bit Rate Register 242

(0xB7) Reserved – – – – – – –

(0xB6) ASSR – EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB 165

(0xB5) Reserved – – – – – – – –

(0xB4) OCR2B Timer/Counter2 Output Compare Register B 163

(0xB3) OCR2A Timer/Counter2 Output Compare Register A 163

(0xB2) TCNT2 Timer/Counter2 (8 -bit) 163

(0xB1) TCCR2B FOC2A FOC2B –– WGM22 CS22 CS21 CS20 162

(0xB0) TCCR2A COM2A1 COM2A0 COM2B1 COM2B0 ––WGM21WGM20 159

(0xAF) Reserved – – – – – – – –

(0xAE) Reserved – – – – – – – –

(0xAD) Reserved – – – – – – – –

(0xAC) Reserved – – – – – – – –

(0xAB) Reserved – – – – – – – –

(0xAA) Reserved – – – – – – – –

(0xA9) Reserved – – – – – – – –

(0xA8) Reserved – – – – – – – –

(0xA7) Reserved – – – – – – – –

(0xA6) Reserved – – – – – – – –

(0xA5) Reserved – – – – – – – –

(0xA4) Reserved – – – – – – – –

(0xA3) Reserved – – – – – – – –

(0xA2) Reserved – – – – – – – –

(0xA1) Reserved – – – – – – – –

(0xA0) Reserved – – – – – – – –

(0x9F) Reserved – – – – – – – –

(0x9E) Reserved – – – – – – – –

(0x9D) Reserved – – – – – – – –

(0x9C) Reserved – – – – – – – –

(0x9B) Reserved – – – – – – – –

(0x9A) Reserved – – – – – – – –

(0x99) Reserved – – – – – – – –

(0x98) Reserved – – – – – – – –

(0x97) Reserved – – – – – – – –

(0x96) Reserved – – – – – – – –

(0x95) Reserved – – – – – – – –

(0x94) Reserved – – – – – – – –

(0x93) Reserved – – – – – – – –

(0x92) Reserved – – – – – – – –

(0x91) Reserved – – – – – – – –

(0x90) Reserved – – – – – – – –

(0x8F) Reserved – – – – – – – –

(0x8E) Reserved – – – – – – – –

(0x8D) Reserved – – – – – – – –

(0x8C) Reserved – – – – – – – –

(0x8B) OCR1BH Timer/Counter1 - Output Compare Register B High Byte 139

(0x8A) OC R1BL Timer/Counter1 - Output Compare Register B Low Byte 139

(0x89) OCR1AH Timer/Counter1 - Output Compare Register A High Byte 139

(0x88) OCR1AL Timer/Counter1 - Output Compare Regis ter A Low Byte 139

(0x87) ICR1H Timer/Counter1 - Input Capture Register High Byte 140

(0x86) ICR1L Timer/Counter1 - Input Capture Register Low Byte 140

(0x85) TCNT1H Timer/Counter1 - Counter Re gister High Byte 139

(0x84) TCNT1L Timer/Counter1 - Counter Register Low Byte 139

(0x83) Reserved – – – – – – – –

(0x82) TCCR1C FOC1A FOC1B – – – – – –138

(0x81) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 137

(0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 ––WGM11WGM10 135

(0x7F) DIDR1 – – – – – –AIN1DAIN0D 250

(0x7E) DIDR0 –– ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 267

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

402 8025D–AVR–03/08

ATmega48P/88P/168P/328P

(0x7D) Reserved – – – – – – – –

(0x7C) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 263

(0x7B) ADCSRB –ACME – – – ADTS2 ADTS1 ADTS0 266

(0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 264

(0x79) ADCH ADC Data Register High byte 266

(0x78) ADCL ADC Data Register Low byte 266

(0x77) Reserved – – – – – – – –

(0x76) Reserved – – – – – – – –

(0x75) Reserved – – – – – – – –

(0x74) Reserved – – – – – – – –

(0x73) Reserved – – – – – – – –

(0x72) Reserved – – – – – – – –

(0x71) Reserved – – – – – – – –

(0x70) TIMSK2 – – – – – OCIE2B OCIE2A TOIE2 164

(0x6F) TIMSK1 ––ICIE1 –– OCIE1B OCIE1A TOIE1 140

(0x6E) TIMSK0 – – – – – OCIE0B OCIE0A TOIE0 112

(0x6D) PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 75

(0x6C) PCMSK1 – PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 75

(0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 75

(0x6A) Reserved – – – – – – – –

(0x69) EICRA – – – –ISC11ISC10ISC01ISC00 72

(0x68) PCICR – – – – – PCIE2 PCIE1 PCIE0

(0x67) Reserved – – – – – – – –

(0x66) OSCCAL Oscillator Calibration Register 38

(0x65) Reserved – – – – – – – –

(0x64) PRR PRTWI PRTIM2 PRTIM0 – PRTIM1 PRSPI PRUSART0 PRADC 43

(0x63) Reserved – – – – – – – –

(0x62) Reserved – – – – – – – –

(0x61) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 38

(0x60) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 55

0x3F (0x5F) SREG I T H S V N Z C 10

0x3E (0x5E) SPH – – – – – (SP10) 5. SP9 SP8 13

0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 13

0x3C (0x5C) Reserved – – – – – – – –

0x3B (0x5B) Reserved – – – – – – – –

0x3A (0x5A) Reserved – – – – – – – –

0x39 (0x59) Reserved – – – – – – – –

0x38 (0x58) Reserved – – – – – – – –

0x37 (0x57) SPMCSR SPMIE (RWWSB)5. – (RWWSRE)5. BLBSET PGWRT PGERS SELFPRGEN 292

0x36 (0x56) Reserved – – – – – – – –

0x35 (0x55) MCUCR – BODS BODSE PUD –– IVSEL IVCE 45/69/93

0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF 55

0x33 (0x53) SMCR – – – –SM2SM1SM0SE 41

0x32 (0x52) Reserved – – – – – – – –

0x31 (0x51) Reserved – – – – – – – –

0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 248

0x2F (0x4F) Reserved – – – – – – – –

0x2E (0x4E) SPDR SPI Data Register 176

0x2D (0x4D) SPSR SPIF WCOL – – – – – SPI2X 175

0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 174

0x2B (0x4B) GPIOR2 General Purpose I/O Register 2 26

0x2A (0x4A) GPIOR1 General Purpose I/O Register 1 26

0x29 (0x49) Reserved – – – – – – – –

0x28 (0x48) OCR0B Timer/Counter0 Output Compare Register B

0x27 (0x47) OCR0A Timer/Counter0 Output Compare Register A

0x26 (0x46) TCNT0 Timer/Counter0 (8-bit)

0x25 (0x45) TCCR0B FOC0A FOC0B –– WGM02 CS02 CS01 CS00

0x24 (0x44) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 ––WGM01WGM00

0x23 (0x43) GTCCR TSM – – – – – PSRASY PSRSYNC 144/166

0x22 (0x42) EEARH (EEPROM Address Register High Byte) 5. 22

0x21 (0x41) EEARL EEPROM Address Register Low Byte 22

0x20 (0x40) EEDR EEPROM Data Register 22

0x1F (0x3F) EECR –– EEPM1 EEPM0 EERIE EEMPE EEPE EERE 22

0x1E (0x3E) GPIOR0 General Purpose I/O Register 0 26

0x1D (0x3D) EIMSK – – – – – –INT1INT0 73

0x1C (0x3C) EIFR – – – – – – INTF1 INTF0 73

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

403

8025D–AVR–03/08

ATmega48P/88P/168P/328P

Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O

Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The

ATmega48P/88 P/168P/328P is a complex microcontroller with more peripheral units than can be supported within the 64

location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only

the ST/STS/STD an d LD/L D S/L D D instructions ca n be use d .

5. Only valid for ATmega88P/168P.

0x1B (0x3B) PCIFR – – – – – PCIF2 PCIF1 PCIF0

0x1A (0x3A) Reserved – – – – – – – –

0x19 (0x39) Reserved – – – – – – – –

0x18 (0x38) Reserved – – – – – – – –

0x17 (0x37) TIFR2 – – – – – OCF2B OCF2A TOV2 164

0x16 (0x36) TIFR1 ––ICF1 –– OCF1B OCF1A TOV1 141

0x15 (0x35) TIFR0 – – – – – OCF0B OCF0A TOV0

0x14 (0x34) Reserved – – – – – – – –

0x13 (0x33) Reserved – – – – – – – –

0x12 (0x32) Reserved – – – – – – – –

0x11 (0x31) Reserved – – – – – – – –

0x10 (0x30) Reserved – – – – – – – –

0x0F (0x2F) Reserved – – – – – – – –

0x0E (0x2E) Reserved – – – – – – – –

0x0D (0x2D) Reserved – – – – – – – –

0x0C (0x2C) Reserved – – – – – – – –

0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 94

0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 94

0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 94

0x08 (0x28) PORTC – PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 93

0x07 (0x27) DDRC – DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 93

0x06 (0x26) PINC – PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 93

0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 93

0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 93

0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 93

0x02 (0x22) Reserved – – – – – – – –

0x01 (0x21) Reserved – – – – – – – –

0x0 (0x20) Reserved – – – – – – – –

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

404 8025D–AVR–03/08

ATmega48P/88P/168P/328P

31. Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1

ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1

ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2

SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1

SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1

SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1

SBCI Rd, K Subtract with Carr y Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1

SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2

AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1

ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1

OR Rd, Rr Log ical OR Registers Rd ← Rd v Rr Z,N,V 1

ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1

EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1

COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1

NEG Rd Two’s Comple ment Rd ← 0x00 − Rd Z,C,N,V,H 1

SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1

CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1

INC Rd Increment Rd ← Rd + 1 Z,N,V 1

DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1

TST Rd Test f or Zero or Minus Rd ← Rd • Rd Z,N,V 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1

SER Rd Set Register Rd ← 0xFF None 1

MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2

MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2

MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2

FMUL Rd , Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2

FMULSU Rd, Rr Fractional Multip ly Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC ← PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC ← Z None 2

JMP(1) k Direct Jump PC ← kNone3

RCALL k Relative Subroutine Cal l PC ← PC + k + 1 None 3

ICALL Indirect Call to (Z) PC ← ZNone3

CALL(1) k Direct Subroutine Call PC ← kNone4

RET Subroutine Return PC ← STACK None 4

RETI Interrupt Return PC ← STACK I 4

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3

CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1

CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1

CPI Rd,K Co m pare Register with Immedi ate Rd − K Z, N,V,C,H 1

SBRC Rr, b Skip if Bit in Register Cleare d if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3

SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 N one 1/2/3

SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2

BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2

BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2

BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2

BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2

BRHC k Branch if Half Car ry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2

BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/ 2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2

405

8025D–AVR–03/08

ATmega48P/88P/168P/328P

BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2

BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b Set Bit in I/O Register I/O(P,b) ← 1None2

CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0None2

LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1

LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1

ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1

ROR Rd Rotate Right Through Ca rry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1

ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1

BSET s Flag Set SREG(s) ← 1 SREG(s) 1

BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b) ← TNone1

SEC Set Carry C ← 1C1

CLC Clear Carry C ← 0 C 1

SEN Set Negative Flag N ← 1N1

CLN Clear Negative Flag N ← 0 N 1

SEZ Set Zero Flag Z ← 1Z1

CLZ Clear Zero Flag Z ← 0 Z 1

SEI Global Interrupt Enable I ← 1I1

CLI Global Interru pt Disable I ← 0 I 1

SES Set Signed Test Flag S ← 1S1

CLS Clear Signed Test Flag S ← 0 S 1

SEV Set Twos Complement Overflow. V ← 1V1

CLV Clear Twos Complement Overflow V ← 0 V 1

SET Set T in SREG T ← 1T1

CLT Clear T in SR EG T ← 0 T 1

SEH Set Half Carry Flag in SREG H ← 1H1

CLH Clear Half Carry Flag in SREG H ← 0 H 1

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr Move Between Registers Rd ← Rr None 1

MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1

LDI Rd, K Load Immediate Rd ← KNone1

LD Rd, X Load Indirect Rd ← (X) None 2

LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2

LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2

LD Rd, Y Load Indirect Rd ← (Y) None 2

LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2

LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2

LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2

LD Rd, Z Load Indirect Rd ← (Z) None 2

LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 Non e 2

LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2

LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2

LDS Rd, k Loa d Direct from SRAM Rd ← (k) None 2

ST X, Rr Store Indirect (X) ← Rr None 2

ST X+, Rr Store Indire ct and Post-Inc. (X) ← Rr, X ← X + 1 None 2

ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2

ST Y, Rr Store Indi rect (Y) ← Rr None 2

ST Y+, Rr Store Indire ct and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2

ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2

STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2

ST Z, Rr Store Indire ct (Z) ← Rr None 2

ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2

ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2

STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2

STS k, Rr St ore Dir ect to SRAM (k) ← Rr None 2

LPM Load Program Memory R0 ← (Z) N one 3

LPM Rd, Z Load Program Memory Rd ← (Z) None 3

LPM Rd, Z+ Load Program Memo ry and Post-Inc Rd ← (Z), Z ← Z+1 No n e 3

SPM Store Program Memory (Z) ← R1:R0 None -

IN Rd, P In Port Rd ← PNone1

OUT P, Rr Out Port P ← Rr None 1

PUSH Rr Push Register on Stack STACK ← Rr None 2

Mnemonics Operands Description Operation Flags #Clocks

406 8025D–AVR–03/08

ATmega48P/88P/168P/328P

Note: 1. T hese instructions are only available in ATmega168P and ATmega328P.

POP Rd Pop Register from Stack R d ← STACK None 2

MCU CONTROL INSTRUCTIONS

NOP No Operation None 1

SLEEP Sleep (see specific descr. for Sleep function) None 1

WDR Watchdog Reset (see specific descr. for WDR/timer) None 1

BREAK Break For On-chip Debug Only None N/A

Mnemonics Operands Description Operation Flags #Clocks

407

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32. Ordering Information

32.1 ATmega48P

Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restrictio n of Hazardous Substances (RoHS directive).Also

Halide free and fully Green.

3. See Figure 28-1 on page 316 and Figure 28-2 on page 316.

Speed (MHz) Power Supply Ordering Code(2) Package(1) Operational Range

10(3) 1.8 - 5.5

ATmega48PV-10AU

ATmega48PV-10MMU

ATmega48PV-10MU

ATmega48PV-10PU

32A

28M1

32M1-A

28P3

Industrial

(-40°C to 85°C)

20(3) 2.7 - 5.5

ATmega48P-20AU

ATmega48P-20MMU

ATmega48P-20MU

ATmega48P-20PU

32A

28M1

32M1-A

28P3

Industrial

(-40°C to 85°C)

Package Type

32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

28M1 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Fr ame Pac k age (QFN/MLF)

32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Fr ame Pac k age (QFN/MLF)

28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

408 8025D–AVR–03/08

ATmega48P/88P/168P/328P

32.2 ATmega88P

Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restrictio n of Hazardous Substances (RoHS directive).Also

Halide free and fully Green.

3. See Figure 28-1 on page 316 and Figure 28-2 on page 316.

Speed (MHz) Power Supply Ordering Code(2) Package(1) Operational Range

10(3) 1.8 - 5.5 ATmega88PV-10AU

ATmega88PV-10MU

ATmega88PV-10PU

32A

32M1-A

28P3

Industrial

(-40°C to 85°C)

20(3) 2.7 - 5.5 ATmega88P-20AU

ATmega88P-20MU

ATmega88P-20PU

32A

32M1-A

28P3

Industrial

(-40°C to 85°C)

Package Type

32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Fr ame Pac k age (QFN/MLF)

409

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ATmega48P/88P/168P/328P

32.3 ATmega168P

Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restrictio n of Hazardous Substances (RoHS directive).Also

Halide free and fully Green.

3. See Figure 28-1 on page 316 and Figure 28-2 on page 316.

Speed (MHz)(3) Power Supply Ordering Code(2) Package(1) Operational Range

10 1.8 - 5.5 ATmega168PV-10AU

ATmega168PV-10MU

ATmega168PV-10PU

32A

32M1-A

28P3

Industrial

(-40°C to 85°C)

20 2.7 - 5.5 ATmega168P-20AU

ATmega168P-20MU

ATmega168P-20PU

32A

32M1-A

28P3

Industrial

(-40°C to 85°C)

Package Type

32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Fr ame Pac k age (QFN/MLF)

410 8025D–AVR–03/08

ATmega48P/88P/168P/328P

32.4 ATmega328P

Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restrictio n of Hazardous Substances (RoHS directive).Also

Halide free and fully Green.

3. See Figure 28-3 on page 317.

Speed (MHz)(3) Power Supply Ordering Code(2) Package(1) Operational Range

20 1.8 - 5.5 ATmega328P-20AU

ATmega328P-20MU

ATmega328P-20PU

32A

32M1-A

28P3

Industrial

(-40°C to 85°C)

Package Type

32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Fr ame Pac k age (QFN/MLF)

411

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33. Packaging Information

33.1 32A

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) B

32A

10/5/2001

PIN 1 IDENTIFIER

0˚~7˚

PIN 1

A1 A2 A

eE1 E

Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.10 mm maximum.

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D8.75 9.00 9.25

D1 6.90 7.00 7.10 Note 2

E8.75 9.00 9.25

E1 6.90 7.00 7.10 Note 2

B 0.30 – 0.45

C 0.09 – 0.20

L 0.45 – 0.75

e0.80 TYP

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

412 8025D–AVR–03/08

ATmega48P/88P/168P/328P

33.2 28M1

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

28M1

9/7/06

28M1, 28-pad, 4 x 4 x 1.0 mm Body, Lead Pitch 0.45 mm,

2.4 mm Exposed Pad, Micro Lead Frame Package (MLF)

SIDE VIEW

Pin 1 ID

BOTTOM VIEW

TOP VIEW

Note: The terminal #1 ID is a Laser-marked Feature.

0.45 COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A 0.80 0.90 1.00

A1 0.00 0.02 0.05

b 0.17 0.22 0.27

C 0.20 REF

D 3.95 4.00 4.05

D2 2.35 2.40 2.45

E 3.95 4.00 4.05

E2 2.35 2.40 2.45

e 0.45

L 0.35 0.40 0.45

y 0.00 – 0.08

K 0.20 – –

R 0.20

413

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ATmega48P/88P/168P/328P

33.3 32M1-A

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, E

32M1-A

5/25/06

3.10 mm Exposed Pad, Micro Lead Frame Package (MLF)

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

E1 E

0.08C

A 0.80 0.90 1.00

A1 – 0.02 0.05

A2 – 0.65 1.00

A3 0.20 REF

b 0.180.230.30

D2 2.953.10 3.25

4.90 5.00 5.10

4.70 4.75 4.80

4.90 5.00 5.10

E2 2.953.10 3.25

e 0.50 BSC

L 0.30 0.40 0.50

P – – 0.60

– – 12o

Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.

TOP VIEW

SIDE VIEW

BOTTOM VIEW

Pin 1 ID

Pin #1 Notch

(0.20 R)

K 0.20 – –

414 8025D–AVR–03/08

ATmega48P/88P/168P/328P

33.4 28P3

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual

Inline Package (PDIP) B

28P3

09/28/01

REF

SEATING PLANE

0º ~ 15º

(4 PLACES)

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A – – 4.5724

A1 0.508––

D 34.544 – 34.798 Note 1

E 7.620 – 8.255

E1 7.112 – 7.493 Note 1

B 0.381 – 0.533

B1 1.143 – 1.397

B2 0.762 – 1.143

L 3.175 – 3.429

C 0.203 – 0.356

eB – – 10.160

e 2.540 TYP

Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

415

8025D–AVR–03/08

ATmega48P/88P/168P/328P

34. Errata

34.1 Errata ATmega48P

The revision letter in this section refers to the revision of the ATmega48P device.

34.1.1 Rev. B No known errata.

34.1.2 Rev. A Not Sampled.

34.2 Errata ATmega88P

The revision letter in this section refers to the revision of the ATmega88P device.

34.2.1 Rev. A No known errata.

34.3 Errata ATmega168P

The revision lette r in this section refers to the revision of the ATmega168P device.

34.3.1 Rev A No known errata.

34.4 Errata ATmega328P

The revision lette r in this section refers to the revision of the ATmega328P device.

34.4.1 Rev B •Unstable 32 kHz Oscillator

1. Unstable 32 kHz Oscillator

The 32 kHz oscillator does not work as system clock.

The 32 kHz oscillator used as asynchronous timer is inaccurate.

Problem Fix/ Workaround

None

34.4.2 Rev A No known errata.

416 8025D–AVR–03/08

ATmega48P/88P/168P/328P

35. Datasheet Revision History

Please note that the referring page numbers in this section are referred to this document. The

referring re visio n in th is section are referring to the document revision.

35.1 Rev. 2545D-03/08

35.2 Rev. 2545C-01/08

35.3 Rev. 2545B-01/08

1. Updated figures in ”Spee d Gr ad es” on page 316 .

2. Updated note in Table 28-4 in ”System and Reset Characteristics” on page 319.

3. Ordering codes for ”ATmega328P” on page 410 updated.

- ATmega328P is offered in 20 MHz op tion only.

4. Added Errata for ATmega328P rev. B, ”Erra ta ATmega328P” on page 415.

1. Power-save Maximum values removed form ”ATmega48P DC Characteristics” on

page 314, ”ATmeg a88P DC Characteristics” on page 315, and ”ATmega168P DC

Characteristics” on page 315.

1. Updated ”Features” on page 1.

2. Added ”Data Retention” on page 8.

3. Updated Table 8-2 on page 29.

4. Removed “Low-frequency Crystal Oscillator Internal Load Capacitance“ table

from”Low Frequency Crystal Oscillator” on page 33.

5. Removed JTD bit from ”MCUCR – MCU Control Register” on page 45.

6. Updated typical and ge ner al pr og ra m setu p f or Reset an d I nt erru pt Ve cto r Add resses

in ”Interrupt Vectors in ATmega168P” on page 63 and ”Interrupt Vectors in

ATmega328P” on page 66.

7. Updated Interrupt Vectors Start Address in Table 11-5 on page 64 and Table 11-7 on

page 67.

8. Updated ”Temperature Measure ment” on page 262.

9. Updated ATmega328P ”Fuse Bits” on page 295.

10. Removed VOL3/VOH3 rows from ”DC Characteristics” on page 313.

11. Updated condition for VOL in ”DC Characteristics” on page 313.

Updated max value for VIL2 in ”DC Characteristics” on page 313.

12. Added ” ATmega48P DC Char acteristics” on p age 314, ”ATmega88P DC Character is-

tics” on page 315, and ”ATmega168P DC Characteristics” on page 315.

13. Updated ”System and Reset Characteristics” on page 319.

14. Added ”ATmega48P Typical Characteristics” on page 328, ”ATmega88P Typical

Characteristics” on page 352, and ”ATmega168P Typical Characteristics” on page

376.

15. Updated note in ”Instruction Set Summary” on page 404.

417

8025D–AVR–03/08

ATmega48P/88P/168P/328P

35.4 Rev. 2545A-07/07

1. Initial revision.

418 8025D–AVR–03/08

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ATmega48P/88P/168P/328P

Table of Contents

Features..................................................................................................... 1

1 Pin Configurations ................................................................................... 2

1.1 Pin Descriptions .......................................................................................................3

1.2 Disclaimer .................................................................................................................4

2 Overview ................................................................................................... 5

2.1 Block Diagram ..........................................................................................................5

2.2 Comparison Be tween ATmega48P, ATmega88 P, ATmega168P, and ATmega328P

3 Resources ................................................................................................. 7

4 Data Retention .......................................................................................... 8

5 About Code Examples ............................................................................. 8

6 AVR CPU Core .......................................................................................... 9

6.1 Overview ..................................................................................................................9

6.2 ALU – Arithmetic Logic Unit ...................................................................................10

6.3 Status Register .......................................................................................................10

6.4 General Purpose Register File ...............................................................................12

6.5 Stack Pointer ..........................................................................................................13

6.6 Instruction Execution Timing ..................................................................................14

6.7 Reset and Interrupt Handling .................................................................................15

7 AVR Memories ........................................................................................ 17

7.1 Overview ................................................................................................................17

7.2 In-System Reprogrammable Flash Program Memory ............................................17

7.3 SRAM Data Memory ..............................................................................................19

7.4 EEPROM Data Memory .........................................................................................20

7.5 I/O Memory .............................................................................................................21

7.6 Register Description ...............................................................................................22

8 System Clock and Clock Options ......................................................... 27

8.1 Clock Systems and th eir Distrib u tio n ...................... ... ................ ... ... .... ................ ...2 7

8.2 Clock Sources ........................................................................................................28

8.3 Low Power Crystal Oscillator ..................................................................................29

8.4 Full Swing Crystal Oscillator ...................................................................................31

8.5 Low Frequency Crystal Oscillator ...........................................................................33

ii 8025D–AVR–03/08

ATmega48P/88P/168P/328P

8.6 Calibrated Internal RC Oscillator ............................................................................34

8.7 128 kHz Internal Oscillator .....................................................................................35

8.8 External Clock ........................................................................................................35

8.9 Clock Output Buffer ................................................................................................36

8.10 Timer/Counter Oscillator ..... .... ... ... ... .... ... ... ... ... .... ................ ... ... ... .... ... ... ... .... ... ...36

8.11 System Clock Prescaler .......................................................................................36

8.12 Regist er Descr ip tion ...................... ... .... ................ ... ... ................ ... .... ................ ...3 8

9 Power Management and Sleep Modes ................................................. 40

9.1 Sleep Modes ..........................................................................................................40

9.2 BOD Disable ...........................................................................................................41

9.3 Idle Mode ................................................................................................................41

9.4 ADC Noise Reduction Mode ..................................................................................41

9.5 Power-down Mode .................................................................................................42

9.6 Power-save Mode ..................................................................................................42

9.7 Standby Mode ........................................................................................................42

9.8 Extended Standby Mode ........................................................................................42

9.9 Power Reduction Register ......................................................................................43

9.10 Minim izing P owe r Co ns um p tio n .................... ... .... ................ ... ... ... ................. ... ...43

9.11 Regist er Descr ip tion ...................... ... .... ................ ... ... ................ ... .... ................ ...4 5

10 System Control and Reset .................................................................... 47

10.1 Resetting the AVR ................................................................................................47

10.2 Reset Sour ce s .................. ... .... ... ... ... ................ .... ... ................ ... ... ................. ... ...4 7

10.3 Power -o n Res et ....................... ... ................ ... ................ .... ................ ... ................4 8

10.4 Extern a l Reset ............................... ... ................ .... ................ ... ................ ... ..........49

10.5 Brown -o ut Dete ctio n ................... ... ... .... ... ... ................ ... .... ................ ... ... ... ..........49

10.6 Watch do g Syst em R es et .................. .... ... ................ ... ... ................ .... ................ ...50

10.7 Interna l Volta g e Ref er en ce ......... ................ ... ... ................. ... ... ... ................ .... ... ...50

10.8 Watch do g Time r ...................... ................ ... ................ ... ................ .... ... ................5 1

10.9 Regist er Descr ip tion ...................... ... .... ................ ... ... ................ ... .... ................ ...5 5

11 Interrupts ................................................................................................ 58

11.1 Interrupt Vectors in ATmega48P ..........................................................................58

11.2 Interrupt Vectors in ATmega88P ..........................................................................60

11.3 Interrupt Vectors in ATmega168P ........................................................................63

11.4 Interrupt Vectors in ATmega328P ........................................................................66

11.5 Regist er Descr ip tion ...... ................ ... .... ................ ... ... ................ ... .... ................ ...6 9

iii

8025D–AVR–03/08

ATmega48P/88P/168P/328P

12 External Interrupts ................................................................................. 71

12.1 Pin Chan ge Inte r ru pt Timing ................ ... ................ ... ... ................ .... ... ................7 1

12.2 Regist er Descr ip tion ...... ................ ... .... ................ ... ... ................ ... .... ................ ...7 2

13 I/O-Ports .................................................................................................. 76

13.1 Overv iew .......... ... ................ .... ................ ... ... ................ .... ................ ... ................7 6

13.2 Ports as Gen er al Digital I/O . .... ... ... ... .... ................ ... ... ................ ... .... ... ................7 7

13.3 Alternate Port Functions .......................................................................................81

13.4 Regist er Descr ip tion ...... ................ ... .... ................ ... ... ................ ... .... ................ ...9 3

14 8-bit Timer/Counter0 with PWM ............................................................ 95

14.1 Feature s .............. ... .... ... ... ................ .... ................ ... ................ ... ... ................. ... ...95

14.2 Overv iew .......... ... ................ .... ................ ... ... ................ .... ................ ... ................9 5

14.3 Timer/Counter Clock Sources ..............................................................................97

14.4 Coun te r Unit ............... ... ... ................ .... ................ ... ... ................ ... ................. ... ...97

14.5 Output Compare Unit ...........................................................................................98

14.6 Comp ar e M atc h Ou tp ut Unit .................... ... ................ ... .... ................ ... ................9 9

14.7 Modes of Operation .................... ................ ... ................ .... ... ................ ... ...........100

14.8 Timer/Counter Timing Diagrams ........................................................................105

14.9 Regist er Descr ip tion ...... ................ ... .... ................ ... ... ................ ... .... ................ .10 7

15 16-bit Timer/Counter1 with PWM ........................................................ 114

15.1 Feature s .............. ... .... ... ... ................ .... ................ ... ................ ... ... ................. ... .11 4

15.2 Overv iew .......... ... ................ .... ................ ... ... ................ .... ................ ... ..............11 4

15.3 Accessing 16-bit Registers .................................................................................116

15.4 Timer/Counter Clock Sources ............................................................................119

15.5 Coun te r Unit ............... ... ... ................ .... ................ ... ... ................ ... ................. ... .12 0

15.6 Input Capture Unit ..............................................................................................121

15.7 Output Compare Units ........................................................................................123

15.8 Comp ar e M atc h Ou tp ut Unit .................... ... ................ ... .... ................ ... ..............12 5

15.9 Modes of Operation .................... ................ ... ................ .... ... ................ ... ...........126

15.10 Timer/Counter Timing Diagrams ......................................................................133

15.11 Register Description .........................................................................................135

16 Timer/Counter0 and Timer/Counter1 Prescalers .............................. 142

16.1 Internal Clock Source .........................................................................................142

16.2 Presca ler Rese t ................ ... .... ... ................ ... ... .... ................ ... ... ................ .... ... .14 2

16.3 Extern a l Clock Sou rc e ................ ... ... ................ .... ... ................ ... ... ................. ... .14 2

16.4 Regist er Descr ip tion ...... ................ ... .... ................ ... ... ................ ... .... ................ .14 4

iv 8025D–AVR–03/08

ATmega48P/88P/168P/328P

17 8-bit Timer/Counter2 with PWM and Asynchronous Operation ...... 145

17.1 Feature s .............. ... .... ... ... ................ .... ................ ... ................ ... ... ................. ... .14 5

17.2 Overv iew .......... ... ................ .... ................ ... ... ................ .... ................ ... ..............14 5

17.3 Timer/Counter Clock Sources ............................................................................146

17.4 Coun te r Unit ............... ... ... ................ .... ................ ... ... ................ ... ................. ... .14 6

17.5 Output Compare Unit .........................................................................................147

17.6 Comp ar e M atc h Ou tp ut Unit .................... ... ................ ... .... ................ ... ..............14 9

17.7 Modes of Operation .................... ................ ... ................ .... ... ................ ... ...........150

17.8 Timer/Counter Timing Diagrams ........................................................................154

17.9 Asynchronous Operation of Timer/Counter2 ......................................................156

17.10 Timer/Counter Prescaler ..................................................................................157

17.11 Register Description .........................................................................................159

18 SPI – Serial Peripheral Interface ......................................................... 167

18.1 Feature s .............. ... .... ... ... ................ .... ................ ... ................ ... ... ................. ... .16 7

18.2 Overv iew .......... ... ................ .... ................ ... ... ................ .... ................ ... ..............16 7

18.3 SS Pin Functionality ...........................................................................................172

18.4 Data Mo d es ...................... ... .... ................ ... ................ ... ................ .... ... ..............17 2

18.5 Regist er Descr ip tion ...... ... ................ .... ... ................ ... ... .... ................ ... ... ...........174

19 USART0 ................................................................................................. 177

19.1 Feature s .............. ... .... ... ... ................ .... ................ ... ................ ... ... ................. ... .17 7

19.2 Overv iew .......... ... ................ .... ................ ... ... ................ .... ................ ... ..............17 7

19.3 Cloc k Gene ra tio n .... .... ... ... ... ................. ... ................ ... ... ................ .... ................ .17 8

19.4 Frame Form at s ................. ... .... ................ ... ... ................ .... ... ... ................ ... .... ... .18 1

19.5 USART Initializatio n ................ ... ... ... .... ................ ... ... ... .... ... ................ ... ... .... ... .18 3

19.6 Data Tran sm iss ion – The USART Tran sm itt er .............. .... ... ... ... ... ................. ... .18 4

19.7 Data Reception – The USART Receiver ............................................................187

19.8 Asynchronous Data Reception ...........................................................................191

19.9 Multi-pr ocessor Comm uni ca tio n Mo d e .......................... .... ... ... ................ ... .... ....194

19.10 Register Description .........................................................................................196

19.11 Examples of Baud Rate Setting .......................................................................200

20 USART in SPI Mode ............................................................................. 205

20.1 Feature s .............. ... .... ... ... ................ .... ................ ... ................ ... ... ................. ... .20 5

20.2 Overv iew .......... ... ................ .... ................ ... ... ................ .... ................ ... ..............20 5

20.3 Cloc k Gene ra tio n .... .... ... ... ... ................. ... ................ ... ... ................ .... ................ .20 5

20.4 SPI Data Modes and Timing ..............................................................................206

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20.5 Frame Form at s ................. ... ................. ... ... ................ ... .... ................ ... ... ... ........207

20.6 Data Tr an sf er ................ ... ... ................. ... ................ ... ................ ... ................. ... .20 9

20.7 AVR USART MSPIM vs. AVR SPI .......... ... ... ... .... ................ ... ... ... .... ... ... ... ........211

20.8 Regist er Descr ip tion ...... ................ ... .... ................ ... ... ................ ... .... ................ .21 2

21 2-wire Serial Interface .......................................................................... 215

21.1 Feature s .............. ... .... ... ... ................ .... ................ ... ................ ... ... ................. ... .21 5

21.2 2-wire Serial Interface Bus Definition .................................................................215

21.3 Data Transfer and Frame Format .......................................................................217

21.4 Multi-master Bus Systems, Arbitration and Synchronization ..............................219

21.5 Overview of the TWI Module ..............................................................................222

21.6 Using th e TWI ......... ................. ... ... ................ ... .... ................ ... ... ................ .... ... .22 4

21.7 Transmission Modes ........... .... ... ... ... ................ .... ... ... ................ ... .... ................ .22 8

21.8 Multi-master Systems and Arbitration .................................................................241

21.9 Regist er Descr ip tion ...... ................ ... .... ................ ... ... ................ ... .... ................ .24 2

22 Analog Comparator ............................................................................. 247

22.1 Overv iew .......... ... ................ .... ................ ... ... ................ .... ................ ... ..............24 7

22.2 Analog Comparator Multiplexed Input ................................................................247

22.3 Regist er Descr ip tion ...... ................ ... .... ................ ... ... ................ ... .... ................ .24 8

23 Analog-to-Digital Converter ................................................................ 251

23.1 Feature s .............. ... .... ... ... ................ .... ................ ... ................ ... ... ................. ... .25 1

23.2 Overv iew .......... ... ................ .... ................ ... ... ................ .... ................ ... ..............25 1

23.3 Startin g a Conv er sio n ................. ... ... ................ .... ................ ... ... ................ .... ....253

23.4 Presca ling and Con ve rsion Timing ....................... ... ... ... ................ .... ... ..............25 4

23.5 Chan ging Ch an n el or Refe re nc e Sele ct io n ...... ................. ... ... ................ ... .... ... .25 6

23.6 ADC Noise Can c e le r ........... .... ... ... ... .... ................ ... ... ... ................ .... ... ... ...........257

23.7 ADC Conversion Result .....................................................................................262

23.8 Tempera tu re Me as ur em e nt .................. ... ................ ... ................ ... ................. ... .26 2

23.9 Regist er Descr ip tion ...... ... ................ .... ... ................ ... ... .... ................ ... ... ...........263

24 debugWIRE On-chip Debug System .................................................. 268

24.1 Feature s .............. ... .... ... ... ................ .... ................ ... ................ ... ... ................. ... .26 8

24.2 Overv iew .......... ... ................ .... ................ ... ... ................ .... ................ ... ..............26 8

24.3 Physica l Inte rf ac e ... .... ... ... ... .... ................ ... ................ ... ................ .... ... ..............26 8

24.4 Softwa re Brea k Poin ts ................ ... ... .... ... ... ... ................ .... ... ... ................ ... .... ....269

24.5 Limitations of debugWIRE ..................................................................................269

24.6 Regist er Descr ip tion ...... ................ ... .... ................ ... ... ................ ... .... ................ .26 9

vi 8025D–AVR–03/08

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25 Self-Programming the Flash, ATmega48P ........................................ 270

25.1 Overv iew .......... ... ................ .... ................ ... ... ................ .... ................ ... ..............27 0

25.2 Addressing the Flash During Self-Programming ................................................271

25.3 Regist er Descr ip tion ’ ........... .... ... ... ................ ... .... ................ ... ... ................ .... ... .27 6

26 Boot Loader Support – Read-While-Write Self-Programming,

ATmega88P, ATmega168P and ATmega328P 278

26.1 Feature s .............. ... .... ... ... ................ .... ................ ... ................ ... ... ................. ... .27 8

26.2 Overv iew .......... ... ................ .... ................ ... ... ................ .... ................ ... ..............27 8

26.3 Applica tio n and Boo t Lo a de r Fla sh Sectio n s ........ ... ................ ... ... .... ... ..............27 8

26.4 Read-While-Write and No Read-While-Write Flash Sections .............................279

26.5 Boot Loader Lock Bits ........................................................................................281

26.6 Entering the Boot Loader Program .....................................................................282

26.7 Addressing the Flash During Self-Programming ................................................283

26.8 Self-Pr og ra m min g the Flash .... ... ... ... .... ... ................ ... ... ................ .... ... ..............28 3

26.9 Regist er Descr ip tion ...... ................ ... .... ................ ... ... ................ ... .... ................ .29 2

27 Memory Programming ......................................................................... 294

27.1 Program And Data Memory Lock Bits ................................................................294

27.2 Fuse Bits ................ .... ... ................ ... .... ................ ... ... ................ ... .... ... ..............29 5

27.3 Signature Bytes .......... ................ ... ................ ... .... ................ ... ................ ... ........298

27.4 Calibra tio n Byte ...... .... ... ... ................ .... ... ................ ... ... ................ .... ... ... ...........299

27.5 Page Size ......... ... ... ................. ... ... ................ ... .... ................ ... ... ................ .... ... .29 9

27.6 Parallel Programming Parameters, Pin Mapping, and Commands ....................299

27.7 Paralle l Progra m m ing ................. ................ ... ... .... ................ ... ... ................ .... ... .30 1

27.8 Serial Downloading ................. ... ... ................ ... .... ................ ... ... ................ .... ... .30 8

28 Electrical Characteristics .................................................................... 313

28.1 Absolute Maximum Ratings* ..............................................................................313

28.2 DC Chara cteristics . .... ................ ... ................ ... ................. ... ... ................ ... ........313

28.3 Speed Gra d es ............... ... ... .... ................ ... ................ ... .... ................ ... ..............31 6

28.4 Cloc k Cha ra cte r istics .. ... ... ... .... ................ ... ................ ... ................ .... ... ..............31 8

28.5 System and Reset Characteristics .....................................................................319

28.6 SPI Timing Characteristics .................................................................................320

28.7 2-wire Serial Interface Characteristics ................................................................322

28.8 ADC Characteristics – Preliminary Data .............................................................324

28.9 Parallel Programming Characteristics ................................................................325

29 Typical Characteristics ........................................................................ 327

vii

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29.1 ATme ga 4 8P Ty pic al Cha r act er istic s ....................... ... ... ................ .... ... ..............32 8

29.2 ATme ga 8 8P Ty pic al Cha r act er istic s ....................... ... ... ................ .... ... ..............35 2

29.3 ATmega168P Typical Characteristics ................................................................376

30 Register Summary ............................................................................... 400

31 Instruction Set Summary .................................................................... 404

32 Ordering Information ........................................................................... 407

32.1 ATme ga 4 8P ............... ... ... ... .... ... ................ ... ................ .... ................ ... ... ...........407

32.2 ATme ga 8 8P ............... ... ... ... .... ... ................ ... ................ .... ................ ... ... ...........408

32.3 ATme ga 1 68 P ................ ... ... ................. ... ................ ... ................ ... .... ................ .40 9

32.4 ATme ga 3 28 P ................ ... ... ................. ... ................ ... ................ ... .... ................ .41 0

33 Packaging Information ........................................................................ 411

33.1 32A ...................... ... .... ................ ... ................ ... ................. ... ... ................ ... ........411

33.2 28M1 ................ ... ................ .... ................ ... ... ................ .... ................ ... ..............41 2

33.3 32M1- A ................... ................. ... ... ................ ... ................. ... ................ ... ... ........413

33.4 28P3 .................... ... .... ................ ... ................ ... ................. ... ... ................ ... ........414

34 Errata ..................................................................................................... 415

34.1 Errata ATm e ga 4 8P ........ ................ ... .... ................ ... ................ ... ................ .... ... .4 1 5

34.2 Errata ATm e ga 8 8P ........ ................ ... .... ................ ... ................ ... ................ .... ... .4 1 5

34.3 Errata ATm e ga 1 68 P ...... ... ... .... ... ................ ... ................ .... ... ................ ... ...........415

34.4 Errata ATm e ga 3 28 P ...... ... ... .... ... ................ ... ................ .... ... ................ ... ...........415

35 Datasheet Revision History ................................................................ 416

35.1 Rev. 25 45 D- 03 /0 8 ............ ... .... ... ................ ... ................ .... ................ ... ... ...........416

35.2 Rev. 25 45 C- 01 /0 8 ............ ... .... ... ................ ... ................ .... ................ ... ... ...........416

35.3 Rev. 25 45 B-0 1/0 8 ............ ... .... ................ ... ................ ... .... ................ ... ..............41 6

35.4 Rev. 25 45 A-0 7 /0 7 ............... .... ... ................ ... ................ .... ... ................ ... ...........417

Table of Contents....................................................................................... i

8025D–AVR–03/08

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