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LMV331-N
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LMV339-N
,
LMV393-N
SNOS018H –AUGUST 1999–REVISED DECEMBER 2014
LMV33x-N / LMV393-N General-Purpose, Low-Voltage, Tiny Pack Comparators
The LMV393-N is available in 8-pin SOIC and
1 Features VSSOP packages. The LMV339-N is available in 14-
1• (For 5-V Supply, Typical Unless Otherwise Noted) pin SOIC and TSSOP packages.
• Ensured 2.7-V and 5-V Performance The LMV331-N/393-N/339-N is the most cost-
• Industrial Temperature Range −40°C to 85°C effective solution where space, low voltage, low
• Low Supply Current 60 µA/Channel power, and price are the primary specification in
circuit design for portable consumer products. They
• Input Common Mode Voltage Range Includes offer specifications that meet or exceed the familiar
Ground LM393/339 at a fraction of the supply current.
• Low Output Saturation Voltage 200 mV The chips are built with TI's advanced Submicron
• Propagation Delay 200 ns Silicon-Gate BiCMOS process. The LMV331-N/393-
• Space-Saving 5-Pin SC70 and 5-Pin SOT23 N/339-N have bipolar input and output stages for
Packages improved noise performance.
2 Applications Table 1. Device Information(1)
• Mobile Communications PART NUMBER PACKAGE BODY SIZE (NOM)
SC70 (5) 2.00 mm × 1.25 mm
• Notebooks and PDAs LMV331-N SOT-23 (5) 2.90 mm × 1.6 mm
• Battery-Powered Electronics SOIC (14) 8.65 mm × 3.91 mm
• General-Purpose Portable Devices LMV339-N TSSOP (14) 5.00 mm × 4.40 mm
• General-Purpose, Low-Voltage Applications SOIC (8) 4.90 mm × 3.91 mm
LMV393-N VSSOP (8) 3.00 mm × 3.00 mm
3 Description
The LMV393-N and LMV339-N are low-voltage (2.7 (1) For all available packages, see the orderable addendum at
the end of the datasheet.
to 5 V) versions of the dual and quad comparators,
LM393/339, which are specified at 5 to 30 V. The
LMV331-N is the single version, which is available in
space-saving, 5-pin SC70 and 5-pin SOT23
packages. The 5-pin SC70 is approximately half the
size of the 5-pin SOT23.
Low Supply Current Fast Response Time
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV331-N
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Table of Contents
7.3 Feature Description................................................... 9
1 Features.................................................................. 17.4 Device Functional Modes.......................................... 9
2 Applications ........................................................... 18 Application and Implementation ........................ 10
3 Description............................................................. 18.1 Application Information............................................ 10
4 Revision History..................................................... 28.2 Typical Applications ................................................ 16
5 Pin Configuration and Functions......................... 39 Power Supply Recommendations...................... 21
6 Specifications......................................................... 410 Layout................................................................... 21
6.1 Absolute Maximum Ratings ..................................... 410.1 Layout Guidelines ................................................. 21
6.2 ESD Ratings.............................................................. 410.2 Layout Example .................................................... 22
6.3 Recommended Operating Conditions....................... 411 Device and Documentation Support................. 23
6.4 Thermal Information.................................................. 411.1 Device Support...................................................... 23
6.5 2.7-V DC Electrical Characteristics........................... 411.2 Documentation Support ........................................ 23
6.6 2.7-V AC Electrical Characteristics........................... 511.3 Related Links ........................................................ 23
6.7 5-V DC Electrical Characteristics.............................. 511.4 Trademarks........................................................... 23
6.8 5-V AC Electrical Characteristics.............................. 611.5 Electrostatic Discharge Caution............................ 23
6.9 Typical Characteristics.............................................. 711.6 Glossary................................................................ 23
7 Detailed Description.............................................. 912 Mechanical, Packaging, and Orderable
7.1 Overview................................................................... 9Information........................................................... 23
7.2 Functional Block Diagram......................................... 9
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (Feburary 2013) to Revision H Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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5 Pin Configuration and Functions
DCK and DBV Package D and DGK Package
5-Pin SC70 / SOT23 8-Pin SOIC / VSSOP
Top View Top View
D and PW Package
14-Pin SOIC / TSSOP
Top View
Pin Functions
PIN TYPE DESCRIPTION
LMV331-N LMV393-N LMV339-N
NAME DVB,DCK D,DGK PW
+IN 1 - - I Noninverting input
+IN A - 3 5 I Noninverting input, channel A
+IN B - 5 7 I Noninverting input, channel B
+IN C - - 9 I Noninverting input, channel C
+IN D - - 11 I Noninverting input, channel D
-IN 3 - - I Inverting input
-IN A - 2 4 I Inverting input, channel A
-IN B - 6 6 I Inverting input, channel B
-IN C - - 8 I Inverting input, channel C
-IN D - - 10 I Inverting input, channel D
OUT 4 - - O Output
OUT A - 1 2 O Output, channel A
OUT B - 7 1 O Output, channel B
OUT C - - 14 O Output, channel C
OUT D - - 13 O Output, channel D
V+ 5 8 3 P Positive (highest) power supply
V- 2 4 12 P Negative (lowest) power supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Differential Input Voltage ±Supply
Voltage
Voltage on any pin (referred to V−pin) 5.5 V
Soldering Information
Infrared or Convection (20 sec) 235 °C
Junction Temperature (3) 150 °C
Storage temperature, Tstg −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for availability and
specifications.
(3) The maximum power dissipation is a function of TJ(MAX),θJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC board.
6.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±800
V(ESD) Electrostatic discharge V
Machine model ±120
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply Voltage 2.7 5 V
Temperature Range (2) −40 85 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The maximum power dissipation is a function of TJ(MAX),θJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC board.
6.4 Thermal Information LMV331-N LMV339-N LMV393-N
THERMAL METRIC(1) DCK DBV D PW D DGK UNIT
5 PINS 5 PINS 14 PINS 14 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 478 265 145 155 190 23 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 2.7-V DC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 2.7V, V−= 0V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1) (2) (1)
VOS Input Offset Voltage 1.7 7 mV
TCVOS Input Offset Voltage Average Drift At the temperature extremes 5 µV/°C
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
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2.7-V DC Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 2.7V, V−= 0V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1) (2) (1)
IBInput Bias Current 10 250 nA
At the temperature extremes 400
IOS Input Offset Current 5 50 nA
At the temperature extremes 150
VCM Input Voltage Range −0.1 V
2.0 V
VSAT Saturation Voltage ISINK ≤1 mA 120 mV
IOOutput Sink Current VO≤1.5V 5 23 mA
ISSupply Current LMV331-N 40 100 µA
LMV393-N 70 140 µA
Both Comparators
LMV339-N 140 200 µA
All four Comparators
Output Leakage Current .003 µA
At the temperature extremes 1
6.6 2.7-V AC Electrical Characteristics
TJ= 25°C, V+= 2.7 V, RL= 5.1 kΩ, V−= 0 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1) (2) (1)
tPHL Propagation Delay (High to Low) Input Overdrive = 10 mV 1000 ns
Input Overdrive = 100 mV 350 ns
tPLH Propagation Delay (Low to High) Input Overdrive = 10 mV 500 ns
Input Overdrive = 100 mV 400 ns
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
6.7 5-V DC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 5 V, V−= 0 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1) (2) (1)
VOS Input Offset Voltage 1.7 7 mV
At the temperature extremes 9
TCVOS Input Offset Voltage Average Drift 5 µV/°C
IBInput Bias Current 25 250 nA
At the temperature extremes 400
IOS Input Offset Current 2 50 nA
At the temperature extremes 150
VCM Input Voltage Range −0.1 V
4.2 V
AVVoltage Gain 20 50 V/mV
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
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5-V DC Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 5 V, V−= 0 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1) (2) (1)
Vsat Saturation Voltage ISINK ≤4 mA 200 400 mV
At the temperature extremes 700
IOOutput Sink Current VO≤1.5V 84 10 mA
ISSupply Current LMV331-N 60 120 µA
At the temperature extremes 150
LMV393-N 100 200
Both Comparators µA
At the temperature extremes 250
LMV339-N 170 300
All four Comparators µA
At the temperature extremes 350
Output Leakage Current .003 µA
At the temperature extremes 1
6.8 5-V AC Electrical Characteristics
TJ= 25°C, V+= 5 V, RL= 5.1 kΩ, V−= 0 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1) (2) (1)
tPHL Propagation Delay (High to Low) Input Overdrive = 10 mV 600 ns
Input Overdrive = 100 mV 200 ns
tPLH Propagation Delay (Low to High) Input Overdrive = 10 mV 450 ns
Input Overdrive = 100 mV 300 ns
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
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0510
0
100
200
300
400
500
VSAT (mV)
ISINK (mA)
85°C
-40°C
25°C
12 3 46 7 8 9
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6.9 Typical Characteristics
Unless otherwise specified, VS= +5V, single supply, TA= 25°C
Figure 1. Supply Current vs. Supply Voltage Output High Figure 2. Supply Current vs. Supply Voltage Output Low
(LMV331-N) (LMV331-N)
Figure 4. Output Voltage vs. Output Current at 2.7-V Supply
Figure 3. Output Voltage vs. Output Current at 5-V Supply
Figure 6. Response Time vs. Input Overdrive Negative
Figure 5. Input Bias Current vs. Supply Voltage Transition
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Typical Characteristics (continued)
Unless otherwise specified, VS= +5V, single supply, TA= 25°C
Figure 7. Response Time for Input Overdrive Positive Figure 8. Response Time vs. Input Overdrive Negative
Transition Transition
Figure 9. Response Time for Input Overdrive Positive Transition
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7 Detailed Description
7.1 Overview
The LMV331-N/393-N/339-N comparators features a supply voltage range of 2.7 V to 5 V with a low supply
current of 55 μA/channel with propagation delays as low as 200ns. They are avaialble in small, space-saving
packages, which makes these comparators versatile for use in a wide range of applications, from portable to
industrial. The open collector output configuration allows the device to be used in wired-OR configurations, such
as a window comparators.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Open Collector Output
The output of the LMV331-N/393-N/339-N series is the uncommitted collector of a grounded-emitter NPN output
transistor, which requires a pull-up resistor to a positive supply voltage for the output to switch properly. Many
collectors can be tied together to provide an output OR’ing function. An output pull-up resistor can be connected
to any available power supply voltage within the permitted V+ supply voltage range. The output pull-up resistor
should be chosen high enough so as to avoid excessive power dissipation yet low enough to supply enough
drive to switch whatever load circuitry is used on the comparator output. On the LMV331-N/393-N/339-N the pull-
up resistor should range between 1 k to 10 kΩ.
7.3.2 Ground Sensing Input
The LMV331-N/393-N/339-N has a typical input common mode voltage range of −0.1V below the ground to 0.8V
below Vcc.
7.4 Device Functional Modes
A basic comparator circuit is used for converting analog signals to a digital output.
The output is HIGH when the voltage on the non-inverting (+IN) input is greater than the inverting (-IN) input.
The output is LOW when the voltage on the non-inverting (+IN) input is less than the inverting (-IN) input.
The inverting input (-IN) is also commonly referred to as the "reference" or "VREF" input.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Basic Comparator
The comparator compares the input voltage (VIN) at the non-inverting pin to the reference voltage (VREF) at the
inverting pin. If VIN is less than VREF, the output voltage (VO) is at the saturation voltage. On the other hand, if VIN
is greater than VREF, the output voltage (VO) is at VCC.
Figure 10. Basic Comparator
8.1.2 Comparator With Hysteresis
The basic comparator configuration may oscillate or produce a noisy output if the applied differential input
voltage is near the comparator's offset voltage. This usually happens when the input signal is moving very slowly
across the switching threshold of the comparator. This problem can be prevented by the addition of hysteresis or
positive feedback.
8.1.2.1 Inverting Comparator With Hysteresis
The inverting comparator with hysteresis requires a three resistor network that are referenced to the supply
voltage VCC of the comparator. When Vin at the inverting input is less than Va, the voltage at the non-inverting
node of the comparator (Vin < Va), the output voltage is high (for simplicity assume VOswitches as high as VCC).
The three network resistors can be represented as R1//R3in series with R2. The lower input trip voltage Va1 is
defined as:
(1)
When Vin is greater than Va(Vin > Va), the output voltage is low very close to ground. In this case the three
network resistors can be presented as R2//R3in series with R1. The upper trip voltage Va2 is defined as:
(2)
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Application Information (continued)
The total hysteresis provided by the network is defined as:
ΔVa= Va1 - Va2 (3)
To assure that the comparator will always switch fully to VCC and not be pulled down by the load the resistors
values should be chosen as follow:
RPULL-UP << RLOAD (4)
and R1> RPULL-UP. (5)
Figure 11. Inverting Comparator With Hysteresis
8.1.2.1.1 Non-inverting Comparator With Hysteresis
Non-inverting comparator with hysteresis requires a two resistor network, and a voltage reference (Vref) at the
inverting input. When Vin is low, the output is also low. For the output to switch from low to high, Vin must rise up
to Vin1 where Vin1 is calculated by:
(6)
When Vin is high, the output is also high. To make the comparator switch back to its low state, Vin must equal Vref
before VAwill again equal Vref. Vin can be calculated by:
(7)
The hysteresis of this circuit is the difference between Vin1 and Vin2.
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Application Information (continued)
ΔVin = VCCR1/R2(8)
Figure 12. Noninverting Comparator With Hystersis
Figure 13. Hysteresis Threshold Points
8.1.3 ORing the Output
By the inherit nature of an open-collector comparator, the outputs of several comparators can be tied together
with a shared pull-up resistor to VCC. If one or more of the comparators outputs goes low, the output VOwill go
low.
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Application Information (continued)
Figure 14. ORing the Outputs
8.1.4 Driving CMOS and TTL
The output of the comparator is capable of driving CMOS and TTL Logic circuits. The pull-up resistor may be
pulled-up to any voltage equal to, or less than the supply voltage on V+. However, it must not be pulled-up to a
voltage higher than V+.
Figure 15. Driving CMOS
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Application Information (continued)
Figure 16. Driving TTL
8.1.5 AND Gates
The comparator can be used as three input AND gate. The operation of the gate is as follows:
The resistor divider at the inverting input establishes a reference voltage at that node. The non-inverting input is
the sum of the voltages at the inputs divided by the voltage dividers. The output will go high only when all three
inputs are high, casing the voltage at the non-inverting input to go above that at inverting input. The circuit values
shown work for a 0 equal to ground and a 1 equal to 5 V.
The resistor values can be altered if different logic levels are desired. If more inputs are required, diodes are
recommended to improve the voltage margin when all but one of the inputs are high.
Figure 17. AND Gate
8.1.6 OR Gates
A three input OR gate is achieved from the basic AND gate simply by increasing the resistor value connected
from the inverting input to Vcc, thereby reducing the reference voltage.
A logic 1 at any of the inputs will produce a logic 1 at the output.
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Application Information (continued)
Figure 18. OR Gate
8.1.7 Large Fan-In Gate
Extra logic inputs may be added by ORing the input with multiple diodes.
Figure 19. Large Fan-In and Gate
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8.2 Typical Applications
8.2.1 Squarewave Oscillator
Figure 20. Squarewave Oscillator
8.2.1.1 Design Requirements
Comparators are ideal for oscillator applications. This square wave generator uses the minimum number of
components. The output frequency is set by the RC time constant of the capacitor C1and the resistor in the
negative feedback R4. The maximum frequency is limited only by the large signal propagation delay of the
comparator in addition to any capacitive loading at the output, which would degrade the output slew rate.
8.2.1.2 Detailed Design Procedure
Figure 21. Squarewave Oscillator Timing Thresholds
To analyze the circuit, assume that the output is initially high. For this to be true, the voltage at the inverting input
Vchas to be less than the voltage at the non-inverting input Va. For Vcto be low, the capacitor C1has to be
discharged and will charge up through the negative feedback resistor R4. When it has charged up to value equal
to the voltage at the positive input Va1, the comparator output will switch.
Va1 will be given by:
(9)
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0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 5 10 15 20 25 30 35 40
VOUT (V)
TIME (µs)
C001
VOUT
Vc
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Typical Applications (continued)
If: R1= R2= R3(10)
Then:Va1 = 2VCC/3 (11)
When the output switches to ground, the value of Vais reduced by the hysteresis network to a value given by:
Va2 = VCC/3 (12)
Capacitor C1must now discharge through R4towards ground. The output will return to its high state when the
voltage across the capacitor has discharged to a value equal to Va2.
For the circuit shown, the period for one cycle of oscillation will be twice the time it takes for a single RC circuit to
charge up to one half of its final value. The time to charge the capacitor can be calculated from:
(13)
Where Vmax is the max applied potential across the capacitor = (2VCC/3)
and VC= Vmax/2 = VCC/3
One period will be given by:
1/freq = 2t (14)
or calculating the exponential gives:
1/freq = 2(0.694) R4C1(15)
Resistors R3and R4must be at least two times larger than R5to ensure that VOwill go all the way up to VCC in
the high state. The frequency stability of this circuit should strictly be a function of the external components.
8.2.1.3 Application Curve
Figure 22. Waveforms for Circuit in Typical Applications
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Typical Applications (continued)
8.2.2 Crystal Controlled Oscillator
Figure 23. Crystal Controlled Oscillator
A simple yet very stable oscillator that generates a clock for slower digital systems can be obtained by using a
resonator as the feedback element. It is similar to the squarewave oscillator, except that the positive feedback is
obtained through a quartz crystal. The circuit oscillates when the transmission through the crystal is at a
maximum, so the crystal in its series-resonant mode.
The value of R1and R2are equal so that the comparator will switch symmetrically about +VCC/2. The RC
constant of R3and C1is set to be several times greater than the period of the oscillating frequency, insuring a
50% duty cycle by maintaining a DC voltage at the inverting input equal to the absolute average of the output
waveform.
When specifying the crystal, be sure to order series resonant with the desired temperature coefficient.
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Typical Applications (continued)
8.2.3 Pulse Generator With Variable Duty Cycle
Figure 24. Pulse Generator With Variable Duty Cycle
The pulse generator with variable duty cycle is just a minor modification of the basic square wave generator.
Providing a separate charge and discharge path for capacitor C1generates a variable duty cycle. One path,
through R2and D2will charge the capacitor and set the pulse width (t1). The other path, R1and D1will discharge
the capacitor and set the time between pulses (t2).
By varying resistor R1, the time between pulses of the generator can be changed without changing the pulse
width. Similarly, by varying R2, the pulse width will be altered without affecting the time between pulses. Both
controls will change the frequency of the generator. The pulse width and time between pulses can be found from:
(16)
Copyright © 1999–2014, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LMV331-N LMV339-N LMV393-N
LMV331-N
,
LMV339-N
,
LMV393-N
SNOS018H –AUGUST 1999–REVISED DECEMBER 2014
www.ti.com
Typical Applications (continued)
Solving these equations for t1and t2
t1= R4C1ln2 (17)
t2= R5C1ln2 (18)
These terms will have a slight error due to the fact that Vmax is not exactly equal to 2/3 VCC but is actually
reduced by the diode drop to:
(19)
(20)
(21)
8.2.4 Positive Peak Detector
Figure 25. Positive Peak Detector
Positive peak detector is basically the comparator operated as a unit gain follower with a large holding capacitor
from the output to ground. Additional transistor is added to the output to provide a low impedance current source.
When the output of the comparator goes high, current is passed through the transistor to charge up the
capacitor. The only discharge path will be the 1-MΩresistor shunting C1 and any load that is connected to the
output. The decay time can be altered simply by changing the 1-MΩresistor. The output should be used through
a high impedance follower to a avoid loading the output of the peak detector.
8.2.5 Negative Peak Detector
Figure 26. Negative Peak Detector
For the negative detector, the output transistor of the comparator acts as a low impedance current sink. The only
discharge path will be the 1-MΩresistor and any load impedance used. Decay time is changed by varying the 1-
MΩresistor.
20 Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated
Product Folder Links: LMV331-N LMV339-N LMV393-N
LMV331-N
,
LMV339-N
,
LMV393-N
www.ti.com
SNOS018H –AUGUST 1999–REVISED DECEMBER 2014
9 Power Supply Recommendations
The TLV170x is specified for operation from 2.2 V to 36 V (±1.1 to ±18 V); many specifications apply from –40°C
to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are
presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 5.5 V can permanently damage the device; see the
Specifications section.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines section
10 Layout
10.1 Layout Guidelines
Comparators are very sensitive to input noise. For best results, the following layout guidelines should be
maintained:
• Use a printed circuit board (PCB) with a good, unbroken low-inductance ground plane. Proper grounding (use
of ground plane) helps maintain specified performance of the comparator
• Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close
to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply
applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information refer to
SLOA089,Circuit Board Layout Techniques.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular
as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible, as shown in Layout Example.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• For slow-moving input signals, take care to prevent parasitic feedback. A small capacitor (1000 pF or less)
placed between the inputs can help eliminate oscillations in the transition region. This capacitor causes some
degradation to propagation delay when the impedance is low. Run the topside ground plane between the
output and inputs.
Copyright © 1999–2014, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LMV331-N LMV339-N LMV393-N
IN+
IN-
V±
V+
OUT
VS+
GND
GND
Only needed for
dual-supply
operation
OUT
IN-
IN+
Run the input traces
as far away from
the supply lines
as possible Use low-ESR, ceramic
bypass capacitor
+
IN+ OUT
(Schematic Representation)
IN-
VS± or GND
V+
V-
LMV331-N
,
LMV339-N
,
LMV393-N
SNOS018H –AUGUST 1999–REVISED DECEMBER 2014
www.ti.com
10.2 Layout Example
Figure 27. Comparator Board Layout
22 Submit Documentation Feedback Copyright © 1999–2014, Texas Instruments Incorporated
Product Folder Links: LMV331-N LMV339-N LMV393-N
LMV331-N
,
LMV339-N
,
LMV393-N
www.ti.com
SNOS018H –AUGUST 1999–REVISED DECEMBER 2014
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
LMV331-N PSPICE Model, SNOM073
LMV339-N PSPICE Model, SNOM074
LMV393-N PSPICE Model, SNOM059
TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti
DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm
TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm
11.2 Documentation Support
11.2.1 Related Documentation
AN-74 - A Quad of Independently Functioning Comparators, SNOA654
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
LMV331-N Click here Click here Click here Click here Click here
LMV339-N Click here Click here Click here Click here Click here
LMV393-N Click here Click here Click here Click here Click here
11.4 Trademarks
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1999–2014, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LMV331-N LMV339-N LMV393-N
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMV331M5 ACTIVE SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 C12
LMV331M5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 C12
LMV331M5X NRND SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 85 C12
LMV331M5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 C12
LMV331M7 NRND SC70 DCK 5 1000 TBD Call TI Call TI -40 to 85 C13
LMV331M7/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 C13
LMV331M7X/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 C13
LMV339M/NOPB ACTIVE SOIC D 14 55 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMV339M
LMV339MT ACTIVE TSSOP PW 14 94 TBD Call TI Call TI -40 to 85 LMV339
MT
LMV339MT/NOPB ACTIVE TSSOP PW 14 94 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMV339
MT
LMV339MTX ACTIVE TSSOP PW 14 2500 TBD Call TI Call TI -40 to 85 LMV339
MT
LMV339MTX/NOPB ACTIVE TSSOP PW 14 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMV339
MT
LMV339MX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMV339M
LMV393M ACTIVE SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMV
393M
LMV393M/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMV
393M
LMV393MM ACTIVE VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 85 V393
LMV393MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 V393
LMV393MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 V393
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMV393MX ACTIVE SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LMV
393M
LMV393MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LMV
393M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LMV331-N, LMV393-N :
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 3
•Automotive: LMV331-Q1, LMV393-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMV331M5 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV331M5/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV331M5X SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV331M5X/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMV331M7 SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV331M7/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV331M7X/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV339MTX TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
LMV339MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
LMV339MX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
LMV393MM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMV393MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMV393MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMV393MX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMV393MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMV331M5 SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV331M5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMV331M5X SOT-23 DBV 5 3000 210.0 185.0 35.0
LMV331M5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMV331M7 SC70 DCK 5 1000 210.0 185.0 35.0
LMV331M7/NOPB SC70 DCK 5 1000 210.0 185.0 35.0
LMV331M7X/NOPB SC70 DCK 5 3000 210.0 185.0 35.0
LMV339MTX TSSOP PW 14 2500 367.0 367.0 35.0
LMV339MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0
LMV339MX/NOPB SOIC D 14 2500 367.0 367.0 35.0
LMV393MM VSSOP DGK 8 1000 210.0 185.0 35.0
LMV393MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LMV393MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
LMV393MX SOIC D 8 2500 367.0 367.0 35.0
LMV393MX/NOPB SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
0.22
0.08 TYP
0.25
3.0
2.6
2X 0.95
1.9
1.45
0.90
0.15
0.00 TYP
5X 0.5
0.3
0.6
0.3 TYP
8
0 TYP
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/E 09/2019
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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