Integrated Device Technology, Inc.
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST CMOS
BUS INTERFACE
LATCHES
DESCRIPTION:
The FCT8xxT series is built using an advanced dual metal
CMOS technology.
The FCT8xxT bus interface latches are designed to elimi-
nate the extra packages required to buffer existing latches
and provide extra data width for wider address/data paths or
buses carrying parity. The FCT841T are buffered, 10-bit wide
versions of the popular FCT373T function. They are ideal for
use as an output port requiring high IOL/IOH.
All of the FCT8xxT high-performance interface family can
drive large capacitive loads, while providing low-capacitance
bus loading at both inputs and outputs. All inputs have clamp
diodes to ground and all outputs are designed for low-capaci-
tance bus loading in high-impedance state.
FEATURES:
• Common features:
– Low input and output leakage ≤1µA (max.)
– CMOS power levels
– True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
– Meets or exceeds JEDEC standard 18 specifications
– Product available in Radiation Tolerant and Radiation
Enhanced versions
– Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
– Available in DIP, SOIC, SSOP, QSOP, CERPACK
and LCC packages
• Features for FCT841T:
– A, B, C and D speed grades
– High drive outputs (-15mA IOH, 48mA IOL)
– Power off disable outputs permit “live insertion”
IDT54/74FCT841AT/BT/CT/DT
MILITARY AND COMMERCIAL TEMPERATURE RANGES JUNE 1996
1996 Integrated Device Technology, Inc. 6.22 2571/6
FUNCTIONAL BLOCK DIAGRAM
D0
D
Y0
LE Q
LE
OE
D1
D
Y1
LE Q
D2
D
Y2
LE Q
D3
D
Y3
LE Q
D4
D
Y4
LE Q
D5
D
Y5
LE Q
D8
D
Y8
LE Q
D9
D
Y9
LE Q
2571 drw 01
6.22 2
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
PIN CONFIGURATIONS
2571 drw 02 2571 drw 03
INDEX
D
2
Y
2
Y
3
Y
4
NC
Y
5
OE
D
1
NC
V
CC
Y
0
D
8
GND
LE
Y
9
Y
8
LCC
TOP VIEW
32
20
19
1
4
5
6
7
8
1817161514
9
10
11
1213
L28-1
D
3
D
4
NC
D
5
D
6
D
7
D
0
Y
1
Y
6
Y
7
21
22
23
24
25
262728
D
9
NC
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
Y0
Y1
Y2
Y3
Y4
Y6
LE
Y5
Y7
VCC1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
P24-1
D24-1
SO24-2
SO24-7
SO24-8
&
E24-1
11
12
21
22
23
24
D8
D9
Y8
Y9
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
PIN DESCRIPTION FUNCTION TABLE(1)
2571 tbl 01 NOTE: 2571 tbl 02
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, Z = High Impedance
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Commercial Military Unit
VTERM(2) Terminal Voltage
with Respect to
GND
–0.5 to +7.0 –0.5 to +7.0 V
VTERM(3) Terminal Voltage
with Respect to
GND
–0.5 to
VCC +0.5 –0.5 to
VCC +0.5 V
TAOperating
Temperature 0 to +70 –55 to +125 °C
TBIAS Temperature
Under Bias –55 to +125 –65 to +135 °C
TSTG Storage
Temperature –55 to +125 –65 to +150 °C
PTPower Dissipation 0.5 0.5 W
IOUT DC Output
Current –60 to +120 –60 to +120 mA
2571 lnk 03
CAPACITANCE (TA = +25°C, f = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested. 2571 lnk 04
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input
Capacitance VIN = 0V 6 10 pF
COUT Output
Capacitance VOUT = 0V 8 12 pF
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
Name I/O Description
DI I The latch data inputs.
LE I The latch enable input. The latches are
transparent when LE is HIGH. Input data
is latched on the HIGH-to-LOW
transition.
YIO The 3-state latch outputs.
OE
I The output enable control. When
OE
is
LOW, the outputs are enabled. When
OE
is HIGH, the outputs VI are in high-
impedance (off) state.
Inputs Internal Output
OE
OE
LE DIQIYIFunction
H H L L Z High Z
H H H H Z High Z
H L X NC Z Latched (High Z)
L H L L L Transparent
L H H H H Transparent
L L X NC NC Latched
6.22 3
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current(4) VCC = Max. VI = 2.7V — — ±1µA
II L Input LOW Current(4) VI = 0.5V — — ±1
IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1µA
IOZL (3-State Output pins)(4) VO = 0.5V — — ±1
II Input HIGH Current(4) VCC = Max., VI = VCC (Max.) — — ±1µA
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V
VHInput Hysteresis — — 200 — mV
ICC Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 0.01 1 mA
2571 lnk 05
Symbol Parameter Test Conditions
(1)
Min. Typ.
(2)
Max.
Unit
V
OH
Output HIGH Voltage V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –6mA MIL.
I
OH
= –8mA COM'L. 2.4 3.3 — V
I
OH
= –12mA MIL.
I
OH
= –15mA COM'L. 2.0 3.0 — V
V
OL
Output LOW Voltage V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 32mA MIL.
I
OL
= 48mA COM'L. — 0.3 0.5 V
I
OS
Short Circuit Current V
CC
= Max., V
O
= GND
(3)
–60 –120 –225 mA
I
OFF
Input/Output Power Off Leakage
(5)
V
CC
= 0V, V
IN
or V
O
≤ 4.5V — —
±
1
µ
A
OUTPUT DRIVE CHARACTERISTICS FOR FCT841T
2571 lnk 06
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
5. This parameter is guaranteed but not tested.
6.22 4
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
∆ICC Quiescent Power Supply Current
TTL Inputs HIGH VCC = Max.
VIN = 3.4V(3) — 0.5 2.0 mA
ICCD Dynamic Power Supply Current(4) VCC = Max.
Outputs Open
OE
= GND
VIN = VCC
VIN = GND — 0.15 0.25 mA/
MHz
LE = VCC
One Input Toggling
50% Duty Cycle
ICTotal Power Supply Current(6) VCC = Max. VIN = VCC — 1.5 3.5 mA
Outputs Open
fi = 10MHz VIN = GND
50% Duty Cycle
OE
= GND VIN = 3.4
VIN = GND — 1.8 4.5
LE = VCC
One Bit Toggling
VCC = Max. VIN = VCC — 3.0 6.0(5)
Outputs Open
fi = 2.5MHz VIN = GND
50% Duty Cycle
OE
= GND VIN = 3.4
VIN = GND — 5.0 14.0(5)
LE = VCC
Eight Bits Toggling
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
2571 tbl 07
6.22 5
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT841AT FCT841BT
Com'l. Mil. Com'l. Mil.
Symbol Parameter Conditions(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
tPLH
tPHL Propagation Delay
DI to YI (LE = HIGH) CL = 50pF
RL = 500Ω1.5 9.0 1.5 10.0 1.5 6.5 1.5 7.5 ns
CL = 300pF(4)
RL = 500Ω1.5 13.0 1.5 15.0 1.5 13.0 1.5 15.0
tPLH
tPHL Propagation Delay
LE to YICL = 50pF
RL = 500Ω1.5 12.0 1.5 13.0 1.5 8.0 1.5 10.5 ns
CL = 300pF(4)
RL = 500Ω1.5 16.0 1.5 20.0 1.5 15.5 1.5 18.0
tPZH
tPZL Output Enable Time
OE
to YICL = 50pF
RL = 500Ω1.5 11.5 1.5 13.0 1.5 8.0 1.5 8.5 ns
CL = 300pF(4)
RL = 500Ω1.5 23.0 1.5 25.0 1.5 14.0 1.5 15.0
tPHZ
tPLZ Output Disable Time
OE
to Y I CL = 5pF(4)
RL = 500Ω1.5 7.0 1.5 9.0 1.5 6.0 1.5 6.5 ns
CL = 50pF
RL = 500Ω1.5 8.0 1.5 10.0 1.5 7.0 1.5 7.5
tSU Data to LE Set-up Time CL = 50pF 2.5 — 2.5 — 2.5 — 2.5 — ns
tHData to LE Hold Time RL = 500Ω2.5 — 3.0 — 2.5 — 2.5 — ns
tWLE Pulse Width HIGH(3) 4.0 — 5.0 — 4.0 — 4.0 — ns
NOTES: 2571 tbl 08
1. See test circuit and waveforms. 3. These parameters are guaranteed but not tested.
2. Minimum limits are guaranteed but not tested on Propagation Delays. 4. These conditions are guaranteed but not tested.
FCT841CT FCT841DT
Com'l. Mil. Com'l. Mil.
Symbol Parameter Conditions(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
tPLH
tPHL Propagation Delay
DI to YI (LE = HIGH) CL = 50pF
RL = 500Ω1.5 5.5 1.5 6.3 1.5 4.2 — — ns
CL = 300pF(4)
RL = 500Ω1.5 13.0 1.5 15.0 1.5 8.0 — —
tPLH
tPHL Propagation Delay
LE to YICL = 50pF
RL = 500Ω1.5 6.4 1.5 6.8 1.5 4.0 — — ns
CL = 300pF(4)
RL = 500Ω1.5 15.0 1.5 16.0 1.5 8.0 — —
tPZH
tPZL Output Enable Time
OE
to YICL = 50pF
RL = 500Ω1.5 6.5 1.5 7.3 1.5 4.8 — — ns
CL = 300pF(4)
RL = 500Ω1.5 12.0 1.5 13.0 1.5 9.0 — —
tPHZ
tPLZ Output Disable Time
OE
to Y I CL = 5pF(4)
RL = 500Ω1.5 5.7 1.5 6.0 1.5 4.0 — — ns
CL = 50pF
RL = 500Ω1.5 6.0 1.5 6.3 1.5 4.0 — —
tSU Data to LE Set-up Time CL = 50pF 2.5 — 2.5 — 1.5 — — — ns
tHData to LE Hold Time RL = 500Ω2.5 — 2.5 — 1.0 — — — ns
tWLE Pulse Width HIGH(3) 4.0 — 4.0 — 3.0 — — — ns
NOTES: 2571 tbl 09
1. See test circuit and waveforms. 3. These parameters are guaranteed but not tested.
2. Minimum limits are guaranteed but not tested on Propagation Delays. 4. These conditions are guaranteed but not tested.
6.22 6
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS SWITCH POSITION
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF 500
Ω
500
Ω
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
OH
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
V
OL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE DISABLE
V
OH
PRESET
CLEAR
CLOCK ENABLE
ETC.
SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH
ENABLE AND DISABLE TIMESPROPAGATION DELAY
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
Test
Switch
Disable Low
Enable Low
Closed
All Other Tests Open
Open Drain
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT =Termination resistance: should be equal to ZOUT of the Pulse
Generator.
2571 drw 04
2571 drw 05
2571 drw 06
2571 drw 07
2571 lnk 11
2571 drw 08
6.22 7
IDT54/74FCT841AT/BT/CT/DT
FAST CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
2571 drw 09
IDT XX
Temp. Range XXXX
Device Type X
Package X
Process
Blank
B
P
D
E
L
SO
PY
Q
841AT
841BT
841CT
841DT
Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Shrink Small Outline Package
Quarter-size Small Outline Package
10-Bit Non-Inverting Latch
54
74 –55°C to +125°C
0°C to +70°C
FCT
