9
AX11001/AX11005
Single Chip Microcontroller with TCP/IP
and 10/100M Fast Ethernet MAC/PHY
Copyright © 2006-2011 ASIX Electronics Corporation. All rights
FIGURE 13: WATCHDOG TIMER BLOCK DIAGRAM ............................................................................................................. 27
FIGURE 14: TIMERS 0, 1, AND 2 BLOCK DIAGRAM ............................................................................................................. 29
FIGURE 15: I/O BUFFER OF RXD0 PIN OF UART 0 AND RXD1 PIN OF RXD1 ................................................................... 30
FIGURE 16: THE I/O BUFFER OF GPIO PINS ...................................................................................................................... 31
FIGURE 17:PROGRAMMABLE COUNTER ARRAY BLOCK DIAGRAM .................................................................................... 34
FIGURE 18: I2C CONTROLLER BLOCK DIAGRAM ............................................................................................................... 35
FIGURE 19: 1-WIRE CONTROLLER BLOCK DIAGRAM ........................................................................................................ 35
FIGURE 20: SPI CONTROLLER BLOCK DIAGRAM ............................................................................................................... 36
FIGURE 21: THE PROGRAM MEMORY MAP OF 1T 80390 CPU CORE ................................................................................. 43
FIGURE 22: THE EXTERNAL DATA MEMORY MAP OF 1T 80390 CPU CORE ..................................................................... 43
FIGURE 23: THE INTERNAL MEMORY MAP OF 1T 80390 CPU CORE ................................................................................. 44
FIGURE 24: AX11001/AX11005 CLOCK GENERATION BLOCK DIAGRAM ........................................................................ 46
FIGURE 25: AX11001/AX11005 RESET GENERATION BLOCK DIAGRAM .......................................................................... 47
FIGURE 26: AX11001/AX11005 RESET TIMING DIAGRAM ............................................................................................... 47
FIGURE 27: CPU CORE BLOCK DIAGRAM ......................................................................................................................... 49
FIGURE 28: STACK BYTES ORDER ..................................................................................................................................... 58
FIGURE 29: ON-CHIP FLASH MEMORY BLOCK DIAGRAM .................................................................................................. 66
FIGURE 30: AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART ....................................................................................... 69
FIGURE 31: AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART .................................................................................. 70
FIGURE 32: ERASE SUSPEND/ERASE RESUME FLOWCHART ............................................................................................... 71
FIGURE 33: AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART ................................................................................. 72
FIGURE 34: DATA# POLLING ALGORITHM ......................................................................................................................... 74
FIGURE 35: TOGGLE BIT ALGORITHM ................................................................................................................................ 76
FIGURE 36: BOOT LOADER, MEMORY ARBITER & FLASH PROGRAMMING CONTROLLER BLOCK DIAGRAM ..................... 78
FIGURE 37: FLASH MEMORY ADDRESS WITHOUT RE-MAPPING, FARM BIT = 0 (IN SFR REGISTER CSREPR.2) (DEFAULT)
.................................................................................................................................................................................. 81
FIGURE 38: FLASH MEMORY ADDRESS RE-MAPPING ENABLED, FARM BIT = 1 (IN SFR REGISTER CSREPR.2) .............. 81
FIGURE 39: DMA ENGINE BLOCK DIAGRAM ..................................................................................................................... 84
FIGURE 40: RING-AWARE SOFTWARE DMA EXAMPLE ...................................................................................................... 86
FIGURE 41: EXAMPLE: ETHERNET PACKET RECEIVE DMA TRANSFER ONLY (RECEIVING A 1500-BYTE PACKET) ............ 91
FIGURE 42: EXAMPLE: ETHERNET PACKET RECEIVE AND TRANSMIT DMA TRANSFERS SIMULTANEOUSLY (RECEIVING AND
TRANSMITTING A 1500-BYTE PACKET) ...................................................................................................................... 91
FIGURE 43: EXAMPLE: ETHERNET PACKET RECEIVE AND TRANSMIT AND SOFTWARE DMA TRANSFERS SIMULTANEOUSLY
(RECEIVING AND TRANSMITTING A 1500-BYTE PACKET, AND SOFTWARE COPYING A 200-BYTES DATA BLOCK) ........ 91
FIGURE 44: WATCHDOG TIMER BLOCK DIAGRAM ............................................................................................................. 98
FIGURE 45: AX11001/AX11005 OPERATING MODE TRANSITION DIAGRAM .................................................................. 103
FIGURE 46: TIMER/COUNTER 0, MODE 0: 13-BIT TIMER/COUNTER ................................................................................. 111
FIGURE 47: TIMER/COUNTER 0, MODE 1: 16-BIT TIMER/COUNTER ................................................................................. 111
FIGURE 48: TIMER/COUNTER 0, MODE 2: 8-BIT TIMER/COUNTER WITH AUTO-RELOAD ................................................ 112
FIGURE 49: TIMER/COUNTER 0, MODE 3: TWO 8-BIT TIMERS/COUNTERS ....................................................................... 112
FIGURE 50: TIMER/COUNTER 1, MODE 0: 13-BIT TIMERS/COUNTERS ............................................................................. 113
FIGURE 51: TIMER/COUNTER 1, MODE 1: 16-BIT TIMERS/COUNTERS ............................................................................. 113
FIGURE 52: TIMER/COUNTER 1, MODE 2: 8-BIT TIMER/COUNTER WITH AUTO-RELOAD ................................................ 114
FIGURE 53: TIMER 2 BLOCK DIAGRAM IN TIMER MODE ................................................................................................. 116
FIGURE 54: TIMER 2 BLOCK DIAGRAM AS UART0 BAUD RATE GENERATOR ................................................................ 116
FIGURE 55: UART 0 BLOCK DIAGRAM ........................................................................................................................... 119
FIGURE 56: UART 0, MODE 0 TRANSMIT TIMING DIAGRAM ........................................................................................... 120
FIGURE 57: UART 0, MODE 1 TRANSMIT TIMING DIAGRAM ........................................................................................... 120
FIGURE 58: UART 0, MODE 2 TRANSMIT TIMING DIAGRAM ........................................................................................... 121
FIGURE 59: UART 0, MODE 3 TRANSMIT TIMING DIAGRAM ........................................................................................... 121
FIGURE 60: UART 1 BLOCK DIAGRAM ........................................................................................................................... 122
FIGURE 61: UART 1, MODE 0 TRANSMIT TIMING DIAGRAM ........................................................................................... 124
FIGURE 62: UART 1, MODE 1 TRANSMIT TIMING DIAGRAM ........................................................................................... 124
FIGURE 63: UART1, MODE 2 TRANSMIT TIMING DIAGRAM ........................................................................................... 125
FIGURE 64: UART 1, MODE 3 TRANSMIT TIMING DIAGRAM ........................................................................................... 125
FIGURE 65: UART 2 BLOCK DIAGRAM ........................................................................................................................... 126
FIGURE 66: PORTS PIN LOGIC .......................................................................................................................................... 137
FIGURE 67: DATA REGISTER ACCESSED BY READ-MODIFY-WRITE INSTRUCTIONS ........................................................ 137
FIGURE 68: PORTS WRITE TIMING DIAGRAM .................................................................................................................... 137