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FEATURES DESCRIPTION
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PWP PACKAGE
(TOP VIEW)
NC
VIN1
VIN1
MR1
MR2
EN
SEQ
GND
VIN2
VIN2
NC
VOUT1
VOUT1
VSENSE1/FB1
PG1
RESET
VSENSE2/FB2
VOUT2
VOUT2
NC
TPS70145, TPS70148TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
Dual-Output Low-Dropout Voltage Regulatorswith Power-Up Sequencing for Split-Voltage DSP Systems
•Dual Output Voltages for Split-Supply
TPS701xx family devices are designed to provide aApplications
complete power management solution for theTMS320™ DSP family, processor power, ASIC,•Selectable Power-Up Sequencing for DSP
FPGA, and digital applications where dual outputApplications
voltage regulators are required. Easy programmability•Output Current Range of 500mA on Regulator
of the sequencing function makes the TPS701xx1 and 250mA on Regulator 2
family ideal for any TMS320 DSP applications with•Fast Transient Response
power sequencing requirements. Differentiated fea-tures, such as accuracy, fast transient response, SVS•Voltage Options: 3.3V/2.5V, 3.3V/1.8V,
supervisory circuit, manual reset inputs, and an3.3V/1.5V, 3.3V/1.2V, and Dual Adjustable
enable function, provide a complete system solution.Outputs
The TPS701xx family of voltage regulators offers very•Open Drain Power-On Reset with 120ms Delay
low dropout voltage and dual outputs with power-up•Open Drain Power Good for Regulator 1
sequence control, which is designed primarily for•Ultra Low 190µA (typ) Quiescent Current
DSP applications. These devices have extremely lownoise output performance without using any added•1µA Input Current During Standby
filter bypass capacitors and are designed to have a•Low Noise: 65µV
RMS
Without Bypass
fast transient response and be stable with 10µF lowCapacitor
ESR capacitors.•Quick Output Capacitor Discharge Feature
These devices have fixed 3.3V/2.5V, 3.3V/1.8V,•Two Manual Reset Inputs
3.3V/1.5V, 3.3V/1.2V, and adjustable/adjustable volt-•2% Accuracy Over Load and Temperature
age options. Regulator 1 can support up to 500mA,and regulator 2 can support up to 250mA. Separate•Undervoltage Lockout (UVLO) Feature
voltage inputs allow the designer to configure the•20-Pin PowerPAD™ TSSOP Package
source power.•Thermal Shutdown Protection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPAD, TMS320 are trademarks of Texas Instruments.All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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1.8 V
VIN1
VIN2
EN
SEQ
VOUT1
VSENSE1
PG1
MR2
RESET
MR1
VSENSE2
VOUT2
TPS70151 PWP
5 V 3.3 V I/O
MR1
Core
0.1 µF
RESET
10 µF
10 µF
0.1 µF
DSP
MR2
PG1
EN
250 kΩ
>2 V
<0.7 V
250 kΩ
>2 V
<0.7 V
>2 V
<0.7 V
TPS70145, TPS70148TPS70151, TPS70158TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170mV onregulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is avoltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230µAover the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN(enable) shuts down both regulators, reducing the input current to 1µA at T
J
= 25 °C.
The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the tworegulators are sensed at the V
SENSE1
and V
SENSE2
pins, respectively.
The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device isenabled and the SEQ terminal is pulled high or left open, V
OUT2
turns on first and V
OUT1
remains off until V
OUT2reaches approximately 83% of its regulated output voltage. At that time V
OUT1
is turned on. If V
OUT2
is pulledbelow 83% (for example, an overload condition), V
OUT1
is turned off. Pulling the SEQ terminal low reverses thepower-up order and V
OUT1
is turned on first. The SEQ pin is connected to an internal pull-up current source.
For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulatoris turned off (disabled).
The PG1 pin reports the voltage conditions at V
OUT1
, which can be used to implement an SVS for the circuitrysupplied by regulator 1.
The TPS701xx features a RESET (SVS, POR, or Power-On Reset). RESET output initiates a reset in DSPsystems and related digital applications in the event of an undervoltage condition. RESET indicates the status ofV
OUT2
and both manual reset pins ( MR1 and MR2). When V
OUT2
reaches 95% of its regulated voltage and MR1and MR2 are in the logic high state, RESET goes to a high impedance state after a 120ms delay. RESET goesto the logic low state when the V
OUT2
regulated output voltage is pulled below 95% (for example, an overloadcondition) of its regulated voltage. To monitor V
OUT1
, the PG1 output pin can be connected to MR1 or MR2.
The device has an undervoltage lockout (UVLO) circuit which prevents the internal regulators from turning onuntil V
IN1
reaches 2.5V.
2
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
TPS70145, TPS70148TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integratedcircuits be handled with appropriate precautions. Failure to observe proper handling and installationprocedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precisionintegrated circuits may be more susceptible to damage because very small parametric changes couldcause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
T
J
REGULATOR 1 V
O
(V) REGULATOR 2 V
O
(V) TSSOP (PWP)
3.3V 1.2V TPS70145PWP3.3V 1.5V TPS70148PWP-40 °C to +125 °C 3.3V 1.8V TPS70151PWP3.3V 2.5V TPS70158PWPAdjustable (1.22V to 5.5V) Adjustable (1.22V to 5.5V) TPS70102PWP
(2)
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.(2) The TPS70102 is programmable using external resistor dividers (see Application Information). The PWP package is available tapedand reeled. Add an Rsuffix to the device type (for example, TPS70102PWPR).
Over operating free-air temperature range (unless otherwise noted)
(1)
TPS701xx UNIT
Input voltage range: V
IN1
, V
IN2
(2)
-0.3 to +7 VVoltage range at EN -0.3 to +7 VOutput voltage range (V
OUT1
, V
SENSE1
) 5.5 VOutput voltage range (V
OUT2
, V
SENSE2
) 5.5 VMaximum RESET, PG1 voltage 7 VMaximum MR1, MR2, and SEQ voltage V
IN1
VPeak output current Internally limited —Continuous total power dissipation See Dissipation Ratings Table —Junction temperature range, T
J
-40 to +150 °CStorage temperature range, T
stg
-65 to +150 °CESD rating, HBM 2 kV
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are tied to network ground.
DERATINGPACKAGE AIR FLOW (CFM) TA ≤25 °C TA = 70 °C TA = 85 °CFACTOR
0 3.067W 30.67mW/ °C 1.687W 1.227WPWP
(1)
250 4.115W 41.15mW/ °C 2.265W 1.646W
(1) This parameter is measured with the recommended copper heat sink pattern on a 4-layer PCB, 1 oz. copper on a 4-in by 4-in groundlayer. For more information, refer to TI technical brief SLMA002.
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(3) If V
O
≤1.8V then V
Imax
= 6V, V
Imin
= 2.7V:
LineReg. (mV) (%V) VOVImax2.7V
100 1000
If V
O
≥2.5V then V
Imax
= 6V, V
Imin
= V
O
+ 1V:
LineReg. (mV) (%V) VOVImaxVO1V
100 1000
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
TPS70145, TPS70148TPS70151, TPS70158TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
Over operating temperature range (unless otherwise noted)
MIN MAX UNIT
Input voltage, V
I
(1)
2.7 6 VOutput current, I
O
(regulator 1) 0 500 mAOutput current, I
O
(regulator 2) 0 250 mAOutput voltage range (for adjustable option) 1.22 5.5 VOperating junction temperature, T
J
-40 +125 °C
(1) To calculate the minimum input voltage for maximum output current, use the following equation: V
I(min)
= V
O(max)
+ V
DO(max load)
.
Over recommended operating junction temperature range (T
J
= -40 °C to +125 °C), V
IN1
or V
IN2
= V
OUT(nom)
+ 1V, I
O
= 1mA,EN = 0, C
O
= 33µF, (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Reference 2.7V < V
I
< 6V,
FB connected to V
O
1.22voltage T
J
= 25 °C2.7V < V
I
< 6V, FB connected to V
O
1.196 1.2441.2V Output 2.7V < V
I
< 6V, T
J
= 25 °C 1.22.7V < V
I
< 6V, 1.176 1.2241.5V Output 2.7V < V
I
< 6V, T
J
= 25 °C 1.5Output
2.7V < V
I
< 6V, 1.47 1.53V
O
Vvoltage
(1)
,
(2)
1.8V Output 2.7V < V
I
< 6V, T
J
= 25 °C 1.82.7V < V
I
< 6V, 1.764 1.8362.5V Output 2.7V < V
I
< 6V, T
J
= 25 °C 2.52.7V < V
I
< 6V, 2.45 2.553.3V Output 2.7V < V
I
< 6V, T
J
= 25 °C 3.32.7V < V
I
< 6V, 3.234 3.366Quiescent current (GND current) for
(2)
T
J
= 25 °C 190
µAregulator 1 and regulator 2, EN = 0V
(1)
(2)
230Output voltage line regulation ( ∆V
O
/V
O
) V
O
+ 1V < V
I
≤6V, T
J
= 25 °C
(1)
0.01%
Vfor regulator 1 and regulator 2
(3)
V
O
+ 1V < V
I
≤6V
(1)
0.1%Load regulation for V
OUT 1
and V
OUT2
T
J
= 25 °C
(2)
1 mVV
n
Output noise Regulator 1 65BW 300Hz to 50kHz, C
O
= 33µF, T
J
= 25 °C µV
RMSvoltage
Regulator 2 65Regulator 1 1.6 1.9Output current limit V
OUT
= 0V ARegulator 2 0.750 1Thermal shutdown junction temperature 150 °CEN = V
I
, T
J
= 25 °C 1Regulator 1 µAEN = V
I
3I
I
Standby(standby) current
EN = V
I
, T
J
= 25 °C 1Regulator 2 µAEN = V
I
3PSRR Power-supply ripple rejec- f = 1kHz, C
O
= 33µF, T
J
= 25 °C
(1)
dB60tion
(1) Minimum input operating voltage is 2.7V or V
O(typ)
+ 1V, whichever is greater. Maximum input voltage = 6 V, minimum outputcurrent = 1mA.(2) I
O
= 1mA to 500mA for Regulator 1 and 1mA to 250mA for Regulator 2.
4
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TPS70145, TPS70148TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)Over recommended operating junction temperature range (T
J
= -40 °C to +125 °C), V
IN1
or V
IN2
= V
OUT(nom)
+ 1V, I
O
= 1mA,EN = 0, C
O
= 33µF, (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RESET Terminal
Minimum input voltage for valid RESET I
RESET
= 300µA, V
(RESET)
≤0.8V 1.0 1.3 VTrip threshold voltage V
O
decreasing 92% 95% 98% V
OUT
Hysteresis voltage Measured at V
O
0.5% V
OUT
t
(RESET)
RESET pulse duration 80 120 160 mst
r(RESET)
Rising edge deglitch 30 µsOutput low voltage V
I
= 3.5V, I
O(RESET)
= 1mA 0.15 0.4 VLeakage current V
(RESET)
= 6V 1 µA
PG1 Terminal
Minimum input voltage for valid PG1 I
(PG1)
= 300µA, V
(PG1)
≤0.8V 1.0 1.3 VTrip threshold voltage V
O
decreasing 92% 95% 98% V
OUT
Hysteresis voltage Measured at V
O
0.5% V
OUT
t
r(PG1)
Rising edge deglitch 30 µsOutput low voltage V
I
= 2.7V, I
O(PG1)
= 1mA 0.15 0.4 VLeakage current V
(PG1)
= 6V 1 µA
EN Terminal
High level EN input voltage 2 VLow level EN input voltage 0.7 VInput current ( EN) -1 1 µAFalling edge deglitch Measured at V
O
140 µs
SEQ Terminal
High level SEQ input voltage 2 VLow level SEQ input voltage 0.7 VFalling edge deglitch Measured at V
O
140 µsSEQ pull-up current source 6 µA
MR1 / MR2 Terminals
High level input voltage 2 VLow level input voltage 0.7 VFalling edge deglitch Measured at V
O
140 µsPull-up current source 6 µA
V
OUT2
Terminal
V
OUT2
UV comparator: Positive-goinginput threshold voltage of V
OUT2
UV 80% V
O
83% V
O
86% V
O
Vcomparator
V
OUT2
UV comparator: Hysteresis 0.5% V
O
mVV
OUT2
UV comparator: Falling edge V
SENSE_2
decreasing below threshold
140 µsdeglitch
Peak output current 2ms pulse width 375 mADischarge transistor current V
OUT2
= 1.5V 7.5 mA
V
OUT1
Terminal
V
OUT1
UV comparator: Positive-goinginput threshold voltage of V
OUT1
UV 80% V
O
83% V
O
86% V
O
Vcomparator
V
OUT1
UV comparator: Hysteresis 0.5% V
O
mVV
OUT1
UV comparator: Falling edge
V
SENSE_1
decreasing below threshold 140 µsdeglitch
5
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DEVICE INFORMATION
UVLO
Thermal
Shutdown
Shutdown
V_UVLO +−
Current
Sense
Reference Vref Vref
ENA_1
ENA_
1
10 kΩ
Rising Edge
Deglitch
0.95 × Vref
FB2 Falling Edge
Delay
VIN1
PG1 Comp
0.95 × Vref
FB1 Rising Edge
Deglitch
Falling Edge
Deglitch
0.83 × Vref
FB2
UV Comp
Falling Edge
Deglitch
0.83 × Vref
FB1
UV Comp
Power
Sequence
Logic
ENA_1
ENA_2
VCC
Current
Sense
+−
10 kΩ
ENA_2
ENA_2
FB2
Vref
VIN1 (2 Pins)
GND
EN
SEQ
(see Note B)
VIN2 (2 Pins)
VOUT1 (2 Pins)
VSENSE1
(see Note
A)
PG1
MR2
RESET
MR1
VSENSE2
(see Note
A)
VOUT2(2 Pins)
FB1
VIN1
Shutdown
TPS70145, TPS70148TPS70151, TPS70158TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)Over recommended operating junction temperature range (T
J
= -40 °C to +125 °C), V
IN1
or V
IN2
= V
OUT(nom)
+ 1V, I
O
= 1mA,EN = 0, C
O
= 33µF, (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Dropout voltage
(4)
I
O
= 500mA, T
J
= 25 °C V
IN1
= 3.2V 170 mVDropout voltage
(4)
I
O
= 500mA, V
IN1
= 3.2V 275 mVPeak output current
(4)
2ms pulse width 750 mADischarge transistor current V
OUT1
= 1.5V 7.5 mAUVLO threshold 2.4 2.65 V
FB Terminal
Input current: TPS70102 FB = 1.8V 1 µA
(4) Input voltage (V
IN1
or V
IN2
) = V
O(typ)
- 100mV. For 1.5V, 1.8V and 2.5V regulators, the dropout voltage is limited by input voltage range.The 3.3V regulator input is set to 3.2V to perform this test.
Fixed Voltage Version
A. For most applications, V
SENSE1
and V
SENSE2
should be externally connected to V
OUT
as close as possible to thedevice. For other implementations, refer to SENSE terminal connection discussion in the Application Informationsection.
B. If the SEQ terminal is floating at the input, V
OUT2
powers up first.
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UVLO
Thermal
Shutdown
Shutdown
2.5 V +−
Current
Sense
Reference Vref Vref
ENA_1
ENA_1
Rising Edge
Deglitch
0.95 × Vref
FB2 Falling Edge
Delay
VIN1
PG1 Comp
0.95 × Vref
FB1 Rising Edge
Deglitch
Falling Edge
Deglitch
0.83 × Vref
FB2
UV Comp
Falling Edge
Deglitch
0.83 × Vref
FB1
UV Comp
Power
Sequence
Logic
Shutdown
ENA_1
ENA_2
VCC
Current
Sense
+−
ENA_2
ENA_2
Vref
VIN1 (2 Pins)
GND
EN
SEQ
(see Note B)
VIN2 (2 Pins)
VOUT1 (2 Pins)
FB1
(see Note
A)
PG1
MR2
RESET
MR1
FB2
(see Note
A)
VOUT2 (2 Pins)
VIN1
TPS70145, TPS70148TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
DEVICE INFORMATION (continued)
Adjustable Voltage Version
A. For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to thedevice. For other implementations, refer to FB terminals connection discussion in the Application Informationsection.
B. If the SEQ terminal is floating at the input, V
OUT2
powers up first
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NOTES: A. VRES is the minimum input voltage for a valid RESET. The symbol VRES is not currently listed within EIA or JEDEC standards
for semiconductor symbology.
VIN2
VRES
(see Note A) VRES
t
t
t
VOUT2
Threshold
Voltage
RESET
Output 120 ms
Delay 120 ms
Delay
Output
Undefined
Output
Undefined
VIT+(see Note B)
VIT−
(see Note B)
VIT+(see Note B)
B. VIT −T rip voltage is typically 5% lower than the output voltage (95%VO) VIT− to VIT+ is the hysteresis voltage.
VIT−
(see Note B)
NOTES: A. VPG1 is the minimum input voltage for a valid PG1. The symbol VPG1 is not currently listed within EIA or JEDEC
standards for semiconductor symbology.
VPG1
t
t
t
Threshold
Voltage
PG1
Output
Output
Undefined
Output
Undefined
VIT+(see Note B)VIT+(see Note B)
B. VIT −T rip voltage is typically 5% lower than the output voltage (95%VO) VIT− to VIT+ is the hysteresis voltage.
VIN1
VOUT2
VPG1
(see Note A)
VIT−
(see Note B) VIT−
(see Note B)
VUVLO VUVLO
TPS70145, TPS70148TPS70151, TPS70158TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
DEVICE INFORMATION (continued)
RESET Timing Diagram (with V
IN1
Powered Up)
PG1 Timing Diagram
8
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Detailed Description
Pin Functions
Enable
Sequence
TPS70145, TPS70148TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
DEVICE INFORMATION (continued)
Table 1. TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
EN 6 I Active low enableGND 8 — GroundMR1 4 I Manual reset input 1, active low, pulled up internallyMR2 5 I Manual reset input 2, active low, pulled up internallyNC 1, 11, 20 — No connection
Open drain output, low when V
OUT1
voltage is less than 95% of the nominal regulatedPG1 16 O
voltageRESET 15 O Open drain output, SVS (power-on reset) signal, active lowPower-up sequence control: SEQ = High, V
OUT2
powers up first;SEQ 7 I
SEQ = Low, V
OUT1
powers up first, SEQ terminal pulled up internally.V
IN1
2, 3 I Input voltage of regulator 1V
IN2
9, 10 I Input voltage of regulator 2V
OUT1
18, 19 O Output voltage of regulator 1V
OUT2
12, 13 O Output voltage of regulator 2V
SENSE2
/FB2 14 I Regulator 2 output voltage sense/regulator 2 feedback for adjustableV
SENSE1
/FB1 17 I Regulator 1 output voltage sense/regulator 1 feedback for adjustable
The TPS701xx low dropout regulator family provides dual regulated output voltages for DSP applications whichrequire high performance power management solutions. These devices provide fast transient response and highaccuracy with small output capacitors, while drawing low quiescent current. Programmable sequencing providesa power solution for DSPs without any external component requirements. This reduces the component cost andboard space while increasing total system reliability. The TPS701xx family has an enable feature which puts thedevice in sleep mode reducing the input currents to less than 3µA. Other features are integrated SVS (Power-OnReset, RESET) and Power Good (PG1) that monitor output voltages and provide logic output to the system.These differentiated features provide a complete DSP power solution.
The TPS701xx, unlike many other LDOs, feature very low quiescent current which remains virtually constanteven with varying loads. Conventional LDO regulators use a pnp pass element, the base current of which isdirectly proportional to the load current through the regulator (I
B
= I
C
/β). The TPS701xx uses a PMOS transistorto pass current; because the gate of the PMOS is voltage=driven, operating current is low and stable over the fullload range.
The EN terminal is an input which enables or shuts down the device. If EN is at a voltage high signal, the deviceis in shutdown mode. When EN goes to voltage low, the device is enabled.
The SEQ terminal is an input that programs which output voltage (V
OUT1
or V
OUT2
) is turned on first. When thedevice is enabled and the SEQ terminal is pulled high or left open, V
OUT2
turns on first and V
OUT1
remains off untilV
OUT2
reaches approximately 83% of its regulated output voltage. At that time, V
OUT1
is turned on. If V
OUT2
ispulled below 83% (for example, an overload condition) V
OUT1
is turned off. These terminals have a 6µA pullupcurrent to V
IN1
.
Pulling the SEQ terminal low reverses the power-up order and V
OUT1
is turned on first. For detailed timingdiagrams, refer to Figure 40 through Figure 44 .
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Power-Good
Manual Reset Pins ( MR1 and MR2)
Sense (V
SENSE1
, V
SENSE2
)
FB1 and FB2
RESET Indicator
V
IN1
and V
IN2
V
OUT1
and V
OUT2
TPS70145, TPS70148TPS70151, TPS70158TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
The PG1 is an open drain, active high output terminal which indicates the status of the V
OUT1
regulator. When theV
OUT1
reaches 95% of its regulated voltage, PG1 will go to a high impedance state. It will go to a low impedancestate when it is pulled below 95% (for example, an overload condition) of its regulated voltage. The open drainoutput of the PG1 terminal requires a pull-up resistor.
MR1 and MR2 are active low input terminals used to trigger a reset condition. When either MR1 or MR2 is pulledto logic low, a POR ( RESET) will occur. These terminals have a 6µA pull-up current to V
IN1
.
The sense terminals of fixed-output options must be connected to the regulator output, and the connectionshould be as short as possible. Internally, sense connects to high-impedance wide-bandwidth amplifiers througha resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route thesense connection in such a way to minimize/avoid noise pickup. Adding RC networks between the V
SENSEterminals and V
OUT
terminals to filter noise is not recommended because it can cause the regulators to oscillate.
FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the externalfeedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route themin such a way as to minimize/avoid noise pickup. Adding RC networks between the FB terminals and V
OUTterminals to filter noise is not recommended because it can cause the regulators to oscillate.
The TPS701xx features a RESET (SVS, POR, or Power-On Reset). RESET can be used to drive power-on resetcircuitry or a low-battery indicator. RESET is an active low, open drain output which indicates the status of theV
OUT2
regulator and both manual reset pins ( MR1 and MR2). When V
OUT2
exceeds 95% of its regulated voltage,and MR1 and MR2 are in the high impedance state, RESET will go to a high-impedance state after 120ms delay.RESET will go to a low-impedance state when V
OUT2
is pulled below 95% (for example, an overload condition) ofits regulated voltage. To monitor V
OUT1
, the PG1 output pin can be connected to MR1 or MR2. The open drainoutput of the RESET terminal requires a pullup resistor. If RESET is not used, it can be left floating.
V
IN1
and V
IN2
are input to the regulators. Internal bias voltages are powered by V
IN1
.
V
OUT1
and V
OUT2
are output terminals of the LDO.
10
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TYPICAL CHARACTERISTICS
IO − Output Current − A
3.296
3.295
3.293
3.292 0 0.1 0.2 0.3
− Output Voltage − V
3.298
3.299
3.300
0.4 0.5 0.6
3.297
3.294
VO
VIN1 = 4.3 V
TA = 25°C
VOUT1
1.799
1.797
1.796
1.795 0 0.05 0.1 0.15
1.800
1.801
1.802
0.2 0.25 0.3
1.798
IO − Output Current − A
− Output Voltage − VVO
VIN2 = 2.8V
TA = 25°C
VOUT2
TPS70145, TPS70148TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
Table 2. Table of Graphs
FIGURE
vs Output current 1 - 3V
O
Output voltage
vs Temperature 4 - 7Ground current vs Junction temperature 8PSRR Power-supply rejection ratio vs Frequency 9 - 12Output spectral noise density vs Frequency 13 - 16Z
O
Output impedance vs Frequency 17 - 20vs Temperature 21, 22Dropout voltage
vs Input voltage 23, 24Load transient response 25, 26Line transient response 27, 28V
O
Output voltage and enable voltage vs Time (start-up) 29, 30Equivalent series resistance vs Output current 31 - 38Test circuit for typical regions of stability (equivalent series resistance) performance 39
TPS70151 TPS70151OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 1. Figure 2.
11
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T − Temperature − °C
3.268
3.270
3.272
3.274
3.276
3.278
3.280
3.282
3.284
3.286
− Output Voltage − VVO
−40 −25 −10 5 20 35 50 65 80 95 110 125
VIN1 = 4.3 V
IO = 1 mA
VOUT1
1.198
1.197
1.196
1.195 0 0.05 0.1 0.15
1.199
1.200
1.201
0.2 0.25 0.3
IO − Output Current − A
− Output Voltage − VVO
VIN2 = 2.7 V
TA = 25°C
VOUT2
3.270
3.272
3.274
3.276
3.278
3.280
3.282
3.284
3.286
3.288
T − Temperature − °C
− Output Voltage − VVO
−40 −25 −10 5 20 35 50 65 80 95 110 125
VIN1 = 4.3 V
IO = 500 mA
VOUT1
1.786
1.788
1.790
1.792
1.794
1.796
1.798
1.800
T − Temperature − °C
− Output Voltage − VVO
−40 −25 −10 5 20 35 50 65 80 95 110 125
VIN2 = 2.8 V
IO = 1 mA
VOUT2
TPS70145, TPS70148TPS70151, TPS70158TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
TPS70145 TPS70151OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsOUTPUT CURRENT TEMPERATURE
Figure 3. Figure 4.
TPS70151 TPS70151OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsTEMPERATURE TEMPERATURE
Figure 5. Figure 6.
12
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1.790
1.791
1.792
1.793
1.794
1.795
1.796
1.797
1.798
1.799
T − Temperature − °C
− Output Voltage − VVO
−40 −25 −10 5 20 35 50 65 80 95 110 125
VIN2 = 2.8 V
IO = 250 mA
VOUT2
150
160
170
180
−40 −25 −10 5 20 35 50 65 80
TJ − Junction Temperature − °C
95 110 125
190
200
210
Ground Current − Aµ
Regulator 1 and Regulator 2
IOUT1 = 1 mA
IOUT2 = 1 mA
IOUT1 = 250 mA
IOUT2 = 500 mA
IO = 10 mA
CO = 22 µF
VOUT1
−60
−80
−9010 100 1 k 10 k
−40
−20
−10
100 k 1 M
−30
−50
−70
PSRR − Power Supply Rejection Ratio − dB
f − Frequency − Hz
−40
−60
−70
−9010 100 1 k 10 k
−20
0
10
100 k 1 M
−10
−30
−50
−80
IO = 500 mA
CO = 22 µF
VOUT1
PSRR − Power Supply Rejection Ratio − dB
f − Frequency − Hz
TPS70145, TPS70148TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
TPS70151
OUTPUT VOLTAGE GROUND CURRENTvs vsTEMPERATURE JUNCTION TEMPERATURE
Figure 7. Figure 8.
TPS70151 TPS70151POWER-SUPPLY REJECTION RATIO POWER-SUPPLY REJECTION RATIOvs vsFREQUENCY FREQUENCY
Figure 9. Figure 10.
13
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−60
−80
−9010 100 1 k 10 k
−40
−20
−10
100 k 1 M
−30
−50
−70
PSRR − Power Supply Rejection Ratio − dB
f − Frequency − Hz
IO = 10 mA
CO = 22 µF
VOUT2
−40
−60
−7010 100 1 k 10 k
−20
0
10
100 k 1 M
−10
−30
−50
PSRR − Power Supply Rejection Ratio − dB
f − Frequency − Hz
IO = 250 mA
CO = 22 µF
VOUT2
0.01
0.1
1
10
100 1 k 10 k 100 k
f − Frequency − Hz
VIN1 = 4.3 V
VOUT1 = 3.3 V
IO = 10 mA
VHzOutput Spectral Noise Density − µ
0.01
0.1
1
10
100 1 k 10 k 100 k
f − Frequency − Hz
VIN1 = 4.3 V
VOUT1 = 3.3 V
IO = 500 mA
VHzOutput Spectral Noise Density − µ
TPS70145, TPS70148TPS70151, TPS70158TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
TPS70151 TPS70151POWER-SUPPLY REJECTION RATIO POWER-SUPPLY REJECTION RATIOvs vsFREQUENCY FREQUENCY
Figure 11. Figure 12.
OUTPUT SPECTRAL NOISE DENSITY OUTPUT SPECTRAL NOISE DENSITYvs vsFREQUENCY FREQUENCY
Figure 13. Figure 14.
14
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0.01
0.1
1
10
100 1 k 10 k 100 k
f − Frequency − Hz
VIN2 = 2.8 V
VOUT2 = 1.8 V
IO = 250 mA
VHzOutput Spectral Noise Density − µ
0.01
0.1
1
10
100 1 k 10 k 100 k
f − Frequency − Hz
VIN2 = 2.8 V
VOUT2 = 1.8 V
IO = 10 mA
VHzOutput Spectral Noise Density − µ
CO = 33 µF
IO = 500 mA
VO = 3.3 V
TA = 25 C
10 100 1 k 10 k
− Output Impedance −
10
f − Frequency − Hz
100
100 k 1 M 10 M
1
0.1
0.01
ZOΩ
CO = 33 µF
IO = 10 mA
VO = 3.3 V
TA = 25 C
10 100 1 k 10 k
− Output Impedance −
10
f − Frequency − Hz
100
100 k 1 M 10 M
1
0.1
0.01
ZOΩ
TPS70145, TPS70148TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
OUTPUT SPECTRAL NOISE DENSITY OUTPUT SPECTRAL NOISE DENSITYvs vsFREQUENCY FREQUENCY
Figure 15. Figure 16.
OUTPUT IMPEDANCE OUTPUT IMPEDANCEvs vsFREQUENCY FREQUENCY
Figure 17. Figure 18.
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CO = 33 µF
IO = 250 mA
VO = 1.8 V
TA = 25 C
10 100 1 k 10 k
− Output Impedance −
10
f − Frequency − Hz
100
100 k 1 M 10 M
1
0.1
0.01
ZOΩ
CO = 33 µF
IO = 10 mA
VO = 1.8 V
TA = 25 C
10 100 1 k 10 k
− Output Impedance −
10
f − Frequency − Hz
100
100 k 1 M 10 M
1
0.1
0.01
ZOΩ
0
50
100
150
200
250
−40 −25 −10 5 20 35 50 65 80
T − Temperature − °C
Dropout Voltage − mV
IO = 500 mA
CO = 33 µF
VIN1 = 3.2 V
95 110 125
0
1
2
3
4
5
6
T − Temperature − °C
Dropout Voltage − mV
−40 −25 −10 5 20 35 50 65 80 95 110 125
IO = 10 mA
IO = 0 mA
CO = 33 µF
VIN1 = 3.2 V
TPS70145, TPS70148TPS70151, TPS70158TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
OUTPUT IMPEDANCE OUTPUT IMPEDANCEvs vsFREQUENCY FREQUENCY
Figure 19. Figure 20.
DROPOUT VOLTAGE DROPOUT VOLTAGEvs vsTEMPERATURE TEMPERATURE
Figure 21. Figure 22.
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0
50
100
150
200
250
2.5 3 3.5 4 4.5 5 5.5
VI − Input Voltage − V
Dropout Voltage − mV
IO = 500 mA
VIN1
300
TJ = 125°C
TJ = 25°C
TJ= −40°C
0
100
200
300
400
500
2.5 3 3.5 4 4.5 5 5.5
VI − Input Voltage − V
Dropout Voltage − mV
IO = 250 mA
VIN2
TJ = 125°C
TJ = 25°C
TJ = −40°C
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
20
250
− Output Current − mA
VO− Change in∆
Output Voltage − mV IO
t − Time − ms
Co = 33 µF
TA = 25°C
VOUT1 = 3.3 V
0
0
−20
500
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
20
0
− Output Current − mA
VO− Change in∆
Output Voltage − mV IO
t − Time − ms
250
0
−20
Co = 33 µF
TA = 25°C
VOUT2 = 1.8 V
TPS70145, TPS70148TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
TPS70102 TPS70102DROPOUT VOLTAGE DROPOUT VOLTAGEvs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 23. Figure 24.
LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
Figure 25. Figure 26.
17
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0 20 40 60 80 100 120
2.8
140 160 180 200
− Input Voltage − VVI
t − Time − µs
IO = 250 mA
Co = 33 µF
VOUT2
VO− Change in∆
Output Voltage − mV
0
10
−10
3.8
0 20 40 60 80 100 120
5.3
4.3
140 160 180 200
− Input Voltage − V
VI
t − Time − µs
IO = 500 mA
Co = 33 µF
VOUT1
0
50
−50
VO− Change in∆
Output Voltage − mV
t − Time (Start-Up) − ms
VO = 3.3 V
Co = 33 µF
IO = 500 mA
VOUT1
SEQ = Low
0 2
−5
2
3
1
0
0
5
0.2 1.81.61.41.210.4 0.6 0.8
− Output Voltage − V
VO
Enable Voltage − V
VO = 1.8 V
Co = 33 µF
IO = 250 mA
VOUT2
SEQ = High
t − Time (Start-Up) − ms
0 2
−5
1
2
0
−1
0
5
0.2 1.81.61.41.210.4 0.6 0.8
Enable Voltage − V − Output V oltage − V
VO
TPS70145, TPS70148TPS70151, TPS70158TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
Figure 27. Figure 28.
OUTPUT VOLTAGE AND ENABLE VOLTAGE OUTPUT VOLTAGE AND ENABLE VOLTAGEvs vsTIME (START-UP) TIME (START-UP)
Figure 29. Figure 30.
18
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10
1
0.1
0.01 0 100 200 300 400 500
IO−Output Current −mA
ESR −Equivalent Series Resistance −Ω
50 mΩ
REGION OF INSTABILITY
REGION OF INSTABILITY
VO = 3.3V
CO = 33 F
TJ = 25C
10
1
0.1
0.01 0 100 200 300 400 500
IO−Output Current −mA
ESR −Equivalent Series Resistance −Ω
50 mΩ
REGION OF INSTABILITY
REGION OF INSTABILITY
VO = 3.3 V
CO = 33 F + 1 F
TJ = 25C
10
1
0.1
0.01 0 100 200 300 400 500
IO−Output Current −mA
ESR −Equivalent Series Resistance −Ω
REGION OF INSTABILITY
REGION OF INSTABILITY
50m
VO = 3.3 V
CO = 10 F
TJ = 25C
10
1
0.1
0.01 0 100 200 300 400 500
IO−Output Current −mA
ESR −Equivalent Series Resistance −Ω
50 mΩ
REGION OF INSTABILITY
REGION OF INSTABILITY
VO = 3.3V
CO = 10 F + 1 F
TJ = 25C
TPS70145, TPS70148TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITYEQUIVALENT SERIES RESISTANCE EQUIVALENT SERIES RESISTANCEvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 31. Figure 32.
TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITYEQUIVALENT SERIES RESISTANCE EQUIVALENT SERIES RESISTANCEvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 33. Figure 34.
19
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10
1
0.1
0.01 0 100 200 300 400 500
IO−Output Current −mA
ESR −Equivalent Series Resistance −Ω
50 mΩ
REGION OF INSTABILITY
REGION OF INSTABILITY
VO = 1.8 V
CO = 33 F
TJ = 25C
10
1
0.1
0.01 0 100 200 300 400 500
IO−Output Current −mA
ESR −Equivalent Series Resistance −Ω
50 mΩ
REGION OF INSTABILITY
REGION OF INSTABILITY
VO = 1.8 V
CO = 33 F + 1 F
TJ = 25C
10
1
0.1
0.01 0 100 200 300 400 500
IO−Output Current −mA
ESR −Equivalent Series Resistance −Ω
REGION OF INSTABILITY
REGION OF INSTABILITY
50m
VO = 1.8 V
CO = 10 F
TJ = 25C
10
1
0.1
0.01 0 100 200 300 400 500
IO−Output Current −mA
ESR −Equivalent Series Resistance −Ω
50 mΩ
REGION OF INSTABILITY
REGION OF INSTABILITY
VO = 1.8 V
CO = 10 F + 1 F
TJ = 25C
IN
EN
OUT
GND CO
ESR
RL
VITo Load
TPS70145, TPS70148TPS70151, TPS70158TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITYEQUIVALENT SERIES RESISTANCE EQUIVALENT SERIES RESISTANCEvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 35. Figure 36.
TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITYEQUIVALENT SERIES RESISTANCE EQUIVALENT SERIES RESISTANCEvs vsOUTPUT CURRENT OUTPUT CURRENT
Figure 37. Figure 38.
Figure 39. Test Circuit for Typical Regions of Stability
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APPLICATION INFORMATION
Sequencing Timing Diagrams
VOUT2
VIN1
VIN2
EN
SEQ
VOUT1
VSENSE1
PG1
MR2
RESET
MR1
VSENSE2
VOUT2
TPS701xxPWP
(Fixed Output Option)
VIVOUT1
MR1
0.1 µF
RESET
10 µF
10 µF
0.1 µF
MR2
EN
>2 V
<0.7 V
250 kΩ
83%
95%
120ms
EN
VOUT2
VOUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
SEQ
95%
83%
NOTE A: t1 − T ime at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high.
t1
(see Note A)
TPS70145, TPS70148TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
This section provides a number of timing diagramsshowing how this device functions in different con-figurations.
Application condition: MR2 is tied to PG1, V
IN1
andV
IN2
are tied to the same input voltage, the SEQ pinis tied to logic low and the device is toggled with theenable ( EN) function.
When the device is enabled ( EN is pulled low), V
OUT1turns on first and V
OUT2
remains off until V
OUT1reaches approximately 83% of its regulated outputvoltage. At that time, V
OUT2
is turned on. When V
OUT1reaches 95% of its regulated output, PG1 turns on(active high). Since MR2 is connected to PG1 for thisapplication, it follows PG1. When V
OUT2
reaches 95%of its regulated voltage, RESET switches to highvoltage level after a120ms delay (see Figure 40 ).
Figure 40. Timing when SEQ = Low
21
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RESET
VOUT2
VIN1
VIN2
EN
SEQ
VOUT1
VSENSE1
PG1
MR2
RESET
MR1
VSENSE2
VOUT2
VIVOUT1
MR1
0.1 µF10 µF
10 µF
0.1 µF
MR2
EN
TPS701xxPWP
(Fixed Output Option)
>2 V
<0.7 V
250 kΩ
83%
95%
83%
95%
120ms
EN
VOUT2
VOUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
SEQ
NOTE A: t1 − T ime at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high.
t1
(see Note A)
TPS70145, TPS70148TPS70151, TPS70158TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
Application condition: MR2 is tied to PG1, V
IN1
andV
IN2
are tied to the same input voltage, the SEQ pinis tied to logic high and the device is toggled with theenable ( EN) function.
When the device is enabled ( EN is pulled low), V
OUT2begins to power up. When it reaches 83% of itsregulated voltage, V
OUT1
begins to power up. PG1turns on when V
OUT1
reaches 95% of its regulatedvoltage, and since MR2 and PG1 are tied together,MR2 follows PG1. When V
OUT1
reaches 95% of itsregulated voltage, RESET switches to high voltagelevel after a 120ms delay (see Figure 41 ).
Figure 41. Timing when SEQ = High
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VOUT2
VIN1
VIN2
EN
SEQ
VOUT1
VSENSE1
PG1
MR2
RESET
MR1
VSENSE2
VOUT2
VIVOUT1
MR1
0.1 µF
RESET
10 µF
10 µF
0.1 µF
MR2
EN 2 V
0.7 V
TPS701xxPWP
(Fixed Output Option)
>2 V
<0.7 V
250 kΩ
83%
95%
120ms
EN
VOUT2
VOUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
SEQ
120ms
83%95%
NOTE A: t1 − T ime at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high.
t1
(see Note A)
TPS70145, TPS70148TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
Application condition: MR2 is tied to PG1, V
IN1
andV
IN2
are tied to the same input voltage, the SEQ pinis tied to logic high and MR1 is toggled.
When the device is enabled ( EN is pulled low), V
OUT2begins to power up. When it reaches 83% of itsregulated voltage, V
OUT1
begins to power up. PG1turns on when V
OUT1
reaches to 95% of its regulatedvoltage, and since MR2 and PG1 are tied together,MR2 follows PG1. When V
OUT1
reaches 95% of itsregulated voltage, the RESET switches to high volt-age level after a 120ms delay. When MR1 is pulledlow, it causes RESET to go low, but the regulatorsremains in regulation (see Figure 42 ).
Figure 42. Timing when MR1 is Toggled
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RESET
VOUT2
VIN1
VIN2
EN
SEQ
VOUT1
VSENSE1
PG1
MR2
RESET
MR1
VSENSE2
VOUT2
VIVOUT1
MR1
0.1 µF10 µF
10 µF
0.1 µF
MR2
EN
TPS701xxPWP
(Fixed Output Option)
>2 V
<0.7 V
250 kΩ
120ms
EN
VOUT2
VOUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
SEQUENCE
95%
83%
83%
95%
NOTE A: t1 − T ime at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high.
t1
(see Note A)
VOUT1 faults out
TPS70145, TPS70148TPS70151, TPS70158TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
Application condition: MR2 is tied to PG1, V
IN1
andV
IN2
are tied to the same input voltage, the SEQ pinis tied to logic high and V
OUT1
faults out.
V
OUT2
begins to power up when the device is enabled( EN is pulled low). When V
OUT2
reaches 83% of itsregulated voltage, then V
OUT1
begins to power up.When V
OUT1
reaches 95% of its regulated voltage,PG1 turns on and RESET switches to high voltagelevel after a 120ms delay. When V
OUT1
faults out,V
OUT2
remains powered on because the SEQ pin ishigh. PG1 is tied to MR2 and both change state tologic low. RESET is driven by MR2 and goes to logiclow when V
OUT1
faults out (see Figure 43 ).
Figure 43. Timing when V
OUT1
Faults Out
24
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RESET
VOUT2
VIN1
VIN2
EN
SEQ
VOUT1
VSENSE1
PG1
MR2
RESET
MR1
VSENSE2
VOUT2
VIVOUT1
MR1
0.1 µF10 µF
10 µF
0.1 µF
MR2
EN
TPS701xxPWP
(Fixed Output Option)
>2 V
<0.7 V
83%
95%
83%
95%
120ms
ENABLE
VOUT2
VOUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
SEQUENCE
NOTE A: t1 − T ime at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high.
t1
(see Note A)
VOUT2 faults out
TPS70145, TPS70148TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
Application condition: MR2 is tied to PG1, V
IN1
andV
IN2
are tied to same input voltage, the SEQ is tied tologic high, the device is enabled, and V
OUT2
faultsout.
V
OUT2
begins to power up when the device is enabled( EN is pulled low). When V
OUT2
reaches 83% of itsregulated voltage, V
OUT1
begins to power up. WhenV
OUT1
reaches 95% of its regulated voltage, PG1turns on and RESET switches to high voltage levelafter a 120ms delay. When V
OUT2
faults out, V
OUT1
ispowered down because SEQ is high. PG1 is tied toMR2 and both change state to logic low. RESETgoes low when V
OUT2
faults out (see Figure 44 ).
Figure 44. Timing when V
OUT2
Faults Out
25
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Split Voltage DSP Application
1.8 V
VIN1
VIN2
EN
SEQ
VOUT1
VSENSE1
PG1
MR2
RESET
MR1
VSENSE2
VOUT2
TPS70151 PWP
5 V 3.3 V I/O
MR1
Core
0.1 µF
RESET
10 µF
10 µF
0.1 µF
DSP
MR2
PG1
EN
250 kΩ
>2 V
<0.7 V
250 kΩ
>2 V
<0.7 V
>2 V
<0.7 V
5 V
83%
95%
120ms
EN
VOUT2
(Core)
PG1
RESET
SEQ
95%
83%
VOUT1
(I/O)
NOTE A: t1 − T ime at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high.
t1
(see Note A)
TPS70145, TPS70148TPS70151, TPS70158TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
Figure 45 shows a typical application where the TPS70151 is powering up a DSP. In this application, bygrounding the SEQ pin, V
OUT1
(I/O) is powered up first, and then V
OUT2
(core).
Figure 45. Application Timing Diagram (SEQ = Low)
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VIN1
VIN2
EN
SEQ
VOUT1
VSENSE1
PG1
MR2
RESET
MR1
VSENSE2
VOUT2
TPS70151 PWP
5 V
0.1 µF
0.1 µF
1.8 V
3.3 V I/O
MR1
Core
RESET
10 µF
10 µF
DSP
MR2
PG1
250 kΩ
EN
>2 V
<0.7 V
250 kΩ
5 V
83%
95%
83%
95%
120ms
EN
VOUT2
(Core)
VOUT1
(I/O)
PG1
RESET
SEQ
NOTE A: t1 − T ime at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high.
t1
(see Note A)
TPS70145, TPS70148TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
Figure 46 shows a typical application where the TPS70151 is powering up a DSP. In this application, by pullingup the SEQ pin, V
OUT2
(core) is powered up first, and then V
OUT1
(I/O).
Figure 46. Application Timing Diagram (SEQ = High)
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Input Capacitor
Output Capacitor
ESR and Transient Response
RESR LESL C
TPS70145, TPS70148TPS70151, TPS70158TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
For a typical application, an input bypass capacitor (0.1µF – 1µF) is recommended. This capacitor filters any highfrequency noise generated in the line. For fast transient condition where droop at the input of the LDO may occurdue to high inrush current, it is recommended to place a larger capacitor at the input as well. The size of thiscapacitor is dependent on the output current and response time of the main power supply, as well as thedistance to the V
I
pins of the LDO.
As with most LDO regulators, the TPS701xx requires an output capacitor connected between OUT and GND tostabilize the internal control loop. The minimum recommended capacitance value is 10µF and the ESR(equivalent series resistance) must be between 50m Ωand 2.5 Ω. Capacitor values 10µF or larger are acceptable,provided the ESR is less than 2.5 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramiccapacitors are all suitable, provided they meet the requirements described above. Larger capacitors provide awider range of stability and better load transient response. Table 3 provides a partial listing of surface-mountcapacitors usable with the TPS701xx for fast transient response application.
This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for theuser’s application. When necessary to achieve low height requirements along with high output current and/orhigh load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above.
Table 3. Partial Listing of TPS701xx-Compatible Surface-Mount Capacitors
VALUE MANUFACTURER MAXIMUM ESR MFR PART NO.
22µF Kemet 345m Ω7495C226K0010AS33µF Sanyo 100m Ω10TPA33M47µF Sanyo 100m Ω6TPA47M68µF Sanyo 45m Ω10TPC68M
LDOs typically require an external output capacitor for stability. In fast transient response applications, capacitorsare used to support the load current while the LDO amplifier is responding. In most applications, one capacitor isused to support both functions.
Besides its capacitance, every capacitor also contains parasitic impedances. These parasitic impedances areresistive as well as inductive. The resistive impedance is called equivalent series resistance (ESR), and theinductive impedance is called equivalent series inductance (ESL). The equivalent schematic diagram of anycapacitor can therefore be drawn as shown in Figure 47 .
Figure 47. ESR and ESL
In most cases one can neglect the effect of inductive impedance ESL. Therefore, the following applicationfocuses mainly on the parasitic resistance ESR.
Figure 48 shows the output capacitor and its parasitic impedances in a typical LDO output stage.
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LDO
Vin
VESR
Iout
RESR
Cout
RLOAD Vout
+
−
ESR 1
ESR 2
ESR 3
3
1
2
t1t2
IO
VO
TPS70145, TPS70148TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
Figure 48. LDO Output Stage with Parasitic Resistances ESR
In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage acrossthe capacitor is the same as the output voltage (V
(CO)
= V
OUT
). This means no current is flowing into the C
Obranch. If I
OUT
suddenly increases (a transient condition), the following occurs:•The LDO is not able to supply the sudden current need due to its response time (t
1
in Figure 45). Therefore,capacitor C
O
provides the current for the new load condition (dashed arrow). C
O
now acts like a battery withan internal resistance, ESR. Depending on the current demand at the output, a voltage drop occurs at R
ESR
.This voltage is shown as V
ESR
in Figure 44.•When C
O
is conducting current to the load, initial voltage at the load will be V
O
= V
(CO)
– V
ESR
. Due to thedischarge of C
O
, the output voltage V
O
drops continuously until the response time t
1
of the LDO is reachedand the LDO resumes supplying the load. From this point, the output voltage starts rising again until itreaches the regulated voltage. This period is shown as t
2
in Figure 49 .
Figure 49. Correlation of Different ESRs and Their Influence on the Regulation of V
O
at a Load Step fromLow-to-High Output Current
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Conclusion
Programming the TPS70102 Adjustable LDO Converter
R1 VO
Vref 1R2
(1)
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VO
VI
OUT
FB
R1
R2
GND
EN
IN
<0.5V
>2.7 V
TPS70102
0.1 µF
+
OUTPUT
VOLTAGE R1 R2
2.5 V
3.3 V
3.6 V
UNIT
174
287
324
169
169
169
kΩ
kΩ
kΩ
Regulator Protection
TPS70145, TPS70148TPS70151, TPS70158TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levelsof ESRs where number 1 displays the lowest and number 3 displays the highest ESR.
From above, the following conclusions can be drawn:•The higher the ESR, the larger the droop at the beginning of load transient.•The smaller the output capacitor, the faster the discharge time and the greater the voltage droop during theLDO response period.
To minimize the transient output droop, capacitors must have a low ESR and be large enough to support theminimum output voltage requirement.
The output voltage of the TPS70102 adjustable regulators are programmed using external resistor dividers asshown in Figure 50 .
Resistors R1 and R2 should be chosen for approximately 50µA divider current. Lower value resistors can beused, but offer no inherent advantage and waste more power. Higher values should be avoided as leakagecurrents at the sense terminal increase the output voltage error. The recommended design procedure is tochoose R2 = 30.1k Ωto set the divider current at approximately 50µA, and then calculate R1 using Equation 1 :
where:
•V
REF
= 1.224V typ (the internal reference voltage)
Figure 50. TPS70102 Adjustable LDO Regulator Programming
Both TPS701xx PMOS-pass transistors have built-in back diodes that conduct reverse currents when the inputvoltage drops below the output voltage (for example, during power-down). Current is conducted from the outputto the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may beappropriate.
The TPS701xx also features internal current limiting and thermal protection. During normal operation, theTPS701xx regulator 1 limits output current to approximately 1.6A (typ) and regulator 2 limits output current toapproximately 750mA (typ). When current limiting engages, the output voltage scales back linearly until theovercurrent condition ends. While current limiting is designed to prevent gross device failure, care should betaken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 150 °C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130 °C (typ), regulatoroperation resumes.
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www.ti.com
Power Dissipation and Junction Temperature
PD(max) TJmaxTA
RJA
(2)
PDVIVOIO
(3)
TPS70145, TPS70148TPS70151, TPS70158
TPS70102
SLVS222D – DECEMBER 1999 – REVISED NOVEMBER 2004
Specified regulator operation is assured to a junction temperature of 125 °C; the maximum junction temperatureshould be restricted to 125 °C under normal operating conditions. This restriction limits the power dissipation theregulator can handle in any given application. To ensure the junction temperature is within acceptable limits,calculate the maximum allowable dissipation, P
D(max)
, and the actual dissipation, P
D
, which must be less than orequal to P
D(max)
.
The maximum-power-dissipation limit is determined using Equation 2 :
where:
•T
Jmax
is the maximum allowable junction temperature•R
θJA
is the thermal resistance junction-to-ambient for the package; that is, 32.6 °C/W for the 20-terminal PWPwith no airflow•T
A
is the ambient temperature
The regulator dissipation is calculated using Equation 3 :
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger thethermal protection circuit.
31
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS70102PWP ACTIVE HTSSOP PWP 20 70 None CU NIPDAU Level-1-220C-UNLIM
TPS70102PWPR ACTIVE HTSSOP PWP 20 2000 None CU NIPDAU Level-1-220C-UNLIM
TPS70145PWP ACTIVE HTSSOP PWP 20 70 None CU NIPDAU Level-1-220C-UNLIM
TPS70145PWPR ACTIVE HTSSOP PWP 20 2000 None CU NIPDAU Level-1-220C-UNLIM
TPS70148PWP ACTIVE HTSSOP PWP 20 70 None CU NIPDAU Level-1-220C-UNLIM
TPS70148PWPR ACTIVE HTSSOP PWP 20 2000 None CU NIPDAU Level-1-220C-UNLIM
TPS70151PWP ACTIVE HTSSOP PWP 20 70 None CU NIPDAU Level-1-220C-UNLIM
TPS70151PWPR ACTIVE HTSSOP PWP 20 2000 None CU NIPDAU Level-1-220C-UNLIM
TPS70158PWP ACTIVE HTSSOP PWP 20 70 None CU NIPDAU Level-1-220C-UNLIM
TPS70158PWPR ACTIVE HTSSOP PWP 20 2000 None CU NIPDAU Level-1-220C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 9-Dec-2004
Addendum-Page 1
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