TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 Dual-Output Low-Dropout Voltage Regulators with Power-Up Sequencing for Split-Voltage DSP Systems FEATURES * * * * * * * * * * * * * * * * Dual Output Voltages for Split-Supply Applications Selectable Power-Up Sequencing for DSP Applications Output Current Range of 500mA on Regulator 1 and 250mA on Regulator 2 Fast Transient Response Voltage Options: 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.2V, and Dual Adjustable Outputs Open Drain Power-On Reset with 120ms Delay Open Drain Power Good for Regulator 1 Ultra Low 190A (typ) Quiescent Current 1A Input Current During Standby Low Noise: 65VRMS Without Bypass Capacitor Quick Output Capacitor Discharge Feature Two Manual Reset Inputs 2% Accuracy Over Load and Temperature Undervoltage Lockout (UVLO) Feature 20-Pin PowerPADTM TSSOP Package Thermal Shutdown Protection DESCRIPTION TPS701xx family devices are designed to provide a complete power management solution for the TMS320TM DSP family, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes the TPS701xx family ideal for any TMS320 DSP applications with power sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit, manual reset inputs, and an enable function, provide a complete system solution. The TPS701xx family of voltage regulators offers very low dropout voltage and dual outputs with power-up sequence control, which is designed primarily for DSP applications. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10F low ESR capacitors. These devices have fixed 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.2V, and adjustable/adjustable voltage options. Regulator 1 can support up to 500mA, and regulator 2 can support up to 250mA. Separate voltage inputs allow the designer to configure the source power. PWP PACKAGE (TOP VIEW) NC VIN1 VIN1 MR1 MR2 EN SEQ GND VIN2 VIN2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 NC VOUT1 VOUT1 VSENSE1/FB1 PG1 RESET VSENSE2/FB2 VOUT2 VOUT2 NC Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD, TMS320 are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1999-2004, Texas Instruments Incorporated TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 TPS70151 PWP 5V VIN1 0.1 F 3.3 V VOUT1 250 k PG1 PG1 MR2 MR2 >2 V <0.7 V 0.1 F >2 V EN 250 k RESET RESET EN MR1 I/O 10 F VSENSE1 VIN2 DSP MR1 >2 V <0.7 V <0.7 V VSENSE2 SEQ 1.8 V VOUT2 Core 10 F Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230A over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN (enable) shuts down both regulators, reducing the input current to 1A at TJ = 25C. The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1 and VSENSE2 pins, respectively. The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time VOUT1 is turned on. If VOUT2 is pulled below 83% (for example, an overload condition), VOUT1 is turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1 is turned on first. The SEQ pin is connected to an internal pull-up current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage conditions at VOUT1, which can be used to implement an SVS for the circuitry supplied by regulator 1. The TPS701xx features a RESET (SVS, POR, or Power-On Reset). RESET output initiates a reset in DSP systems and related digital applications in the event of an undervoltage condition. RESET indicates the status of VOUT2 and both manual reset pins (MR1 and MR2). When VOUT2 reaches 95% of its regulated voltage and MR1 and MR2 are in the logic high state, RESET goes to a high impedance state after a 120ms delay. RESET goes to the logic low state when the VOUT2 regulated output voltage is pulled below 95% (for example, an overload condition) of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected to MR1 or MR2. The device has an undervoltage lockout (UVLO) circuit which prevents the internal regulators from turning on until VIN1 reaches 2.5V. 2 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) TJ REGULATOR 1 VO (V) REGULATOR 2 VO (V) TSSOP (PWP) 3.3V 1.2V TPS70145PWP 3.3V 1.5V TPS70148PWP 3.3V 1.8V TPS70151PWP 3.3V 2.5V TPS70158PWP Adjustable (1.22V to 5.5V) Adjustable (1.22V to 5.5V) TPS70102PWP (2) -40C to +125C (1) (2) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. The TPS70102 is programmable using external resistor dividers (see Application Information). The PWP package is available taped and reeled. Add an R suffix to the device type (for example, TPS70102PWPR). ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted) (1) TPS701xx UNIT Input voltage range: VIN1, VIN2 (2) -0.3 to +7 V Voltage range at EN -0.3 to +7 V Output voltage range (VOUT1, VSENSE1) 5.5 V Output voltage range (VOUT2, VSENSE2) 5.5 V 7 V Maximum RESET, PG1 voltage Maximum MR1, MR2, and SEQ voltage Peak output current Continuous total power dissipation VIN1 V Internally limited -- See Dissipation Ratings Table -- Junction temperature range, TJ -40 to +150 C Storage temperature range, Tstg -65 to +150 C 2 kV ESD rating, HBM (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are tied to network ground. DISSIPATION RATINGS PACKAGE PWP (1) (1) AIR FLOW (CFM) TA 25C DERATING FACTOR TA = 70C TA = 85C 0 3.067W 30.67mW/C 1.687W 1.227W 250 4.115W 41.15mW/C 2.265W 1.646W This parameter is measured with the recommended copper heat sink pattern on a 4-layer PCB, 1 oz. copper on a 4-in by 4-in ground layer. For more information, refer to TI technical brief SLMA002. 3 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 RECOMMENDED OPERATING CONDITIONS Over operating temperature range (unless otherwise noted) MIN Input voltage, VI (1) Output current, IO (regulator 1) Output current, IO (regulator 2) Output voltage range (for adjustable option) Operating junction temperature, TJ (1) MAX UNIT 2.7 6 0 500 mA V 0 250 mA 1.22 5.5 V -40 +125 C To calculate the minimum input voltage for maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load). ELECTRICAL CHARACTERISTICS Over recommended operating junction temperature range (TJ = -40C to +125C), VIN1 or VIN2 = VOUT(nom) + 1V, IO = 1mA, EN = 0, CO = 33F, (unless otherwise noted). PARAMETER Reference voltage 1.2V Output TEST CONDITIONS 2.7V < VI < 6V, TJ = 25C FB connected to VO 2.7V < VI < 6V, FB connected to VO 2.7V < VI < 6V, TJ = 25C 2.7V < VI < 6V, 1.5V Output Output voltage VO (1), (2) 2.7V < VI < 6V, 2.7V < VI < 6V, 2.7V < VI < 6V, 3.3V Output 2.7V < VI < 6V, TJ = 25C (1) VO + 1V < VI 6V (1) Load regulation for VOUT 1 and VOUT2 TJ = 25C (2) Output current limit Regulator 1 Regulator 2 II Standby (standby) current Regulator 2 PSRR (1) (2) (3) 4 Power-supply ripple rejection 2.55 3.3 3.366 190 (2) BW 300Hz to 50kHz, 230 CO = 33F, TJ = 25C VOUT = 0V Thermal shutdown junction temperature Regulator 1 1.836 3.234 TJ = 25C 0.01% 0.1% 1 1.6 1.9 0.750 1 TJ = 25C 3 TJ = 25C 1 3 TJ = 25C (1) 60 Minimum input operating voltage is 2.7V or VO(typ) + 1V, whichever is greater. Maximum input voltage = 6 V, minimum output current = 1mA. IO = 1mA to 500mA for Regulator 1 and 1mA to 250mA for Regulator 2. V Imax2.7V Line Reg. (mV) (% V) V O 1000 100 If VO 1.8V then VImax = 6V, VImin = 2.7V: V ImaxVO1V Line Reg. (mV) (% V) V O 1000 100 If VO 2.5V then VImax = 6V, VImin = VO + 1V: A C 1 EN = VI f = 1kHz, CO = 33F, V VRMS 65 EN = VI EN = VI, A mV 65 150 EN = VI, V 2.5 TJ = 25C VO + 1V < VI 6V, Regulator 2 1.53 1.8 2.45 Output voltage line regulation (VO/VO) for regulator 1 and regulator 2 (3) Regulator 1 1.224 1.5 TJ = 25C Quiescent current (GND current) for regulator 1 and regulator 2, EN = 0V (1) Output noise voltage 1.2 1.764 (2) UNIT 1.244 1.47 2.7V < VI < 6V, Vn 1.196 TJ = 25C 2.7V < VI < 6V, MAX 1.22 TJ = 25C 2.7V < VI < 6V, 2.5V Output TYP 1.176 2.7V < VI < 6V, 1.8V Output MIN A A dB TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 ELECTRICAL CHARACTERISTICS (continued) Over recommended operating junction temperature range (TJ = -40C to +125C), VIN1 or VIN2 = VOUT(nom) + 1V, IO = 1mA, EN = 0, CO = 33F, (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX 1.0 1.3 95% 98% UNIT RESET Terminal Minimum input voltage for valid RESET IRESET = 300A, Trip threshold voltage VO decreasing Hysteresis voltage Measured at VO t(RESET) RESET pulse duration tr(RESET) Rising edge deglitch Output low voltage VI = 3.5V, Leakage current V(RESET) = 6V V(RESET) 0.8V 92% 0.5% 80 120 0.15 VOUT VOUT 160 30 IO(RESET) = 1mA V ms s 0.4 V 1 A PG1 Terminal Minimum input voltage for valid PG1 I(PG1) = 300A, Trip threshold voltage VO decreasing Hysteresis voltage Measured at VO tr(PG1) Rising edge deglitch Output low voltage VI = 2.7V, Leakage current V(PG1) = 6V V(PG1) 0.8V 92% 1.0 1.3 95% 98% 0.5% VOUT 30 IO(PG1) = 1mA 0.15 V VOUT s 0.4 V 1 A EN Terminal High level EN input voltage 2 V Low level EN input voltage Input current (EN) Falling edge deglitch -1 Measured at VO 0.7 V 1 A 140 s SEQ Terminal High level SEQ input voltage 2 V Low level SEQ input voltage Falling edge deglitch 0.7 Measured at VO SEQ pull-up current source V 140 s 6 A MR1 / MR2 Terminals High level input voltage 2 V Low level input voltage Falling edge deglitch 0.7 Measured at VO Pull-up current source V 140 s 6 A VOUT2 Terminal VOUT2 UV comparator: Positive-going input threshold voltage of VOUT2 UV comparator 80% VO VOUT2 UV comparator: Hysteresis 83% VO 86% VO V 0.5% VO mV VOUT2 UV comparator: Falling edge deglitch VSENSE_2 decreasing below threshold 140 s Peak output current 2ms pulse width 375 mA Discharge transistor current VOUT2 = 1.5V 7.5 mA VOUT1 Terminal VOUT1 UV comparator: Positive-going input threshold voltage of VOUT1 UV comparator 80% VO VOUT1 UV comparator: Hysteresis VOUT1 UV comparator: Falling edge deglitch VSENSE_1 decreasing below threshold 83% VO 86% VO V 0.5% VO mV 140 s 5 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 ELECTRICAL CHARACTERISTICS (continued) Over recommended operating junction temperature range (TJ = -40C to +125C), VIN1 or VIN2 = VOUT(nom) + 1V, IO = 1mA, EN = 0, CO = 33F, (unless otherwise noted). PARAMETER TEST CONDITIONS MIN Dropout voltage (4) IO = 500mA, TJ = 25C VIN1 = 3.2V Dropout voltage (4) IO = 500mA, VIN1 = 3.2V Peak output current (4) Discharge transistor current TYP MAX 170 mV 275 2ms pulse width 750 VOUT1 = 1.5V 7.5 UVLO threshold 2.4 UNIT mV mA mA 2.65 V FB Terminal Input current: TPS70102 (4) FB = 1.8V 1 A Input voltage (VIN1 or VIN2) = VO(typ) - 100mV. For 1.5V, 1.8V and 2.5V regulators, the dropout voltage is limited by input voltage range. The 3.3V regulator input is set to 3.2V to perform this test. DEVICE INFORMATION Fixed Voltage Version VOUT1 (2 Pins) VIN1 (2 Pins) Current Sense UVLO Shutdown V_UVLO 10 k - GND Reference Thermal Shutdown VSENSE1 (see Note A) ENA_1 + Vref ENA_ 1 FB1 Vref PG1 FB1 Rising Edge Deglitch 0.95 x Vref VIN1 MR2 Shutdown FB2 UV Comp FB2 Falling Edge Deglitch 0.83 x Vref FB1 Falling Edge Deglitch 0.83 x Vref PG1 Comp 0.95 x Vref Power Sequence Logic VIN1 ENA_1 ENA_2 Vref UV Comp EN SEQ (see Note B) - MR1 FB2 + ENA_2 VCC Current Sense VIN2 (2 Pins) 6 RESET Falling Edge Delay Rising Edge Deglitch ENA_2 10 k VSENSE2 (see Note A) VOUT2(2 Pins) A. For most applications, VSENSE1 and VSENSE2 should be externally connected to VOUT as close as possible to the device. For other implementations, refer to SENSE terminal connection discussion in the Application Information section. B. If the SEQ terminal is floating at the input, VOUT2 powers up first. TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 DEVICE INFORMATION (continued) Adjustable Voltage Version VOUT1 (2 Pins) VIN1 (2 Pins) Current Sense UVLO Shutdown 2.5 V - GND Reference Thermal Shutdown FB1 (see Note A) ENA_1 + ENA_1 Vref Vref PG1 FB1 Rising Edge Deglitch 0.95 x Vref VIN1 MR2 Shutdown FB2 UV Comp FB2 Falling Edge Deglitch 0.83 x Vref FB1 Falling Edge Deglitch 0.83 x Vref PG1 Comp 0.95 x Vref Power Sequence Logic RESET Falling Edge Delay Rising Edge Deglitch VIN1 ENA_1 ENA_2 MR1 Vref UV Comp EN SEQ (see Note B) - VCC Current Sense VIN2 (2 Pins) + ENA_2 ENA_2 FB2 (see Note A) VOUT2 (2 Pins) A. For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the device. For other implementations, refer to FB terminals connection discussion in the Application Information section. B. If the SEQ terminal is floating at the input, VOUT2 powers up first 7 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 DEVICE INFORMATION (continued) RESET Timing Diagram (with VIN1 Powered Up) VIN2 VRES (see Note A) VRES t VOUT2 VIT +(see Note B) VIT +(see Note B) Threshold Voltage VIT - (see Note B) VIT - (see Note B) t RESET Output 120 ms Delay 120 ms Delay Output Undefined Output Undefined t NOTES: A. VRES is the minimum input voltage for a valid RESET. The symbol VRES is not currently listed within EIA or JEDEC standards for semiconductor symbology. B. VIT -Trip voltage is typically 5% lower than the output voltage (95%VO) VIT- to VIT+ is the hysteresis voltage. PG1 Timing Diagram VIN1 VUVLO VUVLO VPG1 (see Note A) VPG1 t VOUT2 VIT +(see Note B) VIT+ (see Note B) Threshold Voltage VIT - (see Note B) VIT - (see Note B) t PG1 Output Output Undefined Output Undefined t NOTES: A. VPG1 is the minimum input voltage for a valid PG1. The symbol VPG1 is not currently listed within EIA or JEDEC standards for semiconductor symbology. B. VIT -Trip voltage is typically 5% lower than the output voltage (95%VO) VIT- to VIT+ is the hysteresis voltage. 8 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 DEVICE INFORMATION (continued) Table 1. TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION EN 6 I Active low enable GND 8 -- MR1 4 I Manual reset input 1, active low, pulled up internally MR2 5 I Manual reset input 2, active low, pulled up internally NC 1, 11, 20 -- No connection PG1 16 O Open drain output, low when VOUT1 voltage is less than 95% of the nominal regulated voltage RESET 15 O Open drain output, SVS (power-on reset) signal, active low SEQ 7 I Power-up sequence control: SEQ = High, VOUT2 powers up first; SEQ = Low, VOUT1 powers up first, SEQ terminal pulled up internally. VIN1 2, 3 I Input voltage of regulator 1 Ground VIN2 9, 10 I Input voltage of regulator 2 VOUT1 18, 19 O Output voltage of regulator 1 VOUT2 12, 13 O Output voltage of regulator 2 VSENSE2/FB2 14 I Regulator 2 output voltage sense/regulator 2 feedback for adjustable VSENSE1/FB1 17 I Regulator 1 output voltage sense/regulator 1 feedback for adjustable Detailed Description The TPS701xx low dropout regulator family provides dual regulated output voltages for DSP applications which require high performance power management solutions. These devices provide fast transient response and high accuracy with small output capacitors, while drawing low quiescent current. Programmable sequencing provides a power solution for DSPs without any external component requirements. This reduces the component cost and board space while increasing total system reliability. The TPS701xx family has an enable feature which puts the device in sleep mode reducing the input currents to less than 3A. Other features are integrated SVS (Power-On Reset, RESET) and Power Good (PG1) that monitor output voltages and provide logic output to the system. These differentiated features provide a complete DSP power solution. The TPS701xx, unlike many other LDOs, feature very low quiescent current which remains virtually constant even with varying loads. Conventional LDO regulators use a pnp pass element, the base current of which is directly proportional to the load current through the regulator (IB = IC/). The TPS701xx uses a PMOS transistor to pass current; because the gate of the PMOS is voltage=driven, operating current is low and stable over the full load range. Pin Functions Enable The EN terminal is an input which enables or shuts down the device. If EN is at a voltage high signal, the device is in shutdown mode. When EN goes to voltage low, the device is enabled. Sequence The SEQ terminal is an input that programs which output voltage (VOUT1 or VOUT2) is turned on first. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time, VOUT1 is turned on. If VOUT2 is pulled below 83% (for example, an overload condition) VOUT1 is turned off. These terminals have a 6A pullup current to VIN1. Pulling the SEQ terminal low reverses the power-up order and VOUT1 is turned on first. For detailed timing diagrams, refer to Figure 40 through Figure 44. 9 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 www.ti.com Power-Good The PG1 is an open drain, active high output terminal which indicates the status of the VOUT1 regulator. When the VOUT1 reaches 95% of its regulated voltage, PG1 will go to a high impedance state. It will go to a low impedance state when it is pulled below 95% (for example, an overload condition) of its regulated voltage. The open drain output of the PG1 terminal requires a pull-up resistor. Manual Reset Pins (MR1 and MR2) MR1 and MR2 are active low input terminals used to trigger a reset condition. When either MR1 or MR2 is pulled to logic low, a POR (RESET) will occur. These terminals have a 6A pull-up current to VIN1. Sense (VSENSE1, VSENSE2) The sense terminals of fixed-output options must be connected to the regulator output, and the connection should be as short as possible. Internally, sense connects to high-impedance wide-bandwidth amplifiers through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route the sense connection in such a way to minimize/avoid noise pickup. Adding RC networks between the VSENSE terminals and VOUT terminals to filter noise is not recommended because it can cause the regulators to oscillate. FB1 and FB2 FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external feedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route them in such a way as to minimize/avoid noise pickup. Adding RC networks between the FB terminals and VOUT terminals to filter noise is not recommended because it can cause the regulators to oscillate. RESET Indicator The TPS701xx features a RESET (SVS, POR, or Power-On Reset). RESET can be used to drive power-on reset circuitry or a low-battery indicator. RESET is an active low, open drain output which indicates the status of the VOUT2 regulator and both manual reset pins (MR1 and MR2). When VOUT2 exceeds 95% of its regulated voltage, and MR1 and MR2 are in the high impedance state, RESET will go to a high-impedance state after 120ms delay. RESET will go to a low-impedance state when VOUT2 is pulled below 95% (for example, an overload condition) of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected to MR1 or MR2. The open drain output of the RESET terminal requires a pullup resistor. If RESET is not used, it can be left floating. VIN1 and VIN2 VIN1 and VIN2 are input to the regulators. Internal bias voltages are powered by VIN1. VOUT1 and VOUT2 VOUT1 and VOUT2 are output terminals of the LDO. 10 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS Table 2. Table of Graphs FIGURE VO Output voltage PSRR ZO 1-3 vs Temperature 4-7 Ground current vs Junction temperature Power-supply rejection ratio vs Frequency 9 - 12 Output spectral noise density vs Frequency 13 - 16 Output impedance vs Frequency 17 - 20 vs Temperature 21, 22 vs Input voltage 23, 24 Dropout voltage VO vs Output current 8 Load transient response 25, 26 Line transient response 27, 28 Output voltage and enable voltage vs Time (start-up) 29, 30 Equivalent series resistance vs Output current 31 - 38 Test circuit for typical regions of stability (equivalent series resistance) performance TPS70151 OUTPUT VOLTAGE vs OUTPUT CURRENT TPS70151 OUTPUT VOLTAGE vs OUTPUT CURRENT 3.300 1.802 VIN1 = 4.3 V TA = 25C VOUT1 3.299 VIN2 = 2.8V TA = 25C VOUT2 1.801 3.298 VO - Output Voltage - V VO - Output Voltage - V 39 3.297 3.296 3.295 3.294 1.800 1.799 1.798 1.797 1.796 3.293 3.292 1.795 0 0.1 0.2 0.3 0.4 IO - Output Current - A Figure 1. 0.5 0.6 0 0.05 0.1 0.15 0.2 0.25 0.3 IO - Output Current - A Figure 2. 11 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 TPS70145 OUTPUT VOLTAGE vs OUTPUT CURRENT TPS70151 OUTPUT VOLTAGE vs TEMPERATURE 1.201 3.286 VIN2 = 2.7 V TA = 25C VOUT2 1.200 3.284 VIN1 = 4.3 V IO = 1 mA VOUT1 VO - Output Voltage - V VO - Output Voltage - V 3.282 1.199 1.198 1.197 3.280 3.278 3.276 3.274 3.272 1.196 3.270 1.195 0 0.05 0.1 0.15 0.2 0.25 3.268 -40 -25 -10 0.3 5 IO - Output Current - A 20 35 50 65 80 T - Temperature - C Figure 3. Figure 4. TPS70151 OUTPUT VOLTAGE vs TEMPERATURE TPS70151 OUTPUT VOLTAGE vs TEMPERATURE 3.288 95 110 125 1.800 VIN1 = 4.3 V IO = 500 mA VOUT1 3.286 1.798 VIN2 = 2.8 V IO = 1 mA VOUT2 VO - Output Voltage - V VO - Output Voltage - V 3.284 3.282 3.280 3.278 3.276 1.796 1.794 1.792 1.790 3.274 1.788 3.272 3.270 -40 -25 -10 5 20 35 50 65 80 T - Temperature - C Figure 5. 12 95 110 125 1.786 -40 -25 -10 5 20 35 50 65 80 T - Temperature - C Figure 6. 95 110 125 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 TPS70151 OUTPUT VOLTAGE vs TEMPERATURE GROUND CURRENT vs JUNCTION TEMPERATURE 210 1.799 VIN2 = 2.8 V IO = 250 mA VOUT2 1.798 Regulator 1 and Regulator 2 200 IOUT1 = 1 mA IOUT2 = 1 mA Ground Current - A VO - Output Voltage - V 1.797 1.796 1.795 1.794 1.793 190 180 IOUT1 = 250 mA IOUT2 = 500 mA 170 1.792 160 1.791 1.790 -40 -25 -10 5 20 35 50 65 80 T - Temperature - C 150 -40 -25 -10 95 110 125 35 50 65 80 95 110 125 Figure 7. Figure 8. TPS70151 POWER-SUPPLY REJECTION RATIO vs FREQUENCY TPS70151 POWER-SUPPLY REJECTION RATIO vs FREQUENCY 10 IO = 10 mA CO = 22 F VOUT1 -20 PSRR - Power Supply Rejection Ratio - dB PSRR - Power Supply Rejection Ratio - dB 20 TJ - Junction Temperature - C -10 -30 -40 -50 -60 -70 -80 -90 5 IO = 500 mA CO = 22 F VOUT1 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 10 100 1k 10 k f - Frequency - Hz Figure 9. 100 k 1M 10 100 1k 10 k f - Frequency - Hz 100 k 1M Figure 10. 13 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 TPS70151 POWER-SUPPLY REJECTION RATIO vs FREQUENCY TPS70151 POWER-SUPPLY REJECTION RATIO vs FREQUENCY 10 IO = 10 mA CO = 22 F VOUT2 -20 PSRR - Power Supply Rejection Ratio - dB PSRR - Power Supply Rejection Ratio - dB -10 -30 -40 -50 -60 -70 -80 -90 10 100 1k 10 k f - Frequency - Hz 100 k -40 -50 -60 10 100 1k 10 k f - Frequency - Hz 100 k OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 1M 10 VIN1 = 4.3 V VOUT1 = 3.3 V IO = 10 mA Output Spectral Noise Density - V Hz Output Spectral Noise Density - V Hz -30 Figure 12. 1 0.1 1k 10 k f - Frequency - Hz Figure 13. 14 -20 Figure 11. 10 0.01 100 -10 -70 1M IO = 250 mA CO = 22 F VOUT2 0 100 k VIN1 = 4.3 V VOUT1 = 3.3 V IO = 500 mA 1 0.1 0.01 100 1k 10 k f - Frequency - Hz Figure 14. 100 k TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 10 VIN2 = 2.8 V VOUT2 = 1.8 V IO = 10 mA Output Spectral Noise Density - V Hz Output Spectral Noise Density - V Hz 10 1 0.1 0.01 100 1k 10 k f - Frequency - Hz 0.1 1k 10 k f - Frequency - Hz Figure 15. Figure 16. OUTPUT IMPEDANCE vs FREQUENCY OUTPUT IMPEDANCE vs FREQUENCY 100 k 100 CO = 33 F IO = 500 mA VO = 3.3 V TA = 25 C 10 Z O - Output Impedance - Z O - Output Impedance - 1 0.01 100 100 k 100 1 0.1 0.01 VIN2 = 2.8 V VOUT2 = 1.8 V IO = 250 mA 10 100 1k 10 k 100 k 1M 10 M CO = 33 F IO = 10 mA VO = 3.3 V TA = 25 C 10 1 0.1 0.01 10 100 1k 10 k 100 k f - Frequency - Hz f - Frequency - Hz Figure 17. Figure 18. 1M 10 M 15 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 OUTPUT IMPEDANCE vs FREQUENCY OUTPUT IMPEDANCE vs FREQUENCY 100 CO = 33 F IO = 250 mA VO = 1.8 V TA = 25 C 10 Z O - Output Impedance - Z O - Output Impedance - 100 1 0.1 0.01 10 100 1k 10 k 100 k 1M 10 1 0.1 0.01 10 M CO = 33 F IO = 10 mA VO = 1.8 V TA = 25 C 10 100 10 k 100 k f - Frequency - Hz Figure 19. Figure 20. DROPOUT VOLTAGE vs TEMPERATURE DROPOUT VOLTAGE vs TEMPERATURE 6 250 CO = 33 F VIN1 = 3.2 V 1M 10 M CO = 33 F VIN1 = 3.2 V 5 200 IO = 10 mA Dropout Voltage - mV IO = 500 mA Dropout Voltage - mV 1k f - Frequency - Hz 150 100 50 4 3 2 1 IO = 0 mA 0 -40 -25 -10 5 20 35 50 65 80 T - Temperature - C Figure 21. 16 95 110 125 0 -40 -25 -10 5 20 35 50 65 80 T - Temperature - C Figure 22. 95 110 125 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 TPS70102 DROPOUT VOLTAGE vs INPUT VOLTAGE 300 TPS70102 DROPOUT VOLTAGE vs INPUT VOLTAGE 500 IO = 500 mA VIN1 IO = 250 mA VIN2 250 400 Dropout Voltage - mV Dropout Voltage - mV TJ = 125C 200 TJ = 25C 150 100 TJ= -40C TJ = 125C 300 TJ = 25C 200 TJ = - 40C 100 50 0 2.5 3 3.5 4 4.5 5 0 2.5 5.5 3 5 LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE IO - Output Current - mA Figure 24. Co = 33 F TA = 25C VOUT1 = 3.3 V 250 0 20 0 -20 0.2 4.5 Figure 23. 500 0 4 0.4 0.6 0.8 1 1.2 1.4 1.6 5.5 VI - Input Voltage - V VO - Change in Output Voltage - mV VO - Change in Output Voltage - mV IO - Output Current - mA VI - Input Voltage - V 3.5 1.8 2 Co = 33 F TA = 25C VOUT2 = 1.8 V 250 0 20 0 -20 0 0.2 0.4 0.6 0.8 1 1.2 t - Time - ms t - Time - ms Figure 25. Figure 26. 1.4 1.6 1.8 2 17 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 VI - Input Voltage - V 5.3 4.3 0 IO = 500 mA Co = 33 F VOUT1 -50 20 40 60 2 10 0 IO = 250 mA Co = 33 F VOUT2 -10 0 20 40 60 80 100 120 140 160 180 200 t - Time - s Figure 28. OUTPUT VOLTAGE AND ENABLE VOLTAGE vs TIME (START-UP) OUTPUT VOLTAGE AND ENABLE VOLTAGE vs TIME (START-UP) 1 0 5 0 -5 0 2.8 Figure 27. VO = 3.3 V Co = 33 F IO = 500 mA VOUT1 SEQ = Low 3 3.8 80 100 120 140 160 180 200 t - Time - s Enable Voltage - V VO - Output Voltage - V Enable Voltage - V VO - Change in Output Voltage - mV 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 t - Time (Start-Up) - ms Figure 29. 18 LINE TRANSIENT RESPONSE VO - Output Voltage - V VO - Change in Output Voltage - mV VI - Input Voltage - V LINE TRANSIENT RESPONSE 1.6 1.8 2 VO = 1.8 V Co = 33 F IO = 250 mA VOUT2 SEQ = High 2 1 0 -1 5 0 -5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 t - Time (Start-Up) - ms Figure 30. 1.6 1.8 2 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE vs OUTPUT CURRENT TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE vs OUTPUT CURRENT 10 REGION OF INSTABILITY ESR -Equivalent Series Resistance - ESR -Equivalent Series Resistance - 10 VO = 3.3V CO = 33 F TJ = 25C 1 0.1 50 m REGION OF INSTABILITY 0.01 REGION OF INSTABILITY 1 VO = 3.3 V CO = 33 F + 1 F TJ = 25C 0.1 50 m REGION OF INSTABILITY 0.01 0 100 200 300 400 500 0 100 IO -Output Current -mA 300 400 Figure 31. Figure 32. TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE vs OUTPUT CURRENT TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE vs OUTPUT CURRENT 10 500 10 REGION OF INSTABILITY ESR -Equivalent Series Resistance - ESR -Equivalent Series Resistance - 200 IO -Output Current -mA VO = 3.3 V CO = 10 F TJ = 25C 1 0.1 50m REGION OF INSTABILITY 0.01 REGION OF INSTABILITY 1 VO = 3.3V CO = 10 F + 1 F TJ = 25C 0.1 50 m REGION OF INSTABILITY 0.01 0 100 200 300 400 IO -Output Current -mA Figure 33. 500 0 100 200 300 400 500 IO -Output Current -mA Figure 34. 19 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE vs OUTPUT CURRENT TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE vs OUTPUT CURRENT 10 REGION OF INSTABILITY ESR -Equivalent Series Resistance - ESR -Equivalent Series Resistance - 10 VO = 1.8 V CO = 33 F TJ = 25C 1 0.1 50 m REGION OF INSTABILITY 0.01 REGION OF INSTABILITY 1 VO = 1.8 V CO = 33 F + 1 F TJ = 25C 0.1 50 m REGION OF INSTABILITY 0.01 0 100 200 300 400 500 0 100 IO -Output Current -mA 400 Figure 36. TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE vs OUTPUT CURRENT TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE vs OUTPUT CURRENT 500 10 ESR -Equivalent Series Resistance - REGION OF INSTABILITY VO = 1.8 V CO = 10 F TJ = 25C 1 0.1 50m REGION OF INSTABILITY 0.01 REGION OF INSTABILITY 1 VO = 1.8 V CO = 10 F + 1 F TJ = 25C 0.1 50 m REGION OF INSTABILITY 0.01 0 100 200 300 400 500 0 IO -Output Current -mA 100 200 VI 300 Figure 38. To Load IN OUT EN 400 IO -Output Current -mA Figure 37. CO GND RL ESR Figure 39. Test Circuit for Typical Regions of Stability 20 300 Figure 35. 10 ESR -Equivalent Series Resistance - 200 IO -Output Current -mA 500 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 APPLICATION INFORMATION TPS701xxPWP (Fixed Output Option) Sequencing Timing Diagrams This section provides a number of timing diagrams showing how this device functions in different configurations. VI VIN1 0.1 F Application condition: MR2 is tied to PG1, VIN1 and VIN2 are tied to the same input voltage, the SEQ pin is tied to logic low and the device is toggled with the enable (EN) function. When the device is enabled (EN is pulled low), VOUT1 turns on first and VOUT2 remains off until VOUT1 reaches approximately 83% of its regulated output voltage. At that time, VOUT2 is turned on. When VOUT1 reaches 95% of its regulated output, PG1 turns on (active high). Since MR2 is connected to PG1 for this application, it follows PG1. When VOUT2 reaches 95% of its regulated voltage, RESET switches to high voltage level after a120ms delay (see Figure 40). VOUT1 VOUT1 10 F VSENSE1 250 k PG1 VIN2 0.1 F >2 V EN EN <0.7 V MR2 MR2 RESET RESET MR1 MR1 VSENSE2 SEQ VOUT2 VOUT2 10 F EN SEQ VOUT2 95% 83% VOUT1 95% 83% PG1 MR1 MR2 (MR2 tied to PG1) RESET t1 120ms (see Note A) NOTE A: t1 - Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high. Figure 40. Timing when SEQ = Low 21 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 Application condition: MR2 is tied to PG1, VIN1 and VIN2 are tied to the same input voltage, the SEQ pin is tied to logic high and the device is toggled with the enable (EN) function. TPS701xxPWP (Fixed Output Option) VI VOUT1 VIN1 When the device is enabled (EN is pulled low), VOUT2 begins to power up. When it reaches 83% of its regulated voltage, VOUT1 begins to power up. PG1 turns on when VOUT1 reaches 95% of its regulated voltage, and since MR2 and PG1 are tied together, MR2 follows PG1. When VOUT1 reaches 95% of its regulated voltage, RESET switches to high voltage level after a 120ms delay (see Figure 41). 0.1 F VOUT1 10 F VSENSE1 250 k PG1 VIN2 0.1 F EN EN MR2 MR2 RESET RESET MR1 MR1 >2 V VSENSE2 <0.7 V SEQ VOUT2 VOUT2 10 F EN SEQ VOUT2 95% 83% VOUT1 95% 83% PG1 MR1 MR2 (MR2 tied to PG1) RESET t1 120ms (see Note A) NOTE A: t1 - Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high. Figure 41. Timing when SEQ = High 22 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 Application condition: MR2 is tied to PG1, VIN1 and VIN2 are tied to the same input voltage, the SEQ pin is tied to logic high and MR1 is toggled. TPS701xxPWP (Fixed Output Option) VI VIN1 When the device is enabled (EN is pulled low), VOUT2 begins to power up. When it reaches 83% of its regulated voltage, VOUT1 begins to power up. PG1 turns on when VOUT1 reaches to 95% of its regulated voltage, and since MR2 and PG1 are tied together, MR2 follows PG1. When VOUT1 reaches 95% of its regulated voltage, the RESET switches to high voltage level after a 120ms delay. When MR1 is pulled low, it causes RESET to go low, but the regulators remains in regulation (see Figure 42). 0.1 F VOUT1 VOUT1 10 F VSENSE1 250 k PG1 VIN2 0.1 F EN EN MR2 MR2 RESET RESET MR1 MR1 2V >2 V 0.7 V VSENSE2 <0.7 V SEQ VOUT2 VOUT2 10 F EN SEQ VOUT2 95% 83% VOUT1 95% 83% PG1 MR1 MR2 (MR2 tied to PG1) RESET t1 120ms 120ms (see Note A) NOTE A: t1 - Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high. Figure 42. Timing when MR1 is Toggled 23 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 Application condition: MR2 is tied to PG1, VIN1 and VIN2 are tied to the same input voltage, the SEQ pin is tied to logic high and VOUT1 faults out. TPS701xxPWP (Fixed Output Option) VI VOUT1 VIN1 VOUT2 begins to power up when the device is enabled (EN is pulled low). When VOUT2 reaches 83% of its regulated voltage, then VOUT1 begins to power up. When VOUT1 reaches 95% of its regulated voltage, PG1 turns on and RESET switches to high voltage level after a 120ms delay. When VOUT1 faults out, VOUT2 remains powered on because the SEQ pin is high. PG1 is tied to MR2 and both change state to logic low. RESET is driven by MR2 and goes to logic low when VOUT1 faults out (see Figure 43). 0.1 F VOUT1 VSENSE1 10 F 250 k PG1 MR2 MR2 RESET RESET VIN2 0.1 F EN MR1 EN MR1 >2 V VSENSE2 <0.7 V SEQ VOUT2 VOUT2 10 F EN SEQUENCE VOUT2 95% 83% VOUT1 95% 83% VOUT1 faults out PG1 MR1 MR2 (MR2 tied to PG1) RESET 120ms t1 (see Note A) NOTE A: t1 - Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high. Figure 43. Timing when VOUT1 Faults Out 24 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 Application condition: MR2 is tied to PG1, VIN1 and VIN2 are tied to same input voltage, the SEQ is tied to logic high, the device is enabled, and VOUT2 faults out. TPS701xxPWP (Fixed Output Option) VI VOUT1 VIN1 VOUT2 begins to power up when the device is enabled (EN is pulled low). When VOUT2 reaches 83% of its regulated voltage, VOUT1 begins to power up. When VOUT1 reaches 95% of its regulated voltage, PG1 turns on and RESET switches to high voltage level after a 120ms delay. When VOUT2 faults out, VOUT1 is powered down because SEQ is high. PG1 is tied to MR2 and both change state to logic low. RESET goes low when VOUT2 faults out (see Figure 44). 0.1 F VOUT1 10 F VSENSE1 PG1 VIN2 0.1 F EN EN MR2 MR2 RESET RESET MR1 MR1 >2 V VSENSE2 <0.7 V SEQ VOUT2 VOUT2 10 F ENABLE SEQUENCE VOUT2 95% 83% VOUT1 VOUT2 faults out 95% 83% PG1 MR1 MR2 (MR2 tied to PG1) RESET t1 120ms (see Note A) NOTE A: t1 - Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high. Figure 44. Timing when VOUT2 Faults Out 25 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 Split Voltage DSP Application Figure 45 shows a typical application where the TPS70151 is powering up a DSP. In this application, by grounding the SEQ pin, VOUT1 (I/O) is powered up first, and then VOUT2 (core). TPS70151 PWP 5V VIN1 0.1 F 10 F VSENSE1 250 k MR2 MR2 >2 V <0.7 V 0.1 F >2 V 5V PG1 PG1 VIN2 DSP 3.3 V VOUT1 250 k RESET RESET EN MR1 EN MR1 >2 V <0.7 V <0.7 V VSENSE2 SEQ 1.8 V VOUT2 Core 10 F EN SEQ VOUT2 (Core) 95% 83% VOUT1 (I/O) 95% 83% PG1 RESET t1 120ms (see Note A) NOTE A: t1 - Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high. Figure 45. Application Timing Diagram (SEQ = Low) 26 I/O TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 Figure 46 shows a typical application where the TPS70151 is powering up a DSP. In this application, by pulling up the SEQ pin, VOUT2 (core) is powered up first, and then VOUT1 (I/O). TPS70151 PWP 5V VIN1 0.1 F DSP 3.3 V VOUT1 10 F VSENSE1 I/O 250 k 5V PG1 PG1 VIN2 0.1 F >2 V EN MR2 MR2 250 k RESET RESET EN <0.7 V MR1 MR1 VSENSE2 SEQ 1.8 V VOUT2 Core 10 F EN SEQ VOUT2 (Core) 95% 83% VOUT1 (I/O) 95% 83% PG1 RESET t1 120ms (see Note A) NOTE A: t1 - Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high. Figure 46. Application Timing Diagram (SEQ = High) 27 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 Input Capacitor For a typical application, an input bypass capacitor (0.1F - 1F) is recommended. This capacitor filters any high frequency noise generated in the line. For fast transient condition where droop at the input of the LDO may occur due to high inrush current, it is recommended to place a larger capacitor at the input as well. The size of this capacitor is dependent on the output current and response time of the main power supply, as well as the distance to the VI pins of the LDO. Output Capacitor As with most LDO regulators, the TPS701xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance value is 10F and the ESR (equivalent series resistance) must be between 50m and 2.5. Capacitor values 10F or larger are acceptable, provided the ESR is less than 2.5. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements described above. Larger capacitors provide a wider range of stability and better load transient response. Table 3 provides a partial listing of surface-mount capacitors usable with the TPS701xx for fast transient response application. This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for the user's application. When necessary to achieve low height requirements along with high output current and/or high load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above. Table 3. Partial Listing of TPS701xx-Compatible Surface-Mount Capacitors VALUE MANUFACTURER MAXIMUM ESR MFR PART NO. 22F Kemet 345m 7495C226K0010AS 33F Sanyo 100m 10TPA33M 47F Sanyo 100m 6TPA47M 68F Sanyo 45m 10TPC68M ESR and Transient Response LDOs typically require an external output capacitor for stability. In fast transient response applications, capacitors are used to support the load current while the LDO amplifier is responding. In most applications, one capacitor is used to support both functions. Besides its capacitance, every capacitor also contains parasitic impedances. These parasitic impedances are resistive as well as inductive. The resistive impedance is called equivalent series resistance (ESR), and the inductive impedance is called equivalent series inductance (ESL). The equivalent schematic diagram of any capacitor can therefore be drawn as shown in Figure 47. RESR LESL C Figure 47. ESR and ESL In most cases one can neglect the effect of inductive impedance ESL. Therefore, the following application focuses mainly on the parasitic resistance ESR. Figure 48 shows the output capacitor and its parasitic impedances in a typical LDO output stage. 28 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 Iout LDO + VESR RESR - Vin RLOAD Vout Cout Figure 48. LDO Output Stage with Parasitic Resistances ESR In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across the capacitor is the same as the output voltage (V(CO) = VOUT). This means no current is flowing into the CO branch. If IOUT suddenly increases (a transient condition), the following occurs: * The LDO is not able to supply the sudden current need due to its response time (t1 in Figure 45). Therefore, capacitor CO provides the current for the new load condition (dashed arrow). CO now acts like a battery with an internal resistance, ESR. Depending on the current demand at the output, a voltage drop occurs at RESR. This voltage is shown as VESR in Figure 44. * When CO is conducting current to the load, initial voltage at the load will be VO = V(CO)- VESR. Due to the discharge of CO, the output voltage VO drops continuously until the response time t1 of the LDO is reached and the LDO resumes supplying the load. From this point, the output voltage starts rising again until it reaches the regulated voltage. This period is shown as t2 in Figure 49. IO VO 1 2 ESR 1 3 ESR 2 ESR 3 t1 t2 Figure 49. Correlation of Different ESRs and Their Influence on the Regulation of VO at a Load Step from Low-to-High Output Current 29 TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels of ESRs where number 1 displays the lowest and number 3 displays the highest ESR. From above, the following conclusions can be drawn: * The higher the ESR, the larger the droop at the beginning of load transient. * The smaller the output capacitor, the faster the discharge time and the greater the voltage droop during the LDO response period. Conclusion To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the minimum output voltage requirement. Programming the TPS70102 Adjustable LDO Converter The output voltage of the TPS70102 adjustable regulators are programmed using external resistor dividers as shown in Figure 50. Resistors R1 and R2 should be chosen for approximately 50A divider current. Lower value resistors can be used, but offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at the sense terminal increase the output voltage error. The recommended design procedure is to choose R2 = 30.1k to set the divider current at approximately 50A, and then calculate R1 using Equation 1: R1 VV 1 R2 O ref (1) where: * VREF = 1.224V typ (the internal reference voltage) OUTPUT VOLTAGE PROGRAMMING GUIDE TPS70102 VI OUTPUT VOLTAGE IN 0.1 F >2.7 V EN OUT VO <0.5V R1 + R1 R2 UNIT 2.5 V 174 169 k 3.3 V 287 169 k 3.6 V 324 169 k FB GND R2 Figure 50. TPS70102 Adjustable LDO Regulator Programming Regulator Protection Both TPS701xx PMOS-pass transistors have built-in back diodes that conduct reverse currents when the input voltage drops below the output voltage (for example, during power-down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS701xx also features internal current limiting and thermal protection. During normal operation, the TPS701xx regulator 1 limits output current to approximately 1.6A (typ) and regulator 2 limits output current to approximately 750mA (typ). When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 150C (typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130C (typ), regulator operation resumes. 30 www.ti.com TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 SLVS222D - DECEMBER 1999 - REVISED NOVEMBER 2004 Power Dissipation and Junction Temperature Specified regulator operation is assured to a junction temperature of 125C; the maximum junction temperature should be restricted to 125C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max). The maximum-power-dissipation limit is determined using Equation 2: T max T A P D(max) J R JA (2) where: * TJmax is the maximum allowable junction temperature * RJA is the thermal resistance junction-to-ambient for the package; that is, 32.6C/W for the 20-terminal PWP with no airflow * TA is the ambient temperature The regulator dissipation is calculated using Equation 3: P D VIV O I O (3) Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the thermal protection circuit. 31 PACKAGE OPTION ADDENDUM www.ti.com 9-Dec-2004 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) TPS70102PWP ACTIVE HTSSOP PWP 20 70 None CU NIPDAU Level-1-220C-UNLIM TPS70102PWPR ACTIVE HTSSOP PWP 20 2000 None CU NIPDAU Level-1-220C-UNLIM TPS70145PWP ACTIVE HTSSOP PWP 20 70 None CU NIPDAU Level-1-220C-UNLIM TPS70145PWPR ACTIVE HTSSOP PWP 20 2000 None CU NIPDAU Level-1-220C-UNLIM TPS70148PWP ACTIVE HTSSOP PWP 20 70 None CU NIPDAU Level-1-220C-UNLIM TPS70148PWPR ACTIVE HTSSOP PWP 20 2000 None CU NIPDAU Level-1-220C-UNLIM TPS70151PWP ACTIVE HTSSOP PWP 20 70 None CU NIPDAU Level-1-220C-UNLIM TPS70151PWPR ACTIVE HTSSOP PWP 20 2000 None CU NIPDAU Level-1-220C-UNLIM TPS70158PWP ACTIVE HTSSOP PWP 20 70 None CU NIPDAU Level-1-220C-UNLIM TPS70158PWPR ACTIVE HTSSOP PWP 20 2000 None CU NIPDAU Level-1-220C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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