National Semiconductor ADD3501 314 Digit DVM with Multiplexed 7-Segment Output General Description The ADD3501 monolithic DVM circuit is manufactured using standard complementary MOS (CMOS) technology. A pulse modulation analog-to-digital conversion technique is used and requires no external precision components. In addition, this technique allows the use of a reference voltage that is the same polarity as the input voltage. One 5V (TTL) power supply is required. Operating with an isolated supply allows the conversion of positive as well as negative voltages. The sign of the input voltage is automati- cally determined and output on the sign pin. If the power supply is not isolated, only one polarity of voltage may be converted. The conversion rate is set by an internal oscillator. The fre- quency of the oscillator can be set by an external RC net- work or the oscillator can be driven from an external fre- quency source. When using the external RC network, a square wave output is available. It is important to note that great care has been taken to synchronize digit multiplexing with the A/D conversion timing to eliminate noise due to power supply transients. The ADD3501 has been designed to drive 7-segment multi- plexed LED displays directly with the aid of external digit buffers and segment resistors. Under condition of over- range, the overflow output will go high and the display will read + OFL or OFL, depending on whether the input volt- age is positive or negative. In addition to this, the most sig- nificant digit is blanked when zero. A start conversion input and a conversion complete output are included on all 4 versions of this product. Features Operates from single 5V supply Converts OV to + 1.999V Multiplexed 7-segment Drives segments directly No external precision component necessary Accuracy specified over temperature @ Medium speed - 200ms/conversion m Internal clock set with RC network or driven externally @ Overrange Indicated by + OFL or OFL display read- ing and OFLO output mB Analog inputs in applications shown can withstand +200 Vaits ADD3501 equivalent to MM74C935 Appiications @ Low cost digital power supply readouts @ Low cost digital multimeters @ Low cost digital panel meters @ Eliminate analog multiplexing by using remote A/D con- verters @ Convert analog transducers (temperature, pressure, dis- placement, etc.) to digital transducers Connection Diagram vec] t 2a Se ANALOG Vcc | 2 211 Se Sdt3 26[-~ $8 Somha 25[- GAD Ss T5 24, DIGIT 1 (MSO) S16 23>- DIGIT 2 oFrLo 4 ADD3501 22- DIGIT 3 CONVERSION COMPLETE J g 21} DIGIT 4 (LSD) START CONVERSION | q 20- tout SIGN 4 59 19i tin VFILTER 1 14 18 VREF VIN(-) md 42 17; sw Vinl+) cel 13 16} swz Vee4g 15} ANALOG GND TL/H/5661~1 Order Number ADD3501CCN See NS Package Number N28B 3-259 LoseaayADD3501 Absolute Maximum Ratings (note 1) If Milltary/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for avallability and specifications. Voltage at Any Pin 0.3V to Voc +0.3V Operating Temperature Range (Ta) 40C to + 85C ESD Susceptibility (Note 3) TBDV Package Dissipation at Ta= 25C derate at By amaxy = 125C/Watt above Ta = 25C Operating Vec Range Absolute Maximum Voc Lead Temp. (Soldering, +0 seconds) Storage Temperature Range Electrical Characteristics appss01 4.75V < Voc < 5.25V, 40C < Ta < +85C, unless otherwise specified. 800 mW 4.5V to 6.0V 6.5V 260C 65C to + 150C Symbol Parameter Conditions Min Typ(2)} Max Units Vint) Logical 1 Input Voltage Veco- 1.6 Vv VINO) Logical 0 Input Voltage 1.5 v Vout} Logical 0 Output Voltage lo=1.1mA (All Digital Outputs except 0.4 Vv Digit Outputs) VouT(o) Logical 0 Output Voltage Ip =0.7 MA 0.4 Vv (Digit Outputs) . Vour(t) Logical 1 Output Voltage Ip =50 MACT= 26C Voc=5V | Voc1.6 Voc1.3 Vv (All Segment Outputs) Ip =30 MA@T = 100C Voeo 1.6 Voo1.3 Vv Vouti) Logical 1 Output Voltage Ip = 500,.A (Digit Outputs) (All Digital Outputs except lo = 360,,A (Conv. Complete, Voco0.4 Vv Segment Outputs) +/, Oflo Outputs) lsounce | Output Source Current VouT= 1.0V 20 mA (Digit Outputs) . ling) Logical 1 Input Current Vin = 1.5V 10 MA (Start Conversion) lino) Logical 0 Input Current Vin=0V ~10 pA (Start Conversion) Ioc Supply Current Segments and Digits Open 0.5 10 mA fosc Oscillator Frequency 0.6/RC kHz fin Clock Frequency 100 640 kHz fo Conversion Rate fin/64,512 conv./sec faux Digit Mux Rate fin/256 Hz tBLANK Inter Digit Blanking Time 1/(32 mux) sec tscpw Start Conversion Pulse Width 200 DC ns Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC elactrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All typicals given for Ta = 25C. Note 3: Human body model, 100 pF discharged through a 1.5 k0 resistor. 3-260Electrical Characteristics appss01 tc=5 conversions/second, 0C<Tas70C, unless otherwise specified. Parameter Conditions Min Typ Max Units Non-Linearity Vin=0-2V Full Scale 0.05 +0025 +0.05 % of Vin = 0200mvV Full Scale 0.05 +0,025 +0.05 full scale Quantization Error 1 +06 counts Offset Error, Viy=0V . -0.5 +15 +3 mV Rollover Error 0 +0 counts Analog Input Current Ta=25C -5 +0.5 +5 nA (Vint. Vin7) Block Diagram ADD3501 3',,-Digit DVM Biock Diagram 34016 LATCH START CONV x DIGITAL TIMING FREG IN AND CONTROL % DIGIT 1 {MED} nr O1GITZ FREQ OUT 104 pigiTa 104 DIGIT BLANK OINGIT 4 (LS0} comma OVERFLOW AOM GNO P vg5 OVERFLOW CONV COMPLETE SIGN VREF DIGITAL Vec ANALOG Vcr VFILTER *Vin Vin ANALOG GND VFB TL/H/5681-2 3-261 LoseaqvADD3501 Theory of Operation A schematic for the analog loop is shown in Figure 7. The output of SW1 is either at Vrper or zero volts, depending on the state of the D flip-flop. If @ is at a high level Vout= Vreer and if Q is at a low level! Voy7 = OV. This volt- age is then applied to the low pass filter comprised of R1 and C1. The output of this filter, Veg, is connected to the negative input of the comparator, where it is compared to the analog input voltage, Vy. The output of the comparator is connected to the D input of the D flip-flop. Information is then transferred from the D input to the Q and Q outputs on the positive edge of clock. This loop forms an oscillator whose duty cycle is precisely related to the analog input voltage, Vip. An example will demonstrate this relationship. Assume the input voltage is equal to 0.500V. If the Q output of the D flip- flop is high then Voy will equal Veer (2.000V) and Veg will charge toward 2V with a time constant equal to RyCy. At some time Vrg will exceed 0.500V and the comparator out- put will switch to OV. At the next clock rising edge the Q output of the D flip-flop will switch to ground, causing Vout to switch to OV. At this time Veg will start discharging toward OV with a time constant R;C,. When Veg is less than 0.5V the comparator output will switch high. On the rising edge of the next clock the Q output of the D flip-flop will switch high and the process will repeat. There exists at the output of SW11 a square wave pulse train with positive amplitude Vagr and negative amplitude OV. The DC value of ms pee train is: Vout= Vrer(y J Vaer(duty cycle) a Schematic Diagram The lowpass filter will pass the DC value and then: Ves = Vrer(duty cycle) Since the closed loop system will always force Veg to equal Vin, We can then say that: Vin= Vre= Vrer(cuty cycle) or !N_ (duty cycle) VREF The duty cycle is logically ANDed with the input frequency fin. The resultant frequency f equals: f= (duty cycle) x (clock) Frequency f is accumulated by counter no. 1 for a time de- termined by counter no. 2. The count contained in counter no. 1 is then: _ f _ (duty cycle) < (clock) (count) = oook)/N (clock)/N VIN ,. ~ VAEF For the ADD3501, N= 2000. ving * Rs i ICOMPARATO b oe sw Ir: et : , Hn " J VREF { c Thte\Osw2 l LL T 4 VeB Ry | _ Co { 1 9 |) COUNTER NO. 1 (=N) RESET rm Vin= Vea = Vrer * (duty cycle) f= (duty cycle) x fiy f | | , COUNTER ND. 2(2N)| TL/H/661-3 (duty cycle) xfin_ Vin Count in Counter No. 1 = = = fin/N fin/N VREF Figure 1. Analog Loop Schematic Pulse Modulation A/D Converter 3-262General Information The timing diagram, shown in Figure 2, gives operation for the free running mode. Free running operation is obtained by connecting the Start Conversion input to logic 1 (Vcc). In this mode the analog input is continuously converted and the display is updated at a rate equal to 64,512 1/fin. The rising edge of the Conversion Complete output indi- cates that new information has been transferred from the internal counter to the display latch. This information will remain in the display jatch until the next low-to-high tran- sition of the Conversion Complete output. A logic 1" will ba maintained on the Conversion Complete output for a time equal to 64 x 1/fipy. Figure 3 gives the operation using the Start Conversion in- put. It is important to note that the Start Conversion input and Conversion Complete output do not influence the actual analog-to-digital conversion in any way. Timing Waveforms fIN mM CONVERSION CYCLE 64,512 x 1/fIN 64,000 x 1/F19 @{#_-} Internally the ADD3501 is always continuously converting the analog voltage present at its inputs. The Start Conver- sion input is used to control the transfer of information from the internal counter to the display latch. An RS latch on the Start Conversion input allows a broad range of input pulse widths to be used on this signal. As shown in Figure 3, the Conversion Complete output goes to a logic 0 on the rising edge of the Start Conversion pulse and goes to a logic 1 some time later when the new con- version is transferred from the internal counter to the dis- play latch. Since the Start Conversion pulse can occur at any time during the conversion cycle, the amount of time from Start Conversion to Conversion Complete will vary. The maximum time is 64,512 1/fiy and the minimum time is 256 x 1/fyn. (INTERNAL SIGNAL) js. 54,956 x 4/tiy - Ld py 64/fin I CONVERSION COMPLETE NEW CONVERSION CONVERSION ENDS STARTS | TLYH/S681-4 Figure 2. Conversion Cycle Timing Diagram for Free Running Operation CONVERSION CYCLE {INTERNAL SIGNAL) | | i | r@=4 Pr START CONVERSION! | | i CONVERSION ees COMPLETE se-eeae TL/H/5881-5 Figure 3. Conversion Cycle Timing Diagram Operating with Start Conversion input LoseqavADD3501 Applications SYSTEM DESIGN CONSIDERATIONS Perhaps the most important thing to consider when design- ing a system using the ADD3501 is power supply noise on the Voc and ground lines. Because a single power supply is used and currents in the 300 mA range are being switched, good circuit layout techniques cannot be overemphasized. Great care has been exercised in the design of the ADD3501 to minimize these problems but poor printed cir- cuit layout can negate these features. Figures 4, 8, and 6 show schematics of DVM systems. An attempt has been made to show, on thase schematics, the proper distribution for ground and Voc. To help isolate digi- tal and analog portions of the circuit, the analog Voc and ground have been separated from the digital Voc and ground. Care must be taken to eliminate high current from flowing in the analog Vcc and ground wires. The most effec- tive method of accomplishing this is to use a single ground point and a single Voc point where all wires are brought together. In addition to this the conductors must be of suffi- cient size to prevent significant voltage drops. To prevent switching noise from causing jitter problems, a voltage regulator with good high frequency response is nec- essary. The LM309 and the LM340-5 voltage regulators both function well and are shown in Figures 4, 5, and 6 Adding more filtering than is shown will in general increase the jitter rather than decrease it. The most important char- acteristic of transients on the Vcc line is the duration of the transient and not its amplitude. Figure 4 shows a DPM system which converts OV to 1.999V operating from a non-solated power supply. In this configu- ration the sign output could be + (logic 1) or (logic 0") and it should be ignored. Higher voltages could be con- verted by placing a fixed divider on the input; lower voltages could be converted by placing a fixed divider on the foeed- back, as shown in Figure 6. Figures 5 and & show systems operating with an isolated supply that will convert positive and negative inputs. 60 Hz common mode input becomes a probiem in this configura- tion and a transformer with an electrostatic shield between primary and secondary windings is shown. The necessity for using a shielded transformer depends on the performance requirements and the actual application. The filter capacitors connected to Veg (pin 14) and Ve_r (pin 11) should be tow leakage. In the application examples shown every 1.0nA of leakage current will cause 0.1mV er- ror (1.0x 10-94 x 100k. =0.1mV). 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