Da ta S heet, Versio n 1.7, 2 007-02-26 TDA5250 D2 ASK/FSK 868MHz Wireless Transceiver Wireless Components N e v e r s t o p t h i n k i n g . Edition 2007-02-26 Published by Infineon Technologies AG, Am Campeon 1-12, D-85579 Neubiberg, Germany (c) Infineon Technologies AG 3/7/07. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Da ta S heet, Versio n 1.7, 2 007-02-26 TDA5250 D2 ASK/FSK 868MHz Wireless Transceiver Wireless Components N e v e r s t o p t h i n k i n g . Data Sheet Revision History: 2007-02-26 Previous Version: V1.6 as of July 2002 Page Subjects (major changes since last revision) 5 indication of the Ordering Code 5, 10 correction of the Package Name 79 indication of the ESD-integrity values TDA5250 D2 For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com ABM(R), AOP(R), ARCOFI(R), ARCOFI(R)-BA, ARCOFI(R)-SP, DigiTape(R), EPIC(R)-1, EPIC(R)-S, ELIC(R), FALC(R)54, FALC(R)56, FALC(R)-E1, FALC(R)-LH, IDEC(R), IOM(R), IOM(R)-1, IOM(R)-2, IPAT(R)-2, ISAC(R)-P, ISAC(R)-S, ISAC(R)-S TE, ISAC(R)-P TE, ITAC(R), IWE(R), MUSAC(R)-A, OCTAT(R)-P, QUAT(R)-S, SICAT(R), SICOFI(R), SICOFI(R)-2, SICOFI(R)-4, SICOFI(R)-4C, SLICOFI(R) are registered trademarks of Infineon Technologies AG. ACETM, ASMTM, ASPTM, POTSWIRETM, QuadFALCTM, SCOUTTM are trademarks of Infineon Technologies AG. Controller Area Network (CAN): License of Robert Bosch GmbH ASK/FSK 868MHz Wireless Transceiver TDA5250 D2 Version 1.7 Product Info General Description The IC is a low power consumption single chip FSK/ASK Transceiver for half duplex low datarate communication in the 868-870MHz band. The IC offers a very high level of integration and needs only a few external components. It contains a highly efficient power amplifier, a low noise amplifier (LNA) with AGC, a double balanced mixer, a complex direct conversion stage, I/ Q limiters with RSSI generation, an FSK demodulator, a fully integrated VCO and PLL synthesizer, a tuneable crystal oscillator, an onboard data filter, a data comparator (slicer), positive and negative peak detectors, a data rate detection circuit and a 2/3-wire bus interface. Additionally there is a power down feature to save battery power. Features Low supply current (Is = 9mA typ. receive, Is = 12mA typ. transmit mode) On-chip low pass channel select filter and data filter with tuneable bandwidth Supply voltage range 2.1 - 5.5V Power down mode with very low supply current consumption Data slicer with self-adjusting threshold and 2 peak detectors FSK and ASK modulation and demodulation capability FSK sensitivity <-109dBm, ASK sensitivity < -109dBm Transmit power up to +13dBm Datarates encoded Self-polling logic with ultra fast data rate detection Fully integrated VCO and PLL synthesizer and loop filter on-chip with on chip crystal oscillator tuning I2C/3-wire Controller Interface up to 64kBit/s Manchester Application Low Bitrate Communication Systems Alarm Systems Telemetry Systems Keyless Entry Systems Electronic Metering Remote Control Systems Home Automation Systems Type Ordering Code Package TDA5250 D2 SP000012956 <Dev_Package1> Data Sheet 5 2007-02-26 TDA5250 D2 Version 1.7 Table of Contents page 1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.4.8 2.4.9 2.4.10 2.4.11 2.4.12 2.4.13 2.4.14 2.4.15 2.4.16 2.4.17 2.4.18 2.4.19 2.4.20 Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Amplifier (PA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Downconverter 1st Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Downconverter 2nd I/Q Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/Q Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/Q Limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bandgap Reference Circuitry & Powerdown . . . . . . . . . . . . . . . Timing and Data Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Interface and Register Definition . . . . . . . . . . . . . . . . . . . . Wakeup Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Valid Detection, Data Pin . . . . . . . . . . . . . . . . . . . . . . . . . Sequence Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RSSI and Supply Voltage Measurement . . . . . . . . . . . . . . . . . . 19 19 19 19 19 20 20 20 21 21 22 22 22 22 23 24 32 33 34 36 37 3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.1 3.1.1 3.1.2 LNA and PA Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 RX/TX Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch in RX-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch in 3.1.3 Data Sheet 6 2007-02-26 TDA5250 D2 Version 1.7 Table of Contents page 3.1.4 TX-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 44 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthesizer Frequency setting . . . . . . . . . . . . . . . . . . . . . . . . . Transmit/Receive ASK/FSK Frequency Assignment . . . . . . . . . Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calculation of the external capacitors . . . . . . . . . . . . . . . . . . . . FSK-switch modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Finetuning and FSK modulation relevant registers . . . . . . . . . . Chip and System Tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 53 53 56 57 57 58 59 3.3 IQ-Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.4 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.5 Limiter and RSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.6 3.6.1 3.6.2 3.6.3 3.6.4 Data Slicer - Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RC Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak Detector - Analog output signal . . . . . . . . . . . . . . . . . . . . Peak Detector - Power Down Mode . . . . . . . . . . . . . . . . . . . . . 64 64 65 67 67 3.7 3.7.1 3.7.2 Data Valid Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Window for Data Rate Detection . . . . . . . . . . . . . . . RSSI threshold voltage - RF input power . . . . . . . . . . . . . . . . . 68 70 71 3.8 Calculation of ON_TIME and OFF_TIME . . . . . . . . . . . . . . . . . . . 71 3.9 Example for Self Polling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.10 3.10.1 3.10.2 3.10.3 3.10.4 3.10.5 Sensitivity Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sensitivity depending on the ambient Temperature . . . . . . . . . BER performance depending on Supply Voltage . . . . . . . . . . . Datarates and Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sensitivity at Frequency Offset . . . . . . . . . . . . . . . . . . . . . . . . . 73 73 75 76 76 77 3.11 Default Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.1 4.1.1 4.1.2 4.1.3 4.1.4 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 79 79 80 83 Data Sheet 7 2007-02-26 TDA5250 D2 Version 1.7 Table of Contents page 4.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.3 Test Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Data Sheet 8 2007-02-26 TDA5250 D2 Version 1.7 Product Description 1 Product Description 1.1 Overview The IC is a low power consumption single chip FSK/ASK Transceiver for the frequency band 868870 MHz. The IC combines a very high level of integration and minimum external part count. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesizer, a crystal oscillator with FSK modulator, a limiter with RSSI generator, an FSK demodulator, a data filter, a data comparator (slicer), a positive and a negative data peak detector, a highly efficient power amplifier and a complex digital timing and control unit with I2C/3-wire microcontroller interface. Additionally there is a power down feature to save battery power. The transmit section uses direct ASK modulation by switching the power amplifier, and crystal oscillator detuning for FSK modulation. The necessary detuning load capacitors are external. The capacitors for fine tuning are integrated. The receive section is using a novel single-conversion/ direct-conversion scheme that is combining the advantages of both receive topologies. The IF is contained on the chip, no RF channel filters are necessary as the channel filter is also on the chip. The self-polling logic can be used to let the device operate autonomously as a master for a decoding microcontroller. 1.2 Features Low supply current (Is = 9 mA typ. receive, Is = 12mA typ. transmit mode, both at 3 V supply voltage, 25C) Supply voltage range 2.1 V to 5.5 V Operating temperature range -40C to +85C Power down mode with very low supply current consumption FSK and ASK modulation and demodulation capability without external circuitry changes, FM demodulation capability Fully integrated VCO and PLL synthesizer and loop filter on-chip with on-chip crystal oscillator tuning, therefore no additional external components necessary Differential receive signal path completely on-chip, therefore no external filters are necessary On-chip low pass channel select and data filter with tuneable bandwith Data slicer with self-adjusting threshold and 2 peak detectors Self-polling logic with adjustable duty cycle and ultrafast data rate detection and timer mode providing periodical interrupt FSK and ASK sensitivity < -109 dBm Adjustable LNA gain Digital RSSI and Battery Voltage Readout Provides Clock Out Pin for external microcontroller Transmit power up to +13 dBm in 50 load at 5V supply voltage Maximum datarate up to 64 kBaud Manchester encoded I2C/3-wire microcontroller interface, working at max. 400kbit/s meets the ETSI EN300 220 regulation and CEPT ERC 7003 recommendation Data Sheet 9 2007-02-26 TDA5250 D2 Version 1.7 Product Description 1.3 Application Low Bitrate Communication Systems Keyless Entry Systems Remote Control Systems Alarm Systems Telemetry Systems Electronic Metering Home Automation Systems 1.4 Package Outlines PG-TSSOP-38.EPS Figure 1-1 PG-TSSOP-38 package outlines Data Sheet 10 2007-02-26 TDA5250 D2 Version 1.7 Functional Description 2 Functional Description 2.1 Pin Configuration VCC 1 38 CI1 BUSMODE 2 37 CI1x LF ____ ASKFSK __ RxTx 3 36 CQ1 4 35 CQ1x 5 34 CI2 LNI 6 33 CI2x LNIx 7 32 CQ2 GND1 8 31 CQ2x GNDPA 9 30 GND PA 10 29 RSSI VCC1 11 28 PDN 12 27 DATA ___ PWDDD PDP 13 26 SLC 14 25 VDD 15 24 CLKDIV ______ RESET ___ EN BUSDATA 16 23 XGND BUSCLK 17 22 XSWA VSS 18 21 XIN XOUT 19 20 XSWF TDA5250 5250D1_pin_conf.wmf Figure 2-1 Data Sheet Pin Configuration 11 2007-02-26 TDA5250 D2 Version 1.7 Functional Description 2.2 Pin Definitions and Functions Table 2-1 Pin Definition and Function Pin No. Symbol Equivalent I/O-Schematic 1 VCC 1 Function Analog supply (antiparallel diodes between VCC, VCC1, VDD) 11 15 2 BUSMODE Bus mode selection (IC/3 wire bus mode selection) 350 2 3 LF Loop filter and VCO control voltage 200 3 4 ASKFSK ASK/FSK- mode switch input 350 4 Data Sheet 12 2007-02-26 TDA5250 D2 Version 1.7 Functional Description 5 RXTX RX/TX-mode switch input/output 350 5 TX 6 LNI RF input to differential Low Noise Amplifier (LNA)) 5k 6 1.1V 5k 7 180 180 PWDN 7 VCC 8 BUSMODE PWDN see Pin 6 Analog supply (antiparallel diodes between VCC, VCC1, VDD Bus mode selection (IC/3 wire bus mode selection) 30 8 18 9 9 10 GNDPA PA see Pin 8 Ground return for PA output stage PA output stage 10 10 9 GndPA 11 VCC1 Data Sheet see Pin 1 Supply for LNA and PA 13 2007-02-26 TDA5250 D2 Version 1.7 Functional Description 12 PDN Output of the negative peak detector 50k PWDN 350 50k 3k 12 13 PDP Output of the positive peakdetector 50k 350 50k 3k 13 PWDN 14 SLC Slicer level for the data slicer 1.2uA 350 50k 50k 50k 50k 50k 50k 14 1.2uA 15 16 VDD BUSDATA see Pin 1 Digital supply Bus data in/output 15k 350 16 17 BUSCLK Bus clock input 350 17 18 VSS Data Sheet see Pin 8 Ground for digital section 14 2007-02-26 TDA5250 D2 Version 1.7 Functional Description 19 XOUT Crystal oscillator output, can also be used as external reference frequency input. 4k Vcc Vcc-860mV 19 150A 20 XSWF FSK modulation switch 21 125fF ..... 4pF 20 250fF ..... 8pF 23 21 22 XIN XSWA see Pin 20 22 ASK modulation/FSK center frequency switch 20 23 23 XGND 24 EN see Pin 22 Crystal oscillator ground return 3-wire bus enable input 350 24 Data Sheet 15 2007-02-26 TDA5250 D2 Version 1.7 Functional Description 25 RESET Reset of the entire system (to default values), active low 110k 350 25 10p 26 CLKDIV Clock output 350 26 27 PWDDD Power Down input (active high), data detect output (active low) 30k 350 27 28 DATA TX Data input, RX data output (RX powerdown: pin 28 @ GND) 350 28 29 RSSI RSSI output S&H 350 29 37k Data Sheet 16p 16 2007-02-26 TDA5250 D2 Version 1.7 Functional Description 30 31 GND CQ2x see Pin 8 Analog ground Pin for external Capacitor Q-channel, stage 2 Stage1:Vcc-630mV Stage2: Vcc-560mV 31 32 33 34 35 36 37 38 CQ2 CI2x CI2 CQ1x CQ1 CI1x CI1 Data Sheet II II II II II II II Q-channel, stage 2 I-channel, stage 2 I-channel, stage 2 Q-channel, stage 1 Q-channel, stage 1 I-channel, stage 1 I-channel, stage 1 17 2007-02-26 Figure 2-2 Data Sheet ANT PA 10 (analog) (LNA/PA) 7 18 GndPA 9 PA high/low Gain (digital) fRX= 1157.73MHz fTX= 868.3MHz MIXER VCO :4 90 0 f = 289.433MHz LP FILTER LF 3 LOOP FILTER MIXER TX/RX :12/16 Channel Filter Q I PHASE DET. Charge P. TX/RX ASK FSK 6-bit SAR-ADC XIN 21 XSWF 20 -Peak Det +Peak Det 100k Data FILTER XSWA 22 CRYSTAL Osc, FSKMod, Finetuning ASK/FSK QUADRI CORRELATOR fQ= 18.0896MHz XOUT 19 ASK DATA LIMITER RSSI CQ1x CQ1 CI1x CI1 LNA 35 36 37 38 LIMITER CQ2x CQ2 CI2x CI2 LNIx 6 fIF= 289.433MHz Channel Filter 31 32 33 34 LNI fRF= 868.3MHz MIXER XGND 23 SLICER FSK DATA CLK Bandgap Reference 100k 100k ASK/FSK - + 24 2 Gnd1 8 Gnd 30 (analog) WAKEUP LOGIC CONTROLLER INTERFACE 17 (LNA/PA) 16 BUSDATA single ended to differential conv. ANT SLC 14 BUSCLK 15 VDD BUSMODE __ EN 1 VCC Vss 18 (digital) 4 5 27 26 28 29 25 12 13 VCC RSSI RESET PDN PDP ASKFSK RXTX PWDDD CLKDIV Data (RX/TX) 2.3 11 VCC1 TDA5250 D2 Version 1.7 Functional Description Functional Block Diagram TDA5250D1_blockdiagram_aktuell.wmf Main Block Diagram 2007-02-26 TDA5250 D2 Version 1.7 Functional Description 2.4 Functional Block Description 2.4.1 Power Amplifier (PA) The power amplifier is operating in C-mode. It can be used in either high or low power mode. In high-power mode the transmit power is approximately +13dBm into 50 Ohm at 5V and +4dBm at 2.1V supply voltage. In low power mode the transmit power is approximately -7dBm at 5V and 32dBm at 2.1V supply voltage using the same matching network. The transmit power is controlled by the D0-bit of the CONFIG register (subaddress 00H) as shown in the following Table 2-2. The default output power mode is high power mode. Table 2-2 Bit D0 Sub Address 00H: CONFIG Function Description PA_PWR 0= low TX Power, 1= high TX Power Default 1 In case of ASK modulation the power amplifier is turned fully on and off by the transmit baseband data, i.e. 100% On-Off-Keying. 2.4.2 Low Noise Amplifier (LNA) The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB and symmetrical inputs. It is possible to reduce the gain to 0 dB via logic. Table 2-3 Bit D4 2.4.3 Sub Address 00H: CONFIG Function Description LNA_GAIN 0= low Gain, 1= high Gain Default 1 Downconverter 1st Mixer The Double Balanced 1st Mixer converts the input frequency (RF) in the range of 868-870 MHz down to the intermediate frequency (IF) at approximately 290MHz. The local oscillator frequency is generated by the PLL synthesizer that is fully implemented on-chip as described in Section 2.4.5. This local oscillator operates at approximately 1157MHz in receive mode providing the above mentioned IF frequency of 290MHz. The mixer is followed by a low pass filter with a corner frequency of approximately 350MHz in order to prevent RF and LO signals from appearing in the 290MHz IF signal. 2.4.4 Downconverter 2nd I/Q Mixers The Low pass filter is followed by 2 mixers (inphase I and quadrature Q) that convert the 289MHz IF signal down to zero-IF. These two mixers are driven by a signal that is generated by dividing the local oscillator signal by 4, thus equalling the IF frequency. Data Sheet 19 2007-02-26 TDA5250 D2 Version 1.7 Functional Description 2.4.5 PLL Synthesizer The Phase Locked Loop synthesizer consists of two VCOs (i.e. transmit and receive VCO), a divider by 4, an asynchronous divider chain with selectable overall division ratio, a phase detector with charge pump and a loop filter and is fully implemented on-chip. The VCOs are including spiral inductors and varactor diodes. The center frequency of the transmit VCO is 868MHz, the center frequency of the receive VCO is 1156MHz. Generally in receive mode the relationship between local oscillator frequency fosc, the receive RF frequency fRF and the IF frequency fIF and thus the frequency that is applied to the I/Q Mixers is given in the following formula: fosc = 4/3 fRF = 4 fIF [2 - 1] The VCO signal is applied to a divider by 4 which is producing approximately 289MHz signals in quadrature. The overall division ratio of the divider chain following the divider by 4 is 12 in transmit mode and 16 in receive mode as the nominal crystal oscillator frequency is 18.083MHz. The division ratio is controlled by the RxTx pin (pin 5) and the D10 bit in the CONFIG register. 2.4.6 I/Q Filters The I/Q IF to zero-IF mixers are followed by baseband 6th order low pass filters that are used for RF-channel filtering. OP INTERNAL BUS iq_filter.wmf Figure 2-3 One I/Q Filter stage The bandwidth of the filters is controlled by the values set in the filter-register. It can be adjusted between 50 and 350kHz in 50kHz steps via the bits D1 to D3 of the LPF register (subaddress 03H). 2.4.7 I/Q Limiters The I/Q Limiters are DC coupled multistage amplifiers with offset-compensating feedback circuit and an overall gain of approximately 80dB each in the frequency range of 100Hz up to 350kHz. Receive Signal Strength Indicator (RSSI) generators are included in both limiters which produce DC voltages that are directly proportional to the input signal level in the respective channels. The resulting I- and Q-channel RSSI-signals are summed to the nominal RSSI signal. Data Sheet 20 2007-02-26 TDA5250 D2 Version 1.7 Functional Description 2.4.8 FSK Demodulator The output differential signals of the I/Q limiters are fed to a quadrature correlator circuit that is used to demodulate frequency shift keyed (FSK) signals. The demodulator gain is 2.4mV/kHz, the maximum frequency deviation is 300kHz as shown in Figure 2-4 below. The demodulated signal is applied to the ASK/FSK mode switch which is connected to the input of the data filter. The switch can be controlled by the ASKFSK pin (pin 4) and via the D11 bit in the CONFIG register. The modulation index m must be significantly larger than 2 and the deviation at least larger than 25kHz for correct demodulation of the signal. 1,6 1,5 1,4 1,3 U /V 1,2 1,1 1 0,9 0,8 0,7 0,6 0,5 -350 -300 -250 -200 -150 -100 -50 0 50 100 150 200 250 300 350 f /kHz Qaudricorrelator.wmf Figure 2-4 2.4.9 Quadricorrelator Demodulation Characteristic Data Filter The 2-pole data filter has a Sallen-Key architecture and is implemented fully on-chip. The bandwidth can be adjusted between approximately 5kHz and 102kHz via the bits D4 to D7 of the LPF register as shown in Table 3-10. Data Sheet 21 2007-02-26 TDA5250 D2 Version 1.7 Functional Description ASK / FSK OTA INTERNAL BUS data_filter.wmf Figure 2-5 2.4.10 Data Filter architecture Data Slicer The data slicer is a fast comparator with a bandwidth of 100kHz. The self-adjusting threshold is generated by a RC-network (LPF) or by use of one or both peak detectors depending on the baseband coding scheme as described in Section 3.6. This can be controlled by the D15 bit of the CONFIG register as shown in the following table. Table 2-4 Bit D15 2.4.11 Sub Address 00H: CONFIG Function Description SLICER 0= Lowpass Filter, 1= Peak Detector Default 0 Peak Detectors Two separate Peak Detectors are available. They are generating DC voltages in a fast-attack and slow-release manner that are proportional to the positive and negative peak voltages appearing in the data signal. These voltages may be used to generate a threshold voltage for non-Manchester encoded signals, for example. The time-constant of the fast-attack/slow-release action is determined by the RC network with external capacitor. 2.4.12 Crystal Oscillator The reference oscillator is an NIC oscillator type (Negative Impedance Converter) with a crystal operating in serial resonance. The nominal operating frequency of 18.083MHz and the frequencies for FSK modulation can be adjusted via 3 external capacitors. Via microcontroller and bus interface the chip-internal capacitors can be used for finetuning of the nominal and the FSK modulation frequencies. This finetuning of the crystal oscillator allows to eliminate frequency errors due to crystal or component tolerances. 2.4.13 Bandgap Reference Circuitry & Powerdown A Bandgap Reference Circuit provides a temperature stable 1.2V reference voltage for the device. A power down mode is available to switch off all subcircuits that are controlled by the bidirectional Powerdown&DataDetect PwdDD pin (pin 27) as shown in the following table. Powerdown mode can either be activated by pin 27 or bit D14 in register 00h. In powerdown mode also pin 28 (DATA) is affected (see Section 2.4.17). Data Sheet 22 2007-02-26 TDA5250 D2 Version 1.7 Functional Description Table 2-5 2.4.14 PwdDD Pin Operating States PwdDD VDD Ground/VSS Operating State Powerdown Mode Device On Timing and Data Control Unit BusMode EN BusCLK BusData The timing and data control unit contains a wake-up logic unit, an I2C/3-wire microcontroller interface, a "data valid" detection unit and a set of configuration registers as shown in the subsequent figure. REGISTERS I2C / 3Wire INTERFACE INTERNAL BUS DATA VALID DETECTOR RSSI 6 Bit ADC FSK DATA CONTROL LOGIC ASK DATA BLOCK ENABLE CLKDiv PwdDD Data ASK / FSK RX / TX 32kHz RC-Osz. DATA VALID FREQUENCY window TH1<TGATE<TH2 RX DATA WAKEUP LOGIC AMPLITUDE threshold TH3 ENABLE RF - BLOCK 18 MHz XTAL-Osz. AskFsk POWER ON SEQUENCER RxTx Reset logic.wmf Figure 2-6 Timing and Data Control Unit The I2C / 3-wire Bus Interface gives an external microcontroller full control over important system parameters at any time. It is possible to set the device in three different modes: Slave Mode, Self Polling Mode and Timer Mode. This is done by a state machine which is implemented in the WAKEUP LOGIC unit. A detailed description is given in Section 2.4.16. Data Sheet 23 2007-02-26 TDA5250 D2 Version 1.7 Functional Description The DATA VALID DETECTOR contains a frequency window counter and an RSSI threshold comparator. The window counter uses the incoming data signal from the data slicer as the gating signal and the crystal oscillator frequency as the timebase to determine the actual datarate. The result is compared with the expected datarate. The threshold comparator compares the actual RSSI level with the expected RSSI level. If both conditions are true the PwdDD pin is set to LOW in self polling mode as you can see in Section 2.4.16. This signal can be used as an interrupt for an external P. Because the PwdDD pin is bidirectional and open drain driven by an internal pull-up resistor it is possible to apply an external LOW thus enabling the device. 2.4.15 Bus Interface and Register Definition The TDA5250 supports the I2C bus protocol (2 wire) and a 3-wire bus protocol. Operation is selectable by the BusMode pin (pin 2) as shown in the following table. All bus pins (BusData, BusCLK, EN, BusMode) have a Schmitt-triggered input stage. The BusData pin is bidirectional where the output is open drain driven by an internal 15k pull up resistor. Table 2-6 Bus Interface Format Function BusMode 2 Low I C Mode 3-wire Mode High EN High= inactive, Low= active BusCLK Clock input BusData Data in/out BusData 17 EN 24 FRONTEND 16 BusCLK I2C / 3-wire INTERFACE INTERNAL BUS BusMode 2 11100000 CHIP ADDRESS i2c_3w_bus.wmf Figure 2-7 Bus Interface Note: The Interface is able to access the internal registers at any time, even in POWER DOWN mode. There is no internal clock necessary for Interface operation. I2C Bus Mode In this mode the BusMode pin (pin 2) = LOW and the EN pin (pin 24) = LOW. Data Sheet 24 2007-02-26 TDA5250 D2 Version 1.7 Functional Description Data Transition: Data transition on the pin BusData can only occur when BusCLK is LOW. BusData transitions while BusCLK is HIGH will be interpreted as start or stop condition. Start Condition (STA): A start condition is defined by a HIGH to LOW transition of the BusData line while BusCLK is HIGH. This start condition must precede any command and initiate a data transfer onto the bus. Stop Condition (STO): A stop condition is defined by a LOW to HIGH transition of the BusData line while BusCLK is HIGH. This condition terminates the communication between the devices and forces the bus interface into the initial state. Acknowledge (ACK): Indicates a successful data transfer. The transmitter will release the bus after sending 8 bit of data. During the 9th clock cycle the receiver will set the SDA line to LOW level to indicate it has received the 8 bits of data correctly. Data Transfer Write Mode: To start the communication, the bus master must initiate a start condition (STA), followed by the 8bit chip address. The chip address for the TDA5250 is fixed as 1110000" (MSB at first). The last bit (LSB=A0) of the chip address byte defines the type of operation to be performed: A0=0, a write operation is selected and A0=1 a read operation is selected. After this comparison the TDA5250 will generate an ACK and awaits the desired sub address byte (00H...0FH) and data bytes. At the end of the data transition the master has to generate the stop condition (STO). Data Transfer Read Mode: To start the communication in the read mode, the bus master must initiate a start condition (STA), followed by the 8 bit chip address (write: A0=0), followed by the sub address to read (80H, 81H), followed by the chip address (read: A0=1). After that procedure the data of the selected register (80H, 81H) is read out. During this time the data line has to be kept in HIGH state and the chip sends out the data. At the end of data transition the master has to generate the stop condition (STO). Bus Data Format in I2C Mode Table 2-7 MSB 1 1 Data Sheet Chip address Organization 1 1 1 1 0 0 0 0 0 0 0 0 LSB 0 1 25 Function Chip Address Write Chip Address Read 2007-02-26 TDA5250 D2 Version 1.7 Functional Description I2C Bus Write Mode 8 Bit Table 2-8 MSB STA CHIP ADDRESS (WRITE) 1 1 1 0 STA 1 0 0 0 1 1 0 0 0 0 0 1 SUB ADDRESS (WRITE) 00H...08H, 0DH, 0EH, 0FH S7 S6 S5 S4 S3 S2 S1 LSB MSB S0 ACK D7 DATA IN LSB D6 D5 D4 D3 D2 D1 D0 ACK STO 1 Table 2-10 0 0 0 0 0 ACK S7 SUB ADDRESS (WRITE) 00H...08H, 0DH, 0EH, 0FH S6 S5 S4 S3 S2 S1 LSB S0 MSB DATA IN LSB ACK D15 ... D8 ACK D7 D6 ... D0 ACK STO MSB ACK S7 SUB ADDRESS (READ) 80H, 81H S6 S5 S4 S3 S2 LSB S1 MSB S0 ACK STA 1 CHIP ADDRESS (READ) 1 1 0 0 0 0 LSB 1 ACK I2C Bus Read Mode (continued) MSB R7 MSB I2C Bus Read Mode MSB CHIP ADDRESS (WRITE) LSB 1 ACK CHIP ADDRESS (WRITE) LSB Table 2-10 STA MSB I2C Bus Write Mode 16 Bit Table 2-9 MSB 0 LSB DATA OUT FROM SUB ADDRESS R6 R5 R4 R3 LSB R2 R1 R0 ACK* STO * mandatory HIGH 3-wire Bus Mode In this mode pin 2 (BusMode)= HIGH and Pin 16 (BusData) is in the data input/output pin. Pin 24 (EN) is used to activate the bus interface to allow the transfer of data to / from the device. When pin 24 (EN) is inactive (HIGH), data transfer is inhibited. Data Transition: Data transition on pin 16 (BusData) can only occur if the clock BusCLK is LOW. To perform a data transfer the interface has to be enabled. This is done by setting the EN line to LOW. A serial transfer is done via BusData, BusCLK and EN. The bit stream needs no chip address. Data Transfer Write Mode: To start the communication the EN line has to be set to LOW. The desired sub address byte and data bytes have to follow. The subaddress (00H...0FH) determines which of the data bytes are transmitted. At the end of data transition the EN must be HIGH. Data transfer Read Mode: To start the communication in the read mode, the EN line has to be set to LOW followed by the sub address to read (80H, 81H). Afterwards the device is ready to read out data. At the end of data transition EN must be HIGH. Data Sheet 26 2007-02-26 TDA5250 D2 Version 1.7 Functional Description Bus Data Format 3-wire Bus Mode Table 2-11 3-wire Bus Write Mode MSB SUB ADDRESS (WRITE) 00H...08H, 0DH, 0EH,0FH S7 S6 S5 S4 S3 S2 S1 LSB MSB S0 Table 2-12 3-wire Bus Read Mode MSB SUB ADDRESS (READ) 80H, 81H S7 S6 S5 S4 S3 S2 S1 DX DATA IN X...0 (X=7 or 15) ... D5 R6 DATA OUT FROM SUB ADDRESS R5 R4 R3 R2 LSB MSB S0 R7 D4 D3 D2 LSB D1 D0 LSB R1 R0 Register Definition Sub Addresses Overview ADC RSSI [8 Bit] FILTER I2C - SPI INTERFACE CONTROL WAKEUP CONFIG [16 Bit] STATUS [8 Bit] CLK_DIV [8 Bit] BLOCK_PD [16Bit] ON_TIME [16 Bit] OFF_TIME [16 Bit] COUNT_TH1 [16Bit] COUNT_TH2 [16Bit] RSSI_TH3 [8 Bit] LPF [8 Bit] XTAL XTAL_TUNE [16Bit] FSK [16Bit] XTAL_CONFIG [8 Bit] register_overview.wmf Figure 2-8 Data Sheet Sub Addresses Overview 27 2007-02-26 TDA5250 D2 Version 1.7 Functional Description Subaddress Organization Table 2-13 Sub Addresses of Data Registers Write MSB 0 0 0 0 0 0 0 LSB 0 HEX 00h Function CONFIG Description General definition of status bits Bit Length 16 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 01h 02h FSK XTAL_TUNING Values for FSK-shift Nominal frequency 16 16 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 03h 04h LPF ON_TIME I/Q and data filter cutoff frequencies ON time of wakeup counter 8 16 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 05h 06h OFF_TIME COUNT_TH1 OFF time of wakeup counter Lower threshold of window counter 16 16 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 07h 08h COUNT_TH2 RSSI_TH3 Higher threshold of window counter Threshold for RSSI signal 16 8 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0Dh 0Eh CLK_DIV XTAL_CONFIG Configuration and Ratio of clock divider XTAL configuration 8 8 0 0 0 0 1 1 1 1 0Fh BLOCK_PD Building Blocks Power Down 16 Table 2-14 Sub Addresses of Data Registers Read MSB 1 0 0 0 0 0 0 LSB 0 HEX 80h Function STATUS Description Results of comparison: ADC & WINDOW Bit Length 8 1 0 0 0 0 0 0 1 81h ADC ADC data out 8 Data Byte Specification Table 2-15 Sub Address 00H: CONFIG Bit D15 D14 D13 D12 Function SLICER ALL_PD TESTMODE CONTROL D11 D10 D9 D8 D7 D6 D5 D4 D3 ASK_NFSK RX_NTX CLK_EN RX_DATA_INV D_OUT ADC_MODE F_COUNT_MODE LNA_GAIN EN_RX D2 D1 D0 MODE_2 MODE_1 PA_PWR Description 0= Lowpass, 1= Peak Detector 0= normal operation, 1= all Power down 0= normal operation, 1=Testmode 0= RX/TX and ASK/FSK external controlled, 1= Register controlled 0= FSK, 1=ASK 0= TX, 1=RX 0= CLK off during power down, 1= always CLK on, ever in PD 0= no Data inversion, 1= Data inversion 0= Data out if valid, 1= always Data out 0= one shot, 1= continuous 0= one shot, 1= continuous 0= low gain, 1= high gain 0= disable receiver, 1= enable receiver (in self polling and timer mode) * 0= slave mode, 1= timer mode 0= slave or timer mode, 1= self polling mode 0= low TX Power, 1= high TX Power Default 0 0 0 0 0 1 0 0 1 1 1 1 1 0 0 1 Note D3: Function is only active in selfpolling and timer mode. When D3 is set to LOW the RX path is not enabled if PwdDD pin is set to LOW. A delayed setting of D3 results in a delayed power ON of the RX building blocks. Data Sheet 28 2007-02-26 TDA5250 D2 Version 1.7 Functional Description Subaddress Organization Table 2-16 Sub Addresses of Data Registers Write MSB 0 0 0 0 0 0 0 LSB 0 HEX 00h Function CONFIG Description General definition of status bits Bit Length 16 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 01h 02h FSK XTAL_TUNING Values for FSK-shift Nominal frequency 16 16 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 03h 04h LPF ON_TIME I/Q and data filter cutoff frequencies ON time of wakeup counter 8 16 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 05h 06h OFF_TIME COUNT_TH1 OFF time of wakeup counter Lower threshold of window counter 16 16 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 07h 08h COUNT_TH2 RSSI_TH3 Higher threshold of window counter Threshold for RSSI signal 16 8 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0Dh 0Eh CLK_DIV XTAL_CONFIG Configuration and Ratio of clock divider XTAL configuration 8 8 0 0 0 0 1 1 1 1 0Fh BLOCK_PD Building Blocks Power Down 16 Table 2-17 Sub Addresses of Data Registers Read MSB Function Description Bit Length 1 0 0 0 0 0 0 LSB HEX 0 80h STATUS Results of comparison: ADC & WINDOW 8 1 0 0 0 0 0 0 1 81h ADC ADC data out 8 Data Byte Specification Table 2-18 Sub Address 00H: CONFIG Bit Function Description Default D15 D14 SLICER ALL_PD 0= Lowpass, 1= Peak Detector 0= normal operation, 1= all Power down 0 0 D13 D12 TESTMODE CONTROL 0= normal operation, 1=Testmode 0= RX/TX and ASK/FSK external controlled, 1= Register controlled 0 0 D11 D10 ASK_NFSK RX_NTX 0= FSK, 1=ASK 0= TX, 1=RX 0 1 D9 D8 CLK_EN RX_DATA_INV 0= CLK off during power down, 1= always CLK on, ever in PD 0= no Data inversion, 1= Data inversion 0 0 D7 D6 D_OUT ADC_MODE 0= Data out if valid, 1= always Data out 0= one shot, 1= continuous 1 1 D5 D4 F_COUNT_MODE LNA_GAIN 0= one shot, 1= continuous 0= low gain, 1= high gain 1 1 D3 D2 EN_RX MODE_2 0= disable receiver, 1= enable receiver (in self polling and timer mode) * 0= slave mode, 1= timer mode 1 0 D1 D0 MODE_1 PA_PWR 0= slave or timer mode, 1= self polling mode 0= low TX Power, 1= high TX Power 0 1 Note D3: Function is only active in selfpolling and timer mode. When D3 is set to LOW the RX path is not enabled if PwdDD pin is set to LOW. A delayed setting of D3 results in a delayed power ON of the RX building blocks. Data Sheet 29 2007-02-26 TDA5250 D2 Version 1.7 Functional Description Table 2-19 Bit Sub Address 01H: FSK Function Value Table 2-20 Sub Address 02H: XTAL_TUNING Description Default Bit Description Default D15 not used 0 D15 not used 0 D14 not used 0 D14 not used 0 Setting for positive frequency shift: +FSK or ASK-RX 0 D13 not used 0 0 D12 not used 0 1 D11 not used 0 0 D10 not used 0 1 D9 not used 0 D13 FSK+5 8pF D12 FSK+4 4pF D11 FSK+3 2pF D10 FSK+2 1pF D9 FSK+1 500fF D8 FSK+0 250fF Function Value 0 D8 not used 0 D7 not used 0 D7 not used 0 D6 not used 0 D6 not used 0 Setting for negative frequency shift: -FSK 0 D5 Nominal_Frequ_5 8pF 0 D4 Nominal_Frequ_4 4pF Setting for nominal frequency 1 D5 FSK-5 4pF D4 FSK-4 2pF D3 FSK-3 1pF 1 D3 Nominal_Frequ_3 2pF D2 FSK-2 500fF 1 D2 Nominal_Frequ_2 1pF D1 FSK-1 250fF 0 D1 Nominal_Frequ_1 500fF D0 FSK-0 125fF 0 D0 Nominal_Frequ_0 250fF Table 2-22 Table 2-21 Sub Address 03H: LPF Bit Function D7 Datafilter_3 D6 Datafilter_2 D5 Datafilter_1 D4 Datafilter_0 D3 IQ_Filter_2 D2 IQ_Filter_1 D1 IQ_Filter_0 D0 not used Table 2-23 Description Default 0 3dB cutoff frequency of data filter 0 0 1 3dB cutoff frequency of IQ-filter 1 0 0 0 Sub Address 06H: COUNT_TH1 Bit Function Default D15 not used 0 D14 not used 0 D13 not used 0 D12 not used 0 D11 TH1_11 0 D10 TH1_10 0 D9 TH1_9 0 D8 TH1_8 0 D7 TH1_7 0 D6 TH1_6 0 D5 TH1_5 0 D4 TH1_4 0 D3 TH1_3 0 D2 TH1_2 0 D1 TH1_1 0 D0 TH1_0 0 Data Sheet 0 0 ASK-TX FSK-RX 1 0 Sub Addresses 04H / 05H: ON/OFF_TIME Bit Function Default ON_TIME Default OFF_TIME D15 ON_15 / OFF_15 1 1 D14 ON_14 / OFF_14 1 1 D13 ON_13 / OFF_13 1 1 D12 ON_12 / OFF_12 1 1 D11 ON_11 / OFF_11 1 0 D10 ON_10 / OFF_10 1 0 D9 ON_9 / OFF_9 1 1 D8 ON_8 / OFF_8 0 1 D7 ON_7 / OFF_7 1 1 D6 ON_6 / OFF_6 1 0 D5 ON_5 / OFF_5 0 0 D4 ON_4 / OFF_4 0 0 D3 ON_3 / OFF_3 0 0 D2 ON_2 / OFF_2 0 0 D1 ON_1 / OFF_1 0 0 D0 ON_0 / OFF_0 0 0 Table 2-24 30 0 Sub Address 07H: COUNT_TH2 Bit Function Default D15 not used 0 D14 not used 0 D13 not used 0 D12 not used 0 D11 TH2_11 0 D10 TH2_10 0 D9 TH2_9 0 D8 TH2_8 0 D7 TH2_7 0 D6 TH2_6 0 D5 TH2_5 0 D4 TH2_4 0 D3 TH2_3 0 D2 TH2_2 0 D1 TH2_1 0 2007-02-26 TDA5250 D2 Version 1.7 Functional Description Table 2-25 Sub Address 08H: RSSI_TH3 Bit Function D7 not used D6 SELECT D5 Description Table 2-26 Sub Address 0DH: CLK_DIV Default Bit Function Default 1 D7 not used 0 1 D6 not used 0 TH3_5 1 D5 DIVMODE_1 0 D4 TH3_4 1 D4 DIVMODE_0 0 D3 TH3_3 1 D3 CLKDIV_3 1 D2 TH3_2 1 D2 CLKDIV_2 0 D1 TH3_1 1 D1 CLKDIV_1 0 D0 TH3_0 1 D0 CLKDIV_0 0 0= VCC, 1= RSSI Table 2-27 Bit Description Default D7 not used 0 D6 not used 0 D5 not used 0 D4 not used 0 D3 not used 0 only in bipolar mode 0 D2 FSK-Ramp 0 D1 FSK-Ramp 1 D0 Bipolar_FET Table 2-28 Table 2-29 Bit Sub Address 0EH: XTAL_CONFIG Function 0 0= FET, 1=Bipolar Sub Address 0FH: BLOCK_PD Bit Function Description Default D15 REF_PD 1= power down Band Gap Reference 1 D14 RC_PD 1= power down RC Oscillator 1 D13 WINDOW_PD 1= power down Window Counter 1 D12 ADC_PD 1= power down ADC 1 D11 PEAK_DET_PD 1= power down Peak Detectors 1 D10 DATA_SLIC_PD 1= power down Data Slicer 1 D9 DATA_FIL_PD 1= power down Data Filter 1 D8 QUAD_PD 1= power down Quadri Correlator 1 D7 LIM_PD 1= power down Limiter 1 D6 I/Q_FIL_PD 1= power down I/Q Filters 1 D5 MIX2_PD 1= power down I/Q Mixer 1 D4 MIX1_PD 1= power down 1st Mixer 1 D3 LNA_PD 1= power down LNA 1 D2 PA_PD 1= power down Power Amplifier 1 D1 PLL_PD 1= power down PLL 1 D0 XTAL_PD 1= power down XTAL Oscillator 1 Table 2-30 Sub Address 80H: STATUS Function 1 Sub Address 81H: ADC Description Bit Function Description PD_ADC ADC power down feedback Bit D7 COMP_LOW 1 if data rate < TH1 D7 D6 COMP_IN 1 if TH1 < data rate < TH2 D6 SELECT SELECT feedback Bit D5 COMP_HIGH 1 if TH2 < data rate D5 RSSI_5 RSSI value Bit5 RSSI_4 RSSI value Bit4 D4 COMP_0,5*LOW 1 if data rate < 0,5*TH1 D4 D3 COMP_0,5*IN 1 if 0,5*TH1 < data rate < 0,5*TH2 D3 RSSI_3 RSSI value Bit3 D2 COMP_0,5*HIGH 1 if 0,5*TH2 < data rate D2 RSSI_2 RSSI value Bit2 RSSI_1 RSSI value Bit1 RSSI_0 RSSI value Bit0 D1 RSSI=TH3 1 if RSSI value is equal TH3 D1 D0 RSSI>TH3 1 if RSSI value is greater than TH3 D0 Data Sheet 31 2007-02-26 TDA5250 D2 Version 1.7 Functional Description 2.4.16 Wakeup Logic SLAVE MODE (default) MODE_1 = 0 MODE_2 = 0 SELF POLLING MODE TIMER MODE MODE_1 = 1 MODE_2 = X MODE_1 = 0 MODE_2 = 1 3_modes.wmf Figure 2-9 Wakeup Logic States Table 2-31 MODE settings: CONFIG register MODE_1 MODE_2 0 0 0 1 1 X Mode SLAVE MODE TIMER MODE SELF POLLING MODE SLAVE MODE: The receive and transmit operation is fully controlled by an external control device via the respective RxTx, AskFsk, PwdDD, and Data pins. The wakeup logic is inactive in this case. After RESET or 1st Power-up the chip is in SLAVE MODE. By setting MODE_1 and MODE_2 in the CONFIG register the mode may be changed. SELF POLLING MODE: The chip turns itself on periodically to receive using a built-in 32kHz RC oscillator. The timing of this is determined by the ON_TIME and OFF_TIME registers, the duty cycle can be set between 0 and 100% in 31.25s increments. The data detect logic is enabled and a 15s LOW impulse is provided at PwdDD pin (Pin 27), if the received data is valid. ON_TIME Action OFF_TIME RX ON: valid Data ON_TIME RX ON: invalid Data t PwdDD pin in SELF POLLING MODE t min. 2.6ms 15s timing_selfpllmode.wmf Figure 2-10 Data Sheet Timing for Self Polling Mode (ADC & Data Detect in one shot mode) 32 2007-02-26 TDA5250 D2 Version 1.7 Functional Description Note: The time delay between start of ON time and the 15s LOW impulse is 2.6ms + 3 period of data rate. If ADC & Data Detect Logic are in continuous mode the 15s LOW impulse is applied at PwdDD after each data valid decision. In self polling mode if D9=0 (Register 00h) and when PwdDD pin level is HIGH the CLK output is on during ON time and off during OFF time. If D9=1, the CLK output is always on. TIMER MODE: Only the internal Timer (determined by the ON_TIME and OFF_TIME registers) is active to support an external logic with periodical Interrupts. After ON_TIME + OFF_TIME a 15s LOW impulse is applied at the PwdDD pin (Pin 27). Action ON_TIME OFF_TIME ON_TIME Register 04H Register 05H Register 04H PwdDD pin in TIMER MODE t t 15s 15s timing_timermode.wmf Figure 2-11 2.4.17 Timing for Timer Mode Data Valid Detection, Data Pin Data signals generate a typical spectrum and this can be used to determine if valid data is on air. Amplitude Frequency & RSSI Window DATA on air no DATA on air RSSI Frequency f data_rate_detect.wmf Figure 2-12 Frequency and RSSI Window The "data valid" criterion is generated from the result of RSSI-TH3 comparison and tGATE between TH1 and TH2 result as shown below. In case of Manchester coding the 0,5*TH1 and 0,5*TH2 gives improved performance. The use of permanent data valid recognition makes it absolutely necessary to set the RSSI-ADC and the Window counter into continuous mode (Register 00H, Bit D5 = D6 = 1). Data Sheet 33 2007-02-26 TDA5250 D2 Version 1.7 Functional Description 0,5*TH1 TGATE TH1 0,5*TH2 TGATE TH2 RSSI TH3 DATA VALID data_valid.wmf Figure 2-13 Data Valid Circuit D_OUT and RX_DATA_INV from the CONFIG register determine the output of data at Pin 28. RxTxint and TX_ON are internally generated signals. In RX and power down mode Data pin (Pin 28) is tied to GND. RxTxint RX_DATA_INV RX DATA Data DATA VALID 28 D_OUT TX DATA TX ON data_switch.wmf Figure 2-14 2.4.18 Data Input/Output Circuit Sequence Timer The sequence timer has to control all the enable signals of the analog components inside the chip. The time base is the 32 kHz RC oscillator. After the first POWER ON or RESET a 1 MHz clock is available at the clock output pin. This clock output can be used by an external P to set the system into the desired state and outputs valid data after 500 s (see Figure 2-15 and Figure 2-16, tCLKSU) There are two possibilities to start the device after a reset or first power on: - PWDDD pin is LOW: Normal operation timing is performed after tSYSSU (see Figure 2-15). - PWDDD pin is HIGH (device in power down mode): A clock is offered at the clock output pin until the device is activated (PWDDD pin is pulled to LOW). After the first activation the time tSYSSU is required until normal operation timing is performed (see Figure 2-16 ). This could be used to extend the clock generation without device programming or activation. Note: It is required to activate the device for the duration of tSYSSU after first power on or a reset. Only if this is done the normal operation timing is performed. Data Sheet 34 2007-02-26 TDA5250 D2 Version 1.7 Functional Description With default settings the clock generating units are disabled during PD, therefore no clock is available at the clock output pin. It is possible to offer a clock signal at the clock output pin every time (also during PD) if the CLK_EN Bit in the CONFIG register is set to HIGH. RESET or 1st POWER ON PWDDD = low STATUS XTAL EN TX activ or RX activ PD * CLOCK FOR EXTERNAL P DC OFFSET COMPENSATION TX activ PD RX activ TX activ RX activ * if RX PEAK DETECTOR EN if RX DATADETECTION EN if RX POWER AMP EN if TX tCLKSU tCLKSU tTXSU 0.5ms tCLKSU 0.5ms tTXSU 1.1ms 0.5ms tTXSU 1.1ms 1.1ms tSYSSU tRXSU tRXSU tDDSU tDDSU 2.2ms 8ms tRXSU 2.2ms 2.6ms 2.2ms 2.6ms tDDSU 2.6ms Sequenzer_Timing_pupstart.wmf Figure 2-15 1st start or reset in active mode Note: The time values are typical values RESET or 1st POWER ON PWDDD = high PWDDD = low STATUS PD XTAL EN CLOCK FOR EXTERNAL P TX activ or RX activ PD TX activ RX activ * DC OFFSET COMPENSATION if RX PEAK DETECTOR EN if RX DATADETECTION EN if RX POWER AMP EN if TX tCLKSU tCLKSU 0.5ms tTXSU 0.5ms 1.1ms tTXSU 1.1ms tRXSU tSYSSU 2.2ms 8ms tRXSU 2.2ms tDDSU 2.6ms tDDSU 2.6ms Sequenzer_Timing_pdstart.wmf Figure 2-16 1st start or reset in PD mode * State is either I" or O" depending on time of setting into powerdown. Note: The time values are typical values Data Sheet 35 2007-02-26 TDA5250 D2 Version 1.7 Functional Description This means that the device needs tDDSU setup time to start the data detection after RX is activated. When activating TX it requires tTXSU setup time to enable the power amplifier. For timing information refer to Table 4.3. For test purposes a TESTMODE is provided by the Sequencer as well. In this mode the BLOCK_PD register be set to various values. This will override the Sequencer timing. Depending on the settings in Config Register 00H the corresponding building blocks are enabled, as shown in the subsequent figure. RC- OSC. INTERNAL BUS BLOCK_PD REGISTER ASK/FSK 16 16 ENABLE / DISABLE BUILDING BLOCKS TX ON XTAL FREQU. SELECT 16 SWITCH RX ON 2 TESTMODE ALL_PD CLK_EN 32 kHz TIMING DECODE RESET sequencer_raw.wmf Figure 2-17 2.4.19 Sequencer`s capability Clock Divider It supports an external logic with a programmable Clock at pin 26 (CLKDIV). 32 kHz WINDOW COUNT COMPLETE DIVMODE_1 SWITCH 4 BIT COUNTER DIVMODE_0 18 MHz DIVIDE BY 2 INTERNAL BUS CLKDiv 26 clk_div.wmf Figure 2-18 Clock Divider The Output Selection and Divider Ratio can be set in the CLK_DIV register. Data Sheet 36 2007-02-26 TDA5250 D2 Version 1.7 Functional Description Table 2-32 D5 0 0 1 1 CLK_DIV Output Selection D4 0 1 0 1 Output Output from Divider (default) 18.089MHz 32kHz Window Count Complete Note: Data are valid 500 s after the crystal oscillator is enabled (see Figure 2-15 and Figure 216, tCLKSU). Table 2-33 CLK_DIV Setting D3 D2 D1 D0 Total Divider Ratio 0 0 0 0 2 0 0 1 4 0 0 0 1 0 6 0 0 1 1 8 0 1 0 0 10 0 1 0 1 12 0 1 1 0 14 1 1 1 16 0 1 0 0 0 18 1 0 0 1 20 1 0 1 0 22 1 0 1 1 24 1 1 0 0 26 1 0 1 28 1 1 1 1 0 30 1 1 1 1 32 Output Frequency [MHz] 9,0 4,5 3,0 2,25 1,80 1,50 1,28 1,125 1,00 (default) 0,90 0,82 0,75 0,69 0,64 0,60 0,56 Note: As long as default settings are used, there is no clock available at the clock output during Power Down. It is possible to enable the clock during Power Down by setting CLK_EN (Bit D9) in the Config Register (00H) to HIGH. 2.4.20 RSSI and Supply Voltage Measurement The input of the 6Bit-ADC can be switched between two different sources: the RSSI voltage (default setting) or a resistor network dividing the Vcc voltage by 5. Table 2-34 Source for 6Bit-ADC Selection (Register 08H) SELECT Input for 6Bit-ADC Vcc / 5 0 1 RSSI (default) Data Sheet 37 2007-02-26 TDA5250 D2 Version 1.7 Functional Description To prevent wrong interpretation of the ADC information (read from Register 81H: ADC) you can use the ADC- Power Down feedback Bit (D7) and the SELECT feedback Bit (D6) which correspond to the actual measurement. Note: As shown in Section 2.4.18 there is a setup time of 2.6ms after RX activating. Thus the measurement of RSSI voltage does only make sense after this setup time. Data Sheet 38 2007-02-26 TDA5250 D2 Version 1.7 Application 3 Application 3.1 LNA and PA Matching 3.1.1 RX/TX Switch VCC C5 L1 50 Ohm SMA-connector D1 C1 C2 L2 C3 R1 PA C4 C7 C9 LNI D2 L3 C10 LNIX TDA5250 RF I/O RX/TX RX/TX C6 RX/TX_Switch.wmf Figure 3-1 RX/TX Switch The RX/TX-switch combines the PA-output and the LNA-input into a single 50 Ohm SMAconnector. Two pin-diodes are used as switching elements. If no current flows through a pin diode, it works as a high impedance for RF with very low capacitance. If the pin-diode is forward biased, it provides a low impedance path for RF. (some ) 3.1.2 Switch in RX-Mode The RX/TX-switch is set to the receive mode by either applying a high level or an open to the RX/ TX-jumper on the evalboard or by leaving it open. Then both pin-diodes are not biased and therefore have a high impedance. Data Sheet 39 2007-02-26 TDA5250 D2 Version 1.7 Application VCC C5 L1 50 Ohm SMA-connector C1 C2 L2 R1 C3 PA C4 C7 C9 LNI L3 C10 LNIX TDA5250 RF I/O RX/TX open or VCC RX/TX C6 RX_Mode.wmf Figure 3-2 RX-Mode The RF-signal is able to run from the RF-input-SMA-connector to the LNA-input-pin LNI via C1, C2, C7, L3 and C9. R1 does not affect the matching circuit due to its high resistance. The other input of the differential LNA LNIX can always be AC-grounded using a large capacitor without any loss of performance. In this case the differential LNA can be used as a single ended LNA, which is easier to match. The S11 of the LNA at pin LNI on the evalboard is 0.945 / -47 (equals a resistor of 1.43kOhm in parallel to a capacitor of 1.6pF) for both high and low-gain-mode of the LNA. (pin LNIX AC-grounded) This impedance has to be matched to 50 Ohm with the parts C9, L3, C7 and C2. C1 is DC-decoupling-capacitor. On the evalboard the most important matching components are (shunt) L3 and (series) C2. The capacitors C7 and C9 are mainly DC-decoupling-capacitors and may be used for some fine tuning of the matching circuit. A good CAE tool (featuring smith-chart) may be used for the calculation of the values of the components. However, the final values of the matching components always have to be found on the board because of the parasitics of the board, which highly influence the matching circuit at RF. Data Sheet 40 2007-02-26 TDA5250 D2 Version 1.7 Application Measured Magnitude of S11 of evalboard: S11_measured.pcx. Figure 3-3 S11 measured Above you can see the measured S11 of the evalboard. The -3dB-points are at 810MHz and 930MHz. So the 3dB-bandwidth is: B = f U - f L = 930MHz - 810MHz = 120MHz The loadedf Q of the868 resonant ,3MHz circuit is: QL = center B = 120 MHz = 7 .2 [3 - 1] [3 - 2] The unloaded Q of the resonant circuit is equal to the Q of the inductor due to its losses. [3 - 3] QU = QINDUCTOR 36 @ 868MHz An approximation of the losses of the input matching network can be made with the formula: Q Loss = -20 log1 - L QU 7 .2 = -20 log1 - = 2dB 36 [3 - 4] The noise figure of the LNA-input-matching network is equal to its losses. The input matching network is always a compromise of sensitivity and selectivity. The loaded Q should not get too high because of 2 reasons: more losses in the matching network and hence less sensitivity Data Sheet 41 2007-02-26 TDA5250 D2 Version 1.7 Application tolerances of components affect matching too much. This will cause problems in a tuning-free mass production of the application. A good CAE-tool will help to see the effects of component tolerances on the input matching more accurate by tweaking each value. A very high selectivity can be reached by using SAW-filters at the expense of higher cost and lower sensitivity which will be reduced by the losses of the SAW-Filter of approx. 4dB. Image-suppression: Due to the quite high 1st-IF of the frontend, the image frequency is quite far away. The image frequency of the receiver is at: f IMAGE = f SIGNAL + 2 f IF = 868.3MHz + 2 * 289.4 = 1447.2MHz [3 - 5] The image suppression on the evalboard is about 16dB. LO-leakage: The LO of the 1st Mixer is at: f LO = f RECEIVE * 4 4 = 868.3MHz = 1157.73MHz 3 3 [3 - 6] The LO-leakage of the evalboard on the RF-input is about -98dBm. This is far below the ETSIradio-regulation-limit for LO-leakage. 3.1.3 Switch in TX-Mode The evalboard can be set into the TX-Mode by grounding the RX/TX-jumper on the evalboard or programming the TDA5250 to operate in the TX-Mode. If the IC is programmed to operate in the TX-Mode, the RX/TX-pin will act as an open drain output at a logical LOW. Then a DC-current can flow from VCC to GND via L1, L2, D1, R1 and D2. I PIN - DIODE = Vcc - 2 V FORWARD , PIN - DIODE [3 - 7] R1 Now both pin-diodes are biased with a current of approx. 0.3mA@3V and have a very low impedance for RF. Data Sheet 42 2007-02-26 TDA5250 D2 Version 1.7 Application VCC C5 L1 C1 50 Ohm SMA-connector C2 L2 C3 R1 PA C4 C7 C9 LNI C10 L3 RX/TX grounded (with jumper or RX/TX-pin of IC) LNIX TDA5250 RF I/O RX/TX C6 TX_Mode.wmf Figure 3-4 TX_Mode R1 does not influence the matching because of its very high resistance. Due to the large capacitance of C1, C6 and C5 the circuit can be further simplified for RF: L1 RF I/O C2 C3 PA C4 C7 C9 LNI L3 C10 LNIX TDA5250 50 Ohm SMA-connector L2 TX_Mode_simplified.wmf Figure 3-5 TX_Mode_simplified The LNA-matching is RF-grounded now, so no power is lost in the LNA-input. The PA-matching consists of C2, C3 L2, C4 and L1. When designing the matching of the PA, C2 must not be changed anymore because its value is already fixed by the LNA-input-matching. Data Sheet 43 2007-02-26 TDA5250 D2 Version 1.7 Application 3.1.4 Power-Amplifier The power amplifier operates in a high efficient class C mode. This mode is characterized by a pulsed operation of the power amplifier transistor at a current flow angle of <<. A frequency selective network at the amplifier output passes the fundamental frequency component of the pulse spectrum of the collector current to the load. The load and its resonance transformation to the collector of the power amplifier can be generalized by the equivalent circuit of Figure 3-6. The tank circuit L//C//RL in parallel to the output impedance of the transistor should be in resonance at the operating frequency of the transmitter. VS L C RL Equivalent_power_wmf. Figure 3-6 Equivalent power amplifier tank circuit The optimum load at the collector of the power amplifier for "critical" operation under idealized conditions at resonance is: RLC = VS 2 2PO [3 - 8] A typical value of RLC for an RF output power of Po= 13mW is: 32 RLC = = 350 2 0.013 [3 - 9] Critical" operation is characterized by the RF peak voltage swing at the collector of the PA transistor to just reach the supply voltage VS. The high efficiency under "critical" operating conditions can be explained by the low power loss at the transistor. During the conducting phase of the transistor there is no or only a very small collector voltage present, thus minimizing the power loss of the transistor (iC*uCE). This is particularly true for low current flow angles of <<. In practice the RF-saturation voltage of the PA transistor and other parasitics will reduce the "critical" RLC. The output power Po will be reduced when operating in an "overcritical" mode at a RL > RLC. As shown in Figure 3-7, however, power efficiency E (and bandwidth) will increase by some degree when operating at higher RL. The collector efficiency E is defined as Data Sheet 44 2007-02-26 TDA5250 D2 Version 1.7 Application E= PO VS I C [3 - 10] The diagram of Figure 3-7 has been measured directly at the PA-output at VS=3V. A power loss in the matching circuit of about 2dB will decrease the output power. As shown in the diagram, 240 Ohm is the optimum impedance for operation at 3V. For an approximation of ROPT and POUT at other supply voltages those 2 formulas can be used: [3 - 11] ROPT ~ VS and POUT ~ ROPT [3 - 12] Power_E_vs_RL.wmf Figure 3-7 Output power Po (mW) and collector efficiency E vs. load resistor RL. The DC collector current Ic of the power amplifier and the RF output power Po vary with the load resistor RL. This is typical for overcritical operation of class C amplifiers. The collector current will show a characteristic dip at the resonance frequency for this type of "overcritical" operation. The depth of this dip will increase with higher values of RL. As Figure 3-8 shows, detuning beyond the bandwidth of the matching circuit results in a significant increase of collector current of the power amplifier and in some loss of output power. This diagram shows the data for the circuit of the test board at the frequency of 868 MHz. The effective load resistor of this circuit is RL= 240Ohm, which is the optimum impedance for operation at 3V. This will lead to a dip of the collector current f approx. 20%. Data Sheet 45 2007-02-26 TDA5250 D2 Version 1.7 Application pout_vs_frequ.wmf Figure 3-8 Power output and collector current vs. frequency C4, L2 and C3||C2 are the main matching components which are used to transform the 50 Ohm load at the SMA-RF-connector to a higher impedance at the PA-output (240Ohm@3V). L1 can be used for finetuning of the resonance frequency but should not be too low in order to keep its loss low. The transformed impedance of 240Ohm+j0 at the PA-output-pin can be verified with a network analyzer using this measurement procedure: 1. Calibrate your network analyzer. 2. Connect a short, low-loss 50 Ohm cable to your network analyzer with an open end on one side. Semirigid cable works best. 3. Use the Port Extension" feature of your network analyzer to shift the reference plane of your network analyzer to the open end of the cable. 4. Connect the center-conductor of the cable to the solder pad of the pin PA" of the IC. The shield has to be grounded. Very short connections must be used. Do not remove the IC or any part of the matching-components! 5. Screw a 50Ohm-dummy-load on the RF-I/O-SMA-connector 6. The TDA5250 has to be in ASK-TX-Mode, Data-Input=LOW. 7. Be sure that your network analyzer is AC-coupled and turn on the power supply of the IC. 8. Measure the S-parameter Data Sheet 46 2007-02-26 TDA5250 D2 Version 1.7 Application Sparam_measured_200M.pcx Figure 3-9 Sparam_measured_200M Above you can see the measurement of the evalboard with a span of 200MHz. The evalboard has been optimized for 3V. The load is about 240+j0 at 868.3MHz. A tuning-free realization requires a careful design of the components within the matching network. A simple linear CAE-tool will help to see the influence of tolerances of matching components. Suppression of spurious harmonics may require some additional filtering within the antenna matching circuit. Both can be seen in Figure 3-10 and Figure 3-11 The total spectrum of the evalboard can be summarized as: Carrier fc +9dBm fc-18.1MHz -62dBm fc+18.1MHz -66dBm 2nd harmonic -40dBm 3rd harmonic -44dBm Data Sheet 47 2007-02-26 TDA5250 D2 Version 1.7 Application oberwellentx.tif Figure 3-10 Transmit Spectrum 13.2GHz spektrum_10r_3v.tif Figure 3-11 Transmit Spectrum 300MHz Regarding CEPT ERC recommendation 70-03 and ETSI regulation EN 300220 both of the following figures show full compliance in case of ASK and FSK modulation spectrum. Data signal is a Manchester encoded PRBS9 (Pseudo Random Binary Sequence), RF output power is +9dBm at a supply voltage of 3V. With these settings ASK allows a maximum data rate of 25kBaud, in FSK case 40kBaud are possible. See also Section 4.1.4 Data Sheet 48 2007-02-26 TDA5250 D2 Version 1.7 Application ASK_25kBaud_Manch_PRBS9_10dBm_3V_Spectrum_CEPT_ERC7003.wmf Figure 3-12 ASK Transmit Spectrum 25kBaud, Manch, PRBS9, 9dBm, 3V FSK_40kBaud_Manch_PRBS9_10dBm_3V_Spectrum_CEPT_ERC7003.wmf Figure 3-13 FSK Transmit Spectrum 40kBaud, Manch, PRBS9, 9dBm, 3V Data Sheet 49 2007-02-26 TDA5250 D2 Version 1.7 Application 3.2 Crystal Oscillator The equivalent schematic of the crystal with its parameters specified by the crystal manufacturer can be taken from the subsequent figure. Here also the load capacitance of the crystal CL, which the crystal wants to see in order to oscillate at the desired frequency, can be seen. C1 L1 -R R1 CL C0 Crystal.wmf Figure 3-14 Crystal L1: motional inductance of the crystal C1: motional capacitance of the crystal C0: shunt capacitance of the crystal Therefore the Resonant Frequency fs of the crystal is defined as: fS = 1 2 L1 * C1 [3 - 13] The Series Load Resonant Frequency fS` of the crystal is defined as: f S = 1 2 L1 * C1 * 1+ C1 C0 + C L [3 - 14] regarding Figure 3-14 fs' is the nominal frequency of the crystal with a specified load when tested by the crystal manufacturer. Pulling Sensitivity of the crystal is defined as the magnitude of the relative change in frequency relating to the variation of the load capacitor. Data Sheet 50 2007-02-26 TDA5250 D2 Version 1.7 Application f S fS - C1 D = = 2 CL CL 2(C0 + C L ) [3 - 15] Choosing CL as large as possible results in a small pulling sensitivity. On the other hand a small CL keeps the influence of the serial inductance and the tolerances associated to it small (see formula [3-17]). Start-up Time t Start ~ L1 - R - Rext where: -R: Rext: [3 - 16] is the negative impedance of the oscillator see Figure 3-15 is the sum of all external resistances (e.g. R1 or any other resistance that may be present in the circuit, see Figure 3-14 The proportionality of L1 and C1 of the crystal is defined by formula [3-13]. For a crystal with a small C1 the start -up time will also be slower. Typically the lower the value of the crystal frequency, the lower the C1. A short conclusion regarding crystal and crystal oscillator dependencies is shown in the following table: Table 3-1 Crystal and crystal oscilator dependency Independent variable C1 > C0 > frequency of quartz > LOSC > CL > Result Relative Tolerance Maximum Deviation >> >> < < >>> > >> > > < tStart-up < << - The crystal oscillator in the TDA5250 is a NIC (negative impedance converter) oscillator type. The input impedance of this oscillator is a negative impedance in series to an inductance. Therefore the load capacitance of the crystal CL (specified by the crystal supplier) is transformed to the capacitance Cv as shown in formula [3-17]. Data Sheet 51 2007-02-26 TDA5250 D2 Version 1.7 Application -R LOSC f, CL CV TDA 5250 QOSZ_NIC.wmf Figure 3-15 CL = Crystal Oscillator 1 1 CV = 1 1 - 2 LOSC + 2 LOSC CV CL CL: : LOSC: [3 - 17] crystal load capacitance for nominal frequency angular frequency inductivity of the crystal oscillator - typ: 2.7H with pad of board 2.45H without pad With the aid of this formula it becomes obvious that the higher the serial capacitance CV is, the higher is the influence of LOSC. The tolerance of the internal oscillator inductivity is much higher, so the inductivity is the dominating value for the tolerance. FSK modulation and tuning are achieved by a variation of Cv. In case of small frequency deviations (up to +/- 1000 ppm), the desired load capacitances for FSK modulation are frequency depending and can be calculated with the formula below. 2 ( C + C ) f 0 L CL - + C 0 ---------- 1 + --------------------------------- Nf C 1 C L = -----------------------------------------------------------------------------------------2 ( C + C ) f 0 L 1 ---------- 1 + --------------------------------- Nf C 1 CL: C0: C1: f: N: Data Sheet [3 - 18] crystal load capacitance for nominal frequency shunt capacitance of the crystal motional capacitance of the crystal crystal oscillator frequency division ratio of the PLL 52 2007-02-26 TDA5250 D2 Version 1.7 Application f: peak frequency deviation With CL+ and CL- the necessary Cv+ for FSK HIGH and Cv- for FSK LOW can be calculated. Alternatively, an external AC coupled (10nF in series to 1k) signal can be applied at pin 19 (Xout). The drive level should be approximately 100mVpp. 3.2.1 Synthesizer Frequency setting Generating ASK and FSK modulation 3 setable frequencies are necessary. 3.2.1.1 Possible crystal oscillator frequencies The resulting possible crystal oscillator frequencies are shown in the following Figure 3-16 RX: TX: FSK- FSK ASK Deviation f1 ASK FSK+ Deviation f0 f2 Nominal Frequency free_reg.wmf Figure 3-16 possible crystal oscillator frequencies In ASK receive mode the crystal oscillator is set to frequency f2 to realize the necessary frequency offset to receive the ASK signal at f0*N (N: division ratio of the PLL). To set the 3 different frequencies 3 different Cv are necessary. Via internal switches 3 external capacitors can be combined to generate the necessary Cv in case of ASK- or FSK-modulation. Internal banks of switchable capacitors allow the finetuning of these frequencies. 3.2.2 Transmit/Receive ASK/FSK Frequency Assignment Depending on whether the device operates in transmit or receive mode or whether it operates in ASK or FSK the following cases can be distinguished: 3.2.2.1 FSK-mode In transmit mode the two frequencies representing logical HIGH and LOW data states have to be adjusted depending on the intended frequency deviation and separately according to the following formulas: Data Sheet 53 2007-02-26 TDA5250 D2 Version 1.7 Application fCOSC HI = (fRF + fDEV) / 48 fCOSC LOW = (fRF - fDEV) / 48 [3 - 19] e.g. fCOSC HI = (868,3E6 + 50E3) / 48 = 18.08438MHz fCOSC LOW = (868,3E6 - 50E3) / 48 = 18.08229MHz with a frequency deviation of 50kHz. Figure 3-17 shows the configuration of the switches and the capacitors to achieve the 2 desired frequencies. Gray parts of the schematics indicate inactive parts. For FSK modulation the ASKswitch is always open. For FSK LOW the FSK-switch is closed and Cv2 and Ctune2 are bypassed. The effective Cv- is given by: CV - = C v1 + C tune1 [3 - 20] For finetuning Ctune1 can be varied over a range of 8 pF in steps of 125fF. The switches of this Cbank are controlled by the bits D0 to D5 in the FSK register (subaddress 01H, see Table 3-6). For FSK HIGH the FSK-switch is open. So the effective Cv+ is given by: ( C v1 + C tune1 ) ( C v2 + C tune2 ) C v+ = --------------------------------------------------------------------------------------C v1 + C tune1 + C v2 + C tune2 [3 - 21] The C-bank Ctune2 can be varied over a range of 16 pF in steps of 250fF for finetuning of the FSK HIGH frequency. The switches of this C-bank are controlled by the bits D8 to D13 in the FSK register (subaddress 01H, see Table 3-6). L XOUT 19 -R f, CL XIN 21 CV1 CV1 Ctune1 XSWF 20 Ctune1 XSWF 20 XSWA 22 XSWA 22 CV2 Ctune2 Ctune2 ASKswitch XGND 23 FSKswitch ASKswitch CV3 FSK LOW FSKswitch CV3 XGND 23 Data Sheet -R f, CL XIN 21 CV2 L XOUT 19 FSK HIGH 54 2007-02-26 TDA5250 D2 Version 1.7 Application QOSC_FSK.wmf Figure 3-17 FSK modulation In receive mode the crystal oscillator frequency is set to yield a direct-to-zero conversion of the receive data. Thus the frequency may be calculated as fCOSC = fRF / 48, [3 - 22] e.g. fCOSC = 868,3E6 / 48 = 18.0833MHz which is identical to the ASK transmit case. XOUT 19 L -R f, CL XIN 21 CV1 Ctune1 XSWF 20 XSWA 22 CV3 Ctune2 ASKswitch XGND 23 FSKswitch CV2 QOSC_ASK.wmf Figure 3-18 FSK receive In this case the ASK-switch is closed. The necessary Cvm is given by: (C + C ) (C + C + C ) v1 tune1 v2 tune2 v3 C vm = -------------------------------------------------------------------------------------------------------C v1 + C tune1 + C v2 + C + C tune2 v3 [3 - 23] The C-bank Ctune2 can be varied over a range of 16 pF in steps of 250fF for finetuning of the FSK receive frequency. In this case the switches of the C-bank are controlled by the bits D0 to D5 of the XTAL_TUNING register (subaddress 02H, see Table 3-5). 3.2.2.2 ASK-mode: In transmit mode the crystal oscillator frequency is the same as in the FSK receive case, see Figure 3-18. In receive mode a receive frequency offset is necessary as the limiters feedback is AC-coupled. This offset is achieved by setting the oscillator frequency to the FSK HIGH transmit frequency, see Figure 3-17. Data Sheet 55 2007-02-26 TDA5250 D2 Version 1.7 Application 3.2.3 Parasitics For the correct calculation of the external capacitors the parasitic capacitances of the pins and the switches (C20, C21, C22) have to be taken into account. L XOUT 19 -R f, CL XIN 21 CV1 C21 Ctune1 XSWF 20 XSWA 22 CV2 CV3 C22 XGND 23 C20 Ctune2 QOSC_parasitics.wmf Figure 3-19 Table 3-2 parasitics of the switching network Typical values of parasitic capacitances Name Value C20 4,5 pF FSK-: 2,8 pF / FSK+&ASK: 2.3pF C21 C22 1,3 pF With the given parasitics the actual Cv can be calculated: C C C v- = C v1 +C tune1 +C [3 - 24] 21 (C + C ) (C + C + C ) v1 tune1 v2 20 tune2 = ------------------------------------------------------------------------------------------------------- + C v+ 21 C +C +C +C +C v1 tune1 v2 20 tune2 (C + C ) (C + C + C + C + C ) v1 tune1 v2 20 22 v3 tune2 = ----------------------------------------------------------------------------------------------------------------------------------------- + C vm 21 C v1 + C tune1 + C v2 + C 20 + C + C 22 + C v3 tune2 Data Sheet 56 [3 - 26] 2007-02-26 TDA5250 D2 Version 1.7 Application Note: Please keep in mind also to include the Pad parasitics of the circuit board. [3 - 25] 3.2.4 Calculation of the external capacitors 1. Determination of necessary crystal frequency using formula [4-19]. e.g. fFSK- = fCOSC LOW 2. Determine corresponding CLoad applying formula [4-18]. e.g. CL FSK- = CL 3. Necessary CV using formula [4-17]. e.g. CV - = 1 1 C L , FSK - + (2f FSK - ) * LOSC 2 1. When the necessary Cv for the 3 frequencies (Cv- for FSK LOW, Cv+ for FSK HIGH and Cvm for FSK-receive) are known the external capacitors and the internal tuning caps can be calculated using the following formulas: -FSK: C v1 + C tune1 = C v- - C 21 [3 - 27] +FSK: ( C v1 + C tune1 ) ( C v+ - C 21 ) C v2 + C tune2 = ---------------------------------------------------------------------- - C 20 ( C v1 + C tune1 ) - ( C v+ - C 21 ) [3 - 28] FSK_RX: ( C v1 + C tune1 ) ( C vm - C 21 ) C v3 + C tune2 = ------------------------------------------------------------------------- - C 20 - C v2 - C 22 ( C v1 + C tune1 ) - ( C vm - C 21 ) [3 - 29] To compensate frequency errors due to crystal and component tolerance Cv1, Cv2 and Cv3 have to be varied. To enable this correction, half of the necessary capacitance variation has to be realized with the internal C-banks. If no finetuning is intended it is recommended to leave XIN (Pin 21) open. So the parasitic capacitance of Pin 21 has no effect. Note: Please keep in mind also to include the Pad parasitics of the circuit board. In the suitable range for the serial capacitor, either capacitors with a tolerance of 0.1pF or 1% are available. A spreadsheet, which can be used to predict the total frequency error by simply entering the crystal specification, may be obtained from Infineon. 3.2.5 FSK-switch modes The FSK-switch can be used either in a bipolar or in a FET mode. The mode of this switch is controlled by bit D0 of the XTAL_CONFIG register (subaddress 0EH). Data Sheet 57 2007-02-26 TDA5250 D2 Version 1.7 Application In the bipolar mode the FSK-switch can be controlled by a ramp function. This ramp function is set by the bits D1 and D2 of the XTAL_CONFIG register (subadress 0EH). With these modes of the FSK-switch the bandwidth of the FSK spectrum can be influenced. When working in the FET mode the power consumption can be reduced by about 200 A. The default mode is bipolar switch with no ramp function (D0 = 1, D1 = D2 = 0), which is suitable for all bitrates. Table 3-3 Sub Address 0EH: XTAL_CONFIG D1 D2 Switch mode D0 0 n.a. n.a. FET 1 0 0 bipolar (default) 1 1 0 bipolar 1 0 1 bipolar 1 1 1 bipolar 3.2.6 Ramp time < 0.2 s < 0.2 s 4 s 8 s 12 s Max. Bitrate > 32 kBit/s NRZ > 32 kBit/s NRZ 32 kBit/s NRZ 16 kBit/s NRZ 12 kBit/s NRZ Finetuning and FSK modulation relevant registers Case FSK-RX or ASK-TX (Ctune2): Table 3-4 Bit D5 D4 D3 D2 D1 D0 Sub Address 02H: XTAL_TUNING Function Value Nominal_Frequ_5 8pF Nominal_Frequ_4 4pF Nominal_Frequ_3 2pF Nominal_Frequ_2 1pF Nominal_Frequ_1 500fF Nominal_Frequ_0 250fF Description Setting for nominal frequency ASK-TX FSK-RX (Ctune2) Default 0 1 0 0 1 0 Case FSK-TX or ASK-RX (Ctune1 and Ctune2): Table 3-5 Bit D13 D12 D11 D10 D9 D8 Data Sheet Sub Address 01H: FSK Function FSK+5 FSK+4 FSK+3 FSK+2 FSK+1 FSK+0 Value 8pF 4pF 2pF 1pF 500fF 250fF 58 Description Setting for positive frequency shift: +FSK or ASK-RX (Ctune2) Default 0 0 1 0 1 0 2007-02-26 TDA5250 D2 Version 1.7 Application D5 D4 D3 D2 D1 D0 FSK-5 FSK-4 FSK-3 FSK-2 FSK-1 FSK-0 4pF 2pF 1pF 500fF 250fF 125fF Setting for negative frequency shift: -FSK 0 0 1 1 0 0 (Ctune1) Default values In case of using the evaluation board, the crystal with its typical parameters (fp=18.08958MHz, C1=8fF, C0=2,08pF, CL=12pF) and external capacitors with Cv1=4.7pF, Cv2=1.8pF, Cv3=12pF each are used the following default states are set in the device. Table 3-6 Default oscillator settings Operating state Frequency ASK-TX / FSK-RX 868.3 MHz +50 kHz +FSK-TX / ASK-RX -FSK-TX -50 kHz 3.2.7 Chip and System Tolerances Quartz: fp=18.08958MHz; C1=8fF; C0=2,08pF; CL=12pF (typical values) Cv1=4.7pF, Cv2=1.8pF, Cv3=12pF Table 3-7 Internal Tuning Part Frequency set accuracy Temperature (-40...+85C) Supply Voltage(2.1...5.5V) Total Frequency tolerance @ 868MHz +/- 3kHz +/- 5kHz +/- 1.5kHz +/- 9.5kHz Rel. tolerance +/- 3.5ppm +/- 6ppm +/- 1.5ppm +/- 11ppm Table 3-8 Default Setup (without internal tuning & without Pin21 usage) Part Frequency tolerance Rel. tolerance @ 868MHz +/- 8kHz +/- 9ppm Internal capacitors (+/- 10%) +/- 18kHz +/- 21ppm Inductivity of the crystal oscillator Temperature (-40...+85C) +/- 5kHz +/- 6ppm Supply Voltage (2.1...5.5V) +/- 1kHz +/- 1.5ppm Total +/- 32kHz +/- 37.5ppm Tolerance values in Table 3-8 are valid, if pin 21 is not connected. Establishing the connection to pin 21 the tolerances increase by +/- 20ppm (internal capacitors), if internal tuning is not used. Data Sheet 59 2007-02-26 TDA5250 D2 Version 1.7 Application Concerning the frequency tolerances of the whole system also crystal tolerances (tuning tolerances, temperature stability, tolerance of CL) have to be considered. In addition to the chip tolerances also the crystal and external component tolerances have to be considered in the tuning and non-tuning case. In case of internal tuning: The crystal on the evaluation board has a temperature stability of +/20ppm (or +/- 17kHz), which must be added to the total tolerances. In case of default setup (without internal tuning and without usage of pin 21) the temperature stability and tuning tolerance of the crystal as well as the tolerance of the external capacitors (+/0.1pF) have to be added. The crystal on the evaluation board has a temperature stability of +/20ppm (or +/- 17kHz) and a tuning tolerance of +/- 10ppm (or +/- 8.5 kHz).The external capacitors add a tolerance of +/- 4ppm (or +/- 3.5kHz). The frequency stabilities of both the receiver and the transmitter and the modulation bandwidth set the limit for the bandwidth of the IQ filter. To achieve a high receiver sensitivity and efficient suppression of adjacent interference signals, the narrowest possible IQ bandwidth should be realized (see Section 3.3). 3.3 IQ-Filter The IQ-Filter should be set to values corresponding to the RF-bandwidth of the received RF signal via the D1 to D3 bits of the LPF register (subaddress 03H). Table 3-9 D3 0 0 0 0 1 1 1 1 Data Sheet 3dB cutoff frequencies I/Q Filter D2 D1 nominal f-3dB in kHz (programmable) 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 not used 350 250 200 150 (default) 100 50 not used 60 resulting effective channel bandwidth in kHz 700 500 400 300 200 100 2007-02-26 TDA5250 D2 Version 1.7 Application 10 50kHz 100kHz 0 150kHz - 10 200kHz 250kHz -20 350kHz -30 -40 -50 -60 -70 -80 10 10 0 10 0 0 10 0 0 0 f [ kHz] iq_filter_curve.wmf Figure 3-20 I/Q Filter Characteristics effective channel bandwidth -f f f 3dB IQ Filter 3dB IQ Filter f iq_char.wmf Figure 3-21 3.4 IQ Filter and frequency characteristics of the receive system Data Filter The Data-Filter should be set to values corresponding to the bandwidth of the transmitted Data signal via the D4 to D7 bits of the LPF register (subaddress 03H). Data Sheet 61 2007-02-26 TDA5250 D2 Version 1.7 Application Table 3-10 D7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 3dB cutoff frequencies Data Filter D6 D5 D4 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 3.5 nominal f-3dB in kHz 5 7 (default) 9 11 14 18 23 28 32 39 49 55 64 73 86 102 Limiter and RSSI The I/Q Limiters are DC coupled multistage amplifiers with offset-compensating feedback circuit and an overall gain of approximately 80dB each in the frequency range of 100Hz up to 350kHz. Receive Signal Strength Indicator (RSSI) generators are included in both limiters which produce DC voltages that are directly proportional to the input signal level in the respective channels. The resulting I- and Q-channel RSSI-signals are summed to the nominal RSSI signal. I- Filter fg Q- Filter fg 33 I Limiter C RSSI 32 CQ2x 34 CQ2 35 Cc CI2x 36 CQ1x 37 CQ1 CI1x 38 CI2 Cc Cc CI1 Cc 29 RSSI 31 Quadr. Corr. 37k Quadr. Corr. Q Limiter limiter input.wmf Figure 3-22 Data Sheet Limiter and Pinning 62 2007-02-26 TDA5250 D2 Version 1.7 Application The DC offset compensation needs 2.2ms after Power On or Tx/Rx switch. This time is hard wired and independent from external capacitors CC on pins 31 to 38. The maximum value for this capacitors is 47nF. RSSI accuracy settling time = 2.2ms + 5*RC=2.2ms+5*37k*2.2nF=2.6ms R - internal resistor; C - external capacitor at Pin 29 Table 3-11 Cc [nF] 220 100 47 22 10 Limiter Bandwidth f3dB lower limit [Hz] 100 220 470 1000 2200 f3dB upper limit IQ Filter - ll - ll - ll - ll - Comment setup time not guaranteed setup time not guaranteed Eval Board v [dB] 80 0 f3dB lower limit f3dB f3dB IQ Filter Limiter f limiter_char.wmf Figure 3-23 Data Sheet Limiter frequency characteristics 63 2007-02-26 TDA5250 D2 Version 1.7 Application ADC 1300 1200 1100 1000 900 RSSI /mV 800 700 600 500 high gain 400 low gain 300 200 100 0 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 RF /dBm RSSI.wmf Figure 3-24 3.6 Typ. RSSI Level (Eval Board) @3V Data Slicer - Slicing Level The data slicer is an analog-to-digital converter. It is necessary to generate a threshold value for the negative comparator input (data slicer). The TDA5250 offers an RC integrator and a peak detector which can be selected via logic. Independent of the choice, the peak detector outputs are always active. 3.6.1 Table 3-12 Bit D15 RC Integrator Sub Address 00H: CONFIG Function Description SLICER 0= LP, 1= Peak Detector Default 0 SET 0 Necessary external component (Pin14): CSLC This integrator generates the mean value of the data filter output. For a stable threshold value, the cut-off frequency has to be lower than the lowest signal frequency. The cutoff frequency results from the internal resistance R=100k and the external capacitor CSLC on Pin14. Cut-off frequency: f cut - off = 1 < Min {f 2 100 k C SLC Signal } [3 - 30] Component calculation: (rule of thumb) TL - longest period of no signal change C Data Sheet SLC 3 TL 100 k [3 - 31] 64 2007-02-26 TDA5250 D2 Version 1.7 Application SLC_RC.wmf Figure 3-25 3.6.2 Table 3-13 Bit D15 Slicer Level using RC Integrator Peak Detectors Sub Address 00H: CONFIG Function Description SLICER 0= LP, 1= Peak Detector Default 0 SET 1 The TDA5250 has two peak detectors built in, one for positive peaks in the data stream and the other for the negative ones. Necessary external components: - Pin12: CN - Pin13: CP Data Sheet 65 2007-02-26 TDA5250 D2 Version 1.7 Application SLC_PkD.wmf Figure 3-26 Slicer Level using Peak Detector For applications requiring fast attack and slow release from the threshold value it is reasonable to use the peak detectors. The threshold value is generated by an internal voltage divider. The release time is defined by the internal resistance values and the external capacitors. posPkD = 100 k C p negPkD = 100 k C Signal [3 - 32] [3 - 33] n posPkD Signal Pos. Peak Detector (pin13) Threshold SLC(pin14) Neg. Peak Detector (pin12) negPkD t PkD_timing.wmf Figure 3-27 Data Sheet Peak Detector timing 66 2007-02-26 TDA5250 D2 Version 1.7 Application Component calculation: (rule of thumb) Cp 2 TL1 [3 - 34] 100k TL1 - longest period of no signal change (LOW signal) Cn 2 TL2 100k 3.6.3 TL2 - longest period of no signal change (HIGH signal) [3 - 35] Peak Detector - Analog output signal The TDA5250 data output can be digital (pin 28) or in analog form by using the peak detector output and changing some settings. To get an analog data output the slicer must be set to lowpass mode (Reg. 0, D15 = LP = 0) and the peak detector capacitor at pin 12 or 13 has to be changed to a resistor of about 47kOhm. PkD_analog.wmf Figure 3-28 3.6.4 Peak Detector as analog Buffer (v=1) Peak Detector - Power Down Mode For a safe and fast threshold value generation the peak detector is turned on by the sequencer circuit (see Section 2.4.18) only after the entire receiving path is active. In the off state the output of the positive peak detector is tied down to GND and the output of the negative peak detector is pulled up to VCC. Data Sheet 67 2007-02-26 TDA5250 D2 Version 1.7 Application PKD_PWDN.wmff Figure 3-29 Peak detector - power down mode Signal Data Signal Vcc Neg. Peak Detector (pin12) Threshold (pin14) 2,2ms Pos. Peak Detector (pin13) 0 Power ON Power Down Power ON Peak Detector Power ON t PkD_PWDN3.wmf Figure 3-30 3.7 Power down mode Data Valid Detection In order to detect valid data two criteria must be fulfilled. One criteria is the data rate, which can be set in register 06h and 07h. The other one is the received RF power level, which can be set in register 08h in form of the RSSI threshold voltage. Thus for using the data valid detection FSK modulation is recommended. Data Sheet 68 2007-02-26 TDA5250 D2 Version 1.7 Application Timing for data detection looks like the following. Two settings are possible: Continuous" and Single Shot", which can be set by D5 and D6 in register 00H. Data t Sequenzer enables data detection t Counter Reset reset reset t Gate time count count t Compare with single TH and latch result comp. comp. t Compare with double TH and latch result comp. t (Frequency) Window Count Complete ready* start of conversion t possible start of next conversion Frequ_Detect_Timing_continuous.wmf Figure 3-31 Frequency Detection timing in continuous mode Note 1: Chip internal signal Sequencer enables data detection" has a LOW to HIGH transition about 2.6ms after RX is activated (see Figure 2-15). Note 2: The positive edge of the Window Count Complete" signal latches the result of comparison of the analog to digital converted RSSI voltage with TH3 (register 08H). A logic combination of this output and the result of the comparison with single/double THx defines the internal signal data_valid". Figure 3-31 shows that the logic is ready for the next conversion after 3 periods of the data signal. Timing in Single Shot mode can be seen in the subsequent figure: Data t Sequenzer enables data detection t Counter Reset reset t Gate time Compare with single TH and latch result count t comp. t Compare with double TH and latch result comp. t (Frequency) Window Count Complete start of conversion ready* no possible start of next conversion because of Single Shot Mode t Frequ_Detect_Timing_singleShot_wmf Figure 3-32 Data Sheet Frequency Detection timing in Single Shot mode 69 2007-02-26 TDA5250 D2 Version 1.7 Application 3.7.1 Frequency Window for Data Rate Detection The high time of data is used to measure the frequency of the data signal. For Manchester coding either the data frequency or half of the data frequency have to be detected corresponding to one high time or twice the high time of data signal. A time period of 3*2*T is necessary to decide about valid or invalid data. T 2*T DATA t 0 0 1 0 T2 T1 possible GATE 1 t 0 2*T2 2*T1 possible GATE 2 t 0 1 window_count_timing.wmf Figure 3-33 Window Counter timing Example to calculate the thresholds for a given data rate: - Data signal manchester coded - Data Rate: 2kbit//s - fclk= 18,0896 MHz Then the period equals to 2T = 1 = 0,5ms 2kbit/s [3 - 36] respectively the high time is 0,25ms. We set the thresholds to +-10% and get: T1= 0,225ms and T2= 0,275ms The thresholds TH1 and TH2 are calculated with following formulas Data Sheet TH1 = T1 f clk 4 TH2 = T2 f clk 4 70 [3 - 37] [3 - 38] 2007-02-26 TDA5250 D2 Version 1.7 Application This yields the following results: TH1~ 1017= 001111111001b TH2~ 1243= 010011011011b which have to be programmed into the D0 to D11 bits of the COUNT_TH1 and COUNT_TH2 registers (subaddresses 06H and 07H), respectively. Default values (window counter inactive): TH1= 000000000000b TH2= 000000000001b Note: The timing window of +-10% of a given high time T in general does not correspond to a frequency window +-10% of the calculated data frequency. 3.7.2 RSSI threshold voltage - RF input power The RF input power level is corresponding to a certain RSSI voltage, which can be seen in Section 3.5. The threshold TH3 of this RSSI voltage can be calculated with the following formula: TH3 = desired RSSI threshold 1.2V voltage (2 6 [3 - 39] - 1) As an example a desired RSSI threshold voltage of 500mV results in TH3~26=011010b, which has to be written into D0 to D5 of the RSSI_TH3 register (sub address 08H). Default value (RSSI detection inactive): TH3=111111b 3.8 Calculation of ON_TIME and OFF_TIME ON= (216-1)-(fRC*tON) OFF=( 216-1)-(f [3 - 40] RC*tOFF) [3 - 41] fRC= Frequency of internal RC Oszillator Example: tON= 0,005s, tOFF= 0,055s, fRC= 32300Hz ON= 65535-(32300*0,005) ~ 65373= 1111111101011101b OFF= 65535-(32300*0,055) ~ 63758= 1111100100001110b The values have to be written into the D0 to D15 bits of the ON_TIME and OFF_TIME registers (subaddresses 04H and 05H). Data Sheet 71 2007-02-26 TDA5250 D2 Version 1.7 Application Default values: ON= 65215 = 1111111011000000b OFF= 62335 = 1111001110000000b tON ~10ms @ fRC= 32kHz tOFF ~100ms @ fRC= 32kHz 3.9 Example for Self Polling Mode The settings for Self Polling Mode depend very much on the timing of the transmitted Signal. To create an example we consider following data structure transmitted in FSK. 4 Frames Data 50ms Data Data Data t [ms] 50ms 400ms Framedetails t [ms] Preamble Data Sync t [ms] Syncronisation Preamble data_timing011.wmf Figure 3-34 Example for transmitted Data-structure According to existing synchronization techniques there are some synchronization bursts in front of the data added (code violation!). A minimum of 4 Frames is transmitted. Data are preferably Manchester encoded to get fastest respond out of the Data Rate Detection. Target Application: - received Signal has code violation as described before - total mean current consumption below 1mA - data reception within max. 400ms after first transmitted frame One possible Solution: tON = 15ms, tOFF= 135ms Data Sheet 72 2007-02-26 TDA5250 D2 Version 1.7 Application This gives 15ms ON time of a total period of 150ms which results in max. 0.9mA mean current consumption in Self Polling Mode. The resulting worst case timing is shown in the following figure: Case A: Data Data 50ms 15ms Data 135ms Data t [ms] P enables Receiver until Data completed Interrupt due PwdDD Case B: Data 50ms Data 15ms Data 135ms Data t [ms] P enables Receiver until Data completed Interrupt due PwdDD Case C: Data 50ms Data 15ms Data 135ms Data t [ms] P enables Receiver until Data completed Interrupt due PwdDD ... Receiver enabled data_timing021.wmf Figure 3-35 3 possible timings Description: Assumption: the ON time comes right after the first frame (Case A). If OFF time is 135ms the receiver turns on during Sync-pulses and the PwdDD- pulse wakes up the P. If the ON time is in the center of the 50ms gap of transmission (Case B), the Data Detect Logic will wake up the P 135ms later. If ON time is over just before Sync-pulses (Case C), next ON time is during Data transmission and Data Detect Logic will trigger a PwdDD- pulse to wake up the P. Note: In this example it is recommended to use the Peak Detector for slicer threshold generation, because of its fast attack and slow release characteristic. To overcome the data zero gap of 50ms larger external capacitors than noted in Section 4.4 at pin12 and 13 are recommended. Further information on calculating these components can be taken from Section 3.6.2. 3.10 Sensitivity Measurements 3.10.1 Test Setup The test setup used for the measurements is shown in the following figure. In case of ASK modulation the Rohde & Schwarz SMIQ generator, which is a vector signal generator, is connected to the I/Q modulation source AMIQ. This "baseband signal generator" is in turn controlled by the PC Data Sheet 73 2007-02-26 TDA5250 D2 Version 1.7 Application based software WinQSIM via a GPIB interface. The AMIQ generator has a pseudo random binary sequence (PRBS) generator and a bit error test set built in. The resulting I/Q signals are applied to the SMIQ to generate a ASK (OOK) spectrum at the desired RF frequency. Data is demodulated by the TDA5250 and then sent back to the AMIQ to be compared with the originally sent data. The bit error rate is calculated by the bit error rate equipment inside the AMIQ. Baseband coding in the form of Manchester is applied to the I signal as can be seen in the subsequent figure. Personal Computer Software WinIQSIM GPIB / RS 232 Clock AMIQ BERT (Bit Error Rate Test Set) Marker Output Data Rohde & Schwarz I/Q Modulation Source AMIQ I Q Manchester Encoder Manchester Decoder DATAout Rohde & Schwarz Vector Signal Generator SMIQ 03 RFin DUT Transceiver Testboard TDA5250 ASK / FSK RF Signal TestSetup.wmf Figure 3-36 BER Test Setup In the following figures the RF power level shown is the average power level. These investigations have been made on an Infineon evaluation board using a data rate of 4 kBit/ s with manchester encoding and a data filter bandwidth of 7 kHz. This is the standard configuration of our evaluation boards. All these measurements have been performed with several evaluation boards, so that production scattering and component tolerances are already included in these results. Regarding the data filter bandwidth it has to be mentioned that a data rate of 4 kBit/s using manchester encoding results in a data frequency of 2 kHz to 4 kHz depending on the occurring data pattern. The test pattern given by the AMIQ is a pseudo random binary sequency (PRBS9) with a 9 bit shift register. This pattern varies the resulting data frequency up to 4 kHz. Data Sheet 74 2007-02-26 TDA5250 D2 Version 1.7 Application The best sensitivity performance can be achieved using a data filter bandwidth of 1.25 times the maximum occuring data frequency. The IQ filter setting is depending on the modulation type. ASK needs an IQ filter of 50kHz, 50kHz deviation at FSK recommend a 100kHz IQ filter and 100kHz deviation were measured with a 150kHz IQ filter A very practicable configuration is to set the chip-internal adjustable IQ filter to the sum of FSK peak deviation and maximum datafrequency. Concerning these aspects the bandwidth should be chosen small enough. With respect to both, the crystal tolerances and the tolerances of the crystal oscillator circuit of receiver and transmitter as well, a too small IQ filter bandwidth will reduce the sensitivity again. So a compromise has to be made. For further details on chip tolerances see also Section 3.2.7 3.10.2 Sensitivity depending on the ambient Temperature Demonstrating a wide band of application possibilities the temperature behavior must not be forgotten. In automotive systems the required temperature range is from -40 C to +85 C. The receivers very good performance is documented in the following graph. The selected supply voltage is 5V, the influence of the supply voltage can be seen in the following Section 3.10.3 The IQ filter setting can be taken from the legend of Figure 3-37. BER_Temp_5V.wmf Figure 3-37 Temperature Behaviour Figure 3-37 shows that ASK as well as FSK sensitivity is in the range of -110 to -111dBm at 20C ambient temperature for a BER of 2E-3. Notice that the sensitivity variation in this temperature range of -40 C to +85 C is only about 1.5 to 2 dB. Data Sheet 75 2007-02-26 TDA5250 D2 Version 1.7 Application 3.10.3 BER performance depending on Supply Voltage Due to the wide supply voltage range of this transeiver chip also the sensitivity behaviour over this parameter is documented is the subsequent graph. BER_VCC_20C..wmf Figure 3-38 BER supply voltage Please notice the tiny sensitivity changes of 1.5 to 2.5dB, when variing the supply voltage. 3.10.4 Datarates and Sensitivity The TDA 5250 can handle datarates up to 64kbit/s, as can be taken from the following figure. (see Section 4.1.4) Data Sheet 76 2007-02-26 TDA5250 D2 Version 1.7 Application BER_Datarate.wmf Figure 3-39 3.10.5 Datarates and Sensitivity Sensitivity at Frequency Offset Applying the test setup in Figure 3-36 even a wide offset in the received frequency spectrum results only in a slight decrease of receiving sensitivity. At an offset of 100kHz one of the two 50kHz FSK peaks is at the 3dB border of the IQ filter (150kHz), which is the reason for the decline of the sensitivity (see point A in Figure 3-40). A frequency offset of 50kHz (FSK deviation: 50kHz) increases the data jitter of the demodulated signal and therefore results in little loss of sensitivity (see point B in Figure 3-40). In this case one of the peaks of the FSK-spectrum lies in the DC-blocking notch of the baseband limiters. BER_FrequOffset_FSK_3V..wmf Figure 3-40 Data Sheet BER Frequency Offset 77 2007-02-26 TDA5250 D2 Version 1.7 Application 3.11 Default Setup Default setup is hard wired on chip and effective after a reset or return of power supply. Table 3-14 Default Setup Parameter Value IFX-Board IQ-Filter Bandwidth Data Filter Bandwidth Limiter lower fg Slicing Level Generation Nom. Frequency Capacity intern (ASK TX, FSK RX) FSK+ Frequency Capacity intern (FSK+, ASK RX) FSK- Frequency Capacity intern (FSK-) 150kHz 7kHz 470Hz RC 4.5pF 2.5pF 1.5pF 47nF 10nF 868.3MHz +50kHz -50kHz LNA Gain Power Amplifier HIGH HIGH +10dBm RSSI accuracy settling time ADC measurement ON-Time OFF-Time Clock out RX PowerON Clock out TX PowerON Clock out RX PowerDOWN Clock out TX PowerDOWN 2.6ms RSSI 10ms 100ms 1MHz 1MHz - XTAL modulation switch XTAL modulation shaping bipolar off RX / TX ASK/FSK PwdDD PWDN Operating Mode Slave Data Sheet 78 Comment 2.2nF Jumper Jumper Jumper removed 2007-02-26 TDA5250 D2 Version 1.7 Reference 4 Reference 4.1 Electrical Data 4.1.1 Absolute Maximum Ratings WARNING The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result. Table 4-1 # Absolute Maximum Ratings Parameter Symbol VESD-CDM Limit Values min max -0.3 5.8 -40 +125 -40 +150 114 -1.5 +1.5 ESD integrity, except pin 8, 9, 11, 15, 18, 23, 30 VESD-HBM -2.0 +2.0 kV ESD integrity, of pin 8, 9, 11, 15, 18, 23, 30 VESD-HBM -500 +500 V 1 2 3 4 5 Supply Voltage Junction Temperature Storage Temperature Thermal Resistance ESD integrity, all pins 6 7 4.1.2 Vs Tj Ts RthJA Unit V C C K/W kV Remarks CDM according EIA/JESD22-C101 HBM according EIA/JESD22-A114-B (1.5k, 100pF) HBM according EIA/JESD22-A114-B (1.5k, 100pF) Operating Range Within the operational range the IC operates as explained in the circuit description. Table 4-2 Operating Range Parameter Symbol # 1 Supply voltage VS Limit Values min max 2.1 5.5 2 3 4 Ambient temperature Receive frequency Transmit frequency TA fRX fTX -40 868 868 Data Sheet 79 85 870 870 Unit Test Conditions L C MHz MHz Item V 2007-02-26 TDA5250 D2 Version 1.7 Reference 4.1.3 AC/DC Characteristics AC/DC characteristics involve the spread of values guaranteed within the specified voltage and ambient temperature range. Typical characteristics are the median of the production. Table 4-3 AC/DC Characteristics with TA = 25 C, VVCC = 2.1 ... 5.5 V # Parameter Symbol Limit Values Unit Test Conditions min typ max L Item RECEIVER Characteristics 1 Supply current RX FSK 2 Supply current RX FSK IRX_FSK IRX_FSK 9 9.5 mA mA 3V, FSK, Default 5V, FSK, Default 3 Supply current RX ASK IRX_ASK 4 Supply current RX ASK IRX_ASK 8.6 9.1 mA mA 3V, ASK, Default 5V, ASK, Default 5 Sensitivity FSK 10-3 BER RFsens -109 6 Sensitivity ASK 10-3 BER RFsens -109 7 Power down current IPWDN_RX 8 System setup time (1st tSYSSU power on or reset) 9 Clock Out setup time tCLKSU 4 5 8 12 nA ms 5.5V, all power down 10 Receiver setup time tRXSU 1.54 2.2 11 tDDSU 1.82 2.6 12 Data detection setup time RSSI stable time ms stable CLKDIV output signal 2.86 ms DATA out (valid or invalid) 3.38 ms Begin of Data detection tRSSI 1.82 2.6 3.38 ms 13 Data Valid time tData_Valid 3.35 ms 14 15 16 Input P1dB, high gain Input P1dB, low gain P1dB P1dB_low VBL_1MHz -48dBm -32dBm 50 17 LO leakage PLO -98 Selectivity Data Sheet 0.5 dBm FSK@50kHz, 4kBit/s Manch. Data, Default 7kHz datafilter, 100kHz IQ filter dBm ASK, 4kBit/s Manch. data, Default setup 7kHz datafilter, 50kHz IQ filter 80 RFin -100dBm see chapter 4.5 4kBit/s Manch. detected (valid) dBm 3V, Default, high gain dBm 3V, Default, low gain dB fRF+/-1MHz, Default, RFsens+3dB dBm 1157.73MHz 2007-02-26 TDA5250 D2 Version 1.7 Reference Table 4-3 AC/DC Characteristics with TA = 25 C, VVCC = 2.1 ... 5.5 V # Parameter Symbol Limit Values Unit Test Conditions min typ max L Item TRANSMITTER Characteristics 1 Supply current TX, FSK 2 Supply current TX, FSK 3 Supply current TX, FSK ITX ITX ITX 9.4 11.9 14.6 mA mA mA 2.1V, high power 3V, high power 5V, high power 4 5 6 Pout Pout Pout 6 9 13 dBm dBm dBm 2.1V, high power 3V, high power 5V, high power ITX ITX ITX 4.1 4.9 6.8 mA mA mA 2.1V, low power 3V, low power 5V, low power Output power Output power Output power 7 Supply current TX, FSK 8 Supply current TX, FSK 9 Supply current TX, FSK 1 1 1 1 1 1 10 11 12 Output power Output power Output power Pout_low Pout_low Pout_low -30 -22 -3 dBm dBm dBm 2.1V, low power 3V, low power 5V, low power 13 Power down current IPWDN_TX 5 nA 5.5V, all power down 14 Clock Out setup time tCLKSU 0.5 15 Transmitter setup time tTXSU 16 Pclock Spurious fRF+/-fclock 17 Spurious fRF+/-fXTAL 18 Spurious 2nd harmonic 19 Spurious 3rd harmonic P1st P2nd P3rd 0.77 1.1 ms stable CLKDIV output signal 1.43 ms PWDN-->PON or RX-->TX dBm -66 -40 -50 dBm dBm dBm 3V, 50Ohm Board, Default (1MHz) 3V, 50Ohm Board 3V, 50Ohm Board 3V, 50Ohm Board 1: without pin diode current (RX/TX-switch) 130uA@2.1V; 310uA@3V; 720uA@5V Data Sheet 81 2007-02-26 TDA5250 D2 Version 1.7 Reference Table 4-4 AC/DC Characteristics with TA = 25 C, VVCC = 2.1 ... 5.5 V # Parameter Symbol Limit Values Unit Test Conditions min typ max L Item GENERAL Characteristics Power down current IPWDN_32k timer mode (standby) 2 Power down current IPWDN_32k timer mode (standby) 3 Power down current with IPWDN_Xtl XTAL ON 4 Power down current with IPWDN_Xtl XTAL ON 1 uA 3V, 32kHz clock on 11 uA 5V, 32kHz clock on 750 uA 3V, CONFIG9=1 860 uA 5V, CONFIG9=1 5 32kHz oscillator freq. f32kHz 6 XTAL startup time tXTAL 0.5 Load capacitance Serial resistance of the crystal 9 Input inductance XOUT CC0max RRmax 5 LOSC 2.7 10 Input inductance XOUT LOSC 2.45 11 FSK demodulator gain GFSK 2.4 0.35 0.55 1 1.2 14 7 8 12 13 14 15 16 RSSI@-120dBm RSSI@-100dBm RSSI@-70dBm RSSI@-50dBm RSSI Gradient U-120dBm U-100dBm U-70dBm U-50dBm GRSSI 17 18 IQ-Filter bandwidth Data Filter bandwidth f3dB_IQ f3dB_LP 19 20 Vcc-Vtune RX, Pin3 Vcc-Vtune TX, Pin3 Data Sheet 24 9 32 40 kHz ms 100 pF W IFX Board with Crystal Q1 as specified in Section 4.4 uH with pad on evaluation board uH without pad on evalution board mV/ kHz V V V V mV/ dB default setup default setup default setup default setup default setup 115 150 185 kHz 5.3 7 8.7 kHz Default setup Default setup Vcc-tune,RX 0.5 Vcc-tune,TX 0.5 1 1.1 82 1.6 1.6 V V fRef=18.08956MHz fRef=18.08956MHz 2007-02-26 TDA5250 D2 Version 1.7 Reference 4.1.4 Digital Characteristics I2C Bus Timing BusMode = LOW t BUF BusData tH D.ST A tR tF tL OW tH D.ST A BusCLK t HD. DAT t H IG H tSU .DAT t SU. STA t SP t SU.S TO t HIG H EN pulsed or mandatory low t SU. ENAS DA tSU. ENA SDA t SU. ENAS DA Figure 4-1 I2C Bus Timing 3-wire Bus Timing BUS_MODE = HIGH SDA tSP tLOW t R SCL tSU.STA tF tHD.DA T tHIGH tSU.DAT tSU.STO BUS_ENA tWHEN Figure 4-2 Data Sheet 3-wire Bus Timing 83 2007-02-26 TDA5250 D2 Version 1.7 Reference Table 4-5 # 1 2 3 4 5 Digital Characteristics with TA = 25 C, VVdd = 2.1 ... 5.5 V Parameter Symbol Limit Values Unit Test Conditions min typ max Data rate TX ASK fTX.ASK 10 25 kBaud PRBS9, Manch.@+10dBm Data rate TX ASK fTX.ASK 10 64 kBaud PRBS9, Manch.@-5dBm Data rate TX FSK fTX.FSK 10 40 kBaud PRBS9, Manch.@+10dBm @50kHz dev. Data rate RX ASK fRX.ASK 10 64 kBaud PRBS9, Manch. Data rate RX FSK fRX.FSK 10 64 kBaud PRBS9, Manch.@100kHz dev. 6 Digital Inputs High-level Input Voltage Low-level Input Voltage 7 RXTX Pin 5 TX operation, int. controlled 8 VIH VIL Vdd -0.35 0 Vdd 0.35 VOL CLKDIV Pin 26 trise (0.1*Vdd to 0.9*Vdd) tfall (0.9*Vdd to 0.1*Vdd) tr tf Output High Voltage Output Low Voltage VOH VOL 0.4 1.15 V V V V 1 1 1 ns ns @Vdd=3V Isink=800uA Isink=3mA @Vdd=3V load 10pF load 10pF V V Isource=350uA Isink=400uA 50 ns Vdd=5V 0.4 V 35 30 Vdd -0.4 0.4 L Item Bus Interface Characteristics 9 Pulse width of spikes which tSP must be suppressed by the input filter 10 LOW level output voltage at VOL BusData 11 SLC clock frequency fSLC 12 Bus free time between tBUF STOP and START condition 13 Hold time (repeated) tHO.STA START condition. Table 4-5 Data Sheet 0 3mA sink current Vdd=5V 0 400 kHz Vdd=5V 1.3 s only I2C mode Vdd=5V 0.6 s After this period, the first clock pulse is generated, only I2C Digital Characteristics with TA = 25 C, VVdd = 2.1 ... 5.5 V 84 2007-02-26 TDA5250 D2 Version 1.7 Reference # 14 Parameter LOW period of BusCLK clock 15 HIGH period of BusCLK clock 16 Setup time for a repeated START condition 17 Data hold time 18 Data setup time 19 Rise, fall time of both BusData and BusCLK signals 20 Setup time for STOP condition 21 Capacitive load for each bus line 22 Setup time for BusCLK to EN 23 H-pulsewidth (EN) Symbol tLOW Limit Values Unit min typ max 1.3 s tHIGH 0.6 tSU.STA Test Conditions L Item Vdd=5V s Vdd=5V 0.6 s only I2C mode tHD.DAT tSU.DAT tR, tF 0 100 20+ 0.1Cb ns ns ns Vdd=5V Vdd=5V Vdd=5V tSU.STO 0.6 s only I2C mode Vdd=5V Vdd=5V only 3-wire mode Vdd=5V Vdd=5V 300 Cb tSU.SCL 400 pF 0.6 s 0.6 s EN tWHEN 2 1: limited by transmission channel bandwidth and depending on transmit power level; ETSI regulation EN 300 220 fullfilled, see Section 3.1 2: Cb= capacitance of one bus line Data Sheet 85 2007-02-26 TDA5250 D2 Version 1.7 Reference 4.2 Test Circuit The device performance parameters marked with in Section 4.1.3 were measured on an Infineon evaluation board (IFX board). TDA5250_v42.schematic.pdf Figure 4-3 Data Sheet Schematic of the Evaluation Board 86 2007-02-26 TDA5250 D2 Version 1.7 Reference 4.3 Test Board Layout Gerberfiles for this Testboard are available on request. TDA5250_v42_layout.pdf Figure 4-4 Layout of the Evaluation Board Note 1: The LNA and PA matching network was designed for minimum required space and maximum performance and thus via holes were deliberately placed into solder pads. In case of reproduction please bear in mind that this may not be suitable for all automatic soldering processes. Note 2: Please keep in mind not to layout the CLKDIV line directly in the neighborhood of the crystal and the associated components. Data Sheet 87 2007-02-26 TDA5250 D2 Version 1.7 Reference 4.4 Bill of Materials Table 4-6 Bill of Materials Reference R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 Data Sheet Value 4k7 10 --1M 4k7 4k7 4k7 6k8 180 180 270 15k 10k 180 180 1M 1M 1M 560 1k 10 0 10 180 22pF 1pF 5,6pF 2,2pF 1nF 1nF 15pF --47pF 22pF --10nF 10nF Specification 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 88 Tolerance +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-5% +/-1% +/-0,1pF +/-0,1pF +/-0,1pF +/-5% +/-5% +/-1% +/-0,1pF +/-1% +/-1% +/-5% +/-10% +/-10% 2007-02-26 TDA5250 D2 Version 1.7 Reference Table 4-6 Bill of Materials Reference Value C14 10nF C15 4.7pF C16 1.8pF 12pF C17 C18 10nF C19 2,2nF C20 47nF C21 47nF C22 47nF 47nF C23 C24 100nF C25 100nF C26 --C27 100nF C28 100nF 100nF C29 C30 --L1 68nH L2 12nH L3 8.2nH IC1 TDA5250 D2 IC2 ILQ74 IC3 SFH6186 Q1 18.08958MHz S1 1-pol. T1 BC847B D1, D2 BAR63-02W X1, X2 SMA-socket X5 SubD 25p. Data Sheet Specification 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 SIMID 0603-C (EPCOS) SIMID 0603-C (EPCOS) SIMID 0603-C (EPCOS) PTSSOP38 Tolerance +/-10% +/-0,1pF +/-0,1pF +/-1% +/-10% +/-10% +/-10% +/-10% +/-10% +/-10% +/-10% +/-10% +/-10% +/-10% +/-10% +/-10% +/-10% +/-2% +/-2% +/-0.2nH Telcona: C0=2,1pF C1=8fF, CL=12pF SOT-23 (Infineon) SCD-80 (Infineon) 89 2007-02-26 TDA5250 D2 Version 1.7 List of Tables Table 2-1 Table 2-2 Table 2-3 Table 2-4 Table 2-5 Table 2-6 Table 2-7 Table 2-8 Table 2-9 Table 2-10 Table 2-11 Table 2-12 Table 2-13 Table 2-14 Table 2-15 Table 2-16 Table 2-17 Table 2-18 Table 2-19 Table 2-20 Table 2-21 Table 2-22 Table 2-23 Table 2-24 Table 2-25 Table 2-26 Table 2-27 Table 2-28 Table 2-29 Table 2-30 Table 2-31 Table 2-32 Table 2-33 Table 2-34 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 3-8 Table 3-9 Data Sheet Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 00H: CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 00H: CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 00H: CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PwdDD Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Interface Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip address Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus Write Mode 8 Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus Write Mode 16 Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-wire Bus Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-wire Bus Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Addresses of Data Registers Write. . . . . . . . . . . . . . . . . . . . . . Sub Addresses of Data Registers Read. . . . . . . . . . . . . . . . . . . . . . Sub Address 00H: CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Addresses of Data Registers Write. . . . . . . . . . . . . . . . . . . . . . Sub Addresses of Data Registers Read. . . . . . . . . . . . . . . . . . . . . . Sub Address 00H: CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 01H: FSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 02H: XTAL_TUNING . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 03H: LPF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Addresses 04H / 05H: ON/OFF_TIME . . . . . . . . . . . . . . . . . . . Sub Address 06H: COUNT_TH1 . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 07H: COUNT_TH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 08H: RSSI_TH3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 0DH: CLK_DIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 0EH: XTAL_CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 0FH: BLOCK_PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 80H: STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 81H: ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODE settings: CONFIG register . . . . . . . . . . . . . . . . . . . . . . . . . . CLK_DIV Output Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK_DIV Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Source for 6Bit-ADC Selection (Register 08H). . . . . . . . . . . . . . . . . Crystal and crystal oscilator dependency . . . . . . . . . . . . . . . . . . . . . Typical values of parasitic capacitances . . . . . . . . . . . . . . . . . . . . . . Sub Address 0EH: XTAL_CONFIG. . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 02H: XTAL_TUNING . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 01H: FSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default oscillator settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Setup (without internal tuning & without Pin21 usage) . . . . . 3dB cutoff frequencies I/Q Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 page 12 page 19 page 19 page 22 page 23 page 24 page 25 page 26 page 26 page 26 page 27 page 27 page 28 page 28 page 28 page 29 page 29 page 29 page 30 page 30 page 30 page 30 page 30 page 30 page 31 page 31 page 31 page 31 page 31 page 31 page 32 page 37 page 37 page 37 page 51 page 56 page 58 page 58 page 58 page 59 page 59 page 59 page 60 2007-02-26 TDA5250 D2 Version 1.7 List of Tables Table 3-10 Table 3-11 Table 3-12 Table 3-13 Table 3-14 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Data Sheet 3dB cutoff frequencies Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . Limiter Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 00H: CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sub Address 00H: CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC/DC Characteristics with TA = 25 C, VVCC = 2.1 ... 5.5 V . . . . . AC/DC Characteristics with TA = 25 C, VVCC = 2.1 ... 5.5 V . . . . . Digital Characteristics with TA = 25 C, VVdd = 2.1 ... 5.5 V . . . . . . Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 page 62 page 63 page 64 page 65 page 78 page 79 page 79 page 80 page 82 page 84 page 88 2007-02-26 TDA5250 D2 Version 1.7 List of Figures Figure 1-1 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 2-7 Figure 2-8 Figure 2-9 Figure 2-10 Figure 2-11 Figure 2-12 Figure 2-13 Figure 2-14 Figure 2-15 Figure 2-16 Figure 2-17 Figure 2-18 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 3-7 Figure 3-8 Figure 3-9 Figure 3-10 Figure 3-11 Figure 3-12 Figure 3-13 Figure 3-14 Figure 3-15 Figure 3-16 Figure 3-17 Figure 3-18 Figure 3-19 Figure 3-20 Figure 3-21 Figure 3-22 Figure 3-23 Figure 3-24 Data Sheet PG-TSSOP-38 package outlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . page Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Main Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page One I/Q Filter stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Quadricorrelator Demodulation Characteristic . . . . . . . . . . . . . . . . . page Data Filter architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Timing and Data Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Sub Addresses Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Wakeup Logic States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Timing for Self Polling Mode (ADC & Data Detect in one shot mode) page Timing for Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Frequency and RSSI Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Data Valid Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Data Input/Output Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 1st start or reset in active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 1st start or reset in PD mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Sequencer`s capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page RX/TX Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page RX-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page S11 measured . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page TX_Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page TX_Mode_simplified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Equivalent power amplifier tank circuit . . . . . . . . . . . . . . . . . . . . . . . page Output power Po (mW) and collector efficiency E vs. load resistor RL. page Power output and collector current vs. frequency . . . . . . . . . . . . . . . page Sparam_measured_200M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Transmit Spectrum 13.2GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Transmit Spectrum 300MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page ASK Transmit Spectrum 25kBaud, Manch, PRBS9, 9dBm, 3V . . . . page FSK Transmit Spectrum 40kBaud, Manch, PRBS9, 9dBm, 3V . . . . page Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page possible crystal oscillator frequencies . . . . . . . . . . . . . . . . . . . . . . . . page FSK modulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page FSK receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page parasitics of the switching network . . . . . . . . . . . . . . . . . . . . . . . . . . page I/Q Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page IQ Filter and frequency characteristics of the receive system. . . . . . page Limiter and Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page Limiter frequency characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . page Typ. RSSI Level (Eval Board) @3V . . . . . . . . . . . . . . . . . . . . . . . . . page 92 10 11 18 20 21 22 23 24 27 32 32 33 33 34 34 35 35 36 36 39 40 41 43 43 44 45 46 47 48 48 49 49 50 52 53 55 55 56 61 61 62 63 64 2007-02-26 TDA5250 D2 Version 1.7 List of Figures Figure 3-25 Figure 3-26 Figure 3-27 Figure 3-28 Figure 3-29 Figure 3-30 Figure 3-31 Figure 3-32 Figure 3-33 Figure 3-34 Figure 3-35 Figure 3-36 Figure 3-37 Figure 3-38 Figure 3-39 Figure 3-40 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Data Sheet Slicer Level using RC Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slicer Level using Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak Detector timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peak Detector as analog Buffer (v=1) . . . . . . . . . . . . . . . . . . . . . . . . Peak detector - power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . Power down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Detection timing in continuous mode . . . . . . . . . . . . . . . Frequency Detection timing in Single Shot mode . . . . . . . . . . . . . . . Window Counter timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example for transmitted Data-structure. . . . . . . . . . . . . . . . . . . . . . . 3 possible timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BER Test Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Behaviour. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BER supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Datarates and Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BER Frequency Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . Layout of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 page page page page page page page page page page page page page page page page page page page page 65 66 66 67 68 68 69 69 70 72 73 74 75 76 77 77 83 83 86 87 2007-02-26 TDA5250 D2 Version 1.7 Index A O Absolute Maximum Ratings 79 AC/DC Characteristics 80 Application 10, 39 Operating Range 79 Overview 9 P E Package Outlines 10 Pin Configuration 11 Pin Definitions and Functions 12 Product Description 9 Electrical Data 79 F Features 9 Functional Block Description 19 Functional Block Diagram 18 Functional Description 11 R Reference 79 S Standards 83 Data Sheet 94 2007-02-26