Low Distortion Differential RF/IF Amplifier AD8351 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM -3 dB bandwidth of 2.2 GHz for AV = 12 dB Single resistor programmable gain: 0 dB AV 26 dB Differential interface Low noise input stage 2.7 nV/Hz at AV = 10 dB Low harmonic distortion -79 dBc second at 70 MHz -81 dBc third at 70 MHz OIP3 of 31 dBm at 70 MHz Single-supply operation: 3 V to 5.5 V Low power dissipation: 28 mA at 5 V Adjustable output common-mode voltage Fast settling and overdrive recovery Slew rate of 13,000 V/s Power-down capability AD8351 PWUP VPOS RGP1 INHI OPHI INLO OPLO COMM RGP2 0 AD8351 WITH 10dB OF DRIVING THE -10 GAIN AD6645 (R = 1k) -20 -30 -40 -50 APPLICATIONS VOCM BIAS CELL L ANALOG INPUT = 70MHz ENCORE = 80MHz SNR = 69.1dB FUND = -1.1dBFS HD2 = -78.5dBc HD3 = -80.7dBc THD = -75.9dBc SFDR = 78.2dBc 100nF 25 INHI RG 200 AD6645 14-BIT ADC AD8351 INLO 100nF 25 -60 Differential ADC drivers Single-ended-to-differential conversion IF sampling receivers RF/IF gain blocks SAW filter interfacing -70 2 -80 -90 3 + -100 03145-001 -110 -120 -130 Figure 1. GENERAL DESCRIPTION The AD8351 is a low cost differential amplifier useful in RF and IF applications up to 2.2 GHz. The voltage gain can be set from unity to 26 dB using a single external gain resistor. The AD8351 provides a nominal 150 differential output impedance. The excellent distortion performance and low noise characteristics of this device allow for a wide range of applications. The AD8351 is designed to satisfy the demanding performance requirements of communications transceiver applications. The device can be used as a general-purpose gain block, an ADC driver, and a high speed data interface driver, among other functions. The AD8351 can also be used as a single-ended-todifferential amplifier with similar distortion products as in the Rev. D differential configuration. The exceptionally good distortion performance makes the AD8351 an ideal solution for 12-bit and 14-bit IF sampling receiver designs. Fabricated in Analog Devices, Inc., high speed XFCB process, the AD8351 has high bandwidth that provides high frequency performance and low distortion. The quiescent current of the AD8351 is 28 mA typically. The AD8351 amplifier comes in a compact 10-lead MSOP package or in a 16-lead LFCSP package, and operates over the temperature range of -40C to +85C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2003-2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8351 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Gain Adjustment ........................................................................ 12 Applications ....................................................................................... 1 Common-Mode Adjustment .................................................... 12 Functional Block Diagram .............................................................. 1 Input and Output Matching ...................................................... 12 General Description ......................................................................... 1 Single-Ended-to-Differential Operation ................................. 13 Revision History ............................................................................... 2 ADC Driving............................................................................... 13 Specifications..................................................................................... 3 Analog Multiplexing .................................................................. 14 Absolute Maximum Ratings............................................................ 5 I/O Capacitive Loading ............................................................. 14 ESD Caution .................................................................................. 5 Transmission Line Effects ......................................................... 15 Pin Configurations and Function Descriptions ........................... 6 Characterization Setup .............................................................. 16 Typical Performance Characteristics ............................................. 7 Evaluation Board ............................................................................ 17 Theory of Operation ...................................................................... 12 Outline Dimensions ....................................................................... 19 Basic Concepts ............................................................................ 12 Ordering Guide............................................................................... 19 REVISION HISTORY 1/15--Rev. C to Rev. D Changes to Noise Distortion Parameter, Table 1 .......................... 3 Changes to Ordering Guide .......................................................... 19 3/14--Rev. B to Rev. C Updated Format .................................................................. Universal Added 16-Lead LFCSP Package................................... Throughout Changes to Features.......................................................................... 1 Changes to Table 3 and Added Figure 3; Renumbered Sequentially ....................................................................................... 6 Updated Outline Dimensions; Added Figure 52 ........................ 19 Moved, Changes to Ordering Guide ............................................ 19 2/04--Rev. A to Rev. B Changes to Ordering Guide ............................................................ 4 Changes to TPC 4 ............................................................................. 5 3/03--Rev. 0 to Rev. A Changes to Ordering Guide ............................................................ 4 Change to Table 3 ........................................................................... 15 3/03--Revision 0: Initial Version Rev. D | Page 2 of 19 Data Sheet AD8351 SPECIFICATIONS VS = 5 V, RL = 150 , RG = 110 (AV = 10 dB), f = 70 MHz, T = 25C, parameters specified differentially, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Bandwidth for 0.1 dB Flatness Bandwidth for 0.2 dB Flatness Gain Accuracy Gain Supply Sensitivity Gain Temperature Sensitivity Slew Rate Settling Time Overdrive Recovery Time Reverse Isolation (S12) INPUT/OUTPUT CHARACTERISTICS Input Common-Mode Voltage Adjustment Range Max Output Voltage Swing Output Common-Mode Offset Output Common-Mode Drift Output Differential Offset Voltage Output Differential Offset Drift Input Bias Current Input Resistance1 Input Capacitance1 CMRR Output Resistance1 Output Capacitance1 POWER INTERFACE Supply Voltage PWUP Threshold PWUP Input Bias Current Quiescent Current NOISE/DISTORTION 10 MHz Second/Third Harmonic Distortion2 Third-Order IMD Output Third-Order Intercept Noise Spectral Density (RTI) 1 dB Compression Point Test Conditions/Comments Min GAIN = 6 dB, VOUT 1.0 V p-p GAIN = 12 dB, VOUT 1.0 V p-p GAIN = 18 dB, VOUT 1.0 V p-p 0 dB GAIN 20 dB, VOUT 1.0 V p-p 0 dB GAIN 20 dB, VOUT 1.0 V p-p Using 1% resistor for RG, 0 dB AV 20 dB VS 5% -40C to +85C RL = 1 k, VOUT = 2 V step RL = 150 , VS = 2 V step 1 V step to 1% VIN = 4 V to 0 V step, VOUT 10 mV 1 dB compressed -40C to +85C -40C to +85C Typ RL = 1 k, VOUT = 2 V p-p RL = 150 , VOUT = 2 V p-p RL = 1 k, f1 = 9.5 MHz, f2 = 10.5 MHz, VOUT = 2 V p-p composite RL = 150 , f1 = 9.5 MHz, f2 = 10.5 MHz, VOUT = 2 V p-p composite f1 = 9.5 MHz, f2 = 10.5 MHz Rev. D | Page 3 of 19 Unit 3,000 2,200 600 200 400 1 0.08 3.9 13,000 7,500 <3 <2 -67 MHz MHz MHz MHz MHz dB dB/V mdB/C V/s V/s ns ns dB 1.2 to 3.8 4.75 40 0.24 20 0.13 15 5 0.8 43 150 0.8 V V p-p mV mV/C mV mV/C A k pF dB pF 3 PWUP at 5 V PWUP at 0 V Max 5.5 1.3 100 25 28 32 V V A A mA -95/-93 -80/-69 -90 dBc dBc dBc -70 dBc 33 2.65 13.5 dBm nV/Hz dBm AD8351 Parameter 70 MHz Second/Third Harmonic Distortion2 Third-Order IMD Output Third-Order Intercept Noise Spectral Density (RTI) 1 dB Compression Point 140 MHz Second/Third Harmonic Distortion2 Third-Order IMD Output Third-Order Intercept Noise Spectral Density (RTI) 1 dB Compression Point 240 MHz Second/Third Harmonic Distortion2 Third-Order IMD Output Third-Order Intercept Noise Spectral Density (RTI) 1 dB Compression Point 1 2 Data Sheet Test Conditions/Comments Min Typ Max Unit RL = 1 k, VOUT = 2 V p-p RL = 150 , VOUT = 2 V p-p RL = 1 k, f1 = 69.5 MHz, f2 = 70.5 MHz, VOUT = 2 V p-p composite RL = 150 , f1 = 69.5 MHz, f2 = 70.5 MHz, VOUT = 2 V p-p composite f1 = 69.5 MHz, f2 = 70.5 MHz -79/-81 -65/-66 -85 dBc dBc dBc -69 dBc 31 2.70 13.3 dBm nV/Hz dBm RL = 1 k, VOUT = 2 V p-p RL = 150 , VOUT = 2 V p-p RL = 1 k, f1 = 139.5 MHz, f2 = 140.5 MHz, VOUT = 2 V p-p composite RL = 150 , f1 = 139.5 MHz, f2 = 140.5 MHz, VOUT = 2 V p-p composite f1 = 139.5 MHz, f2 = 140.5 MHz -69/-69 -54/-53 -79 dBc dBc dBc -67 dBc 29 2.75 13 dBm nV/Hz dBm RL = 1 k, VOUT = 2 V p-p RL = 150 , VOUT = 2 V p-p RL = 1 k, f1 = 239.5 MHz, f2 = 240.5 MHz, VOUT = 2 V p-p composite RL = 150 , f1 = 239.5 MHz, f2 = 240.5 MHz, VOUT = 2 V p-p composite f1 = 239.5 MHz, f2 = 240.5 MHz -60/-66 -46/-50 -76 dBc dBc dBc -62 dBc 27 2.90 13 dBm nV/Hz dBm Values are specified differentially. See the Single-Ended-to-Differential Operation section for single-ended-to-differential performance. Rev. D | Page 4 of 19 Data Sheet AD8351 ABSOLUTE MAXIMUM RATINGS ESD CAUTION Table 2. Parameter Supply Voltage VPOS PWUP Voltage Internal Power Dissipation JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 sec) Rating 6V VPOS 320 mW 125C/W 125C -40C to +85C -65C to +150C 300C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. D | Page 5 of 19 AD8351 Data Sheet 8 OPHI 7 OPLO 6 COMM INLO 4 RGP2 5 RGP1 1 INHI 2 INLO 3 12 VPOS AD8351 11 OPHI TOP VIEW (Not to Scale) 10 OPLO 9 COMM NC 8 NC 7 NC 6 NC 5 RGP2 4 NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD IS INTERNALLY CONNECTED TO GND AND MUST BE SOLDERED TO A LOW IMPEDANCE GROUND PLANE. Figure 2. 10-Lead MSOP Pin Configuration 03145-002 VPOS TOP VIEW (Not to Scale) 13 VOCM AD8351 INHI 3 14 NC VOCM 9 15 NC 10 RGP1 2 03145-050 PWUP 1 16 PWUP PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 3. 16-Lead LFCSP Pin Configuration Table 3. Pin Function Descriptions Pin No. 10-Lead MSOP 16-Lead LFCSP 1 16 2 1 3 2 4 3 5 4 6 9 7 10 8 11 9 12 10 13 5, 6, 7, 8, 14, 15 Mnemonic PWUP RGP1 INHI INLO RGP2 COMM OPLO OPHI VPOS VOCM NC EPAD Description Apply a positive voltage (1.3 V VPWUP VPOS) to activate device. Gain Resistor Input 1. Balanced Differential Input. Biased to midsupply, typically ac-coupled. Balanced Differential Input. Biased to midsupply, typically ac-coupled. Gain Resistor Input 2. Device Common. Connect to low impedance ground. Balanced Differential Output. Biased to VOCM, typically ac-coupled. Balanced Differential Output. Biased to VOCM, typically ac-coupled. Positive Supply Voltage. 3 V to 5.5 V. Voltage applied to this pin sets the common-mode voltage at both the input and output. Typically decoupled to ground with a 0.1 F capacitor. No connect. Do not connect to this pin. Exposed Pad. The exposed pad is internally connected to GND and must be soldered to a low impedance ground plane. Rev. D | Page 6 of 19 Data Sheet AD8351 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, T = 25C, unless otherwise noted. 20 30 RG = 20 RG = 10 25 15 RG = 80 GAIN (dB) GAIN (dB) 20 10 RG = 200 5 RG = 50 15 10 RG = 200 0 10 100 1000 10000 FREQUENCY (MHz) 0 1 30 GAIN FLATNESS (dB) 25 GAIN (dB) 20 15 RL = OPEN 5 RL = 150 0 10 100 1k 10k RG () 03145-004 RL = 1k -10 1000 10000 Figure 7. Gain vs. Frequency for a 1 k Differential Load (AV = 10 dB, 18 dB, and 26 dB) 35 -5 100 FREQUENCY (MHz) Figure 4. Gain vs. Frequency for a 150 Differential Load (AV = 6 dB, 12 dB, and 18 dB) 10 10 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 RL = 150 RL = 1k 1 10 100 1000 FREQUENCY (MHz) 03145-007 1 03145-003 -5 03145-006 5 Figure 8. Gain Flatness vs. Frequency (RL = 150 and 1 k, AV = 10 dB) Figure 5. Gain vs. Gain Resistor, RG (f = 100 MHz, RL = 150 , 1 k, and Open) 10.75 10.50 10.50 10.25 0 -10 10.00 10.00 9.75 9.75 9.50 9.50 9.25 ISOLATION (dB) 10.25 GAIN; RL = 150 (dB) -30 -40 -50 -60 -70 9.25 -50 -30 -10 10 30 50 70 90 9.00 110 TEMPERATURE (C) -90 0 100 200 300 400 500 600 700 800 900 FREQUENCY (MHz) Figure 9. Isolation vs. Frequency (AV = 10 dB) Figure 6. Gain vs. Temperature at 100 MHz (AV = 10 dB Rev. D | Page 7 of 19 1000 03145-008 -80 03145-005 GAIN; RL = 1k (dB) -20 AD8351 Data Sheet -50 -45 HD2 HD2 -60 -75 HD3 -70 -85 -80 -95 DIFFERENTIAL INPUT -90 -105 -100 0 25 50 75 100 125 150 175 200 225 -115 250 FREQUENCY (MHz) -30 -50 -60 -50 -70 -60 -80 HD3 DIFFERENTIAL INPUT -70 -90 HD2 -80 -100 -90 0 25 50 75 100 125 150 175 200 225 HD3 -85 -90 -50 -110 250 FREQUENCY (MHz) Figure 11. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 150 (AV = 10 dB) 2.65 2.60 60 70 80 90 100 HD3 -75 -80 HD2 -85 -90 -95 -100 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (MHz) Figure 14. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 150 Using Single-Ended Input (AV = 10 dB) NOISE SPECTRAL DENSITY (nV/Hz) 2.70 50 -70 2.95 2.75 40 SINGLE-ENDED INPUT -65 2.95 2.80 30 -60 3.00 2.85 20 -55 3.00 2.90 10 FREQUENCY (MHz) 03145-010 HD2 -40 HD2 -80 0 HARMONIC DISTORTION (dBc) -40 -75 Figure 13. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 1 k Using Single-Ended Input (AV = 10 dB) HARMONIC DISTORTION; VPOS = 3V (dBc) -20 2.90 2.85 2.80 2.75 2.70 2.65 2.60 2.50 0 50 100 150 200 FREQUENCY (MHz) 250 2.50 0 50 100 150 200 FREQUENCY (MHz) Figure 15. Noise Spectral Density (RTI) vs. Frequency (RL = 150 , 3 V Supply, AV = 10 dB) Figure 12. Noise Spectral Density (RTI) vs. Frequency (RL = 150 , 5 V Supply, AV = 10 dB) Rev. D | Page 8 of 19 250 03145-014 2.55 2.55 03145-011 NOISE SPECTRAL DENSITY (nV/Hz) HARMONIC DISTORTION; VPOS = 5V (dBc) -30 HD3 -70 -100 -20 -10 -65 -95 Figure 10. Harmonic Distortion vs. Frequency for 2 V p-p into RL = 1 k (AV = 10 dB, at 3 V and 5 V Supplies) 0 -60 03145-012 -65 03145-013 -50 HARMONIC DISTORTION (dBc) -55 HD3 SINGLE-ENDED INPUT -55 03145-009 -40 HARMONIC DISTORTION; VPOS = 3V (dBc) HARMONIC DISTORTION; VPOS = 5V (dBc) -30 Data Sheet AD8351 -70 14 -75 10 THIRD-ORDER IMD (dBc) RL = 150 VPOS = 5V RL = 1k 12 8 RL = 150 VPOS = 3V RL = 1k 6 4 -85 -90 0 25 50 75 100 125 150 175 200 225 250 FREQUENCY (MHz) -95 0 25 50 75 100 125 150 175 200 225 250 FREQUENCY (MHz) 03145-018 0 Figure 19. Third-Order Intermodulation Distortion vs. Frequency for a 2 V p-p Composite Signal into RL = 1 k (AV = 10 dB, at 5 V Supplies) Figure 16. Output Compression Point, P1 dB, vs. Frequency (RL = 150 and 1 k, AV = 10 dB, at 3 V and 5 V Supplies) -50 16 VPOS = 5V 14 -55 THIRD-ORDER IMD (dBc) 12 10 8 VPOS = 3V 6 4 -60 -65 -70 1000 GAIN RESISTOR () OUTPUT 1dB COMPRESSION (dB) 0 25 50 75 100 125 150 175 200 225 250 FREQUENCY (MHz) Figure 20. Third-Order Intermodulation Distortion vs. Frequency for a 2 V p-p Composite Signal into RL = 150 (AV = 10 dB, at 5 V Supplies) -68.0 -68.2 -68.4 -68.6 -68.8 -69.0 -69.2 -69.4 -69.6 -69.8 -70.0 03145-017 13.41 13.40 13.39 13.38 13.37 13.36 13.35 13.34 13.33 13.32 13.31 13.30 Figure 17. Output Compression Point, P1 dB, vs. RG (f =100 MHz, RL = 150 , AV = 10 dB, at 3 V and 5 V Supplies) -75 THIRD-ORDER INTERMODULATION DISTORTION (dBc) 03145-020 100 03145-016 0 10 03145-019 2 13.29 OUTPUT 1dB COMPRESSION (dBm) -80 2 03145-015 OUTPUT 1dB COMPRESSION (dBm) 16 Figure 21. Third-Order Intermodulation Distortion Distribution (f = 70 MHz, RL = 150 , AV = 10 dB) Figure 18. Output Compression Point Distribution (f = 70 MHz, RL = 150 , AV = 10 dB) Rev. D | Page 9 of 19 AD8351 Data Sheet 4000 0 3000 -25 2500 2000 -50 1500 1000 PHASE (Degrees) IMPEDANCE MAGNITUDE () 3500 3GHz -75 500MHz 3GHz 500 -100 1000 100 500MHz 03145-024 FREQUENCY (MHz) WITH 50 TERMINATIONS WITHOUT TERMINATIONS 03145-021 0 10 10MHz 10MHz Figure 25. Input Reflection Coefficient vs. Frequency (RS = RL = 100 With and Without 50 Terminations) 30 150 25 140 20 130 15 120 10 110 5 100 10 IMPEDANCE PHASE (Degrees) 160 0 1000 100 500MHz 10MHz 3GHz 03145-022 IMPEDANCE MAGNITUDE () Figure 22. Input Impedance vs. Frequency 03145-025 FREQUENCY (MHz) Figure 26. Output Reflection Coefficient vs. Frequency (RS = RL = 100 ) -2 PHASE (Degrees) -4 -6 -8 -10 -12 -14 -16 -18 0 25 50 75 100 125 150 175 200 225 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 1 0 250 FREQUENCY (MHz) 03145-023 0 GROUP DELAY (ps) Figure 23. Output Impedance vs. Frequency Figure 24. Phase and Group Delay (AV = 10 dB, at 5 V Supplies) Rev. D | Page 10 of 19 Data Sheet AD8351 80 3 VOUT 2 70 RL = 150 1 RL = 1k 40 -1 30 -2 20 1 10 100 1000 FREQUENCY (MHz) -3 0 5 10 15 20 25 30 35 40 45 50 TIME (ns) Figure 30. Overdrive Recovery Using Sinusoidal Input Waveform RL = 150 (AV = 10 dB, at 5 V Supplies) Figure 27. Common-Mode Rejection Ratio, CMRR (RS = 100 ) 1.00 0.6 0pF 0.75 0.4 5pF 2pF 0.50 10pF VOLTAGE (V) 0.2 VOLTAGE (V) VIN 0 03145-029 VOLTAGE (V) 50 03145-026 CMRR (dB) 60 0 -0.2 0.25 0 -0.25 -0.50 -0.4 -0.75 17 18 19 20 21 22 23 24 25 TIME (ns) Figure 28. Transient Response Under Capacitive Loading (RL = 150 , CL = 0 pF, 2 pF, 5 pF, 10 pF) 0 4.5 4 4.0 3 3.5 2 SETTLING (%) 5 3.0 2.5 2.0 -3 0.5 -4 0 20 25 30 35 2.5 3.0 3.5 4.0 -1 -2 15 2.0 0 1.0 10 1.5 1 1.5 5 1.0 Figure 31. Large Signal Transient Response for a 1 V p-p Output Step (AV = 10 dB, RIP = 25 ) 5.0 0 0.5 TIME (ns) 40 TIME (ns) Figure 29. 2x Output Overdrive Recovery (RL = 150 , AV = 10 dB) -5 03145-028 OUTPUT (V) -1.00 03145-030 16 0 3 6 9 TIME (ns) 12 15 03145-031 15 03145-027 -0.6 Figure 32. 1% Settling Time for a 2 V p-p Step (AV = 10 dB, RL = 150 ) Rev. D | Page 11 of 19 AD8351 Data Sheet THEORY OF OPERATION BASIC CONCEPTS 16 Figure 33. Differential Circuit Representation Figure 33 illustrates the expected input and output waveforms for a typical application. Usually the applied input waveform is a balanced differential drive, where the signal applied to the INHI and INLO pins are equal in amplitude and differ in phase by 180. In some applications, baluns may be used to transform a singleended drive signal to a differential signal. The AD8351 may also be used to transform a single-ended signal to a differential signal. 1 RG 3 4 14 RGP1 13 VPOS 12 INHI OPHI 11 INLO OPLO RGP2 RL 10 COMM 9 5 6 7 8 Figure 34. Common-Mode Adjustment GAIN ADJUSTMENT The differential gain of the AD8351 is set using a single external resistor, RG, which is connected between the RGP1 pin and the RGP2 pin. The gain can be set to any value between 0 dB and 26 dB using the resistor values specified in Figure 5, with common gain values provided in Table 4. The board traces used to connect the external gain resistor must be balanced and as short as possible to help prevent noise pickup and to ensure balanced gain and stability. The low frequency voltage gain of the AD8351 can be modeled as V RL RG (5.6) 9.2 RF RL OUT RG RL 4.6 19.5 RG RL RF 39 RG VIN where: RF is 350 (internal). RL is the single-ended load resistance. RG is the gain setting resistor. INPUT AND OUTPUT MATCHING The AD8351 provides a moderately high differential input impedance of 5 k. In practical applications, the input of the AD8351 is terminated to a lower impedance to provide an impedance match to the driving source, as shown in Figure 35. Place the terminating resistor, RT, as close as possible to the input pins to minimize reflections due to impedance mismatch. The 150 output impedance may need to be transformed to provide the desired output match to a given load. Matching components can be calculated using a Smith chart or by using a resonant approach to determine the matching network that results in a complex conjugate match. The input and output impedances and reflection coefficients are provided in Figure 22, Figure 23, Figure 24, and Figure 25. For additional information on reactive matching to differential sources and loads, refer to the Applications section of the AD8350 data sheet. VPOS BALANCED SOURCE RS RT 0.1F RG RS = RT RS RT 0.1F LS 27nF 0.1F AD8351 150 0.1F 190MHz SAW 50 CP 8pF LS 27nF Figure 35. Example of Differential SAW Filter Interface (fC = 190 MHz) Rev. D | Page 12 of 19 03145-034 AV 2 BALANCED SOURCE 15 VS VOCM CDECL 1.2V 0.1F TO 3.8V 0.1F 03145-033 13 VOCM 14 NC 15 NC VOCM 16 NC NC COMM 9 NC 2A NC RL 10 A RGP2 RG (RL = 500 ) 2 k 470 200 43 The output common-mode voltage level is the dc offset voltage present at each of the differential outputs. The ac signals are of equal amplitude with a 180 phase difference but are centered at the same common-mode voltage level. The common-mode output voltage level can be adjusted from 1.2 V to 3.8 V by driving the desired voltage level into the VOCM pin, as illustrated in Figure 34. PWUP NC OPLO RG (RL = 75 ) 680 200 100 22 NC 4 A OPHI 11 INLO Gain, AV 0 dB 6 dB 10 dB 20 dB COMMON-MODE ADJUSTMENT VPOS 12 INHI Table 4. Gain Resistor Selection for Common Gain Values (Load Resistance Is Specified as Single-Ended) 03145-032 3 13 NC RG 14 NC 2 15 NC BALANCED SOURCE 16 RGP1 NC 1 PWUP Differential signaling is used in high performance signal chains, where distortion performance, signal-to-noise ratio, and low power consumption is critical. Differential circuits inherently provide improved common-mode rejection and harmonic distortion performance as well as better immunity to interference and ground noise. Data Sheet AD8351 35 30 RL = 1000 25 GAIN (dB) 20 RL = 500 RL = 150 15 10 It is possible to drive a single-ended SAW filter by connecting the unused output to ground using the appropriate terminating resistance. The overall gain of the system is reduced by 6 dB because only half of the signal is available to the input of the SAW filter. 0 10 100 1000 03145-037 5 1000 03145-038 Figure 35 illustrates a surface acoustic wave (SAW) filter interface. Many SAW filters are inherently differential, allowing for a low loss output match. In this example, the SAW filter requires a 50 source impedance to provide the desired center frequency and Q. The series L shunt C output network provides a 150 to 50 impedance transformation at the desired frequency of operation. The impedance transformation is illustrated on a Smith chart in Figure 36. RG () 50 Figure 38. Gain Selection 100 25 7 6 10 RL = 1000 200 5 50 150 SHUNT C SERIES L RF (k) 500 0 500 200 4 RL = 500 3 2 100 50 1 RL = 150 25 0 10 03145-035 10 Figure 36. Smith Chart Representation of SAW Filter Output Matching Network 0.1F 50 50 RG 0.1F RL RF 03145-036 0.1F 25 Figure 39. Feedback Resistor Selection ADC DRIVING 0.1F AD8351 100 RG () Figure 37. Single-Ended Application SINGLE-ENDED-TO-DIFFERENTIAL OPERATION The AD8351 can easily be configured as a single-ended-todifferential gain block, as illustrated in Figure 37. The input signal is ac-coupled and applied to the INHI input. The unused input is ac-coupled to ground. Select the values of C1 through C4 such that their reactances are negligible at the desired frequency of operation. To balance the outputs, an external feedback resistor, RF, is required. To select the gain resistor and the feedback resistor, refer to Figure 38 and Figure 39. From Figure 38, select an RG for the required dB gain at a given load. Next, select from Figure 39 an RF resistor for the selected RG and load. Even though the differential balance is not perfect under these conditions, the distortion performance is still impressive. Figure 13 and Figure 14 show the second and third harmonic distortion performance when driving the input of the AD8351 using a single-ended 50 source. The circuit in Figure 40 represents a simplified front end of the AD8351 driving the AD6645, which is a 14-bit, 105 MSPS ADC. For optimum performance, the AD6645 and the AD8351 are driven differentially. The resistors R1 and R2 present a 50 differential input impedance to the source with R3 and R4 providing isolation from the analog-to-digital input. The gain setting resistor for the AD8351 is RG. The AD6645 presents a 1 k differential load to the AD8351 and requires a 2.2 V p-p differential signal between AIN and AIN for a full-scale output. This AD8351 circuit then provides the gain, isolation, and source matching for the AD6645. The AD8351 also provides a balanced input, not provided by the balun, to the AD6645, which is essential for second-order cancellation. The signal generator is bipolar, centered around ground. Connecting the VOCM pin (Pin 10 on the MSOP and Pin 13 on the LFCSP) of the AD8351 to the VREF pin of the AD6645 sets the common-mode output voltage of the AD8351 at 2.4 V. This voltage is bypassed with a 0.1 F capacitor. Increasing the gain of the AD8351 increases the system noise and thus decrease the SNR but does not significantly affect the distortion. The circuit in Figure 40 can provide SFDR performance of better than -90 dBc with a 10 MHz input and -80 dBc with a 70 MHz input at a gain of 10 dB. Rev. D | Page 13 of 19 AD8351 Data Sheet 100nF INHI 25 BALANCE 50 SOURCE RG 100nF 25 OPHI OPLO 25 INLO INHI AD6645 AD8351 AIN VREF DIGITAL OUT PWUP OPHI RGP1 SIGNAL INPUT 1 VOCM AD8351 RG 03145-039 25 N-BIT DIGITAL INTERFACE BIT 1 AIN RGP2 INLO OPLO Figure 40. ADC Driving Application Using Differential Input BIT 2 The circuit of Figure 41 represents a single-ended input to differential output configuration of the AD8351 driving the AD6645. In this case, R1 provides the input impedance. RG is the gain setting resistor. The resistor RF is required to balance the output voltages required for second-order cancellation by the AD6645 and can be selected using a chart (see the SingleEnded-to-Differential Operation section). The circuit depicted in Figure 41 can provide SFDR performance of better than -90 dBc with a 10 MHz input and -77 dBc with a 70 MHz input. INHI SIGNAL INPUT 2 RGP2 INLO BIT N AD6645 AD8351 INLO 25 100nF SIGNAL INPUT N AIN OPLO 25 AIN VREF OPHI RGP1 AD8351 RG RGP2 DIGITAL OUT INLO VOCM 100nF PWUP Figure 41. ADC Driving Application Using Single-Ended Input ANALOG MULTIPLEXING The AD8351 can be used as an analog multiplexer in applications where it is desirable to select multiple high speed signals. The isolation of each device when in a disabled state (PWUP pin pulled low) is about 60 dBc for the maximum input level of 0.5 V p-p out to 100 MHz. The low output noise spectral density allows for a simple implementation as depicted in Figure 42. The PWUP interface can be easily driven using most standard logic interfaces. By using an N-bit digital interface, up to N devices can be controlled. Output loading effects and noise need to be considered when using a large number of input signal paths. Each disabled AD8351 presents approximately a 700 load in parallel with the 150 output source impedance of the enabled device. As the load increases due to the addition of N devices, the distortion performance will degrade due to the heavier loading. Distortion better than -70 dBc can be achieved with four devices muxed into a 1 k load for signal frequencies up to 70 MHz. OPLO Figure 42. Using Several AD8351s to Form an N-Channel Analog MUX I/O CAPACITIVE LOADING Input or output direct capacitive loading greater than a few picofarads can result in excessive peaking and/or oscillation outside the pass band. This results from the package and bond wire inductance resonating in parallel with the input/output capacitance of the device and the associated coupling that results internally through the ground inductance. For low resistive load or source resistance, the effective Q is lower, and higher relative capacitance termination or terminations can be allowed before oscillation or excessive peaking occurs. These effects can be eliminated by adding series input resistors (RIP) for high source capacitance, or series output resistors (ROP) for high load capacitance. Generally less than 25 is all that is required for I/O capacitive loading greater than ~2 pF. The higher the C, the smaller the R parasitic suppression resistor required. In addition, RIP helps to reduce low gain in-band peaking, especially for light resistive loads. RIP CSTRAY CSTRAY RG RIP ROP CL AD8351 ROP CL RL 1k 03145-042 25 OPLO 03145-041 RG OPHI 03145-040 SINGLEENDED 50 SOURCE R1 25 MUX OUTPUT LOAD AD8351 RG INHI INHI OPHI RGP1 RF 100nF PWUP Figure 43. Input and Output Parasitic Suppression Resistors, RIP and ROP, Used to Suppress Capacitive Loading Effects Rev. D | Page 14 of 19 Data Sheet AD8351 Due to package parasitic capacitance on the RG ports, high RG values (low gain) cause high ac-peaking inside the pass band, resulting in poor settling in the time domain. As an example, when driving a 1 k load, using 25 for RIP reduces the peaking by ~7 dB for RG equal to 200 (AV = 10 dB) (see Figure 44). TRANSMISSION LINE EFFECTS As noted, stray transmission line capacitance, in combination with package parasitics, can potentially form a resonant circuit at high frequencies, resulting in excessive gain peaking. RF transmission lines connecting the input and output networks must be designed to minimize stray capacitance. The output single-ended source impedance of the AD8351 is dynamically set to a nominal value of 75 . Therefore, for a matched load termination, design the characteristic impedance of the output transmission lines to be 75 . In many situations, the final load impedance may be relatively high, greater than 1 k. It is suggested that the board be designed as shown in Figure 45 for high impedance load conditions. In most practical board designs, this requires that the printed circuit board traces be dimensioned to a small width (~5 mils) and that the underlying and adjacent ground planes are far enough away to minimize capacitance. 25 NO RIP 15 10 RIP = 25 100 1k 10k FREQUENCY (MHz) Figure 44. Reducing Gain Peaking with Parasitic Suppressing Resistors (RIP = 25 , RL = 1 k) It is important to ensure that all I/O, ground, and RG port traces be kept as short as possible. In addition, the ground plane must be removed from under the package. Due to the inverse relationship between the gain of the device and the value of the RG resistor, any parasitic capacitance on the RG ports can result in gain-peaking at high frequencies. Following the precautions outlined in Figure 45 helps to reduce parasitic board capacitance, thus extending the bandwidth of the device and reducing potential peaking or oscillation. AGND RT 1 10 2 9 RIP COPLANAR WAVEGUIDE OR STRIP Typically the driving source impedance into the device is below and terminating resistors are used to prevent input reflections. The transmission line must be designed to have the appropriate characteristic impedance in the low-Z region. The high impedance environment between the terminating resistors and device input pins must not have ground planes underneath or near the signal traces. Small parasitic suppressing resistors may be necessary at the device input pins to help desensitize (de-Q) the resonant effects of the device bond wires and surrounding parasitic board capacitance. Typically, 25 series resistors (size 0402) adequately de-Q the input system without a significant decrease in ac performance. Figure 46 illustrates the value of adding input and output series resistors to help desensitize the resonant effects of board parasitics. Overshoot and undershoot can be significantly reduced with the simple addition of RIP and ROP. 1.5 8 4 7 5 6 ROP = 25 HIGH-Z RIP 1.0 ROP RG 0.5 AGND Figure 45. General Description of Recommended Board Layout for High-Z Load Conditions (10-Lead MSOP Package) 03145-044 RT NO RIP OR ROP ROP 3 RIP = ROP = 25 0 -0.5 -1.0 -1.5 0 1 2 TIME (ns) 3 4 03145-045 0 10 03145-043 5 VOLTAGE (V) 2log; AV (dB) 20 Figure 46. Step Response Characteristics With and Without Input and Output Parasitic Suppression Resistors Rev. D | Page 15 of 19 AD8351 Data Sheet The output L-pad matching networks provide a broadband impedance match with minimum insertion loss. The input lines are terminated with 50 resistors for input impedance matching. The power loss associated with these networks must be accounted for when attempting to measure the gain of the device. The required resistor values and the appropriate insertion loss and correction factors used to assess the voltage gain are shown in Table 5. CHARACTERIZATION SETUP The test circuit used for 150 and 1 k load testing is shown in Figure 47. The evaluation board uses balun transformers to simplify interfacing to single-ended test equipment. Balun effects must be removed from the measurements to accurately characterize the performance of the device at frequencies exceeding 1 GHz. Table 5. Load Conditions Specified Differentially R1 () 43.2 475 R2 () 86.6 52.3 RS 50 Total Insertion Loss (dB) 5.8 15.9 RT 50 0.1nF BALANCED SOURCE 0.1nF RS 50 100nF 50 CABLE AD8351 DUT 50 CABLE RT 50 100nF Conversion Factor 20 log (S21) to 20 log (AV) 7.6 dB 25.9 dB R1 50 CABLE 50 R2 RLOAD R1 Figure 47. Test Circuit Rev. D | Page 16 of 19 50 CABLE R2 50 TEST EQUIPMENT 50 03145-046 Load Condition 150 1 k Data Sheet AD8351 EVALUATION BOARD 03145-048 An evaluation board is available for experimentation. Various parameters such as gain, common-mode level, and input and output network configurations can be modified through minor resistor changes. The schematic and evaluation board artwork are presented in Figure 48, Figure 49, and Figure 50. 03145-047 Figure 49. Component Side Silkscreen Figure 48. Component Side Layout R7 0 R12 0 R8 C5 100nF 0 R4 24.9 4 J5 TEST IN2 VOCM NC OPHI 11 INHI C6 100nF R13 OPEN R11 61.9 R10 61.9 AD8351 OPLO 10 INLO RGP2 5 R15 0 R16 0 COMM 9 6 7 T3 1:1 ETC1-1-13 (MACOM) C7 100nF R9 61.9 T2 J3 RF_OUT+ J4 RF_OUT- 1:1 ETC1-1-13 (MACOM) R14 0 8 C10 100nF C9 100nF T4 1:1 ETC1-1-13 (MACOM) Figure 50. Evaluation Board Schematic Rev. D | Page 17 of 19 J6 TEST OUT2 03145-049 1:1 ETC1-1-13 (MACOM) C2 100nF 13 NC 3 VPOS VPOS 12 NC 2 14 NC R1 100 15 RGP1 NC J2 RF_IN- T1 1 C4 R5 100nF 0 NC PWUP C3 0.1F 16 R3 OPEN AGND R6 OPEN R18 0 J1 RF_IN+ ACOM ENBL VCOM R17 0 W1 R2 24.9 VPOS P1 AD8351 Data Sheet Table 6. Evaluation Board Configuration Options Component P1-1, P1-2, VPOS, AGND P1-3 W1, R7, P1-4, R17, R18 R2, R3, R4, R5, R8, R12, T1, C4, C5 R9, R10, R11, R13, R14, R15, R16, T2, C4, C5, C6, C7 R1 C2 R6, C3, P1-3 T3, T4, C9, C10 Function Supply and Ground Pins. Default Condition Not Applicable Common-Mode Offset Pin. Allows for monitoring or adjustment of the output common-mode voltage. Device Enable. Configured such that switch W1 disables the device when Pin 1 is set to ground. Device can be disabled remotely using Pin 4 of header P1. Not Applicable Input Interface. R3 and R12 are used to ground one side of the differential drive interface for single-ended applications. T1 is a 1-to-1 impedance ratio balun used to transform a single-ended input into a balanced differential signal. R2 and R4 are used to provide a differential 50 input termination. R5 and R8 can be increased to reduce gain peaking when driving from a high source impedance. The 50 termination provides an insertion loss of 6 dB. C4 and C5 are used to provide ac coupling. Output Interface. R13 and R14 are used to ground one side of the differential output interface for single-ended applications. T2 is a 1-to-1 impedance ratio balun used to transform a balanced differential signal into a single-ended signal. R9, R10, and R11 are provided for generic placement of matching components. R15 and R16 allow additional output series resistance when driving capacitive loads. The evaluation board is configured to provide a 150 to 50 impedance transformation with an insertion loss of 9.9 dB. C4 through C7 are used to provide ac coupling. Gain Setting Resistor. Resistor R1 is used to set the gain of the device. Refer to Figure 5 when selecting gain resistor. When R1 is 100 , the overall system gain of the evaluation board is approximately -6 dB. Power Supply Decoupling. The supply decoupling consists of a 100 nF capacitor to ground. Common-Mode Offset Adjustment. Used to trim common-mode output level. By applying a voltage to Pin 3 of header P1, the output common-mode voltage can be directly adjusted. Typically decoupled to ground using a 0.1 F capacitor. Calibration Networks. Calibration path provided to allow for compensation of the insertion loss of the baluns and the reactance of the coupling capacitors. Rev. D | Page 18 of 19 W1 = Installed R7 = 0 (Size 0603) R17 = R18 = 0 (Size 0603) R2 = R4 = 24.9 (Size 0805) R3 = Open (Size 0603) R5 = R8 = R12 = 0 (Size 0603) C4 = C5 = 10 0 nF (Size 0603) T1 = MacomTM ETC1-1-13 R9 = R10 = 61.9 (Size 0603) R11 = 61.9 (Size 0603) R13 = Open (Size 0603) R14 = 0 (Size 0603) R15 = R16 = 0 (Size 0402) C4 = C5 = 100 nF (Size 0603) C6 = C7 = 100 nF (Size 0603) T2 = Macom ETC1-1-13 R1 = 100 (Size 0603) C2 = 100 nF (Size 0805) R6 = 0 (Size 0603) C3 = 0.1 F (Size 0805) T3 = T4 = Macom ETC1-1-13 C9 = C10 = 100 nF (Size 0603) Data Sheet AD8351 OUTLINE DIMENSIONS 3.10 3.00 2.90 3.10 3.00 2.90 10 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15 MAX 1.10 MAX 0.70 0.55 0.40 0.23 0.13 6 0 0.30 0.15 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 51. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters PIN 1 INDICATOR 0.32 0.25 0.20 0.50 BSC 13 PIN 1 INDICATOR (0.30) 16 1 12 1.80 1.70 SQ 1.60 EXPOSED PAD 9 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 4 5 8 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF PKG-004326 SEATING PLANE 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WEED-2. 10-09-2013-A 3.10 3.00 SQ 2.90 Figure 52. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm x 3 mm Body, Very Very Thin Quad (CP-16-35) Dimensions shown in millimeters ORDERING GUIDE Model1 AD8351ARM AD8351ARM-REEL7 AD8351ARMZ AD8351ARMZ-REEL7 AD8351ACPZ-R7 AD8351-EVALZ 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board Z = RoHS Compliant Part. (c)2003-2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03145-0-1/15(D) Rev. D | Page 19 of 19 Package Option RM-10 RM-10 RM-10 RM-10 CP-16-35 Branding JDA JDA #JDA #JDA Q20