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P/N:PM0954 REV. 0.3, NOV. 22, 2002
MX69F1602/1604C3T/B
ADVANCED INFORMATION
FEATURES
• Supply voltage range: 2.7V to 3.6V
• F ast access time: Flash memory:70/90ns
SRAM memory:70/85ns
• Operation temperature range: -40 ~ 85°C
FLASH
• Word mode only
• VCCf=VCCQ=2.7V~3.6V for read, erase and program
operation
• VPP=12V for fast production programming
• Low power consumption
- 9mA typical active read current, f=5MHz
- 18mA typical program current (VPP=1.65~3.6V)
- 21mA typical erase current (VPP=1.65~3.6V)
- 7uA typical standby current under power saving mode
• Sector architecture
- Sector structure : 4Kword x 2 (boot sectors), 4Kword
x 6 (parameter sectors), 32Kword x 31 (main sectors)
- Top/Bottom Boot
• Auto Erase and Auto Program
- Automatically program and verify data at specified
address
- Auto sector erase at specified sector
• Automatic Suspend Enhance
- Word write suspend to read
- Sector erase suspend to word write
- Sector erase suspend to read register report
• Automatic sector erase, word write and sector lock/
unlock configuration
• 100,000 minimum erase/program cycles
• Boot Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Status Register feature for detection of program or
erase cycle completion
• Data protection performance
- Sectors to be locked/unlocked
• Common Flash Interface (CFI)
• 128-bit Protection Register
- 64-bit Unique Device Identifier
- 64-bit User-Programmable
• Latch-up protected to 100mA from -1V to VCC+1V
SRAM
• MX69F1602C3T/B: 128K wordx16 Bit
• MX69F1604C3T/B: 256K wordx16 Bit
• 70mA maximum active current
• 1uA typical standby current
• Data retention supply voltage: 2.0V~3.6V
• Byte data control : LBs(Q0 to Q7) and UBs(Q8 to Q15)
16M-BIT [X16] FLASH AND 2M-BIT/4M-BIT [X16] SRAM
MIXED MULTI CHIP PACKAGE MEMORY
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MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
GENERAL DESCRIPTION
The MXIC's mixed multi chip memory combines Flash
and SRAM into a single package. The mixed multi chip
memory operates 2.7 to 3.6V power supply to allow for
simple in-system operation.
The Flash memory of mixed multi chip memory manu-
factured with MXIC's advanced nonvolatile memory tech-
nology, the flash memor y of mixed multi chip memor y
is designed to be re-programmed and erased in system
or in standard EPROM programmers. The device offers
access times of 70ns/90ns, and 7uA typical standby
current.
Flash memories augment EPROM functionality with in-
circuit electrical erasure and programming and use a
command register to manage this functionality . The com-
mand register allows for 100% TTL level control inputs
and fixed power supply levels during erase and program-
ming, while maintaining maximum EPROM compatibil-
ity.
Flash memory reliably stores memory contents even af-
ter 100,000 erase and program cycles. The cell is de-
signed to optimize the erase and programming mecha-
nisms. In addition, the combination of advanced tunnel
oxide processing and low internal electric fields for erase
and program operations produces reliable cycling.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamperes on
address and data pin from -1V to VCC + 1V.
The dedicated VPP pin gives complete data protection
when VPP< VPPLK.
The Flash contains both a Command User Interface (CUI)
and a W rite State Machine (WSM). A Command User
Interface (CUI) serves as the interface between the sys-
tem processor and internal operation of the device. A
valid command sequence written to the CUI initiates
device automation. An internal Write State Machine
(WSM) automatically executes the algorithms and tim-
ings necessary for erase, word write and sector lock/
unlock configuration operations.
Flash erase automation allows sector erase operation to
be executed using an industry-standard two-write com-
mand sequence to the CUI. A sector erase operation
erases one of the device's 32K-word sectors typically
within 1.0s, 4K-word sectors typically within 0.5s inde-
pendent of other sectors. Each sector can be indepen-
dently erased minimum 100,000 times. Sector erase
suspend mode allows system software to suspend sec-
tor erase to read or write data from any other sector .
Flash program automation allows program operation to
be executed using an industry-standard two-write com-
mand sequence to the CUI. Writing memory data is per-
formed in word increments of the device's 32K-word sec-
tors typically within 0.8s and 4K-word sectors typically
within 0.1s. Word program suspend mode enables the
system to read data or execute code from any other
memory array location.
The Flash features with individual sectors locking by
using a combination of thir ty-nine sector lock-bits and
WP, to lock and unlock sectors.
The Flash status register indicates the status of the WSM
when the sector erase, word program or lock configura-
tion operation is done.
The Flash power saving mode feature substantially re-
duces active current when the device is in static mode
(addresses not switching). In this mode, the typical ICCS
current is 7uA (CMOS) at 3.0V VCC . As CEf and R E -
SET are at VCC, ICC CMOS standb y mode is enabled.
When RESET is at GND , the reset mode is enabled which
minimize power consumption and provide data write pro-
tection.
The Flash require a reset time (tPHQV) from RESET
switching high until outputs are valid. Similarly , the flash
has a wak e time (tPHEL) from RESET-high until writes
to the CUI are recognized. With RESET at GND, the
WSM is reset and the status register is cleared.
The 2M-bit SRAM of MX69F1602C3T/B is organized as
128K-word by 16-bit. The 4M-bit SRAM of
MX69F1604C3T/B is organized 256K-word by 16-bit. The
advanced CMOS technology and circuit techniques pro-
vide both high speed and low power features of with a
typical CMOS standby current of 1uA and maximum
access time of 70ns/85ns in 3V operation.
The mixed multi chip memory is available in 10mm x
8mm FBGA P ackage to suit a variety of design applica-
tions.
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MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
Feature Summary
Feature MX69F1602/1604C3T/B
Vcc Operating V oltage 2.7~3.6V
Configuration Flash 16M:1M Word x16bit
SRAM MX69F1602C3T/B:128K Word x16bit
MX69F1604C3T/B:256K Word x16bit
Fast Access Time - 70 : Flash/70ns, SRAM/70ns
- 90 : Flash/90ns, SRAM/85ns
Block Architecture Flash 2 x 4K Word Boot
6 x 4K Word P arameter
31 x 32K W ord Main
Address Pin Flash A0~A19
SRAM MX69F1602C3T/B:A0~A16
MX69F1604C3T/B:A0~A17
Manufacture Code Flash 00C2H
Device ID Code Flash MX69F1602/1604C3T=88C2H
MX69F1602/1604C3B=88C3H
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MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
SYMBOL PIN NAME
A0 to A16 Address Inputs (Common) for
MX69F1602C3T/B
A0 to A17 Address Inputs (Common) for
MX69F1604C3T/B
A17 to A19 Address Input (Flash) fo r
MX69F1602C3T/B
A18 to A19 Address Input (Flash) fo r
MX69F1604C3T/B
Q0 to Q15 Data Inputs/Outputs (Common)
CEf Chip Enable (Flash)
CE1s Chip Enable (SRAM)
CE2s Chip Enable (SRAM)
OEf Output Enable (Flash)
OEs Output Enable (SRAM)
PIN DESCRIPTION
SYMBOL PIN NAME
WEf Write Enable (Flash)
WEs Write Enable (SRAM)
UBs Upper Byte Control (SRAM)
LBs Lower Byte Control (SRAM)
RESET Hardware Reset Pin/Deep P ower
Down (Flash)
WP Write Protect
N.C. No Connection
GND Ground Pin (Common)
VCCf Power Supply (Flash, 2.7V~3.6V)
VCCs Power Supply (SRAM, 2.7V~3.6V)
VPP Program/Erase Power Supply
(1.65V~3.6V or 11.4V~12.6V)
VCCQ I/O Power Supply (Flash) tied to VCCf
PIN ASSIGNMENT
1.66-ball CSP for MX69F1602/1604C3T/B (Top View Balls Down, 10 x 8 x 1.4mm, Ball Pitch=0.8mm)
Notes:
1.To maintain compatibility with all JEDEC Variation B options f or this ball location C6, this C6 land pad should be
connected directly to the land pad for ball G4 (A17).
NC NC NC
NC NC
A
B
C
D
E
F
G
H
NC NC
A15 A14
Q2
WP VPP A19 Q11 Q10
Q0
Q3
LBs UBs OEs Q9 Q8 Q1
A18 A17 A7 A6 A3 A2 A1 CE1s
NC NC NC NCA5 A4 A0 CEf GNDf OEf
123456789101112
VCCs VCCf
GNDs Q12 CE2s
A16
A11 A12 GNDf
VCCQ
A13
A8 A10 A9 Q15 WEs Q14 Q7
Q4 Q5
WEf NC Q13 Q6
RESET
8.0 mm
10.0 mm
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MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
BLOCK DIAGRAM for MX69F1602/1604C3T/B
1MWx16bit (16M)
Flash Memory
2M/4M bit
Static RAM
Vccs
CE1s
CE2s
OEs
WEs
UBs
LBs
GND
VCCf
A0~A19 A0~A19
A0~A16/A0~A17
GND
Q0 to Q15
Q0 to Q15
Q0 to Q15
VPP VCCQ
CEf
OEf
WEf
RESET
WP
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MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
DEVICE BUS OPERATIONS for MX69F1602/1604C3T/B
Legend:
L=VIL, H=VIH, X at control pins=VIL or VIH. See "ELECTRIAL CHARACTERISTICS 1.DC Char acteristics" for v olt-
age levels.
Notes:
1. Do not apply CEf=VIL, CE1s=VIL and CE2s=VIH at a time.
2. ID=Device Identifier Code. See "Table 3. Configuration Code"
3. Outputs are dependent on a seperate device controlling bus output.
4. Modes of the flash and SRAM can be interleaved so that while one is disabled the other controls outputs.
5. To program or erase the lockab le sectors hold WP at VIH.
6. RESET at GND ± 0.2V to ensure the lowest power consumption.
7. Ref er to Tab le 2 for valid Din during a write operation.
Notes CEf OEf WEf CE1s CE2s OEs WEs LBs UBs Q0~ Q8~ RESET
(1) (1) (1) Q7 Q15
Full Standby 3,4 H X X H X X X X X High Z High Z H
XL
Flash Output Disable 3,4 L H H H X X X X X High Z High Z H
XL
Array L L H H X X X X X Dout Dout H
XL
Read Query L L H H X X X X X Dout Dout H
from X L
Flash Configuration L L H H X X X X X ID(2) ID(2) H
XL
Status L L H H X X X X X Dout Dout H
Register X L
Write to Flash 5, 7 L H L H X X X X X D in D in H
XL
Reset 3,4,6 X X X H X X X X X High Z High Z L
XL
SRAM Output 3,4 H X X L H H H X X High Z High Z H
Disable X X H H
Read from SRAM H X X L H L H L L Dout Dout H
H L High Z Dout H
L H Dout High Z H
Write to SRAM H X X L H H L L L D i n D i n H
H L X Din H
L H Din X H
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MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operating T emperature
During Read, Sector Erase, Word
Write . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Storage Temperature . . . . . . . . . . . . . .-65oC to +125oC
Voltage on Any Ball (e xcept VCCf , VCCs, VCCQ and
VPP) with respect to GND . . . . . . . . .-0.5 V to +3.7V(1)
VPP Supply V oltage (for Sector Erase and W ord Write)
with respect to GND . . . . . . . . . .-0.5V to +13.5V(1,2,4)
VCCf, VCCs and VCCQ Supply Voltage
with respect to GND. . . . . . . . . . . . . . . . .-0.2V to +3.6V(1)
Output Short Circuit Voltage . . . . . . . . . . . . .100mA(3)
W ARNING: Stressing the device bey ond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex-
tended exposure beyond the "Operation Conditions" may
affect device reliability.
Capacitance (1) (TA=+25oC, f=1MHz)
Symbol Parameter Min. Max. Unit Notes
T A Operating Temperature -40 +85 oC
VCCf Flash VCC Supply Voltage 2.7 3.6 V 1
VCCs SRAM VCC Supply V oltage 2.7 3.6 V
VCCQ Flash I/O Supply Voltage 2. 7 3. 6 V 1
VPP1 Supply Voltage 1.65 3.6 V 1
VPP2 Supply Voltage 11.4 12.6 V 1,2
Cycling Sector Erase Cycling 100,000 2
Operating Conditions (Temperature and VCC Operating Conditions)
Symbol Parameter Typ. Max. Unit Test Condition
CIN Input Capacitance 1 6 1 8 pF VIN=0.0V
COUT Output Capacitance 2 0 22 pF VOUT=0.0V
NOTE:
1.Sampled, not 100% tested.
1. Minimum DC voltage is -0.5V on input/output pins.
During transitions, this level may undershoot to -2.0V
for periods <20ns. Maximum DC voltage on input/out-
put balls to VCCf/VCCs/VCCQ+0.5V which during tran-
sition; may overshoot to VCCf/VCCs/VCCQ+2.0V for
periods <20ns.
2. Maximum DC voltage on VPP may overshoot to
+14.0V for periods <20ns.
3. Output shorted for no more than one second. No more
than one output shorted at a time.
4. VPP voltage is normally 1.65V~3.6V. Connection to
supply of 11.4V~12.6V can only be done for 1000
cycles on the main sectors and 2500 cycles on the
parameter sectors during program/erase. VPP may
be connected to 12V for a total of 80 hours maximum.
NOTE:
1.VCCf and VCCQ must share the same supply.
2.Applying VPP=11.4~12.6V during a program/er ase can only be done f or a maximum of 1000 cycles on the main
sectors and 2500 cycles on the parameter sectors. VPP may be connected to 12V f or a total of 80 hours maximum.
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MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
FLASH SECTOR STRUCTURE (MX69F1602/1604C3T)
Sector Sector Size Address Range (h)
Boot Sector 0 4K W or d FF000 ~ FFFFF
Boot Sector 1 4K W or d FE000 ~ FEFFF
Parameter Sector 0 4K Word FD000 ~ FDFFF
Parameter Sector 1 4K Word FC000 ~ FCFFF
Parameter Sector 2 4K Word FB000 ~ FBFFF
Parameter Sector 3 4K Word F A000 ~ F AFFF
Parameter Sector 4 4K W ord F9000 ~ F9FFF
Parameter Sector 5 4K W ord F8000 ~ F8FFF
Main Sector 0 32K Word F0000 ~ F7FFF
Main Sector 1 32K Word E8000 ~ EFFFF
Main Sector 2 32K Word E0000 ~ E7FFF
Main Sector 3 32K Word D8000 ~ DFFFF
Main Sector 4 32K Word D0000 ~ D7FFF
Main Sector 5 32K Word C8000 ~ CFFFF
Main Sector 6 32K Word C0000 ~ C7FFF
Main Sector 7 32K Word B8000 ~ BFFFF
Main Sector 8 32K Word B0000 ~ B7FFF
Main Sector 9 32K Word A8000 ~ AFFFF
Main Sector 10 32K Word A0000 ~ A7FFF
Main Sector 11 32K Word 98000 ~ 9FFFF
Main Sector 12 32K Word 90000 ~ 97FFF
Main Sector 13 32K Word 88000 ~ 8FFFF
Main Sector 14 32K Word 80000 ~ 87FFF
Main Sector 15 32K Word 78000 ~ 7FFFF
Main Sector 16 32K Word 70000 ~ 77FFF
Main Sector 17 32K Word 68000 ~ 6FFFF
Main Sector 18 32K Word 60000 ~ 67FFF
Main Sector 19 32K Word 58000 ~ 5FFFF
Main Sector 20 32K Word 50000 ~ 57FFF
Main Sector 21 32K Word 48000 ~ 4FFFF
Main Sector 22 32K Word 40000 ~ 47FFF
Main Sector 23 32K Word 38000 ~ 3FFFF
Main Sector 24 32K Word 30000 ~ 37FFF
Main Sector 25 32K Word 28000 ~ 2FFFF
Main Sector 26 32K Word 20000 ~ 27FFF
Main Sector 27 32K Word 18000 ~ 1FFFF
Main Sector 28 32K Word 10000 ~ 17FFF
Main Sector 29 32K Word 08000 ~ 0FFFF
Main Sector 30 32K Word 00000 ~ 07FFF
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FLASH SECTOR STRUCTURE (MX69F1602/1604C3B)
Sector Sector Size Address Range (h)
Boot Sector 0 4K W ord 00000 ~ 00FFF
Boot Sector 1 4K W ord 01000 ~ 01FFF
Parameter Sector 0 4K Word 02000 ~ 02FFF
Parameter Sector 1 4K Word 03000 ~ 03FFF
Parameter Sector 2 4K Word 04000 ~ 04FFF
Parameter Sector 3 4K Word 05000 ~ 05FFF
Parameter Sector 4 4K Word 06000 ~ 06FFF
Parameter Sector 5 4K Word 07000 ~ 07FFF
Main Sector 0 32K Word 08000 ~ 0FFFF
Main Sector 1 32K Word 10000 ~ 17FFF
Main Sector 2 32K Word 18000 ~ 1FFFF
Main Sector 3 32K Word 20000 ~ 27FFF
Main Sector 4 32K Word 28000 ~ 2FFFF
Main Sector 5 32K Word 30000 ~ 37FFF
Main Sector 6 32K Word 38000 ~ 3FFFF
Main Sector 7 32K Word 40000 ~ 47FFF
Main Sector 8 32K Word 48000 ~ 4FFFF
Main Sector 9 32K Word 50000 ~ 57FFF
Main Sector 10 32K Word 58000 ~ 5FFFF
Main Sector 11 32K Word 60000 ~ 67FFF
Main Sector 12 32K Word 68000 ~ 6FFFF
Main Sector 13 32K Word 70000 ~ 77FFF
Main Sector 14 32K Word 78000 ~ 7FFFF
Main Sector 15 32K Word 80000 ~ 87FFF
Main Sector 16 32K Word 88000 ~ 8FFFF
Main Sector 17 32K Word 90000 ~ 97FFF
Main Sector 18 32K Word 98000 ~ 9FFFF
Main Sector 19 32K Word A0000 ~ A7FFF
Main Sector 20 32K Word A8000 ~ AFFFF
Main Sector 21 32K Word B0000 ~ B7FFF
Main Sector 22 32K Word B8000 ~ BFFFF
Main Sector 23 32K Word C0000 ~ C7FFF
Main Sector 24 32K Word C8000 ~ CFFFF
Main Sector 25 32K Word D0000 ~ D7FFF
Main Sector 26 32K Word D8000 ~ DFFFF
Main Sector 27 32K Word E0000 ~ E7FFF
Main Sector 28 32K Word E8000 ~ EFFFF
Main Sector 29 32K Word F0000 ~ F7FFF
Main Sector 30 32K Word F8000 ~ FFFFF
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FLASH
1.0 PRINCIPLES OF OPERATION
The product includes an on-chip WSM to manage sec-
tor erase, word write and lock-bit configuration functions.
After initial device power-up or return from reset mode
(see section on Bus Operations), the device defaults to
read array mode. Manipulation of external memory con-
trol pins allow array read, standby and output disable
operations.
Status register and identifier codes can be accessed
through the CUI independent of the VPP voltage. All
functions associated with altering memory contents -
sector erase, word write, sector lock/unlock, status and
identifier codes - are accessed via the CUI and verified
through the status register .
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the sector erase, word write and
sector lock/unlock. The internal algorithms are regulated
by the WSM, including pulse repetition, internal verifica-
tion and margining of data. Addresses and data are in-
ternally latched during write cycles. Address is latched
at falling edge of CEf and data latched at rising edge of
WEf. Writing the appropriate command outputs array data,
accesses the identifier codes or outputs status register
data.
Interface software that initiates and polls progress of
sector erase, word write and sector lock/unlock can be
stored in any sector . This code is copied to and executed
from system RAM during flash memory updates. After
successful completion, reads are again possible via the
Read Array command. Sector erase suspend allows
system software to suspend a sector erase to read/write
data from/to sectors other than that which is suspend.
Word write suspend allows system software to suspend
a word write to read data from any other flash memory
array location.
With the mechanism of sector lock, memory contents
cannot be altered due to noise or unwanted operation.
When RESET=VIH and VCCf<VLK O (loc kout voltage),
any data write alteration can be failure. During read op-
eration, if write VPP voltage is below VPPLK, then hard-
w are level data protection is achieved. With CUI's two-
step command sequence sector erase, word write or
sector lock/unlock, software level data protection is
achieved also .
2.0 BUS OPERATION
The local CPU reads and writes flash memory in-sys-
tem. All bus cycles to or from the flash memory conform
to standard microprocessor bus cycles.
2.1 Read
Inf ormation can be read from any sector, configuration
codes or status register independent of the VPP volt-
age. RESET can be at VIH.
The first task is to write the appropriate read mode com-
mand (Read Arra y , Read Configuration, Read Query or
Read Status Register) to the CUI. Upon initial device
power-up or after exit from reset, the device automati-
cally resets to read array mode. In order to read data,
control pins set for CEf, OEf, WEf, RESET and WP must
be driven to active. CEf and OEf must be active to ob-
tain data at the outputs. CEf is the device selection con-
trol. OEf is the data output (Q0-Q15) control and active
drives the selected memory data onto the I/O bus, WEf
must be VIH, RESET must be VIH, WP must be at VIL
or VIH.
2.2 Output Disable
With OEf at a logic-high level (VIH), the device outputs
are disabled. Output pins (Q0-Q15) are placed in a high-
impedance state.
2.3 Standby
CEf at a logic-high level (VIH) places the device in
standby mode which substantially reduces device power
consumption. Q0~Q15 outputs are placed in a high-im-
pedance state independent of OEf. If deselected during
sector erase, word write or sector lock/unlock, the de-
vice continues functioning, and consuming active power
until the operation completes.
2.4 Reset
As RESET=VIL, it initiates the reset mode. The device
enters reset/deep power down mode. However, the data
stored in the memory has to be sustained at least 100ns
in the read mode before the device becomes deselected
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REV. 0.3, NOV. 22, 2002
and output high impedance state.
In read modes, RESET-low deselects the memory,
places output drivers in a high-impedance state and turns
off all internal circuits. RESET must be held low for a
minimum of 100ns. Time tPHQV is required after return
from reset mode until initial memory access outputs are
valid. After this wake-up interval tPHEL or tPHWL, nor-
mal operation is restored. The CUI is reset to read array
mode and status register is set to 80H. Sector lock bit is
set at lock status.
During sector erase, word write or sector lock/unlock
modes, RESET-low will abort the operation. Memory con-
tents being altered are no longer valid; the data may be
partially erased or written.
In addition, CUI will go into either array read mode or
erase/write interrupted mode. When power is up and the
device reset subsequently, it is necessary to read sta-
tus register in order to assure the status of the device.
Recognizing status register (SR.7~0) will assure if the
device goes back to normal reset and enters array read
mode.
2.5 Read Configuration Codes
The read configuration codes operation outputs the manu-
facturer code, device code, sector lock configuration
codes, and the protection register. Using the manufac-
turer and device codes, the system CPU can automati-
cally match the device with its proper algor ithms. The
sector lock codes identify locked and unlocked sectors.
2.6 Write
Writing commands to the CUI enable reading of device
data and identifier codes. They also control inspection
and clearing of the status register. When VCCf=2.7V-
3.6V and VPP within VPP1 or VPP2 r ange, the CUI ad-
ditionally controls sector erase, word write and sector
lock/unlock.
The Sector Erase command requires appropriate com-
mand data and an address within the sector to be erased.
The Full Chip Erase command requires appropriate com-
mand data and an address within the de vice. The W ord
Write command requires the command and address of
the location to be written. Set Sector lock/unlock com-
mands require the command and address within the de-
vice or sector within the device (Sector Lock) to be
locked. The Clear Sector Lock-Bits command requires
the command and address within the device.
The CUI does not occupy an addressable memory loca-
tion. It is written when WEf and CEf are active (which-
ever goes high first). The address and data needed to
execute a command are latched on the rising edge of
WEf or CEf. Standard microprocessor write timings are
used.
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REV. 0.3, NOV. 22, 2002
Table 2. Command Definition (1)
Command Bus Notes First Bus Cycle Second Bus Cycle
Cycles Operation Address Data Operation Address Data
Required (1) (2) (3) (1) (2) (3)
Read Array 1 Write X FFH
Read Configuration > 2 2,4 Write X 90H Read IA ID
Read Query 2 2,7 Write X 98H Read QA QD
Read Status Register 2 3 Write X 70H Read X SRD
Clear Status Register 1 3 Write X 50H
Sector Erase/Confirm 2 Write X 20H Write SA D0H
Word Write 2 2,5 Write X 40H/10H Write WA WD
Program/Erase Suspend 1 Write X B0H
Program/Erase Resume 1 Write X D 0H
Sector Lock 2 Write X 60H Write SA 01H
Sector Unlock 2 6 Write X 60H Write SA D0H
Lock-Down Sector 2 Write X 60H Write SA 2FH
Protection Program 2 Write X C0H Write PA PD
Lock Protection Register 2 Write X C0H Write PA FFFD
Notes:
1. Bus operation are defined at page 6 and referred to AC Timing Wavef orm.
2. X=Any address within device.
IA=ID-Code Address (refer to Table 3).
ID=Data read from identifier code.
SA=Sector Address within the sector being erased.
W A=Address of memory location to be written.
WD=Data to be written at location W A.
PA=Program Address, PD=Program Data
QA=Query Address, QD=Query Data.
3. Data is latched from the rising edge of WEf or CEf (whiche v er goes high first)
SRD=Data read from status register , see Table 5 for description of the status register bits .
4. Following the Read Configuration codes command, read operation access manufacturer, device codes, sector
lock/unlock codes, see chapter 4.2.
5. Either 40H or 10H command is recognized by the WSM as word write setup .
6. The sector unlock operation simultaneously clear all sector lock.
7. Read Query Command is read for CFI query information.
3.0 COMMAND DEFINITIONS
The flash memory has four read modes: read array, read
configuration, read status, read query, and two write
modes: prog ram, er ase. These read modes are acces-
sible independent of the VPP voltage. But write modes
are disable during VPP<VPPLK. Placing VPP on VPP1/
2 enables successful sector erase, word write and sec-
tor lock/unlock.
Device operations are selected by writing specific com-
mands into the CUI. Table 2 defines these commands .
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3.1 Read Array Command
Upon initial device power-up and after exit from reset
mode, the de vice def aults to read arr a y mode. This op-
eration is also initiated by writing the Read Array com-
mand. The device remains enabled for reads until an-
other command is written. Once the internal WSM has
started a sector erase, word write or sector lock con-
figuration the device will not recognize the Read Array
command until the WSM completes its operation unless
the WSM is suspended via a Sector Er ase Suspend or
Word Wr ite Suspend command. If RESET=VIL device
is in read Read Array command mode, this read opera-
tion no longer requires VPP. The Read Arr ay command
functions independently of the VPP voltage and RESET
can be VIH.
3.2 Read Configuration Codes Command
The configuration code operation is initiated by writing
the Read Configuration Codes command (90H). To re-
turn to read array mode, write the Read Array Command
(FFH). Following the command write, read cycles from
addresses shown in Table 3 retrieve the manuf acturer,
device, sector lock configuration codes and the protec-
tion register(see Table 3 f or configuration code values).
To terminate the operation, write another valid command.
Like the Read Array command, the Read Configuration
Codes command functions independently of the VPP
voltage and RESET can be VIH. Following the Read Con-
figuration Codes command, the information is shown:
Code Address Data
(A19-A0) (Q15-Q0)
Manufacturer Code 00000H 00C2H
Device Code(Top/Bottom) 00001H 88C2/88C3H
Sector Lock Configuration XX002H LocK
- Sector is unlocked Q0=0
- Sector is locked Q0=1
- Sector is locked-down Q1=1
Protection Register Lock 8 0 PR-LK
Protection Register 81-88 PR
Table 3. Configuration Code
3.3 Read Status Register Command
CUI writes read status command (70H). The status reg-
ister may be read to determine when a sector erase,
word write or lock-bit configuration is complete and
whether the operation completed successfully. (ref er to
table 5) It may be read at any time by writing the Read
Status Register command. After writing this command,
all subsequent read operations output data from the sta-
tus register until another v alid command is written. The
status register contents are latched on the falling edge
of CEf or OEf, whichever occurs last. CEf or OEf must
toggle to VIH before further reads to update the status
register latch. The Read Status Register command func-
tions independently of the VPP voltage . RESET can be
VIH.
3.4 Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 or SR.1 are set to
"1"s by the WSM and can only be reset by the Clear
Status Register command (50H). These bits indicate
various failure conditions (see Table 5). By allowing sys-
tem software to reset these bits, several operations (such
as cumulatively erasing multiple sectors or writing sev-
eral words in sequence) ma y be perf ormed. The status
register may be polled to determine if an error occurred
during the sequence.
To clear the status register, the Clear Status Register
command (50H) is written on CUI. It functions indepen-
dently of the applied VPP Voltage. RESET can be VIH.
This command is not functional during sector erase or
word write suspend modes.
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3.5 Sector Erase Command
Erase is executed one sector at a time and initiated by a
two-cycle command. A sector erase setup is first writ-
ten (20H), followed by a sector erase confirm (D0H). This
command sequence requires appropriate sequencing and
an address within the sector to be erased. Sector pre-
conditioning, erase, and verify are handled internally by
the WSM. After the two-cycle sector erase sequence is
written, the device automatically outputs status register
data when read (see Figure 8). The CPU can detect sec-
tor erase completion by analyzing the output data of the
status register bit SR.7.
When the sector erase is complete, status register bit
SR.5 should be checked. If a sector erase error is de-
tected, the status register should be cleared before sys-
tem software attempts corrective actions. The CUI re-
mains in read status register mode until a new com-
mand is issued.
This two-step command sequence of set-up followed by
execution ensures that sector contents are not acciden-
tally erased. An invalid sector Erase command sequence
will result in both status register bits SR.4 and SR.5
being set to "1". Also, reliable sector erasure can only
occur when 2.7V~3.6V and VPP=VPP1/2. In the absence
of this high voltage, sector contents are protected against
erasure. If sector erase is attempted while VPP<VPPLK
SR.3 and SR.5 will be set to "1". To successfully erase
the boot sector, the corresponding sector lock-bit m ust
be clear first. In parameter and sectors case, it must be
cleared the corresponding sector lock-bit. If sector erase
is attempted when the excepting above sector being
locked conditions, SR.1 and SR.5 will be set to "1". Sec-
tor erase is not functional.
3.6 W ord Write Command
Word write is executed by a two-cycle command se-
quence. Word write setup (standard 40H or alternate 10H)
is written, followed by a second write that specifies the
address and data. The WSM then takes over , controlling
the word write and write v erify algorithms internally. Af-
ter the word write sequence is written, the device auto-
matically outputs status register data when read (see
Figure 6). The CPU can detect the completion of the
word write event by analyzing the status register bit SR.7.
When word write is complete, status register bit SR.4
should be checked. If word write error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for "1"s that do not successfully write
to "0"s. The CUI remains in read status register mode
until it receives another command.
Reliable word writes can only occur when
VCCf=2.7V~3.6V and VPP=VPP1/2. If VPP is not within
acceptable limits , the WSM doesn't ex ecut the program
command. If word write is attempted while VPP<VPPLK,
status register bits SR.3 and SR.4 will be set to "1".
Successful word write requires for boot sector that WP
is VIH the corresponding sector lock-bit be cleared. In
parameter and main sectors case, it must be cleared
the corresponding sector lock-bit. If word write is at-
tempted when the excepting above sector being clocked
conditions, SR.1 and SR.4 will be set to "1". Word write
is not functional.
3.7 Sector Erase Suspend Command
The Sector Erase Suspend command (50H) allows sec-
tor-erase interruption to read or word write data in an-
other sector of memory . Once the sector erase process
starts, writing the Sector Erase Suspend command re-
quests that the WSM suspend the sector erase sequence
at a predetermined point in the algor ithm. The device
outputs status register data when read after the Sector
Erase Suspend command is written. P olling status reg-
ister bits SR.7 and SR.6 can determine when the sector
erase operation has been suspended (both will be set to
"1"). Specification tWHRH2/tEHRH2 defines the sector
erase suspend latency.
When Sector Erase Suspend command is written to the
CUI, if sector erase was finished, the device would be
placed read array mode. Therefore , after Sector Er ase
Suspend command is written to the CUI, Read Status
Register command (70H) has to be written to CUI, then
status register bit SR.6 should be checked if/when the
device is in suspend mode.
At this point, a Read Array command can be written to
read data from sectors other than that which is sus-
pended. A Word Write commands sequence can also be
issued during erase suspend to program data in other
sectors. Using the Word Write Suspend command (see
Section 4.9), a word write operation can also be sus-
pended. During a word write operation with sector erase
suspended, status register bit SR.7 will return to "0".
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However, SR.6 will remain "1" to indicate sector erase
suspend status.
The only other valid commands while sector erase is
suspended are Read Status Register , Read Configura-
tion, Read Query, Program Setup, Program Resume,
Sector Lock, Sector Unlock, Sector Lock-Down and sec-
tor erase Resume. After a Sector Erase Resume com-
mand is written to the flash memory, the WSM will con-
tinue the sector erase process. Status register bits SR.6
and SR.7 will automatically be cleared. After the Erase
Resume command is written, the device automatically
outputs status register data when read (see Figure 9).
VPP must remain at VPP1/2 while sector erase is sus-
pended. RESET must also remain at VIH (the same
RESET level used for sector erase). Sector cannot re-
sume until word write operations initiated during sector
erase suspend has completed.
If the time between writing the Sector Erase Resume
command and writing the Sector Erase Suspend com-
mand is shorter than 15ms and both commands are writ-
ten repeatedly, a longer time is required than standard
sector erase until the completion of the operation.
3.8 Word Write Suspend Command
The Word Write Suspend command allows word write
interruption to read data in other flash memory locations.
Once the word write process starts, writing the Word
Write Suspend command requests that the WSM sus-
pend the Word write sequence at a predetermined point
in the algorithm. The device continues to output status
register data when read after the Word Write Suspend
command is written. Polling status register bits SR.7 and
SR.2 can determine when the word write operation has
been suspended (both will be set to "1"). Specification
tWHRH1/tEHRH1 defines the word write suspend latency .
When Word Write Suspend command write to the CUI, if
word write was finished, the device places read array
mode. Theref ore, after Word Write Suspend command
write to the CUI, Read Status Register command (70H)
has to be written to CUI, then status register bit SR.2
should be checked for if/when the device is in suspend
mode.
At this point, a Read Array command can be written to
read data from locations other than that which is sus-
pended. The only other valid commands while word write
is suspended are Read Status Register Read Configura-
tion, Read Query and W ord Write Resume. After Word
Write Resume command is written to the flash memory ,
the WSM will continue the Word write process. Status
register bits SR.2 and SR.7 will automatically be cleared.
After the Word Write Resume command is written, the
device automatically outputs status register data when
read (see Figure 7). VPP must remain at VPP1/2 while
in word write suspend mode. RESET must also remain
at VIH (the same RESET le vel used f or w ord write).
If the time between writing the Word Write Resume com-
mand and writing the Word Write Suspend command is
short and both commands are written repeatedly , a longer
time is required than standard word write until the comple-
tion of the operation.
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3.9 Sector Lock/Unlock /Lockdown Command
3.9.1 Sector Locked State
The default status of all sectors upon power-up or reset
is locked. Any attempt on program or erase operations
will result in an error on bit SR.1 of a lock ed sector . The
status of a locked sector can be changed to unlocked or
lock-down using software commands. An unlocked sec-
tor can be locked by writing the sector lock command
sequence, 60H followed by 01H.
3.9.2 Sector Unlocked State
An unlocked sector can be programmed or erased. All
unlocked sector return to the locked state when the de-
vice is either reset or powered down. The status of an
unlocked sector can be changed to locked or locked-
down using software commands. A locked sector can
be unlocked by writing unlock command sequence, 60H
followed by D0H.
3.9.3 Sector Locked-Down State
Sectors which are locked-down are protected from pro-
gr am and erase operation; how ev er , the protection sta-
tus of these sectors cannot be changed using software
commands alone. Any sector locked or unlocked can be
locked-down by writing the lock-down command se-
quence, 60H f ollowed b y 2FH. When the de vice is reset
or powered down, the locked-down sectors will re vert to
the locked state.
The status of WP will determine the function of sector
lock-down and is summarized is followed:
WP Sector Lock-down Description
WP=0 - sectors are protected from program, erase,
and lock status changes
WP=1 - the sector lock-down function is disabled
- an individual lock-down sector can be un-
locked and relocked via software command.
Once WP goes low, sectors that previously
locked-down returns to lock-down state
regardless of any changes when WP was
high.
3.9.4 Read Sector Lock Status
The lock status of every sector can be read through
Read Configuration mode. To enter this mode, first com-
mand write 90H to the device. The subsequent reads at
sector address +00002 will output the lock status of this
sector . The loc k status can be read from the lowest tw o
output pins Q0 and Q1. Q0 indicates the sector lock/
unlock status and set by the lock command and cleared
by the unlock command. When entering lock-down, the
lock status is automatically set. Q1 indicates lock-down
status and is set by the lock-down command. It cannot
be further cleared by software, only by device reset or
power-down.
Sector Lock Configuration Table
Lock Status Data
Sector is unlocked Q0=0
Sector is locked Q0=1
Sector is locked-down Q1=1
In addition, sector lock-down is cleared only when the
device is reset or powered down.
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3.9.5 Sector Locking while Erase Suspend
The sector lock status can be performed during an erase
suspend by using standard locking command sequences
to unlock, lock, or lock-do wn a sector.
In order to change sector locking during an erase opera-
tion, the write erase suspend command (B0H) is placed
first; then check the status register until it is shown that
the actual erase operation has been suspended. Subse-
quent writing the desired lock command sequence to a
sector and the lock status will be changed. When com-
pleting any desired lock, read or program operation, re-
sume the erase operation with the Erase Resume Com-
mand (D0H).
If a sector is locked or locked-down during the same
3.9.6 Status Register Error Checking
The operation of locking system for this device can be
used the term "state (X,Y,Z)" to specify locking status,
where X=value of WP, Y=bit Q1 of the sector lock status
register , and Z=bit Q0 of the sector loc k status register.
Q0 indicates if a sector is locked (1) or unlocked (0). Q1
indicates if a sector has been locked-down(1) or not (0).
Current State Erase/Prog. Lock Command Input Result (Next State)
(X, Y, Z)= Operation if (X, Y, Z)=
WP Q1 Q0 Name Enable ? Lock Unlock Lock-Down
0 0 0 Unlocked Yes (001) Unchanged (011)
0 0 1 Locked (default) N o Unchanged (000) (011)
0 1 1 Locked-Down No Unchanged Unchanged Unchanged
1 0 0 Unlocked Yes (101) Unchanged (111)
1 0 1 Locked No Unchanged (100) (111)
1 1 0 Lock-Down Disabled Yes (111) Unchanged (111)
1 1 1 Lock-Down Disabled N o Unchanged (110) Unchanged
Table 4. Sector Locking State Transitions
sector is being placed in erase suspend, the locking sta-
tus bits will be changed immediately, but when the erase
is resumed, the erase operation will complete.
Locking operation cannot be performed during a program
suspend.
Note:
At power-up or device reset, all sectors def ault to loc ked state (001) (if WP=0).
Holding WP=0 is the recommended default.
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Table 5. Status Register Definition
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = SECT OR ERASE SUSPEND STATUS (SESS)
1 = Sector ERASE Suspended
0 = Sector Erase in Progress/Completed
SR.5 = ERASE STATUS (ES)
1 = Error in Programming
0 = Successful Sector Erase or Clear Sector Lock-
Bits
SR.4 = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Programming
SR.3 = VPP STATUS (VPPS)
1 = VPP Lo w Detect, Operation Abort
0 = VPP OK
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
SR.1 = SECTOR LOCK STATUS (SLS)
1 =Program/Erase attempted an a locked sector;
operation aborted
0 = No operation to locked sectors
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
(R)
NOTES:
Check WSM bit first to determine word program or sec-
tor Erase completion, before checking Program or Erase
Status bits.
When Sector Erase Suspend is issued, WSM halts e x-
ecution and sets both WSMS and SESS bits to "1". SESS
bit remains set to "1" until an Sector Erase Resume
command is issued.
When this bit (SR.5) is set to "1", it means WSM is
unable to verify successful sector erasure.
When this bit is set to "1", WSM has attempted but failed
to program a word.
The WSM interrogates VPP level only after the Program
or Erase command sequences have been entered and
informs the system if VPP has not been switched on.
SR.3 bit is not guaranteed to report accurate feedback
between VPPLK and VPP1 min.
When program suspend is issued, WSM halts the ex-
ecution and sets both WSMS and PSS bits to "1". SR.2
remains set to "1" until a Program Resume command is
issued.
If a program or erase operation is attempted to one of
the locked sectors, this bit is set by the WSM. The op-
eration specified is aborted and the device is returned to
read status mode.
SR. 0 is reserved for future use and should be masked
out when polling the status register .
WSMS SESS ES PS VPPS PSS SLS R
76543 2 1 0
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4.0 128-Bit Protection Register
The 128 bits of protection register are divided into two
64-bit segments. One of the segments is programmed
at MXIC side with unique 64-bit number; where changes
are f orbidden. The other segment is left empty for cus-
tomer to program. Once the customer segment is pro-
grammed, it can be locked to prevent further reprogram-
ming.
4.1 Protection Register Read & Programming
The protection register is read in the configuration read
mode, which follows the stated Command Bus Defini-
tions.
The device is switched to this read mode by writing the
Read Configuration command (90H). Once in this mode,
read cycles from addresses shown in Table 6 will re-
trieve the specified information. To return to read array
mode, write the Read Array Command (FFH).
Two-cycle Protection Program Command is used to pro-
gram protection register bits . The 64-bit n umber is pro-
grammed 16 bits at a time. First, write C0H Protection
Program Setup command. The ne xt write to the de vice
will latch in address and data and program the specified
location. The allowable address are also shown in Table
6. Refer to Figure 11 for the Protection Register Pro-
gramming Flowchart.
Any attempt to address Protection Program command
onto undefined protection register address space will
result in a Status Register error (SR.4 set to "1"). In
addition, attempting to program to a previously locked
protection register segment will result in a status regis-
ter error (SR.4=1, SR.1=1).
Word User A7 A6 A5 A4 A3 A2 A1 A0
Lock Both 1 0 0 0 0 0 0 0
0 Factory 1 0 0 0 0 0 0 1
1 Factory 1 0 0 0 0 0 1 0
2 Factory 1 0 0 0 0 0 1 1
3 Factory 1 0 0 0 0 1 0 0
4 Customer 1 0 0 0 0 1 0 1
5 Customer 1 0 0 0 0 1 1 0
6 Customer 1 0 0 0 0 1 1 1
7 Customer 1 0 0 0 1 0 0 0
Table 6. Word-Wide Protection Register Addressing
4.2 Protection Register Locking
The user-programmable segment of the protection reg-
ister is lockable by programming Bit 1 of the PR-Lock
location to 0. Bit 0 of this location is programmed to 0 at
MXIC to protect the unique device number. This bit is
set using the protection program command to program
"FFFD" to PR-LOCK location. After these bits have been
programmed, no fur ther changes can be made to the
value stored in the protection register. Protection Pro-
gram command to a locked section will result in a status
register error (Program Error bit SR.4 and Lock Error bit
SR.1 will be set to 1). Protection register lockout state is
not reversible.
Protection Register Purpose
Bit Address
88H~85H 4 words User Program
Register
84H~81H 4 words Factory Program
Register
80H(Bit0 & Bit1) Protection Register Lock
Table 7. Protection Register Memory Map
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AC Input/Output Test Conditions
Figure 1. T ransient Input/Output Reference W aveform
TEST POINTS VCCQ/2 Output
Note:AC test inputs are driven at VCCQ/2 for a Logic "1" and 0.0V for a Logic "0".
VCCQ
0.0
Input VCCQ/2
Figure 2. SWITCHING TEST CIRCUITS TEST SPECIFICA TIONS
Test Condition 70 9 0 Unit
Output Load 1 TTL gate
Output Load Capacitance, CL 30 1 00 pF
(including jig capacitance)
Input Rise and F all Times 5 ns
Input Pulse Levels 0.0-3.0 V
Input timing measurement 1.5 V
reference levels
Output timing measurement 1.5 V
reference levels
DEVICE UNDER
TEST
DIODES=IN3064
OR EQUIVALENT
CL 6.2K ohm
2.7K ohm 3.3V
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AC Characteristic -- Read Only Operation (1)
-70 -90
Sym. Parameter Notes Min. Max. Min. Max. Unit
tAVAV Read Cycle Time 7 0 90 ns
tA VQV Address to Output Delay 7 0 9 0 ns
tELQV CEf to Output Delay 2 70 90 ns
tGLQV OEf to Output Delay 2 20 3 0 ns
tPHQV RESET to Output Delay 1 5 0 1 5 0 ns
tELQX CEf to Output in Low Z 3 0 0 ns
tGLQX OEf to Output in Low Z 3 0 0 n s
tEHQZ CEf to Output in High Z 3 20 20 ns
tGHQZ OEf to Output in High Z 3 2 0 20 n s
tO H Output Hold from Address, 3 0 0 ns
CEf, or OEf Change,
Whichever Occurs First
Notes:
1. See AC W aveform: Read Operations at Figure 3.
2. OEf may be dela y ed up to tELQV-tGLQV after the falling edge of CEf without impact on tELQV.
3. Sampled, but not 100% tested.
4. See test Configuration.
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Figure 3. READ-ONLY OPERATION AC WAVEFORM
tEHQZ
tAVAV
tGHQZ
tGLQV
tELQV
tELQX
tAVQV
tPHQV
tGLQX tOH
High Z
High Z Valid Output
Address Stable
Device and
Address Selection Data
Valid Standby
VIH
VIL
Addresses(A)
VIH
VIL
CEf (E)
VIH
VIL
OEf (G)
VIH
VIL
WEf (W)
VIH
VIL
RESET (P)
VOH
VOL
DATA
(D/Q)
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AC Characteristic -- Write Operation
Notes:
1. Write timing characteristics during erase suspend are the same as during write-only operations.
2. Ref er to Table 4 f or v alid AIN or DIN.
3. Sampled, not 100% tested.
4. Write pulse width (tWP) is defined from CEf or WEf going lo w (whichev er goes low last) to CEf or WEf going high
(whichever goes high first). Hence, tWP=tWL WH=tELEH=tWLEH=tEL WH. Similarly , Write pulse width high (tWPH)
is defined from CEf or WEf going high (whichever goes high first) to CEf or WEf going low (whichever goes low
first). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL.
5. See Test Configuration.
-70 -90
Sym. Parameter Note Min. Min. Unit
tPHWL/tPHEL RESET High Recovery to WEf(CEf) Going Low 150 1 50 ns
tELWL/tWLEL CEf(WEf) Setup to WEf(CEf) Going Low 0 0 ns
tWLWH/tELEH WEf(CEf) Pulse Width 4 4 5 6 0 ns
tDVWH/tDVEH Data Setup to WEf(CEf) Going High 2 4 0 5 0 ns
tA VWH/tA VEH Address Setup to WEf(CEf) Going High 2 5 0 60 ns
tWHEH/tEHWH CEf(WEf) Hold Time from WEf(CEf) High 0 0 ns
tWHDX/tEHDX Data Hold Time from WEf(CEf) High 2 0 0 ns
tWHAX/tEHAX Address Hold Time from WEf(CEf) High 2 0 0 ns
tWHWL/tEHEL WEf(CEf) Pulse Width High 4 2 5 3 0 ns
tVPWH/tVPEH VPP Setup to WEf(CEf) Going High 3 2 0 0 2 00 ns
tQVVL VPP Hold from V alid SRD 3 0 0 ns
tBHWH/tBHEH WP Setup to WEf(CEf)Going High 3 0 0 ns
tQVBL WP Hold from V alid SRD 3 0 0 ns
t WH G L WEf High to OEf Going Low 3 30 3 0 ns
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Figure 4. WRITE AND ERASE OPERATION AC WAVEFORM
Notes:
1. CEf must be toggled low when reading Status Register Data. WEf must be inactive (high) when reading Status
Register Data.
A.VCCf Power-Up and Standby .
B.Write Program or Erase Setup Command.
C.Write V alid Address and Data (for Program) or Erase Confirm Command.
D .Automated Program or Erase Delay .
E.Read Status Register Data (SRD): reflects completed program/erase operation.
F.Write Read Array Command.
tVPWH
(tVPEH) tQVVL
tWHWL
(tEHEL) tWHGL
tPHWL
(tPHEL)
(Note 1)
(Note 1)
tELEH
(tWLWH)
tWHDX
(tEHDX)
tWHEH
(tEHWH)
tELWL
(tWLEL)
tAVWH
(tAVEH) tWHAX
(tEHAX)
tDVWH
(tEVEH)
tBHWH
(tBHEH) tQVBL
High Z
DIN
Address (A)
AB CD E F
VIH
VIL
OEf(G)
VIH
VIL
VIH
VIL
CEf(WEf)[E(W)]
VIH
Disable
Enable VIL
WEf,(CEf)[W(E)]
VIH
VIL
DATA[D/Q]
VOH
VOL
RESET[P]
VIH
VIL
VPPH1
VPPH2
VPPLK
VIL
WP
VPP[V]
DIN
AIN AIN
DIN
Valid
SRD
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Erase and Program Timing (1)
Vpp 1.65V-3.6V 11.4V-12.6V
Symbol Parameter Note Typ(1) Max Typ(1) Max Unit
tBWPB 4-KW Parameter Sector 2,3 0.10 0.30 0.03 0.12 s
Word Program Time
tBWMB 32-KW Main Sector 2,3 0.8 2.4 0.24 1 s
Word Program Time
tWHQV1/ Word Program Time 2,3 12 20 0 8 185 us
tEHQV1
tWHQV2/ 4-KW Parameter Sector 2,3 0.5 4 0.4 4.0 s
tEHQV2 Erase Time
tWHQV3/ 32-KW Main Sector 2,3 1 5 0.6 5 s
tEHQV3 Erase Time
tWHRH1/ Program Suspend Latency 3 15 2 0 15 20 us
tEHRH1
tWHRH2/ Erase Suspend Latency 3 1 5 20 1 5 2 0 us
tEHRH2
Notes:
1. Typical values measured at TA=+25°C and nominal voltage.
2. Excludes external system-level overhead.
3. Sampled, but not 100% tested.
26
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REV. 0.3, NOV. 22, 2002
AC Characteristic -- Under Reset Operation
Sym. Parameter VCCf=2.7V~3.6V Unit Notes
Min. Max.
tPLPH RESET Low to Reset during Read 100 ns 1,3
(If RESET is tied to VCCf, this specification is not applicable)
tPLRH1 RESET Low to Reset during Sector Erase 2 2 us 1 ,4
tPLRH2 RESET Low to Reset during Program 1 2 us 1,4
Notes:
1. See Section 3.4 for a full description of these conditions.
2. If tPLPH is < 100ns the device may still reset but this is not guaranteed.
3. If RESET is asser ted while a sector erase or word program operation is not executing, the reset will complete
within 100ns.
4. Sampled, but not 100% tested.
Figure 5. RESET WAVEFORM
tPLPH
tPLRH Abort
Complete
tPHQV
tPHWL
tPHEL
tPHQV
tPHWL
tPHEL
VIH
VIL
(A) Reset during Read Mode
tPLPH
VIH
VIL
(B) Reset during Program or Sector Erase, tPLPH < tPLRH
tPLRH
Abort
Complete Deep
Power-
Down tPHQV
tPHWL
tPHEL
tPLPH
VIH
VIL
RESET (P)
(C) Reset Program or Sector Erase, tPLPH > tPLRH
RESET (P)
RESET (P)
27
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MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
DC Characteristics
VCCf 2.7V-3.6V
Sym. Parameter VCCQ 2.7V-3.6V Unit Test Conditions
Note Typ. Max.
ILI Input Load Current 1,2 ± 1 u A VCCf=VCCf Max. ; VCCQ=VCCQ Max.
VIN=VCCQ or GND
ILO Output Leakage 1,2 0.2 ± 10 uA VCCf=VCCf Max. ; VCCQ=VCCQ Max.
Current VIN=VCCQ or GND
ICCS VCC Standby Current 1 7 15 uA VCCf=VCCf Max. ; CEf=RESET=VCCQ
or during Program/Erase Suspend
WP=VCCQ or GND
ICCD VCC Power-Down 1,2 7 15 uA VCCf=VCCf Max. ; VCCQ=VCCQ Max
Current VIN=VCCQ or GND
RESET=GND±0.2V
ICCR VCC Read Current 1,2,3 9 18 mA VCCf=VCCf Max. ; VCCQ=VCCQ Max
OEf=VIH, CEf=VIL, f=5MHz,
IOUT=0mA, Inputs=VIL or VIH
IPPD VPP Deep Power- 1 0.2 5 uA RESET=GND±0.2V
Down Current VPP < VCCf
IPPR VPP Read Current 1,4 2 ±15 uA VPP < VCCf
50 200 uA VPP > VCCf
ICCW+ VCC+VPP Program 1 ,4 18 5 5 mA VPP=VPP1, Program in Progress
IPPW Current 10 30 mA VPP=VPP2(12V), Program in Progress
ICCE+ VCC+VPP Erase 1 , 4 21 45 mA VPP=VPP1, Erase in Progress
IPPE Current 16 45 mA VPP=VPP2(12V), Erase in Progress
ICCES VCC Program 1,4 7 1 5 uA CEf=VCCf,
o r or Erase Suspend Program or Erase Suspend in Progress
ICCWS Current
VIL Input Low V oltage -0.4 VCCf*0.22V V
VIH Input High V oltage 2.0 VCCQ+0.3V V
V OL Output Low V oltage -0.1 0.1 V VCCf=VCCf Min, VCCQ=VCCQ Min
IOL=100uA
V O H Output High V oltage VCCQ V VCCf=VCCf Min, VCCQ=VCCQ Min
-0.1V IOH=-100uA
VPPLK VPP Lock-Out Voltage 6 1. 0 V Complete Write Protection
VPP1 VPP during Program/ 6 1.65 3.6 V
VPP2 Erase Operations 6 11.4 12.6 V
VLKO VCC Prog/Erase 1.5 V
Lock V oltage
VLK O2 VCCQ Prog/Erase 1.2 V
Lock V oltage
28
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MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
Notes:
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCCf , TA=+25°C.
2. The test conditions VCCf Max, VCCQ Max, VCCf Min, and VCCQ Min refer to the maximum or minimum VCCf or
VCCQ voltage listed at the top of each column.
3. P ower Sa vings (Mode) reduces ICCR to approximately standb y lev els in static operation (CMOS inputs).
4. Sampled, but not 100% tested.
5. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is
sum of ICCES and ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS and
ICCR.
6. Erase and Program are inhibited when VPP<VPPLK.
29
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MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
Figure 6. Automated Word Programming Flowchar t
Bus Command Comments
Operation
Write Program Data=40H
Setup
Write Program Data=Data to Program
Addr=Location to Program
Read Status Register Data Toggle
CEf or OEf to Update
Status Register Data
Standby Check SR.7
1=WSM Ready
0=WSM Busy
Repeat for subsequent programming operations.
SR full status check can be done after each program
or after a sequence of program operations.
Write FFH after the last program operation to reset
device to read array mode.
Bus Command Comments
Operation
Standby Check SR.3
1=VPP Low Detect
Standby Check SR.4
1=VPP Program Error
Standby Check SR.1
1=Attempted Program to
Locked Sector-Program
Aborted
SR.3 MUST be cleared, if set during a program at-
tempt, before further attempts are allowed by the Write
State Machine.
SR.4, SR.3, and SR.1 are only cleared by the Clear
Status Register Command, in cases where multiple
bytes are programmed before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery .
Start
Write 40H
Full Status
Check if Desired
Read Status Register
Program Address/Data
No
Yes
SR.7=1 ?
Program Ccomplete
Read Status Register
Data(See Above)
FULL STATUS CHECK PROCEDURE
Program Successful
SR.3=
0
0
0
VPP Range Error
1
Programming Error
1
Attempted Program to
Locked Sector- Aborted
1
SR.4=
SR.1=
30
P/N:PM0954
MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
Figure 7. Program Suspend/Resume Flowchart
Bus Command Comments
Operation
Write Program Data=B0H
Suspend Addr=X
Write Read Status Data=70H
Addr=X
Read Status Register Data T oggle
CEf or OEf to Update
Status Register Data
Addr=X
Standby Check SR.7
1=WSM Ready
0=WSM Busy
Stanby Check SR.2
1=Program Suspended
0=Program Completed
Write Read Array Data=FFH
Addr=X
Read Read array data from
sector other than the one
being programmed.
Write Program Data=D0H
Resume Addr=X
Start
Program Write Resumed
Program Completed
Write B0H
Write 70H
Read
Status Register
0
0
1
Write FFH
Read Array Data
Write D0H
SR.7=
1
SR.2=
Yes
No
Done Reading
Read Array Data
Write FFH
31
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MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
Figure 8. Automated Sector Erase Flowchart
Bus Command Comments
Operation
Write Erase Setup Data=20H
Addr=Within Sector to Be
Erased
Write Erase Data=D0H
Confirm Addr=Within Sector to Be
Erased
Read Status Register Data Toggle
CEf or OEf to Update
Status Register Data
Standby Check SR.7
1=WSM Ready
0=WSM Busy
Repeat for subsequent sector erasures.
Full status check can be done after each sector erase
or after a sequence of sector erasures.
Write FFH after the last write operation to reset device
to read array mode.
Bus Command Comments
Operation
Standby Check SR.3
1=VPP Low Detect
Standby Check SR.4, 5
Both 1=Command
Sequence Error
Standby Check SR.5
1=Sector Erase Error
Standby Check SR.1
1=Attempted Erase of
Locked Sector- Erase
Aborted
SR.1 and SR.3 MUST be cleared, if set during an erase
attempt, before further attempts are allowed by the
Write State Machine.
SR.1,3,4,5 are only cleared by the Clear Status Reg-
ister Command, in cases where multiple bytes are
erased before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery .
Start
Write 20H
Write D0H and
Sector Address
Full Status Check if Desired
Sector Erase Complete
Read
Status Register Suspend
Erase Loop
0
No
Yes
1
SR.7= Suspend Erase
Read Status Register
Data(See Above)
FULL STATUS CHECK PROCEDURE
Sector Erase Successful
SR.3=
0
0
0
0
VPP Range Error
1
Command Sequence Error
1
Sector Erase Error
1
SR.4,5=
SR.5=
Attempted Erase of Locked
Sector - Aborted
1
SR.1=
32
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MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
Figure 9. Erase Suspend/Resume Flowchart
Bus Command Comments
Operation
Write Erase Data=B0H
Suspend Addr=X
Write Read Status Data=70H
Addr=X
Read Status Register Data T oggle
CEf or OEf to Update
Status Register Data
Addr=X
Standby Check SR.7
1=WSM Ready
0=WSM Busy
Stanby Check SR.6
1=Erase Suspended
0=Erase Completed
Write Read Array Data=FFH
Addr=X
Read Read array data from
sector other than the one
being erased.
Write Erase Data=D0H
Resume Addr=X
Start
Erase Write Resumed
Erase Completed
Write B0H
Write 70H
Read
Status Register
0
0
1
Write FFH
Read Array Data
Write D0H
SR.7=
1
SR.6=
Yes
No
Done Reading
Read Array Data
Write FFH
33
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MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
Figure 10. Locking Operations Flowchart Bus Command Comments
Operation
Write Config. Setup Data=60H
Addr=X
Write Lock, unlock Data=01H (Sector Lock)
or Lockdown D0H(Sector Unlock)
2FH(Sector Lockdown)
Addr=Within sector to lock
Write Read Status Data=70H
(Optional) Register Addr=X
Read Status Register Register
(Optional) Addr=X
Stanby Check Status Register
(Optional) 80H=no error
30H=Lock Command
Sequence Error
Write Read Data=90H
(Optional) Configuration Addr=X
Read Sector Lock Sector Lock Status Data
(Optional) Status Addr=Second addr of
sector
Stanby Confirm Locking Change
on Q1, Q0 (See Sector
Locking State Table f or
valid combinations.)
Start
Locking Change
Complete
Lock Command
Sequence Error
Write 60H
(Configuration Setup)
Write
01H, D0H, or 2FH
Write 70H
(Read Status Register)
Read Status Register
1,1
0,0
Write 90H
(Read Configuration)
Read Sector Lock Status
SR.4, SR.5=
Yes
No
Locking Change
Confirmed ?
34
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MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
Figure 11. Protection Register Programming Flowchart
Start
Write C0H
(Protection Reg. Program Setup)
Full Status
Check if Desired
Read Status Register
Write Protect. Register
Address/Data
No
Yes
SR.7=1 ?
Program Ccomplete
Read Status Register
Data(See Above)
FULL STATUS CHECK PROCEDURE
Program Successful
SR.3, SR.4= VPP Range Error
1,1
Protection Register
programming Error
0,1
Attempted Program to
Locked Register Aborted
1,1
SR.1, SR.4=
SR.1, SR.4=
Bus Command Comments
Operation
Write Protection Data=C0H
Program
Setup
Write Protection Data=Data to Program
Program Addr=Location to Program
Read Status Register Data Toggle
CEf or OEf to Update
Status Register Data
Standby Check SR.7
1=WSM Ready
0=WSM Busy
Protection Program operations can only be addressed
within the protection register address space. Addresses
outside the defined space will return an error.
Repeat for subsequent programming operations.
SR Full Status Check can be done after each program
or after a sequence of program operations.
Write FFH after the last operation to reset device to
read array mode.
Bus Command Comments
Operation
Standby SR.1, SR.3, SR.4
0 1 1 VPP Low
Standby 0 0 1 Prot. Reg.
Prog. Error
Stanby 1 0 1 Register
Locked:
Aborted
SR.3 MUST be cleared, if set during a program at-
tempt, before further attempts are allowed by the Write
State Machine.
SR.1,3,4 are only cleared by the Clear Status Regis-
ter Command, in cases of multiple protection register
program operations before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery .
35
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REV. 0.3, NOV. 22, 2002
5.0 VPP Program and Erase Voltage
MX69F1602/1604C3T/B product provides in-system pro-
gramming and erase in the 1.65V~3.6V of VPP range. In
addition, VPP pin on 12V provides f ast production pro-
gramming.
5.1 VPP Fast manufacturing Programming
When VPP is between 1.65V and 3.6V, all program and
erase current is drawn through the VCCf pin. If VPP is
driven by a logic signal, VIH=1.65V. That is, VPP must
remain above 1.65V to perform in-system flash update/
modifications. When VPP is connected to a 12V power
supply, the de vice draws program and erase current di-
rectly from the VPP pin.
5.2 Protection Under VPP<VPPLK
VPP can off additional hardware write protection. The
VPP programming voltage can be kept low for the abso-
lute hardware protection of all sector in the flash device.
As VPP is below VPPLK, any program or er ase oper a-
tion will result in a error, prompting the corresponding
status register bit (SR.3) to be set.
36
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REV. 0.3, NOV. 22, 2002
6.0 QUERY COMMAND AND COMMON FLASH
INTERFACE (CFI) MODE
MX69F1602/1604C3T/B is capable of operating in the
CFI mode. This mode allows the host system to deter-
mine the manufacturer of the device such as operating
parameters and configuration. Two commands are re-
quired in CFI mode. Query command of CFI mode is
placed first, then the Reset command exits CFI mode.
These are described in Table 2.
The single cycle Query command is valid only when the
device is in the Read mode, including Erase Suspend,
Program Suspend, Standby mode, and Read ID mode;
however, it is ignored otherwise.
The Reset command exits from the CFI mode to the
Read mode, or Erase Suspend mode, Program Suspend
or read ID mode. The command is valid only when the
device is in the CFI mode.
Table 8-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Description Address h Data h
Query-unique ASCII string "QRY" 1 0 0051
11 0052
12 0059
Primary vendor command set and control interface ID code 1 3 0003
14 0000
Address for primary algorithm extended query table 1 5 0035
16 0000
Alternate vendor command set and control interface ID code (none) 1 7 0000
18 0000
Address for secondary algorithm extended query table (none) 19 0000
1A 0000
Table 8-2. CFI Mode: System Interface Data Values
Description Address h Data h
VCC supply, minimum (2.7V) 1B 0027
VCC supply, maximum (3.6V) 1 C 0036
VPP supply, minimum (11.4V) 1D 00B4
VPP supply, maximum (12.6V) 1E 00C6
Typical timeout for single word write (2N us) 1F 0005
Typical timeout for maximum size buffer write (2N us) 2 0 0000
Typical timeout for individual sector erase (2N ms) 2 1 000A
Typical timeout for full chip erase (2N ms) (not supported) 2 2 0000
Maximum timeout for single word write times (2N X Typ) 23 0004
Maximum timeout for maximum size buffer write times (2N X Typ) 24 0000
Maximum timeout for individual sector erase times (2N X Typ) 2 5 0003
Maximum timeout for full chip erase times (not supported) 2 6 0000
37
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REV. 0.3, NOV. 22, 2002
Table 8-3. CFI Mode: Device Geometry Data Values
Description Address h Data h
Device size (2n bytes) 27 0015
Flash device interface code (asynchronous x16) 2 8 0001
29 0000
Maximum number of bytes in write buffer=2n (not supported) 2A 0000
2B 0000
Number of erase sector regions within device (one or more continuous 2 C 0002
same-size erase sectors at one sector region) TB
Erase Sector Region 1 information 2 D 1E 07
[2E,2D] = number of same-size sectors in region 1-1 2E 0 0 0 0
[30, 2F] = region erase sector size in multiples of 256-bytes 2 F 00 2 0
30 01 00
TB
Erase Sector Region 2 information 3 1 07 1E
[32,31] = number of same-size sectors in region 2-1 3 2 0 0 0 0
[34,33] = region erase sector size in multiples of 256-bytes 33 20 0 0
34 00 01
38
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REV. 0.3, NOV. 22, 2002
Table 8-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
Description Address h Data h
Query-unique ASCII string "PRI" 3 5 0050
36 0052
37 0049
Major version number, ASCII 3 8 0031
Minor version number, ASCII 3 9 0030
Optional Feature & Command Support 3A 66
bit 0 Chip Erase Supported (1=yes, 0=no) 3B 0 0
bit 1 Suspend Erase Supported (1=yes, 0=no) 3 C 0 0
bit 2 Suspend Program Supported (1=yes, 0=no) 3 D 0 0
bit 3 Lock/Unlock Supported (1=yes, 0=no)
bit 4 Queued Erase Supported (1=yes, 0=no)
bit 5 Instant individual sector locking supported (1=yes, 0=no)
bit 6 Protection bits supported (1=yes, 0=no)
bit 7 Page mode read supported (1=yes, 0=no)
bit 8 Synchronous read support (1=yes, 0=no)
bits 9-31 revered for future use; undefined bits are "0"
Supported functions after suspend 3E 01
bit 0 Program supported after erase suspend (1=yes, 0=no)
bit 1-7 Reserved for other supported options; undefined bits are "0"
Sector Lock Status 3F 03
Define which bits in the sector status Register section of the Query are 4 0 00
implemented.
bit 0 sector Lock Status Register Lock/Unlock bit (bit 0) active; (1=yes, 0=no)
bit 1 sector Lock Status Register Lock-Down bit (bit 1) active; (1=yes, 0=no)
Bits 2-15 reserved for future use. Undefined bits are "0".
VCC Logic Supply Optimum Program/Erase Voltage (highest performance) 41 33
bits 7-4 BCD value in volts
bits 3-0 BCD value in 100mV
VPP Supply Optimum Program/Erase Voltage 4 2 C 0
bits 7-4 HEX value in volts
bits 3-0 BCD value in 100mV
Number of protection register in JEDEC ID space "00" indicates that 43 0 1
256 protection bytes are available
Protection Description
bit 0-7 = Lock/bytes JEDEC-plane physical low address 44 80
bit 8-15 = Lock/bytes JEDEC-plane physical high address 4 5 0 0
bit 16-23 = "n" such that 2n=factory pre-programmed bytes 46 0 3
bit 24-31 = "n" such that 2n=user programmed bytes 4 7 0 3
39
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REV. 0.3, NOV. 22, 2002
2. SRAM--DESCRIPTION
The SRAM of mixed multi chip memory is a high perfor-
mance, very low power CMOS Static Random Access
Memory.
The SRAM of MX69F1602/1604C3T/B is organized as
131,072 words by 16 bits / 262,144 words by 16 bits
and operates from a very low range of 2.7V to 3.6V sup-
ply voltage.
Advanced CMOS technology and circuit techniques pro-
vide both high speed and low power features with a typi-
cal CMOS standby current of 1uA and maximum ac-
cess time of 70ns in 3V operation.
Easy memory expansion is provided by an active HIGH
chip enable 2(CE2s) active LOW chip enable (CE1s)
and active LOW output enable (OEs) and three-state
output drivers.
The SRAM of MX69F1602/1604C3T/B has an autmatic
power down feature, reducing the power consumption
significantly when chip is deselected.
Parameter Parameter Test Conditions MIN. TYP. MAX. Units
Name (1)
VIL Guaranteed Input Low -0.3 - 0.6 V
V oltage (2)
VIH Guaranteed Input High 2.2 - Vcc+0.3 V
V oltage (2)
IIL Input Leakage Current Vccs=Max, VIN=0V to Vcc - - ±1uA
IOL Output Leakage Current Vccs=Max, CE1s=VIH or CE2s=VIL - - ±1uA
VI/O=0V to Vcc or LB=UB=VIH or OEs=VIH,
VI/O=0V to Vcc
V OL Output Low Voltage Vccs=Max, IOL=2mA - - 0.4 V
V O H Output High V oltage Vccs=Min, IOH=-0.5mA 2.4 - - V
ICC1 Active supply current LBs and UBs<0.2V, CE1s<0.2V f=10MHz - 5 0 70 mA
(AC, MOS level) CE2s>(Vccs)-0.2V other
inputs<0.2V or >(Vccs)-0.2V f=1MHz - 7 15 mA
Output-open (duty 100%)
ICC2 Active supply current LBs and UBs=VIL, CE1s=VIL f=10MHz - 50 70 mA
(AC , TTL lev el) CE2s=VIH other inputs=VIH or VIL
Output-open (duty 100%) f=1MHz - 7 15 mA
ICC3 Standby Power Suppply Vcc=max, CE1s=VIH or CE2s=VIL - 1 40 uA
Current (AC, CMOS) IDQ=0mA
ICC4 Standby supply current 1)CE2s=VIL, Other inputs=0 - Vccs - - 1 . 0 mA
(A C, TTL) 2)CE1s=VIH, CE2s=VIH or VIL, Other
inputs=0 - Vccs
3) LBs and UBs=VIH, CE1s=VIH or VIL
CE2s=VIH or VIL, Other inputs=0 Vccs
1.Typical characteristics are at TA=25°C and Vcc=3.0V
2.These are absolute values with respect to device ground and all overshoots due to system or tester notice are
included.
3.Fmax=1/tRC.
DC ELECTRICAL CHARACTERISTICS
40
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MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
Limits
Symbol Parameter Test Conditions MIN. TYP. MAX. Units
S-Vcc(PD) P ower down supply voltage 2.0 V
VI(S-BC) Byte control input LBs, UBs 2.0 V
VI(CE1s) Chip select input CE1s 2 .0 V
VI(CE2s) Chip select input CE2s 0. 2 V
+70 ~ +85°C- - 30uA
ICC(PD) Power Down supply current VCCs=3.0V +40 ~ +70°C- - 15uA
CE2s<0.2V +25 ~ +40°C- 1 3 uA
other inputs=0~3V -40 ~ +25°C - 0.3 1 uA
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
(2) TIMING REQUIREMENTS
(3) TIMING DIAGRAM
Limits
Symbol Parameter Test Conditions MIN. TYP. MAX. Units
tsu(PD) P ower down set up time 0 ns
trec(PD) P ower down recovery time 5 ms
LBs, UBs control mode
tsu(PD)
LBs, UBs > (VCCs)-0.2V
2.7V
2.2V 2.2V
trec(PD)
S-Vcc
LBs
UBs
CE1s
2.7V
CE1s control mode
tsu(PD)
CE1s > (VCCs)-0.2V
2.7V
2.2V 2.2V
trec(PD)
VCCs
2.7V
CE2s
CE2s control mode
CE2s < 0.2V
2.7V
0.2V 0.2V
tsu(PD) trec(PD)
VCCs
2.7V
41
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MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
AC TEST LOADS AND WAVEFORMS AC TEST LOADS AND WAVEFORMS
Input Pulse Levels 3.0/0V
Input Rise and F all Times 5n s
Input and Output Timing
Reference Level 1.5V
Supply Voltage 2.7V~3.6V
DQ
CL Including scope and
jig capacitance
FIGURE 1. Output load
Output loads: CL=30pF
CL=5pF (for ten. tdis)
42
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REV. 0.3, NOV. 22, 2002
AC ELECTRICAL CHARACTERISTICS
READ CYCLE
Limits SRAM
Symbol Parameter 70 8 5 Units
MIN. MAX. MIN. MAX.
t C R Read cycle time 70 85 ns
ta(A) Address access time 70 85 ns
ta(CE1) Chip select 1 access time 70 85 ns
ta(CE2) Chip select 2 access time 70 85 ns
ta(LB) Lower Byte control access time 70 85 ns
ta(UB) Upper Byte control access time 70 85 ns
ta(OE) Output enable access time 4 5 4 5 ns
tdis(CE1) Output disable time after CE1s high 3 0 3 0 ns
tdis(CE2) Output disable time after CE2s low 3 0 3 0 ns
tdis(LB) Output disable time after LBs high 30 30 ns
tdis(UB) Output disable time after UBs high 3 0 3 0 ns
tdis(OE) Output disable time after OEs high 3 0 3 0 ns
ten(CE1) Output enable time after CE1s low 1 0 1 0 ns
ten(CE2) Output enable time after CE2s low 1 0 1 0 ns
te n( LB ) Output enable time after LBs low 1 0 1 0 ns
ten(UB) Output enable time after UBs low 1 0 1 0 ns
te n( OE) Output enable time after OEs low 5 5 ns
tv(A) Data valid time after address 1 0 1 0 ns
43
P/N:PM0954
MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
READ CYCLE TIMING DIAGRAMS
tCR
ta(A) tv(A)
tdis(LB) or tdis(UB)
tdis(CE1)
tdis(CE2)
tdis(OE)
ta(LB) or ta(UB)
ta(CE1)
ta(CE2)
ta(OE)
ten(OE)
ten(LB)
ten(UB)
ten(CE1)
ten(CE2)
A0~A16/A0~A17
Q0~15
LBs
UBs
CE1s
CE2s
OEs
WEs="H" level
VALID DATA
(Note3)(Note3)
(Note3)
(Note3)
(Note3)
(Note3)
(Note3)
(Note3)
44
P/N:PM0954
MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
AC ELECTRICAL CHARACTERISTICS
WRITE CYCLE
Limits SRAM
Symbol Parameter 70 8 5 Units
MIN. MAX. MIN. MAX.
tCW Write cycle time 70 85 ns
tw(W) Write pulse width 50 50 ns
tsu(A) Address setup time 0 0 ns
tsu(A-WH) Address setup time with respect to WEs 70 70 ns
tsu(LB) Lower Byte control setup time 7 0 7 0 ns
tsu(UB) Upper Byte control setup time 7 0 7 0 ns
tsu(CE1) Chip select 1 setup time 70 70 ns
tsu(CE2) Chip select 2 setup time 70 70 ns
tsu(D) Data setup time 3 5 3 5 ns
th(D) Data hold time 0 0 ns
trec(W) Write recovery time 0 0 ns
tdis(W) Output disable time WEs lo w 3 0 3 0 ns
tdis(OE) Output disable time OEs high 3 0 3 0 ns
ten(W) Output enable time WEs high 5 5 ns
ten(OE) Output enable time from OEs low 5 5 ns
45
P/N:PM0954
MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
WRITE CYCLE (WEs control mode)
tCW
tsu(LB) or tsu(UB)
tsu(CE1)
tsu(CE2)
tsu(A-WH)
tw(W) trec(W)
tsu(A)
tdis(W)
th(D)tsu(D)
tdis(OE) ten(W)
ten(OE)
LBs
UBs
CE1s
CE2s
OEs
WEs
DATA IN
STABLE
(Note3)
(Note3)
(Note3)
(Note3)
(Note3)
(Note3)
A0~A16/A0~A17
Q0~15
46
P/N:PM0954
MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
WRITE CYCLE (LBs, UBs control mode)
Note 3: Hatching indicates the state is "don't care".
Note 4: A Write occurs during CE1s low , CE2s high o verlaps LBs and/or UBs low and WEs low.
Note 5: When the falling edge of WEs is simultaneously or prior to the f alling edge of LBs and/or UBs or the f alling
edge of CE1s or rising edge of CE2s the outputs are maintained in the high impedance state.
Note 6: Don't apply inv erted phase signal externally when I/O pin is in output mode.
tCW
tsu(A) tsu(LB) or
tsu(UB) trec(W)
DATA IN
STABLE
tsu(D) th(D)
LBs
UBs
CE1s
CE2s
WEs
(Note3)
(Note3)
(Note3)
(Note5)
(Note4)
(Note3)
(Note3)
(Note3)
A0~A16/A0~A17
Q0~15
47
P/N:PM0954
MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
WRITE CYCLE (CE1s control mode)
WRITE CYCLE (CE2s control mode)
tCW
tsu(A) tsu(CE1) trec(W)
DATA IN
STABLE
tsu(D) th(D)
CE1s
LBs
UBs
CE2s
WEs
(Note3)
(Note3)
(Note3)
(Note5)
(Note4)
(Note3)
(Note3)
(Note3)
A0~A16/A0~A17
Q0~15
tCW
tsu(A) tsu(CE1) trec(W)
DATA IN
STABLE
tsu(D) th(D)
CE1s
LBs
UBs
CE2s
WEs
(Note3)
(Note3)
(Note3)
(Note5)
(Note4)
(Note3)
(Note3)
(Note3)
A0~A16/A0~A17
Q0~15
48
P/N:PM0954
MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
ORDERING INFORMATION
PLASTIC PACKAGE
PART NO. Access Time Temperature
(ns) Range Type Package Type Ball Pitch
MX69F1602C3TXBI-70 70 -40~85°C 66 Ball FBGA FBGA 0.8mm
MX69F1602C3BXBI-70 70 -40~85°C 66 Ball FBGA FBGA 0.8mm
MX69F1602C3TXBI-90 90 -40~85°C 66 Ball FBGA FBGA 0.8mm
MX69F1602C3BXBI-90 90 -40~85°C 66 Ball FBGA FBGA 0.8mm
MX69F1604C3TXBI-70 70 -40~85°C 66 Ball FBGA FBGA 0.8mm
MX69F1604C3BXBI-70 70 -40~85°C 66 Ball FBGA FBGA 0.8mm
MX69F1604C3TXBI-90 90 -40~85°C 66 Ball FBGA FBGA 0.8mm
MX69F1604C3BXBI-90 90 -40~85°C 66 Ball FBGA FBGA 0.8mm
49
P/N:PM0954
MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
PACKAGE INFORMATION
50
P/N:PM0954
MX69F1602/1604C3T/B
REV. 0.3, NOV. 22, 2002
REVISION HISTORY
Revision No. Description Page Date
0. 1 1. Add Package Information P4 9 NOV/06/2002
0.2 1. Changed Part No. from MX28F1602/1604C3T/B to All NOV/20/2002
MX69F1602/1604C3T/B
0. 3 1. Modified Pin Assignment P4 NOV/22/2002
MX69F1602/1604C3T/B
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