19-1428; Rev 0; 2/99 +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference Features The MAX5120/MAX5121 are low-power, 12-bit, voltageoutput digital-to-analog converters (DACs) with an internal precision bandgap reference and an output amplifier. The MAX5120 operates on a +5V supply with an internal amplifier reference of +2.5V and is capable of a +4.095V full-scale output range. The MAX5121, operating on +3V, delivers its +2.0475V full-scale output with an internal precision reference of +1.25V. If necessary, the user can override the internal, <10ppm/C voltage reference with an external reference. Both devices draw only 500A of supply current, which reduces to 3A in power-down mode. In addition, their power-up reset feature allows for a user-selectable initial output state of either 0V or midscale and minimizes output voltage glitches during power-up. Single-Supply Operation +5V (MAX5120) +3V (MAX5121) The serial interface is compatible with SPITM, QSPITM and MICROWIRETM, which makes the MAX5120/ MAX5121 suitable for cascading multiple devices. Each DAC has a double-buffered input organized as an input register followed by a DAC register. A 16-bit shift register loads data into the input register. The DAC register may be updated independently or simultaneously with the input register. SPI/QSPI/MICROWIRE-Compatible, 3-Wire Serial Interface Both devices are available in a 16-pin QSOP package and are specified for the extended industrial (-40C to +85C) temperature range. For pin-compatible 14-bit upgrades, see the MAX5170/MAX5172 data sheet; for pin-compatible 13-bit versions, see the MAX5130/ MAX5131 data sheet. Space-Saving 16-Pin QSOP Package Full-Scale Output Range +4.095V (MAX5120) +2.0475V (MAX5121) Built-In 10ppm/C (max) Precision Bandgap Reference +2.5V (MAX5120) +1.25V (MAX5121) Adjustable Output Offset Pin-Programmable Shutdown Mode and PowerUp Reset (0V or Midscale Output Voltage) Buffered Output Capable of Driving 5k 100pF or 4-20mA Loads Pin-Compatible 13-Bit Upgrades Available (MAX5130/MAX5131) Pin-Compatible 14-Bit Upgrades Available (MAX5170/MAX5172) ________________________Applications Industrial Process Controls Automatic Test Equipment (ATE) Digital Offset and Gain Adjustment Motion Control P-Controlled Systems Pin Configuration TOP VIEW 15 REFADJ RSTVAL 3 CLR 5 PART TEMP. RANGE PINPACKAGE INL (LSB) MAX5120AEEE -40C to +85C 16 QSOP 0.5 MAX5120BEEE -40C to +85C 16 QSOP 1 MAX5121AEEE -40C to +85C 16 QSOP 1 MAX5121BEEE -40C to +85C 16 QSOP 2 16 VDD OS 1 OUT 2 PDL 4 Ordering Information 14 REF MAX5120 MAX5121 13 AGND 12 PD CS 6 11 UPO DIN 7 10 DOUT SCLK 8 9 QSOP DGND SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX5120/MAX5121 General Description MAX5120/MAX5121 +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference ABSOLUTE MAXIMUM RATINGS VDD to AGND, DGND ...............................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V Digital Inputs to DGND.............................................-0.3V to +6V Digital Outputs (DOUT, UPO) to DGND .....-0.3V to (VDD + 0.3V) OUT to AGND.............................................-0.3V to (VDD + 0.3V) OS to AGND ...................................(AGND - 4V) to (VDD + 0.3V) REF, REFADJ to AGND ..............................-0.3V to (VDD + 0.3V) Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) QSOP (derate 8.00mW/C above +70C) .....................667mW Operating Temperature Range ..........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS--MAX5120 (+5V) (VDD = +5V 10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution N 12 Bits MAX5120A -0.5 0.5 MAX5120B -1 1 1 LSB Integral Nonlinearity (Note 1) INL Differential Nonlinearity DNL -1 Offset Error (Note 2) VOS -10 10 mV Gain Error GE -3 -0.2 3 mV Full-Scale Voltage VFS 4.0458 4.095 4.1442 V Code = FFF hex, TA = +25C MAX5120A 3 10 MAX5120B 10 30 PSRR 4.5V VDD 5.5V 20 250 VREF TA = +25C 2.5 MAX5120A 3 MAX5120B 10 0 IOUT 100A (sourcing) 0.1 Full-Scale Temperature Coefficient (Note 3) TCVFS Power-Supply Rejection Ratio LSB ppm/C V/V REFERENCE Output Voltage Output Voltage Temperature Coefficient Reference External Load Regulation TCVREF VOUT/IOUT Reference Short-Circuit Current V ppm/C 1 4 REFADJ Current REFADJ = VDD 3.3 V/A mA 7 A DIGITAL INPUT Input High Voltage Input Low Voltage Input Hysteresis VIH 3 V VIL 0.8 VHYS Input Leakage Current IIN Input Capacitance CIN 200 VIN = 0 or VDD -1 0.001 V mV 1 8 A pF DIGITAL OUTPUTS Output High Voltage VOH ISOURCE = 2mA Output Low Voltage VOL ISINK = 2mA 2 VDD - 0.5 V 0.13 _______________________________________________________________________________________ 0.4 V +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference (VDD = +5V 10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE Voltage Output Slew Rate SR Output Settling Time To 0.5LSB, VSTEP = 4V Output Voltage Swing (Note 4) OS Input Resistance ROS 83 Time Required to Exit Shutdown CS = VDD, fSCLK = 100kHz, VSCLK = 5Vp-p Digital Feedthrough 0.6 V/s 20 s 0 to VDD V 121 k 2 ms 5 nV-s POWER REQUIREMENTS Power-Supply Voltage (Note 5) Power-Supply Current (Note 5) Power-Supply Current in Shutdown VDD 4.5 5.5 V IDD 500 600 A ISHDN 3 20 A ELECTRICAL CHARACTERISTICS--MAX5121 (+3V) (VDD = +3V 10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution N 12 Bits MAX5121A -1 1 MAX5121B -2 2 Integral Nonlinearity (Note 1) INL Differential Nonlinearity DNL -1 1 LSB Offset Error (Note 2) VOS -10 10 mV Gain Error GE -5 -0.2 5 mV Full-Scale Voltage VFS 2.0229 2.0475 2.0721 V Data = FFF hex, TA = +25C MAX5121A 3 10 MAX5121B 10 30 PSRR 2.7V VDD 3.3V 20 250 VREF TA = +25C 1.25 MAX5121A 3 MAX5121B 10 0 IOUT 100A (sourcing) 0.1 Full-Scale Temperature Coefficient (Note 3) TCVFS Power-Supply Rejection Ratio LSB ppm/C V/V REFERENCE Output Voltage Output Voltage Temperature Coefficient Reference External Load Regulation TCVREF VOUT/IOUT Reference Short-Circuit Current V ppm/C 1 4 REFADJ Current REFADJ = VDD 3.3 V/A mA 7 A DIGITAL INPUT Input High Voltage Input Low Voltage Input Hysteresis VIH 2.2 V VIL VHYS 0.8 200 V mV _______________________________________________________________________________________ 3 MAX5120/MAX5121 ELECTRICAL CHARACTERISTICS--MAX5120 (+5V) (continued) MAX5120/MAX5121 +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference ELECTRICAL CHARACTERISTICS--MAX5121 (+3V) (continued) (VDD = +3V 10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL Input Leakage Current IIN Input Capacitance CIN CONDITIONS VIN = 0 or VDD MIN TYP MAX UNITS -1 0.001 1 A 8 pF DIGITAL OUTPUTS Output High Voltage VOH ISOURCE = 2mA Output Low Voltage VOL ISINK = 2mA VDD - 0.5 V 0.13 0.4 V DYNAMIC PERFORMANCE Voltage Output Slew Rate SR Output Settling Time To 0.5LSB, VSTEP = 2V Output Voltage Swing (Note 4) OS Input Resistance ROS 83 Time Required to Exit Shutdown CS = VDD, fSCLK = 100kHz, VSCLK = 3Vp-p Digital Feedthrough 0.6 V/s 20 s 0 to VDD V 121 k 2 ms 5 nV-s POWER REQUIREMENTS Power-Supply Voltage (Note 5) VDD 3.6 V Power-Supply Current (Note 5) IDD 500 600 A ISHDN 3 20 A Power-Supply Current in Shutdown 2.7 TIMING CHARACTERISTICS--MAX5120 (+5V) (VDD = +5V 10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK Clock Period tCP 100 ns SCLK Pulse Width High tCH 40 ns SCLK Pulse Width Low tCL 40 ns CS Fall to SCLK Rise Setup Time tCSS 40 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns SDI Setup Time tDS 40 ns SDI Hold Time tDH 0 ns SCLK Rise to DOUT Valid Propagation Delay Time tDO1 CLOAD = 200pF 80 ns SCLK Fall to DOUT Valid Propagation Delay Time tDO2 CLOAD = 200pF 80 ns SCLK Rise to CS Fall Delay Time tCS0 10 ns CS Rise to SCLK Rise Hold Time tCS1 40 ns CS Pulse Width High tCSW 100 ns 4 _______________________________________________________________________________________ +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference (VDD = +3V 10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, RL = 5k, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK Clock Period tCP 150 ns SCLK Pulse Width High tCH 75 ns SCLK Pulse Width Low tCL 75 ns CS Fall to SCLK Rise Setup Time tCSS 60 ns SCLK Rise to CS Rise Hold Time tCSH 0 ns SDI Setup Time tDS 60 ns SDI Hold Time tDH 0 ns SCLK Rise to DOUT Valid Propagation Delay Time tDO1 CLOAD = 200pF 200 ns SCLK Fall to DOUT Valid Propagation Delay Time tDO2 CLOAD = 200pF 200 ns SCLK Rise to CS Fall Delay Time tCS0 10 ns CS Rise to SCLK Rise Hold Time tCS1 75 ns CS Pulse Width High tCSW 150 ns Note 1: Accuracy is guaranteed as shown in the following table: Accuracy Guaranteed VDD (V) From Code: To Code: 5 10 4095 3 20 4095 Note 2: Offset is measured at the code closest to 10mV. Note 3: The temperature coefficient is determined by the "box" method in which the maximum VOUT over the temperature range is divided by T. Note 4: Accuracy is better than 1.0LSB for VOUT = 10mV to (VDD - 180mV). Guaranteed by PSR test on end points. Note 5: RLOAD = and digital inputs are at either VDD or DGND. Typical Operating Characteristics (VDD = +5V (MAX5120), VDD = +3V (MAX5121), RL = 5k, CL = 100pF, OS = AGND, TA = +25C, unless otherwise noted.) 0.10 DNL (LSB) 0.05 0.15 0 0.05 0 -0.05 -0.05 -0.10 -0.10 -0.15 -0.15 -0.20 1000 2000 3000 DIGITAL INPUT CODE 4000 5000 2.505 2.500 2.495 2.490 -0.20 0 2.510 REFERENCE VOLTAGE (V) 0.10 MAX5120 REFERENCE VOLTAGE vs. TEMPERATURE MAX5120/21 toc02 0.15 INL (LSB) 0.20 MAX5120/21 toc01 0.20 MAX5120 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE MAX5120/21 toc03 MAX5120 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE 0 1000 2000 3000 DIGITAL INPUT CODE 4000 5000 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) _______________________________________________________________________________________ 5 MAX5120/MAX5121 TIMING CHARACTERISTICS--MAX5121 (+3V) Typical Operating Characteristics (continued) (VDD = +5V (MAX5120), VDD = +3V (MAX5121), RL = 5k, CL = 100pF, OS = AGND, TA = +25C, unless otherwise noted.) (CODE = AAA HEX) 350 (CODE = 000 HEX) MAX5120/21 toc05 (CODE = AAA HEX) 400 350 (CODE = 000 HEX) 300 250 200 4.0 3.5 SHUTDOWN CURRENT (A) 400 300 450 SUPPLY CURRENT (A) 450 -40 -20 0 20 40 60 80 100 4.5 5.0 5.5 6.0 MAX5120 FULL-SCALE OUTPUT vs. TEMPERATURE MAX5120 FULL-SCALE ERROR vs. RESISTIVE LOAD 4.097 4.096 4.095 4.094 0.50 0.25 FULL-SCALE ERROR (LSB) RL = 5k CL = 100pF MAX5120/21 toc07 SUPPLY VOLTAGE (V) 4.098 2.0 1.0 4.0 TEMPERATURE (C) 4.099 2.5 1.5 250 -60 3.0 -60 -40 -20 0 20 0 40 60 80 100 TEMPERATURE (C) MAX5120 DYNAMIC RESPONSE RISE TIME MAX5120/21-09 MAX5120/21 toc08 SUPPLY CURRENT (A) 500 MAX5120/21 toc04 500 MAX5120 SHUTDOWN CURRENT vs. TEMPERATURE MAX5120 SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX5120/21 toc06 MAX5120 SUPPLY CURRENT vs. TEMPERATURE FULL-SCALE OUTPUT (V) MAX5120/MAX5121 +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference CS 5V/div -0.25 -0.50 OUT 1V/div -0.75 -1.00 -1.25 4.093 -1.50 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) 0.1 1 10 100 5s/div RL (k) MAX5120 DYNAMIC RESPONSE FALL TIME MAX5120 DIGITAL FEEDTHROUGH (SCLK, OUT) MAX5120/21-10 MAX5120 MAJOR CARRY TRANSITION MAX5120/21-12 MAX5120/21-11 CS 5V/div SCLK 2V/div CS 2V/div OUT 1mV/div AC COUPLED OUT 100mV/div AC COUPLED OUT 1V/div 5s/div 6 2s/div 5s/div _______________________________________________________________________________________ +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference MAX5121 DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE 0.15 DNL (LSB) 0 0.05 -0.05 -0.1 -0.15 -0.2 -0.25 -0.3 0 1000 2000 3000 4000 1.244 1000 2000 3000 4000 1.240 5000 -60 -40 -20 0 20 40 60 80 100 DIGITAL INPUT CODE TEMPERATURE (C) MAX5121 SUPPLY CURRENT vs. TEMPERATURE MAX5121 SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX5121 SHUTDOWN CURRENT vs. TEMPERATURE 300 CODE = 000 HEX 250 200 375 150 CODE = AAA HEX 350 325 300 -60 -40 -20 0 20 40 60 80 100 0.6 0.4 0 250 100 0.8 0.2 CODE = 000 HEX 275 1.0 MAX5120/21 toc-18 MAX5120/21 toc-17 400 SUPPLY CURRENT (A) MAX5120/21 toc-16 CODE = AAA HEX 350 2.5 2.7 2.9 3.1 3.3 3.5 3.7 -60 -40 -20 0 20 40 60 80 TEMPERATURE (C) SUPPLY VOLTAGE (V) TEMPERATURE (C) MAX5121 FULL-SCALE OUTPUT vs. TEMPERATURE MAX5121 FULL-SCALE OUTPUT vs. RESISTIVE LOAD MAX5121 DYNAMIC RESPONSE RISE TIME 2.044 2.042 2.040 2.038 MAX5120/21 toc-20 RL = 5k CL = 100pF 100 MAX5120/21-21 0.50 0.25 FULL-SCALE ERROR (LSB) MAX5120/21 toc-19 2.046 FULL-SCALE OUTPUT (V) 1.246 DIGITAL INPUT CODE 400 SUPPLY CURRENT (A) 0 5000 1.248 1.242 SHUTDOWN CURRENT (A) INL (LSB) 0.1 1.250 MAX5120/21 toc-15 0.2 MAX5120/21 toc-14 0.25 MAX5120/21 toc-13 0.3 MAX5121 REFERENCE VOLTAGE vs. TEMPERATURE REFERENCE VOLTAGE (V) MAX5121 INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE CS 2V/div 0 -0.25 -0.50 OUT 500mV/div -0.75 1.00 2.036 -60 -40 -20 0 20 40 TEMPERATURE (C) 60 80 100 MAX5120/MAX5121 Typical Operating Characteristics (continued) (VDD = +5V (MAX5120), VDD = +3V (MAX5121), RL = 5k, CL = 100pF, OS = AGND, TA = +25C, unless otherwise noted.) 0.1 10 1 100 2s/div RL (k) _______________________________________________________________________________________ 7 MAX5120/MAX5121 +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference Typical Operating Characteristics (continued) (VDD = +5V (MAX5120), VDD = +3V (MAX5121), RL = 5k, CL = 100pF, OS = AGND, TA = +25C, unless otherwise noted.) MAX5121 MAJOR CARRY TRANSITION MAX5121 DIGITAL FEEDTHROUGH (SCLK, OUT) MAX5121 DYNAMIC RESPONSE FALL TIME MAX5120/21-24 MAX5120/21-23 MAX5120/21-22 CS 2V/div SCLK 2V/div CS 2V/div OUT 500mV/div OUT 500V/div AC COUPLED OUT 100mV/div AC COUPLED 5s/div 2s/div 2s/div Pin Description 8 PIN NAME 1 OS FUNCTION 2 OUT 3 RSTVAL Reset Value Input (Digital Input) 1: Tie to VDD to select midscale as the output reset value. 0: Tie to DGND to select 0V as the output reset value. 4 PDL Power-Down Lockout (Digital Input) 1: Normal operation. 0: Disallows shutdown (device cannot be powered down). 5 CLR Reset DAC Input (Digital Input). Clears the DAC to its predetermined (RSTVAL) output state. Clearing the DAC will cause it to exit a software shutdown state. Offset Adjust (Analog Input) Analog Output Voltage. High impedance if part is in shutdown. 6 CS Active-Low Chip-Select Input (Digital Input) 7 DIN Serial Data Input. Data is clocked in on the rising edge of SCLK. 8 SCLK Serial Clock Input 9 DGND Digital Ground 10 DOUT Serial Data Output 11 UPO 12 PD 13 AGND 14 REF 15 REFADJ 16 VDD User-Programmable Output (Digital Output) Power-Down Input (Digital Input). Pulling PD high when PDL = VDD places the IC into shutdown with a maximum shutdown current of 20A. Analog Ground Buffered Reference Output/Input. In internal reference mode, the reference buffer provides a +2.5V (MAX5120) or +1.25V (MAX5121) nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal reference by pulling REFADJ to VDD and applying the external reference to REF. Analog Reference Adjust Input. Bypass with a 33nF capacitor to AGND. Connect to VDD when using an external reference. Positive Power Supply. Bypass with a 0.1F capacitor in parallel with a 4.7F capacitor to AGND. _______________________________________________________________________________________ +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference PDL PD MAX5120/MAX5121 CS VDD AGND DGND DIN SCLK SR CONTROL 16-BIT SHIFT REGISTER DOUT LOGIC OUTPUT UPO OS R RSTVAL DECODE CONTROL CLR 12 0.6384R MAX5120 MAX5121 INPUT REGISTER DAC REGISTER OUT DAC GAIN = 1.6384X BANDGAP 1.25V REFERENCE ( ) FOR MAX5121 ONLY 2X (1X) 4k 2.5V, (1.25V) REFERENCE BUFFER REFADJ REF Figure 1. Simplified Functional Diagram _______________Detailed Description OS The MAX5120/MAX5121 12-bit, voltage-output DACs are easily configured with a 3-wire serial interface. They include a 16-bit data-in/data-out shift register and have a double-buffered input consisting of an input register and a DAC register. In addition, these devices employ precision bandgap references and trimmed internal resistors to produce a gain of 1.6384V/V, maximizing the output voltage swing (Figure 1). The MAX5120/ MAX5121 output amplifier's offset-adjust pin allows for a DC shift in the DAC outputs. The full-scale output voltage is +4.095V for the MAX5120 and +2.0475V for the MAX5121. These DACs are designed with an inverted R-2R ladder network (Figure 2) that produces a weighted output voltage proportional to the digital input code. REF* Internal Reference AGND Both the MAX5120 and MAX5121 use an on-board precision bandgap reference to generate an output voltage of +2.5V (MAX5120) or +1.25V (MAX5121). With a low temperature coefficient of only 10ppm/C (max), the REF pin can source up to 100A and may become unstable with capacitive loads exceeding 100pF. REFADJ can be used for minor adjustments (1%) to the reference voltage. Use the circuits shown in Figure 3a R 0.6384R R 2R 2R D0 R 2R D9 OUT R 2R D10 2R D11 SHOWN FOR ALL 1s ON DAC *INTERNAL 2.5V (MAX5120) AND 1.25V (MAX5121) OR EXTERNAL REFERENCE. Figure 2. Simplified Inverted R-2R DAC Structure _______________________________________________________________________________________ 9 MAX5120/MAX5121 +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference (MAX5120) and Figure 3b (MAX5121) to achieve these adjustments. Connect a 33nF capacitor from REFADJ to AGND to establish low-noise operation of the DAC. Larger capacitor values may be used, but will result in increased start-up delay. The time constant () for the start-up delay is determined by the REFADJ input impedance of 4k and CREFADJ: = 4k * CREFADJ External Reference An external reference may be applied to the REF pin. Disable the internal reference by pulling REFADJ to VDD. This allows an external reference signal (AC- or DC-based) to be fed into the REF pin. For proper operation, do not exceed the input voltage range limits of 0V to (VDD - 1.4V) for VREF. Determine the output voltage using the following equation (REFADJ = VDD; OS = AGND): VOUT = [VREF * (NB / 4096)] * 1.6384V/V where NB is the numeric value of the MAX5120/ MAX5121 input code (0 to 4095), VREF is the external reference voltage, and 1.6384V/V is the gain of the internal output amplifier. The REF pin has a minimum input resistance of 40k and is code-dependent. Output Amplifier The output amplifier of the MAX5120/MAX5121 employs a trimmed resistor-divider to set a gain of +1.6384V/V and minimize the gain error. With its onboard laser-trimmed +1.25V reference and the output buffer gain, the MAX5121 achieves a full-scale output of +2.0475V, while the MAX5120 provides a +4.095V full-scale output with a +2.5V reference. The output amplifier has a typical slew rate of 0.6V/s and settles to 0.5LSB within 20s, with a load of 5k in parallel with 100pF. Loads less than 1k may result in degraded performance. The OS pin may be used to adjust the output offset voltage. For instance, to achieve a +1V offset, apply -1.566V (Offset = -[Output Buffer Gain - 1] * VOS) to OS to produce an output voltage range from +1V to (1V + VREF * 1.6384V/V). Note that the DAC's output range is still limited by the maximum output voltage specification. Power-Down Mode The MAX5120/MAX5121 feature software- and hardware-programmable (PD pin) shutdown modes that reduce the typical supply current to 3A. To enter software shutdown mode, program the control sequence for the DAC as shown in Table 1. In shutdown mode, the amplifier output becomes high impedance and the serial interface remains active. Data in the input registers is saved, allowing the MAX5120/MAX5121 to recall the output state prior to entering shutdown when returning to normal operation mode. To exit shutdown mode, load both input and DAC registers simultaneously or update the DAC register from the input register. When returning from shutdown mode, wait 2ms for the reference to settle. When using an external reference, the DAC requires only 20s for the output to stabilize. +5V +3V MAX5120 90k 400k 100k 400k REFADJ 33nF Figure 3a. MAX5120 Reference Adjust Circuit 10 MAX5121 15k 100k REFADJ 33nF Figure 3b. MAX5121 Reference Adjust Circuit ______________________________________________________________________________________ +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference MAX5120/MAX5121 Table 1. Serial-Interface Programming Commands 16-BIT SERIAL WORD FUNCTION C2 C1 C0 D11 ............... D0 S0* 0 0 0 XXXXXXXXXXXX 0 No operation. 0 0 1 12-Bit DAC Data 0 Load input register; DAC register unchanged. 0 1 0 12-Bit DAC Data 0 Simultaneously load input and DAC registers; exit shutdown. 0 1 1 XXXXXXXXXXXX 0 Update DAC register from input register; exit shutdown. 1 0 1 XXXXXXXXXXXX 0 Shutdown DAC (provided PDL = 1) 1 0 0 XXXXXXXXXXXX 0 UPO goes low (default). 1 1 0 XXXXXXXXXXXX 0 UPO goes high. 1 1 1 1XXXXXXXXXXX 0 Mode 1; DOUT clocked out on SCLK's rising edge. 1 1 1 00XXXXXXXXXX 0 Mode 0; DOUT clocked out on SCLK's falling edge (default). X = Don't care * S0 is a sub-bit and is always zero. Power-Down Lockout Input (PDL) The power-down lockout pin (PDL) disables shutdown when low. When in shutdown mode, a high-to-low transition on PDL will wake up the DAC with its output still set to the state prior to power-down. PDL can also be used to wake up the device asynchronously. Power-Down Input (PD) Pulling PD high places the MAX5120/MAX5121 in shutdown mode. Pulling PD low will not return the MAX5120/ MAX5121 to normal operation. A high-to-low transition on PDL or appropriate commands (Table 1) via the serial interface are required to exit power-down. VDD SS DIN MAX5120 MAX5121 SCLK CS Serial-Interface Configuration (SPI/QSPI/MICROWIRE/PIC16/PIC17) The MAX5120/MAX5121 3-wire serial interface is compatible with SPI, QSPI, PIC16/PIC17 (Figure 4) and MICROWIRE (Figure 5) interface standards. The 2-bytelong serial input word contains three control bits, 12 data bits in MSB-first format and one sub-bit, which is always zero (Table 2). The MAX5120/MAX5121's digital inputs are double buffered, which allows the user to: * Load the input register without updating the DAC register; * Update the DAC register with data from the input register; * Update the input and DAC registers concurrently. MOSI SCK SPI/QSPI PORT (PIC16/PIC17) I/O CPOL = 0, CPHA = 0 CHE = 1, CKP = 0, SMP = 0, SSPM3-SSPMO = 0001 ( ): PIC16/PIC17 ONLY Figure 4. SPI/QSPI Interface Connections (PIC16/PIC17) SCLK MAX5120 MAX5121 SK MICROWIRE PORT DIN SO CS I/O Figure 5. MICROWIRE Interface Connections ______________________________________________________________________________________ 11 MAX5120/MAX5121 +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference PIC16 with SSP Module and PIC17 Interface The 16-bit input word may be sent in two 1-byte packets (SPI-, MICROWIRE- and PIC16/PIC17-compatible), with CS low during this period. The control bits C2, C1, and C0 (Table 1) determine: * The clock edge on which DOUT is to be clocked out via the serial interface; * The state of the user-programmable logic output; * The configuration of the device after shutdown. The MAX5120/MAX5121 are compatible with a PIC16/ PIC17 controller (C), using the synchronous serial port (SSP) module. To establish SPI communication connect the controller as shown in Figure 4 and configure the PIC16/PIC17 as system master by initializing its synchronous serial port control register (SSPCON) and synchronous serial port status register (SSPSTAT) to the bit patterns shown in Tables 3 and 4. In SPI mode, the PIC16/PIC17 Cs allow 8 bits of data to be transmitted synchronously and received simultaneously. Two consecutive 8-bit writings (Figure 6) are necessary to feed the DAC with three control bits and 12 data bits plus one sub-bit. DIN data transitions on the serial clock's falling edge and is clocked into the DAC on SCLK's rising edge. The first 8 bits on DIN contain the 3 control bits (C2, C1, and C0) and the first five data bits (D11-D7). The second 8-bit word contains the remaining bits (D6-D0), and the sub-bit S0. The general timing diagram in Figure 6 illustrates how data is acquired. CS must be low for the part to receive data. With CS low, data at DIN is clocked into the register on the rising edge of SCLK. When CS transitions high, data is latched into the input and/or DAC registers, depending on the setting of the three control bits C2, C1, and C0. The maximum serial clock frequency guaranteed for proper operation is 10MHz for the MAX5120 and 6.6MHz for the MAX5121. Figure 7 depicts a more detailed timing diagram of the serial interface. Table 2. Serial Data Format MSB ............................................................................... LSB 16 BITS OF SERIAL DATA Control Bits MSB .... Data Bits ..... LSB Sub-Bit C2, C1, C0 D11................................D0 S0 CS COMMAND EXECUTED SCLK 1 DIN C2 8 C1 C0 D11 D10 D9 D8 9 D7 D6 16 D5 D4 D3 D2 D1 D0 S0 Figure 6. Serial-Interface Timing tCSW CS tCS0 tCSH tCSS tCS1 SCLK tCH tCL tCP DIN tDS tDO1 tDO2 tDH DOUT Figure 7. Detailed Serial-Interface Timing 12 ______________________________________________________________________________________ +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference CONTROL BIT MAX5120/MAX5121 SETTINGS SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON) WCOL BIT7 X Write Collision Detection Bit SSPOV BIT6 X Receive Overflow Detection Bit SSPEN BIT5 1 Synchronous Serial Port Enable Bit. 0: Disables serial port and configures these pins as I/O port pins. 1: Enables serial port and configures SCK, SDO, and SCI as serialport pins. Clock Polarity Select Bit. CKP = 0 for SPI master-mode selection. CKP BIT4 0 SSPM3 BIT3 0 SSPM2 BIT2 0 SSPM1 BIT1 0 SSPM0 BIT0 1 Synchronous Serial Port Mode Select Bit. Sets SPI master mode and selects fCLK = fOSC / 16. X = Don't care Table 4. Detailed SSPSTAT Register Contents CONTROL BIT MAX5120/MAX5121 SETTINGS SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPSTAT) SMP BIT7 0 SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time. CKE BIT6 1 SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock. D/A BIT5 X Data Address Bit P BIT4 X Stop Bit S BIT3 X Start Bit R/W BIT2 X Read/Write Bit Information UA BIT1 X Update Address BF BIT0 X Buffer Full Status Bit X = Don't care Serial Data Output User-Programmable Output (UPO) The contents of the internal shift register are output serially on DOUT, which allows for daisy-chaining (see Applications Information) of multiple devices as well as data readback. The MAX5120/MAX5121 may be programmed to shift data out on DOUT on the serial clock's rising edge (Mode 1) or falling edge (Mode 0). The latter is the default during power-up and provides a lag of 16 clock cycles, maintaining SPI, QSPI, MICROWIRE, and PIC16/PIC17 compatibility. In Mode 1, the output data lags DIN by 15.5 clock cycles. During power-down, DOUT retains its last digital state prior to shutdown. The UPO feature allows an external device to be controlled through the serial-interface setup (Table 1), thereby reducing the number of microcontroller I/O ports required. During power-down, this output will retain the last digital state before shutdown. With CLR pulled low, UPO will reset to the default state after wake up. ______________________________________________________________________________________ 13 MAX5120/MAX5121 Table 3. Detailed SSPCON Register Contents __________Applications Information Definitions Integral Nonlinearity (INL) Integral nonlinearity (Figure 8a) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every single step. Differential Nonlinearity (DNL) Differential nonlinearity (Figure 8b) is the difference between an actual step height and the ideal value of 1LSB. If the magnitude of the DNL is less than 1LSB, the DAC guarantees no missing codes and is monotonic. Offset Error The offset error (Figure 8c) is the difference between the ideal and the actual offset point. For a DAC, the offset point is the step value when the digital input is zero. This error affects all codes by the same amount and can usually be compensated for by trimming. Gain Error Gain error (Figure 8d) is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step. 6 6 ANALOG OUTPUT VALUE (LSB) ANALOG OUTPUT VALUE (LSB) 7 5 4 AT STEP 011 (1/2 LSB ) 3 2 AT STEP 001 (1/4 LSB ) 1 1 LSB 5 DIFFERENTIAL LINEARITY ERROR (-1/4 LSB) 4 3 1 LSB 2 DIFFERENTIAL LINEARITY ERROR (+1/4 LSB) 1 0 0 000 001 010 011 100 101 110 000 111 001 IDEAL DIAGRAM IDEAL OFFSET POINT 0 000 001 OFFSET ERROR (+1 1/4 LSB) ANALOG OUTPUT VALUE (LSB) 2 ACTUAL OFFSET POINT 14 101 GAIN ERROR (-1 1/4 LSB) 6 IDEAL DIAGRAM ACTUAL FULL-SCALE OUTPUT 5 4 0 010 011 000 100 101 110 DIGITAL INPUT CODE DIGITAL INPUT CODE Figure 8c. Offset Error 100 IDEAL FULL-SCALE OUTPUT 7 ACTUAL DIAGRAM 1 011 Figure 8b. Differential Nonlinearity Figure 8a. Integral Nonlinearity 3 010 DIGITAL INPUT CODE DIGITAL INPUT CODE ANALOG OUTPUT VALUE (LSB) MAX5120/MAX5121 +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference Figure 8d. Gain Error ______________________________________________________________________________________ 111 +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference +5V/+3V REF OS VDD Digital Feedthrough Digital feedthrough is noise generated on the DAC's output when any digital input transitions. Proper board layout and grounding will significantly reduce this noise, but there will always be some feedthrough caused by the DAC itself. 0.6384R DAC OUT AGND Unipolar Output Figure 9 shows the MAX5120/MAX5121 setup for unipolar, Rail-to-Rail (R) operation with a gain of 1.6384V/V. With its +2.5V internal reference, the MAX5120 can generate a unipolar output range of 0V to +4.095V. The MAX5121 produces a range of 0V to +2.0475V with its on-board +1.25V reference. Table 5 lists example codes for unipolar output voltages. An offset to the output voltage can be achieved by simply connecting the appropriate voltage to the OS pin, as shown in Figure 10. Figure 9. Unipolar Output Circuit (OS = AGND) Using Internal (1.25V/2.5V) or External Reference. With external reference, pull REFADJ to VDD. +5V/+3V REF VOS R MAX5120 MAX5121 0.6384R DAC OUT AGND DGND Figure 10. Circuit for Adding Offset to the DAC's Output +5V/+3V 50k REF Reset (RSTVAL) and Clear (CLR) Functions The CLR pin has a minimum input resistance of 40k in series with a diode to the supply voltage (VDD). If the digital voltage is higher than the supply voltage for the part, a small input current may flow, but this current will be limited to (V CLR - VDD - 0.5V) / 40k. Note: Clearing the DAC will also cause the part to exit software shutdown (PD = 0). OS REFADJ VDD Bipolar Output The MAX5120/MAX5121 DACs offer a clear pin (CLR) that resets the output to a certain value, depending upon how RSTVAL is set. RSTVAL = DGND sets the output to 0, and RSTVAL = VDD sets the output to midscale when CLR is pulled low. DGND GAIN = 1.638V/V The MAX5120/MAX5121 can be configured for unitygain bipolar operation (OS = OUT) using the circuit shown in Figure 11. The output voltage VOUT is thereby given by the following equation: VOUT = VREF * [ {G * (NB / 4096)} - 1] where NB is the numeric value of the DAC's binary input code, VREF is the voltage of the internal (or external) precision reference, and G is the overall gain. The application circuit in Figure 11 uses a low-cost operational amplifier (MAX4162) external to the MAX5120/ MAX5121 in a unity-gain configuration. This provides an overall circuit gain of 2V/V. Table 6 lists example codes for bipolar output voltages. R MAX5120 MAX5121 50k OS VDD R MAX5120 MAX5121 V+ 0.6384R VOUT DAC OUT DGND AGND MAX4162 V- Figure 11. Unity-Gain Bipolar Output Circuit Using Internal (+1.25V/+2.5V) or External Reference. With external reference, pull REFADJ to VDD. Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. ______________________________________________________________________________________ 15 MAX5120/MAX5121 Settling Time The settling time is the amount of time required from the start of a transition until the DAC output settles to its new output value within the converter's specified accuracy. MAX5120/MAX5121 +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference Table 5. Unipolar Code Table (Gain = 1.6384V/V) DAC CONTENTS ANALOG OUTPUT INTERNAL REFERENCE SUB-BIT S0 MAX5120 MAX5121 1111 1111 1111 0 +4.0950V +2.0475V +VREF (4095 / 4096) * 1.6384 1000 0000 0001 0 +2.049V +1.0245V +VREF (2049 / 4096) * 1.6384 1000 0000 0000 0 +2.048V +1.024V +VREF (2048 / 4096) * 1.6384 0111 1111 1111 0 +2.047V +1.0235V +VREF (2047 / 4096) * 1.6384 0000 0000 0001 0 +1mV +0.5mV 0000 0000 0000 0 0V 0V +VREF (1 / 4096) * 1.6384 0V MSB LSB EXTERNAL REFERENCE Table 6. Bipolar Code Table for Figure 11 DAC CONTENTS MSB ANALOG OUTPUT SUB-BIT SO LSB INTERNAL REFERENCE MAX5120 MAX5121 EXTERNAL REFERENCE 1111 1111 1111 0 +2.49878V +1.24939V VREF * [ {2 * (4095 / 4096)} - 1] 1000 0000 0001 0 +1.2207mV +610.35V VREF * [ {2 * (2049 / 4096)} - 1] 1000 0000 0000 0 0V 0V VREF * [ {2 * (2048 / 4096)} - 1] 0111 1111 1111 0 -1.2207V -610.35V VREF * [ {2 * (2047 / 4096)} - 1] 0000 0000 0001 0 -2.49878V -1.24939V VREF * [ {2 * (14096)} - 1] 0000 0000 0000 0 -2.5V -1.25V -VREF SCLK DIN CS SCLK SCLK I II III MAX5120 MAX5121 MAX5120 MAX5121 MAX5120 MAX5121 DOUT DIN DOUT DIN CS DOUT CS TO OTHER SERIAL DEVICES Figure 12. Daisy-Chaining Multiple Devices with the Digital I/Os DIN/DOUT Daisy-Chaining Devices Any number of MAX5120/MAX5121s can be daisychained simply by connecting the serial data output pin (DOUT) of one device to the digital input pin (DIN) of the following device in the chain (Figure 12). 16 Another configuration allows several MAX5120/ MAX5121 DACs to share one common DIN signal line (Figure 13). In this configuration, the data bus is common to all devices; data is not shifted through a daisychain. However, more I/O lines are required in this configuration, because each IC needs a dedicated CS line. ______________________________________________________________________________________ +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference = VDD). Bypass the power supply with a 4.7F capacitor in parallel with a 0.1F capacitor to AGND. Minimize lead lengths to reduce lead inductance. The MAX5120/MAX5121 have multiplying capabilities within the reference input voltage range specifications. Figure 14 shows a technique for applying a sinusoidal input to REF, where the AC signal is offset before being applied to the reference input. Layout Considerations Digital and AC transient signals coupling to AGND can create noise at the output. Connect AGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a lowinductance ground plane. Wire-wrapped boards and sockets are not recommended. If noise becomes an issue, shielding may be required. Power-Supply and Bypassing Considerations On power-up, the input and DAC registers are cleared to either zero (RSTVAL = DGND) or midscale (RSTVAL DIN SCLK CS1 CS2 TO OTHER SERIAL DEVICES CS3 I CS II CS MAX5120 MAX5121 III CS MAX5120 MAX5121 MAX5120 MAX5121 SCLK SCLK SCLK DIN DIN DIN Figure 13. Multiple Devices Share One Common Digital Input (DIN) +5V/+3V +5V/+3V AC REFERENCE INPUT 26k MAX495 500mVp-p 10k REF VDD R OS 0.6384R DAC AGND OUT MAX5120 MAX5121 DGND Figure 14. External Reference with AC Components ______________________________________________________________________________________ 17 MAX5120/MAX5121 Using an External Reference with AC Components ___________________Chip Information TRANSISTOR COUNT: 3308 SUBSTRATE CONNECTED TO AGND. Package Information QSOP.EPS MAX5120/MAX5121 +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference 18 ______________________________________________________________________________________ +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference ______________________________________________________________________________________ MAX5120/MAX5121 NOTES 19 MAX5120/MAX5121 +3V/+5V, 12-Bit, Serial Voltage-Output DACs with Internal Reference NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.