Super Sequencer and Monitor
ADM1065
Rev. D
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved.
FEATURES
Complete supervisory and sequencing solution for up to
10 supplies
10 supply fault detectors enable supervision of supplies to
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
5 selectable input attenuators allow supervision of supplies to
14.4 V on VH
6 V on VP1 to VP4 (VPx)
5 dual-function inputs, VX1 to VX5 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
10 programmable driver outputs, PDO1 to PDO10 (PDOx)
Open-collector with external pull-up
Push/pull output driven to VDDCAP or VPx
Open collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external
N-FET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Device powered by the highest of VPx, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 40-lead, 6 mm × 6 mm LFCSP and
48-lead, 7 mm × 7 mm TQFP packages
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
For more information about the ADM1065 register map,
refer to the AN-698 Application Note at www.analog.com.
FUNCTIONAL BLOCK DIAGRAM
04634-001
PDO7
PDO8
PDO9
PDO10
PDOGND
VDD
ARBITRATOR
VCCP GND
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
VH
AGND
V
DDCAP
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
SEQUENCING
ENGINE
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LO GIC SIGNALS )
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
SD
A
SCL
A
1
A
0
SMBus
INTERFACE
REFOUT REFGND
VREF
EEPROM
ADM1065
CONFIGURABLE
OUTPUT
DRIVERS
(HV CA PABLE OF
DRIVING GATES
OF N-FET)
Figure 1.
GENERAL DESCRIPTION
The ADM1065 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple-supply systems.
The device also provides up to 10 programmable inputs for moni-
toring undervoltage faults, overvoltage faults, or out-of-window
faults on up to 10 supplies. In addition, 10 programmable outputs
can be used as logic enables. Six of these programmable outputs
can each provide up to a 12 V output for driving the gate of an
N-FET that can be placed in the path of a supply.
The logical core of the device is a sequencing engine. This state
machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs
based on the condition of the inputs.
The ADM1065 is controlled via configuration data that can be
programmed into an EEPROM. The whole configuration can
be programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.
ADM1065
Rev. D | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Detailed Block Diagram .................................................................. 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 9
Powering the ADM1065................................................................ 11
Inputs................................................................................................ 12
Supply Supervision..................................................................... 12
Programming the Supply Fault Detectors............................... 12
Input Comparator Hysteresis.................................................... 12
Input Glitch Filtering ................................................................. 13
Supply Supervision with VXx Inputs....................................... 13
VXx Pins as Digital Inputs ........................................................ 13
Outputs ............................................................................................ 14
Supply Sequencing Through Configurable Output Drivers ..... 14
Default Output Configuration.................................................. 14
Sequencing Engine......................................................................... 15
Overview ..................................................................................... 15
Warnings...................................................................................... 15
SMBus Jump (Unconditional Jump)........................................ 15
Sequencing Engine Application Example............................... 16
Fault and Status Reporting........................................................ 17
Applications Diagram.................................................................... 18
Communicating with the ADM1065........................................... 19
Configuration Download at Power-Up................................... 19
Updating the Configuration ..................................................... 19
Updating the Sequencing Engine............................................. 20
Internal Registers........................................................................ 20
EEPROM ..................................................................................... 20
Serial Bus Interface..................................................................... 20
SMBus Protocols for RAM and EEPROM.............................. 23
Write Operations........................................................................ 23
Read Operations......................................................................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
REVISION HISTORY
6/11—Rev. C to Rev. D
Changes to Serial Bus Timing Parameter in Table 1.................... 4
Changes to Figure 3.......................................................................... 7
Added Exposed Pad Notation to Outline Dimensions ............. 26
Changes to Ordering Guide .......................................................... 26
5/08—Rev. B to Rev. C
Changes to Table 1............................................................................ 4
Changes to Powering the ADM1065 Section ............................. 10
Changes to Default Output Configuration Section ................... 13
Changes to Sequence Detector Section ....................................... 15
Changes to Configuration Download at Power-Up Section..... 18
Changes to Table 9.......................................................................... 19
Changes to Figure 26...................................................................... 20
Changes to Figure 27...................................................................... 21
Changes to Figure 36 and Error Correction Section ................. 24
Changes to Ordering Guide .......................................................... 25
7/06—Rev. A to Rev. B
Changes to Features.......................................................................... 1
Changes to Figure 1.......................................................................... 1
Changes to Figure 2...........................................................................3
Changes to Table 1.............................................................................4
Changes to Table 2.............................................................................6
Changes to Table 3.............................................................................7
Inserted Table 4; Renumbered Sequentially ..................................7
Changes to Programming the Supply Fault Detectors Section 11
Changes to Outputs Section.......................................................... 14
Changes to Fault Reporting Section ............................................ 19
Changes to Figure 24...................................................................... 20
Inserted Table 9; Renumbered Sequentially ............................... 23
Changes to Ordering Guide.......................................................... 28
1/05—Rev. 0 to Rev. A.
Changes to Specifications Section...................................................3
Change to Absolute Maximum Ratings Section ...........................7
Change to Supply Sequencing through Configurable
Output Drivers Section.................................................................. 14
Changes to Figure 24...................................................................... 18
Change to Table 8 ........................................................................... 28
10/04—Revision 0: Initial Version
ADM1065
Rev. D | Page 3 of 28
DETAILED BLOCK DIAGRAM
04634-002
GPI SIGNAL
CONDITIONING
SFD
GPI SIGNAL
CONDITIONING
SFD
SFD
SFD
SELECTABLE
ATTENUATOR
SELECTABLE
ATTENUATOR
DEVICE
CONTROLLER
OSC
EEPROM
SDA SCL A1 A0
SMBus
INTERFACE
REFOUT REFGND
VREF
ADM1065
CONFIGURABLE
OUTPUT DRIVER
(HV) PDO1
PDO2
PDOGND
PDO3
GND
PDO4
PDO5
PDO8
PDO9
CONFIGURABLE
OUTPUT DRIVER
(HV) PDO6
CONFIGURABLE
OUTPUT DRIVER
(LV) PDO7
CONFIGURABLE
OUTPUT DRIVER
(LV) PDO10
SEQUENCING
ENGINE
VX2
VX3
VX4
VP2
VP3
VP4
VH
VP1
VX1
AGND
VX5
VDDCAP VDD
ARBITRATOR
VCCP
REG 5. 25V
CHARGE P UMP
Figure 2.
ADM1065
Rev. D | Page 4 of 28
SPECIFICATIONS
VH = 3.0 V to 14.4 V1, VPx = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY ARBITRATION
VH, VPx 3.0 V Minimum supply required on one of VH, VPx
VPx 6.0 V Maximum VDDCAP = 5.1 V typical
VH 14.4 V VDDCAP = 4.75 V
VDDCAP 2.7 4.75 5.4 V Regulated LDO output
CVDDCAP 10 μF
Minimum recommended decoupling
capacitance
POWER SUPPLY
Supply Current, IVH, IVPx 4.2 6 mA VDDCAP = 4.75 V, PDO1 to PDO10 off
Additional Currents
All PDO FET Drivers On 1 mA VDDCAP = 4.75 V, PDO1 to PDO6 loaded with
1 μA each, PDO7 to PDO10 off
Current Available from VDDCAP 2 mA Maximum additional load that can be drawn
from all PDO pull-ups to VDDCAP
EEPROM Erase Current 10 mA 1 ms duration only, VDDCAP = 3 V
SUPPLY FAULT DETECTORS
VH Pin
Input Impedance 52 kΩ
Input Attenuator Error ±0.05 % Midrange and high range
Detection Ranges
High Range 6 14.4 V
Midrange 2.5 6 V
VPx Pins
Input Impedance 52 kΩ
Input Attenuator Error ±0.05 % Low range and midrange
Detection Ranges
Midrange 2.5 6 V
Low Range 1.25 3 V
Ultralow Range 0.573 1.375 V No input attenuation error
VXx Pins
Input Impedance 1 MΩ
Detection Ranges
Ultralow Range 0.573 1.375 V No input attenuation error
Absolute Accuracy ±1 % VREF error + DAC nonlinearity + comparator
offset error + input attenuation error
Threshold Resolution 8 Bits
Digital Glitch Filter 0 μs Minimum programmable filter length
100 μs Maximum programmable filter length
REFERENCE OUTPUT
Reference Output Voltage 2.043 2.048 2.053 V No load
Load Regulation −0.25 mV Sourcing current
0.25 mV Sinking current
Minimum Load Capacitance 1 μF Capacitor required for decoupling, stability
PSRR 60 dB DC
ADM1065
Rev. D | Page 5 of 28
Parameter Min Typ Max Unit Test Conditions/Comments
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge Pump) Mode
(PDO1 to PDO6)
Output Impedance 500 kΩ
VOH 11 12.5 14 V IOH = 0 μA
10.5 12 13.5 V IOH = 1 μA
IOUTAVG 20 μA 2 V < VOH < 7 V
Standard (Digital Output) Mode
(PDO1 to PDO10)
VOH 2.4 V VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA
4.5 V VPU to VPx = 6.0 V, IOH = 0 mA
V
PU − 0.3 V VPU ≤ 2.7 V, IOH = 0.5 mA
VOL 0 0.50 V IOL = 20 mA
IOL2 20 mA Maximum sink current per PDO pin
ISINK2 60 mA Maximum total sink for all PDO pins
RPULL-UP 16 20 29 kΩ Internal pull-up
ISOURCE (VPx)2 2 mA
Current load on any VPx pull-ups, that is, total
source current available through any number of
PDO pull-up switches configured onto any one
VPx pin
Three-State Output Leakage Current 10 μA VPDO = 14.4 V
Oscillator Frequency 90 100 110 kHz All on-chip time delays derived from this clock
DIGITAL INPUTS (VXx, A0, A1)
Input High Voltage, VIH 2.0 V Maximum VIN = 5.5 V
Input Low Voltage, VIL 0.8 V Maximum VIN = 5.5 V
Input High Current, IIH −1 μA VIN = 5.5 V
Input Low Current, IIL 1 μA VIN = 0 V
Input Capacitance 5 pF
Programmable Pull-Down Current,
IPULL-DOWN
20 μA
VDDCAP = 4.75 V, TA = 25°C if known logic state
is required
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
Output Low Voltage, VOL2 0.4 V IOUT = −3.0 mA
SERIAL BUS TIMING3
Clock Frequency, fSCLK 400 kHz
Bus Free Time, tBUF 1.3 μs
Start Setup Time, tSU;STA 0.6 μs
Stop Setup Time, tSU;STO 0.6 μs
Start Hold Time, tHD;STA 0.6 μs
SCL Low Time, tLOW 1.3 μs
SCL High Time, tHIGH 0.6 μs
SCL, SDA Rise Time, tR 300 ns
SCL, SDA Fall Time, tF 300 ns
Data Setup Time, tSU;DAT 100 ns
Data Hold Time, tHD;DAT 5 ns
Input Low Current, IIL 1 μA VIN = 0 V
SEQUENCING ENGINE TIMING
State Change Time 10 μs
1 At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 Timing specifications are guaranteed by design and supported by characterization data.
ADM1065
Rev. D | Page 6 of 28
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Voltage on VH Pin 16 V
Voltage on VPx Pins 7 V
Voltage on VXx Pins −0.3 V to +6.5 V
Voltage on A0, A1 Pins −0.3 V to +7 V
Voltage on REFOUT Pin 5 V
Voltage on VDDCAP, VCCP Pins 6.5 V
Voltage on PDOx Pins 16 V
Voltage on SDA, SCL Pins 7 V
Voltage on GND, AGND, PDOGND, REFGND Pins −0.3 V to +0.3 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature,
Soldering Vapor Phase, 60 sec
215°C
ESD Rating, All Pins 2000 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA Unit
40-Lead LFCSP 25 °C/W
48-Lead TQFP 50 °C/W
ESD CAUTION
ADM1065
Rev. D | Page 7 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
04634-003
NOTES
1. NC = NO CO NNE C T.
2. THE LFCSP HAS AN EXPOSED PAD ON T HE BOTTOM.
THIS PAD IS A NO CO NNE CT (NC). I F POSSIBLE, THI S
PAD SHO UL D BE S O L DE RED TO THE BO ARD F O R
IM P ROVE D M E CHANICAL STABIL ITY.
ADM1065
TOP VIEW
(Not to Scale)
GND
40
VDDCAP
39
NC
38
NC
37
SDA
36
SCL
35
A1
34
A0
33
VCCP
32
PDOGND
31
AGND
11
REFGND
12
NC
13
REFOUT
14
NC
15
NC
16
NC
17
NC
18
NC
19
NC
20
VX1
1
VX2
2
VX3
3
VX4
4
VX5
5
VP1
6
VP2
7
VP3
8
VP4
9
VH
10
PDO1
30
PDO2
29
PDO3
28
PDO4
27
PDO5
26
PDO6
25
PDO7
24
PDO8
23
PDO9
22
PDO10
21
PIN 1
INDICATOR
Figure 3. LFCSP Pin Configuration
04634-004
NC = NO CONNECT
NC
48
GND
47
VDDCAP
46
NC
45
NC
44
SDA
43
SCL
42
A1
41
A0
40
VCCP
39
PDOGND
38
NC
37
NC
13
AGND
14
REFGND
15
NC
16
REFOUT
17
NC
18
NC
19
NC
20
NC
21
NC
22
NC
23
NC
24
NC
1
V
X1
2
V
X2
3
V
X3
4
V
X4
5
V
X5
6
V
P1
7
V
P2
8
V
P3
9
V
P4
10
VH
11
NC
12
NC
36
PDO1
35
PDO2
34
PDO3
33
PDO4
32
PDO5
31
PDO6
30
PDO7
29
PDO8
28
PDO9
27
PDO10
26
NC
25
ADM1065
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
Figure 4. TQFP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
LFCSP1 TQFP Mnemonic Description
13, 15 to 20,
37, 38
1, 12, 13, 16,
18 to 25, 36,
37, 44, 45, 48
NC No Connection.
1 to 5 2 to 6 VX1 to VX5
(VXx)
High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V
to 1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.
6 to 9 7 to 10 VP1 to VP4
(VPx)
Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering
the input attenuation on a potential divider connected to these pins, the output of which
connects to a supply fault detector. These pins allow thresholds from 2.5 V to 6.0 V, from
1.25 V to 3.00 V, and from 0.573 V to 1.375 V.
10 11 VH High Voltage Input to Supply Fault Detectors. Two input ranges can be set by altering the
input attenuation on a potential divider connected to this pin, the output of which connects
to a supply fault detector. This pin allows thresholds from 6.0 V to 14.4 V and from 2.5 V to 6.0 V.
11 14 AGND2 Ground Return for Input Attenuators.
12 15 REFGND2 Ground Return for On-Chip Reference Circuits.
14 17 REFOUT
Reference Output, 2.048 V. Note that the capacitor must be connected between this pin
and REFGND. A 10 μF capacitor is recommended for this purpose.
21 to 30 26 to 35 PDO10 to PDO1 Programmable Output Drivers.
31 38 PDOGND2 Ground Return for Output Drivers.
32 39 VCCP Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between
this pin and GND. A 10 μF capacitor is recommended for this purpose.
33 40 A0 Logic Input. This pin sets the seventh bit of the SMBus interface address.
34 41 A1 Logic Input. This pin sets the sixth bit of the SMBus interface address.
35 42 SCL SMBus Clock Pin. Bidirectional open drain requires external resistive pull-up.
36 43 SDA SMBus Data Pin. Bidirectional open drain requires external resistive pull-up.
ADM1065
Rev. D | Page 8 of 28
Pin No.
LFCSP1 TQFP Description Mnemonic
39 46 VDDCAP
Device Supply Voltage. Linearly regulated from the highest of the VPx, VH pins to a typical
of 4.75 V. Note that the capacitor must be connected between this pin and GND. A 10 μF
capacitor is recommended for this purpose.
40 47 GND2 Supply Ground.
1 Note that the LFCSP has an exposed pad on the bottom. This pad is a no connect (NC). If possible, this pad should be soldered to the board for improved mechanical stability.
2 In a typical application, all ground pins are connected together.
ADM1065
Rev. D | Page 9 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
6
0
1
2
3
4
5
0654321
04634-050
V
VP1
(V)
V
VDDCAP
(V)
Figure 5. VVDDCAP vs. VVP1
6
0
1
2
3
4
5
011412108642
04634-051
V
VH
(V)
V
VDDCAP
(V)
6
Figure 6. VVDDCAP vs. VVH
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
00123456
04634-052
V
VP1
(V)
I
VP1
(mA)
Figure 7. IVP1 vs. VVP1 (VP1 as Supply)
180
160
140
120
100
80
60
40
20
00123456
04634-053
VVP1 (V)
IVP1 (µA)
Figure 8. IVP1 vs. VVP1 (VP1 Not as Supply)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0011412108642
04634-054
V
VH
(V)
I
VH
(mA)
6
Figure 9. IVH vs. VVH (VH as Supply)
350
300
250
200
150
100
50
00654321
04634-055
VVH (V)
IVH (µA)
Figure 10. IVH vs. VVH (VH Not as Supply)
ADM1065
Rev. D | Page 10 of 28
14
12
10
8
6
4
2
00 15.012.510.07.55.02.5
04634-056
ILOAD (µA)
CHARGE- PUMP E D VPDO1 (V)
Figure 11. Charge-Pumped VPDO1 (FET Drive Mode) vs. ILOAD
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
00654321
04634-057
I
LOAD
(mA)
V
PDO1
(V)
VP1 = 5V
VP1 = 3V
Figure 12. VPDO1 (Strong Pull-Up to VPx) vs. ILOAD
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0065040302010
04634-058
ILOAD (µA)
VPDO1 (V)
0
VP1 = 5V
VP1 = 3V
Figure 13. VPDO1 (Weak Pull-Up to VPx) vs. ILOAD
2.058
2.038
2.043
2.048
2.053
–40 –20 0 20 40 60 10080
04634-061
TEMPERATURE (°C)
REFOUT (V)
VP1 = 3.0V
VP1 = 4.75V
Figure 14. REFOUT vs. Temperature
ADM1065
Rev. D | Page 11 of 28
POWERING THE ADM1065
The ADM1065 is powered from the highest voltage input on either
the positive-only supply inputs (VPx) or the high voltage supply
input (VH). This technique offers improved redundancy because
the device is not dependent on any particular voltage rail to keep it
operational. The same pins are used for supply fault detection
(see the Supply Supervision section). A VDD arbitrator on the
device chooses which supply to use. The arbitrator can be
considered an OR’ing of five low dropout regulators (LDOs)
together. A supply comparator chooses the highest input to
provide the on-chip supply. There is minimal switching loss with
this architecture (~0.2 V), resulting in the ability to power the
ADM1065 from a supply as low as 3.0 V. Note that the supply on
the VXx pins cannot be used to power the device.
An external capacitor to GND is required to decouple the on-chip
supply from noise. This capacitor should be connected to the
VDDCAP pin, as shown in Figure 15. The capacitor has another
use during brownouts (momentary loss of power). Under these
conditions, when the input supply (VPx or VH) dips transiently
below VDD, the synchronous rectifier switch immediately turns
off so that it does not pull VDD down. The VDD capacitor can
then act as a reservoir to keep the device active until the next
highest supply takes over the powering of the device. A 10 μF
capacitor is recommended for this reservoir/decoupling function.
The VH input pin can accommodate supplies up to 14.4 V, which
allows the ADM1065 to be powered using a 12 V backplane supply.
In cases where this 12 V supply is hot swapped, it is recommended
that the ADM1065 not be connected directly to the supply. Suitable
precautions, such as the use of a hot swap controller, should be
taken to protect the device from transients that could cause
damage during hot swap events.
When two or more supplies are within 100 mV of each other,
the supply that first takes control of VDD keeps control. For
example, if VP1 is connected to a 3.3 V supply, VDD powers up
to approximately 3.1 V through VP1. If VP2 is then connected
to another 3.3 V supply, VP1 still powers the device unless VP2
goes 100 mV higher than VP1.
SUPPLY
COMPARATOR
IN
EN
OUT
4.75V
LDO
IN
EN
OUT
4.75V
LDO
IN
EN
OUT
4.75V
LDO
IN
EN
OUT
4.75V
LDO
IN
EN
OUT
4.75V
LDO
VH
VP4
VP3
VP2
VP1 VDDCAP
INTERNAL
DEVICE
SUPPLY
0
4634-022
Figure 15. VDD Arbitrator Operation
ADM1065
Rev. D | Page 12 of 28
INPUTS
SUPPLY SUPERVISION
The ADM1065 has 10 programmable inputs. Five of these are
dedicated supply fault detectors (SFDs). These dedicated inputs
are called VH and VPx (VP1 to VP4) by default. The other five
inputs are labeled VXx (VX1 to VX5) and have dual functionality.
They can be used either as SFDs, with functionality similar to VH
and VPx, or as CMOS-/TTL-compatible logic inputs to the device.
Therefore, the ADM1065 can have up to 10 analog inputs, a
minimum of five analog inputs and five digital inputs, or a
combination thereof. If an input is used as an analog input, it
cannot be used as a digital input. Therefore, a configuration
requiring 10 analog inputs has no available digital inputs. Table 6
shows the details of each input.
PROGRAMMING THE SUPPLY FAULT DETECTORS
The ADM1065 can have up to 10 SFDs on its 10 input channels.
These highly programmable reset generators enable the supervision
of up to 10 supply voltages. The supplies can be as low as 0.573 V
and as high as 14.4 V. The inputs can be configured to detect
an undervoltage fault (the input voltage drops below a prepro-
grammed value), an overvoltage fault (the input voltage rises
above a preprogrammed value), or an out-of-window fault (the
input voltage is outside a preprogrammed range). The thresholds
can be programmed to an 8-bit resolution in registers provided in
the ADM1065. This translates to a voltage resolution that is
dependent on the range selected.
The resolution is given by
Step Size = Threshold Range/255
Therefore, if the high range is selected on VH, the step size can
be calculated as follows:
(14.4 V − 6.0 V)/255 = 32.9 mV
Table 5 lists the upper and lower limits of each available range,
the bottom of each range (VB), and the range itself (VR).
Table 5. Voltage Range Limits
Voltage Range (V) VB (V) VR (V)
0.573 to 1.375 0.573 0.802
1.25 to 3.00 1.25 1.75
2.5 to 6.0 2.5 3.5
6.0 to 14.4 6.0 8.4
The threshold value required is given by
VT = (VR × N)/255 + VB
where:
VT is the desired threshold voltage (undervoltage or overvoltage).
VR is the voltage range.
N is the decimal value of the 8-bit code.
VB is the bottom of the range.
Reversing the equation, the code for a desired threshold is given by
N = 255 × (VT − VB)/VR
For example, if the user wants to set a 5 V overvoltage threshold
on VP1, the code to be programmed in the PS1OVTH register
(as discussed in the AN-698 Application Note at www.analog.com)
is given by
N = 255 × (5 − 2.5)/3.5
Therefore, N = 182 (1011 0110 or 0xB6).
INPUT COMPARATOR HYSTERESIS
The UV and OV comparators shown in Figure 16 are always
monitoring VPx. To avoid chatter (multiple transitions when the
input is very close to the set threshold level), these comparators
have digitally programmable hysteresis. The hysteresis can be
programmed up to the values shown in Table 6.
04634-023
+
–
+
–
UV
COMPARATOR
VREF
FAULT TYPE
SELECT
OV
COMPARATOR
FAULT
OUTPUT
GLITCH
FILTER
VPx
MID
LOW
RANGE
SELECT
ULTRA
LOW
Figure 16. Supply Fault Detector Block
The hysteresis is added after a supply voltage goes out of
tolerance. Therefore, the user can program the amount above
the undervoltage threshold to which the input must rise before
an undervoltage fault is deasserted. Similarly, the user can program
the amount below the overvoltage threshold to which an input
must fall before an overvoltage fault is deasserted.
Table 6. Input Functions, Thresholds, and Ranges
Input Function Voltage Range (V) Maximum Hysteresis Voltage Resolution (mV) Glitch Filter (μs)
VH High Voltage Analog Input 2.5 to 6.0 425 mV 13.7 0 to 100
6.0 to 14.4 1.02 V 32.9 0 to 100
VPx Positive Analog Input 0.573 to 1.375 97.5 mV 3.14 0 to 100
1.25 to 3.00 212 mV 6.8 0 to 100
2.5 to 6.0 425 mV 13.7 0 to 100
VXx High-Z Analog Input 0.573 to 1.375 97.5 mV 3.14 0 to 100
Digital Input 0 to 5.0 N/A N/A 0 to 100
ADM1065
Rev. D | Page 13 of 28
The hysteresis value is given by
VHYST = VR × NTHRESH/255
where:
VHYST is the desired hysteresis voltage.
NTHRESH is the decimal value of the 5-bit hysteresis code.
Note that NTHRESH has a maximum value of 31. The maximum
hysteresis for the ranges is listed in Table 6.
INPUT GLITCH FILTERING
The final stage of the SFDs is a glitch filter. This block provides
time-domain filtering on the output of the SFD comparators,
which allows the user to remove any spurious transitions such
as supply bounce at turn-on. The glitch filter function is in addition
to the digitally programmable hysteresis of the SFD comparators.
The glitch filter timeout is programmable up to 100 μs.
For example, when the glitch filter timeout is 100 μs, any pulse
appearing on the input of the glitch filter block that is less than
100 μs in duration is prevented from appearing on the output of
the glitch filter block. Any input pulse that is longer than 100 μs
appears on the output of the glitch filter block. The output is
delayed with respect to the input by 100 μs. The filtering process
is shown in Figure 17.
04634-024
t
0
t
GF
t
0
t
GF
t
0
t
GF
t
0
t
GF
INPUT
INPUT PULSE SHORTER
THAN G L I T CH F ILTE R TIMEOUT INPUT PULSE LONGE
R
THAN GLITCH FILTER TIMEOUT
OUTPUT
PROGRAMMED
TIMEOUT PROGRAMMED
TIMEOUT
INPUT
OUTPUT
Figure 17. Input Glitch Filter Function
SUPPLY SUPERVISION WITH VXx INPUTS
The VXx inputs have two functions. They can be used as either
supply fault detectors or digital logic inputs. When selected as
analog (SFD) inputs, the VXx pins have functionality that is
very similar to the VH and VPx pins. The primary difference is
that the VXx pins have only one input range: 0.573 V to 1.375 V.
Therefore, these inputs can directly supervise only the very
low supplies. However, the input impedance of the VXx pins
is high, allowing an external resistor divide network to be
connected to the pin. Thus, potentially any supply can be
divided down into the input range of the VXx pin and
supervised. This enables the ADM1065 to monitor other
supplies, such as +24 V, +48 V, and −5 V.
An additional supply supervision function is available when the
VXx pins are selected as digital inputs. In this case, the analog
function is available as a second detector on each of the dedi-
cated analog inputs, VPx and VH. The analog function of VX1
is mapped to VP1, VX2 is mapped to VP2, and so on. VX5 is
mapped to VH. In this case, these SFDs can be viewed as secondary
or warning SFDs.
The secondary SFDs are fixed to the same input range as the
primary SFDs. They are used to indicate warning levels rather
than failure levels. This allows faults and warnings to be generated
on a single-supply using only one pin. For example, if VP1 is set
to output a fault when a 3.3 V supply drops to 3.0 V, VX1 can be
set to output a warning at 3.1 V. Warning outputs are available for
readback from the status registers. They are also OR’ed together and
fed into the SE, allowing warnings to generate interrupts on the
PDOs. Therefore, in this example, if the supply drops to 3.1 V,
a warning is generated, and remedial action can be taken before
the supply drops out of tolerance.
VXx PINS AS DIGITAL INPUTS
As discussed in the Supply Supervision with VXX Inputs section,
the VXx input pins on the ADM1065 have dual functionality.
The second function is as a digital logic input to the device.
Therefore, the ADM1065 can be configured for up to five digital
inputs. These inputs are TTL-/CMOS-compatible. Standard logic
signals can be applied to the pins, RESET from reset generators,
PWRGD signals, fault flags, manual resets, and more. These signals
are available as inputs to the SE and, therefore, can be used to
control the status of the PDOs. The inputs can be configured to
detect either a change in level or an edge.
When configured for level detection, the output of the digital
block is a buffered version of the input. When configured for edge
detection, a pulse of programmable width is output from the
digital block, once the logic transition is detected. The width is
programmable from 0 μs to 100 μs.
The digital blocks feature the same glitch filter function that is
available on the SFDs. This function enables the user to ignore
spurious transitions on the inputs. For example, the filter can be
used to debounce a manual reset switch.
When configured as digital inputs, each VXx pin has a weak
(10 μA) pull-down current source available for placing the input
into a known condition, even if left floating. The current source,
if selected, weakly pulls the input to GND.
04634-027
DETECTOR
VXx
(DIGITAL INPUT) GLITCH
FILTER
VREF = 1.4V
TO
SEQUENCING
ENGINE
+
–
Figure 18. VXx Digital Input Function
ADM1065
Rev. D | Page 14 of 28
OUTPUTS
SUPPLY SEQUENCING THROUGH
CONFIGURABLE OUTPUT DRIVERS
The data driving each of the PDOs can come from one of three
sources. The source can be enabled in the PDOxCFG configu-
ration register (see the AN-698 Application Note for details).
Supply sequencing is achieved with the ADM1065 using the
programmable driver outputs (PDOs) on the device as control
signals for supplies. The output drivers can be used as logic
enables or as FET drivers.
The data sources are as follows:
• Output from the SE.
• Directly from the SMBus. A PDO can be configured so that
the SMBus has direct control over it. This enables software
control of the PDOs. Therefore, a microcontroller can be
used to initiate a software power-up/power-down sequence.
The sequence in which the PDOs are asserted (and, therefore,
the supplies are turned on) is controlled by the sequencing engine
(SE). The SE determines what action is taken with the PDOs,
based on the condition of the ADM1065 inputs. Therefore, the
PDOs can be set up to assert when the SFDs are in tolerance, the
correct input signals are received on the VXx digital pins, no
warnings are received from any of the inputs of the device, and at
other times. The PDOs can be used for a variety of functions. The
primary function is to provide enable signals for LDOs or dc-to-dc
converters that generate supplies locally on a board. The PDOs
can also be used to provide a PWRGD signal when all the SFDs
are in tolerance or a RESET output if one of the SFDs goes out
of specification (this can be used as a status signal for a DSP, FPGA,
or other microcontroller).
• On-chip clock. A 100 kHz clock is generated on the device.
This clock can be made available on any of the PDOs. It can be
used, for example, to clock an external device such as an LED.
DEFAULT OUTPUT CONFIGURATION
All of the internal registers in an unprogrammed ADM1065
device from the factory are set to 0. Because of this, the PDOx pins
are pulled to GND by a weak (20 kΩ) on-chip pull-down resistor.
As the input supply to the ADM1065 ramps up on VPx or VH,
all PDOx pins behave as follows:
• Input supply = 0 V to 1.2 V. The PDOs are high impedance.
The PDOs can be programmed to pull up to a number of different
options. The outputs can be programmed as follows:
• Input supply = 1.2 V to 2.7 V. The PDOs are pulled to
GND by a weak (20 kΩ) on-chip pull-down resistor.
• Supply > 2.7 V. Factory programmed devices continue to pull
all PDOs to GND by a weak (20 kΩ) on-chip pull-down
resistor. Programmed devices download current EEPROM
configuration data, and the programmed setup is latched. The
PDO then goes to the state demanded by the configuration.
This provides a known condition for the PDOs during
power-up.
• Open drain (allowing the user to connect an external pull-
up resistor).
• Open drain with weak pull-up to VDD.
• Open drain with strong pull-up to VDD.
• Open drain with weak pull-up to VPx.
• Open drain with strong pull-up to VPx.
• Strong pull-down to GND.
The internal pull-down can be overdriven with an external pull-
up of suitable value tied from the PDOx pin to the required pull-up
voltage. The 20 kΩ resistor must be accounted for in calculating
a suitable value. For example, if PDOx must be pulled up to 3.3 V,
and 5 V is available as an external supply, the pull-up resistor
value is given by
• Internally charge-pumped high drive
(12 V, PDO1 to PDO6 only).
The last option (available only on PDO1 to PDO6) allows the
user to directly drive a voltage high enough to fully enhance an
external N-FET, which is used to isolate, for example, a card-
side voltage from a backplane supply (a PDO can sustain greater
than 10.5 V into a 1 μA load). The pull-down switches can also
be used to drive status LEDs directly.
3.3 V = 5 V × 20 kΩ/(RUP + 20 kΩ)
Therefore,
RUP = (100 kΩ − 66 kΩ)/3.3 V = 10 kΩ
04634-028
PDO
SE DATA
CFG4 CFG5 CFG6
SMBus DATA
CLK DATA
10Ω
20kΩ
10Ω
20kΩ
VP1
SEL VP4
10Ω
20kΩ
V
DD
V
FET (PDO1 TO PDO6 ONLY)
20kΩ
Figure 19. Programmable Driver Output
ADM1065
Rev. D | Page 15 of 28
SEQUENCING ENGINE
OVERVIEW
The ADM1065 sequencing engine (SE) provides the user with
powerful and flexible control of sequencing. The SE implements
a state machine control of the PDO outputs with state changes
conditional on input events. SE programs can enable complex
control of boards such as power-up and power-down sequence
control, fault event handling, and interrupt generation on
warnings, among others. A watchdog function that verifies the
continued operation of a processor clock can be integrated into
the SE program. The SE can also be controlled via the SMBus,
giving software or firmware control of the board sequencing.
The SE state machine comprises 63 state cells. Each state has the
following attributes:
• Monitors signals indicating the status of the 10 input pins,
VP1 to VP4, VH, and VX1 to VX5.
• Can be entered from any other state.
• Three exit routes move the state machine onto a next state:
sequence detection, fault monitoring, and timeout.
• Delay timers for the sequence and timeout blocks can be
programmed independently, and changed with each state
change. The range of timeouts is from 0 ms to 400 ms.
• Output condition of the 10 PDO pins is defined and fixed
within a state.
• Transition from one state to the next is made in less than
20 μs, which is the time needed to download a state
definition from EEPROM to the SE.
04634-029
SEQUENCE
TIMEOUT
MONITOR
FAULT STATE
Figure 20. State Cell
The ADM1065 offers up to 63 state definitions. The signals
monitored to indicate the status of the input pins are the outputs
of the SFDs.
WARNINGS
The SE also monitors warnings. These warnings can be generated
when the ADC readings violate their limit register value or when
the secondary voltage monitors on VPx and VH are triggered.
The warnings are OR’ed together and are available as a single
warning input to each of the three blocks that enable exiting a state.
SMBus JUMP (UNCONDITIONAL JUMP)
The SE can be forced to advance to the next state unconditionally.
This enables the user to force the SE to advance. Examples of
the use of this feature include moving to a margining state or
debugging a sequence. The SMBus jump or go-to command can
be seen as another input to sequence and timeout blocks to provide
an exit from each state.
Table 7. Sample Sequence State Entries
State Sequence Timeout Monitor
IDLE1 If VX1 is low, go to State IDLE2.
IDLE2 If VP1 is okay, go to State EN3V3.
EN3V3 If VP2 is okay, go to State EN2V5. If VP2 is not okay after 10 ms,
go to State DIS3V3.
If VP1 is not okay, go to State IDLE1.
DIS3V3 If VX1 is high, go to State IDLE1.
EN2V5 If VP3 is okay, go to State PWRGD. If VP3 is not okay after 20 ms,
go to State DIS2V5.
If VP1 or VP2 is not okay, go to State FSEL2.
DIS2V5 If VX1 is high, go to State IDLE1.
FSEL1 If VP3 is not okay, go to State DIS2V5. If VP1 or VP2 is not okay, go to State FSEL2.
FSEL2 If VP2 is not okay, go to State DIS3V3. If VP1 is not okay, go to State IDLE1.
PWRGD If VX1 is high, go to State DIS2V5. If VP1, VP2, or VP3 is not okay, go to State FSEL1.
ADM1065
Rev. D | Page 16 of 28
SEQUENCING ENGINE APPLICATION EXAMPLE
The application in this section demonstrates the operation of
the SE. Figure 22 shows how the simple building block of a
single SE state can be used to build a power-up sequence for a
three-supply system. Table 8 lists the PDO outputs for each state
in the same SE implementation. In this system, a good 5 V supply
on VP1 and the VX1 pin held low are the triggers required to
start a power-up sequence. The sequence next turns on the 3.3 V
supply, then the 2.5 V supply (assuming successful turn-on of
the 3.3 V supply). When all three supplies have turned on correctly,
the PWRGD state is entered, where the SE remains until a fault
occurs on one of the three supplies or until it is instructed to go
through a power-down sequence by VX1 going high.
Faults are dealt with throughout the power-up sequence on a case-
by-case basis. The following three sections (the Sequence Detector
section, the Monitoring Fault Detector section, and the Timeout
Detector section) describe the individual blocks and use the
sample application shown in Figure 22 to demonstrate the
actions of the state machine.
Sequence Detector
The sequence detector block is used to detect when a step in
a sequence has been completed. It looks for one of the SE inputs
to change state, and is most often used as the gate for successful
progress through a power-up or power-down sequence. A timer
block that is included in this detector can insert delays into a
power-up or power-down sequence, if required. Timer delays
can be set from 10 μs to 400 ms. Figure 21 is a block diagram of
the sequence detector.
04634-032
SUPPLY FAULT
DETECTION
LOGIC INPUT CHANGE
OR FAULT DETECTION
WARNINGS
FORCE FLOW
(UNCONDITIONAL JUMP)
VP1
VX5
INVERT
SEQUENCE
DETECTOR
SELECT
TIMER
Figure 21. Sequence Detector Block Diagram
If a timer delay is specified, the input to the sequence detector
must remain in the defined state for the duration of the timer
delay. If the input changes state during the delay, the timer is reset.
The sequence detector can also help to identify monitoring
faults. In the sample application shown in Figure 22, the FSEL1
and FSEL2 states first identify which of the VP1, VP2, or VP3
pins has faulted, and then they take appropriate action.
04634-030
IDLE1
IDLE2
EN3V3
DIS3V3
DIS2V5PWRGD
FSEL1
FSEL2
SEQUENCE
STATES
MONITOR FAULT
STATES TIMEOUT
STATES
VX1 = 0
VP1 = 1
VP1 = 0
(VP1 + VP2) = 0
(VP1 + VP2 + VP3) = 0
(VP1 +
VP2) = 0
VP2 = 1
VP3 = 1
VP2 = 0
VX1 = 1
VP3 = 0
VP2 = 0
VP1 = 0
VX1 = 1
VX1 = 1
10ms
20ms
EN2V5
Figure 22. Sample Application Flow Diagram
Table 8. PDO Outputs for Each State
PDO Outputs IDLE1 IDLE2 EN3V3 EN2V5 DIS3V3 DIS2V5 PWRGD FSEL1 FSEL2
PDO1 = 3V3ON 0 0 1 1 0 1 1 1 1
PDO2 = 2V5ON 0 0 0 1 1 0 1 1 1
PDO3 = FAULT 0 0 0 0 1 1 0 1 1
ADM1065
Rev. D | Page 17 of 28
Monitoring Fault Detector
The monitoring fault detector block is used to detect a failure
on an input. The logical function implementing this is a wide
OR gate that can detect when an input deviates from its expected
condition. The clearest demonstration of the use of this block
is in the PWRGD state, where the monitor block indicates that
a failure on one or more of the VP1, VP2, or VP3 inputs has
occurred.
No programmable delay is available in this block because the
triggering of a fault condition is likely to be caused by a supply
falling out of tolerance. In this situation, the device needs to
react as quickly as possible. Some latency occurs when moving
out of this state, however, because it takes a finite amount of time
(~20 μs) for the state configuration to download from the
EEPROM into the SE. Figure 23 is a block diagram of the
monitoring fault detector.
04634-033
SUPPLY FAULT
DETECTION
LOGIC INPUT CHANGE
OR FAULT DETECTION
V
P1
V
X5
MONITORING FAULT
DETECTOR
MASK
SENSE
1-BIT FAULT
DETECTOR
FAULT
WARNINGS
MASK
1-BIT FAULT
DETECTOR
FAULT
MASK
SENSE
1-BIT FAULT
DETECTOR
FAULT
Figure 23. Monitoring Fault Detector Block Diagram
Timeout Detector
The timeout detector allows the user to trap a failure to ensure
proper progress through a power-up or power-down sequence.
In the sample application shown in Figure 22, the timeout next-
state transition is from the EN3V3 and EN2V5 states. For the
EN3V3 state, the signal 3V3ON is asserted on the PDO1 output
pin upon entry to this state to turn on a 3.3 V supply. This supply
rail is connected to the VP2 pin, and the sequence detector looks
for the VP2 pin to go above its undervoltage threshold, which is
set in the supply fault detector (SFD) attached to that pin.
The power-up sequence progresses when this change is detected.
If, however, the supply fails (perhaps due to a short circuit
overloading this supply), the timeout block traps the problem.
In this example, if the 3.3 V supply fails within 10 ms, the SE
moves to the DIS3V3 state and turns off this supply by bringing
PDO1 low. It also indicates that a fault has occurred by taking
PDO3 high. Timeout delays of 100 μs to 400 ms can be
programmed.
FAULT AND STATUS REPORTING
The ADM1065 has a fault latch for recording faults. Two registers,
FSTAT1 and FSTAT2, are set aside for this purpose. A single bit
is assigned to each input of the device, and a fault on that input sets
the relevant bit. The contents of the fault register can be read
out over the SMBus to determine which input(s) faulted. The
fault register can be enabled or disabled in each state. To latch
data from one state, ensure that the fault latch is disabled in the
following state. This ensures that only real faults are captured and
not, for example, undervoltage conditions that may be present
during a power-up or power-down sequence.
The ADM1065 also has a number of status registers. These
include more detailed information, such as whether an under-
voltage or overvoltage fault is present on a particular input. The
status registers also include information on ADC limit faults. Note
that the data in the status registers is not latched in any way and,
therefore, is subject to change at any time.
See the AN-698 Application Note at www.analog.com for full
details about the ADM1065 registers.
ADM1065
Rev. D | Page 18 of 28
APPLICATIONS DIAGRAM
04634-068
3.3V OUT
3.3V OUT
VH
PDO8
PDO9
SYSTE M RE SET
PDO7
PDO6
PDO2
PDO1
PDO5
PDO4
PDO3
EN OUT
DC-TO-DC1
IN
3.3V OUT
3V O UT
5V O UT
12V O UT
EN OUT
DC-TO-DC2
IN
2.5V OUT
EN OUT
DC-TO-DC3
IN
EN OUT
LDO
IN
1.8V OUT
0.9V OUT
1.2V OUT
5V O UT
12V IN
5V IN
3V IN
VP1
3V OUT VP2
3.3V OUT VP3
2.5V OUT VP4
1.8V OUT VX1
1.2V OUT VX2
0.9V OUT VX3
VX4
VX5
10µF
VCCP
10µF
VDDCAP
10µF
REFOUT GND
PDO10
ADM1065
SIGNAL VALID
PWRGD
POWRON
RESET
EN OUT
DC-TO-DC4
IN
Figure 24. Applications Diagram
ADM1065
Rev. D | Page 19 of 28
COMMUNICATING WITH THE ADM1065
CONFIGURATION DOWNLOAD AT POWER-UP
The configuration of the ADM1065 (undervoltage/overvoltage
thresholds, glitch filter timeouts, PDO configurations, and so
on) is dictated by the contents of the RAM. The RAM comprises
digital latches that are local to each of the functions on the device.
The latches are double-buffered and have two identical latches,
Latch A and Latch B. Therefore, when an update to a function
occurs, the contents of Latch A are updated first, and then the
contents of Latch B are updated with identical data. The advantages
of this architecture are explained in detail in the Updating the
Configuration section.
The two latches are volatile memory and lose their contents at
power-down. Therefore, the configuration in the RAM must be
restored at power-up by downloading the contents of the EEPROM
(nonvolatile memory) to the local latches. This download occurs
in steps, as follows:
1. With no power applied to the device, the PDOs are all high
impedance.
2. When 1.2 V appears on any of the inputs connected to the
VDD arbitrator (VH or VPx), the PDOs are all weakly
pulled to GND with a 20 kΩ resistor.
3. When the supply rises above the undervoltage lockout of
the device (UVLO is 2.5 V), the EEPROM starts to
download to the RAM.
4. The EEPROM downloads its contents to all Latch As.
5. When the contents of the EEPROM are completely
downloaded to the Latch As, the device controller signals
all Latch As to download to all Latch Bs simultaneously,
completing the configuration download.
6. At 0.5 ms after the configuration download completes, the
first state definition is downloaded from the EEPROM into
the SE.
Note that any attempt to communicate with the device prior to
the completion of the download causes the ADM1065 to issue
a no acknowledge (NACK).
UPDATING THE CONFIGURATION
After power-up, with all the configuration settings loaded from
the EEPROM into the RAM registers, the user may need to alter
the configuration of functions on the ADM1065, such as changing
the undervoltage or overvoltage limit of an SFD, changing the
fault output of an SFD, or adjusting the rise time delay of one of
the PDOs.
The ADM1065 provides several options that allow the user to
update the configuration over the SMBus interface. The following
three options are controlled in the UPDCFG register.
Option 1
Update the configuration in real time. The user writes to the RAM
across the SMBus and the configuration is updated immediately.
Option 2
Update the Latch As without updating the Latch Bs. With this
method, the configuration of the ADM1065 remains unchanged
and continues to operate in the original setup until the instruction
is given to update the Latch Bs.
Option 3
Change the EEPROM register contents without changing the RAM
contents, and then download the revised EEPROM contents to the
RAM registers. With this method, the configuration of the
ADM1065 remains unchanged and continues to operate in the
original setup until the instruction is given to update the RAM.
The instruction to download from the EEPROM in Option 3 is
also a useful way to restore the original EEPROM contents if
revisions to the configuration are unsatisfactory. For example,
if the user needs to alter an overvoltage threshold, the RAM
register can be updated, as described in Option 1. However, if
the user is not satisfied with the change and wants to revert to
the original programmed value, the device controller can issue a
command to download the EEPROM contents to the RAM
again, as described in Option 3, restoring the ADM1065 to its
original configuration.
The topology of the ADM1065 makes this type of operation
possible. The local, volatile registers (RAM) are all double-
buffered latches. Setting Bit 0 of the UPDCFG register to 1 leaves
the double-buffered latches open at all times. If Bit 0 is set to 0
when a RAM write occurs across the SMBus, only the first side
of the double-buffered latch is written to. The user must then
write a 1 to Bit 1 of the UPDCFG register. This generates a pulse
to update all the second latches at once. EEPROM writes occur
in a similar way.
The final bit in this register can enable or disable EEPROM
page erasure. If this bit is set high, the contents of an EEPROM
page can all be set to 1. If this bit is set low, the contents of
a page cannot be erased, even if the command code for page
erasure is programmed across the SMBus. The bit map for the
UPDCFG register is shown in the AN-698 Application Note at
www.analog.com. A flow diagram for download at power-up
and subsequent configuration updates is shown in Figure 25.
ADM1065
Rev. D | Page 20 of 28
04634-035
POWER-UP
(V
CC
> 2.5V)
EEPROM
E
E
P
R
O
M
L
D
D
A
T
A
R
A
M
L
D
U
P
D
SMBus
DEVICE
CONTROLLER
LATCH A LATCH B FUNCTION
(OV THRESHOLD
ON VP1)
Figure 25. Configuration Update Flow Diagram
UPDATING THE SEQUENCING ENGINE
Sequencing engine (SE) functions are not updated in the same
way as regular configuration latches. The SE has its own dedicated
512-byte, nonvolatile, electrically erasable, programmable, read-
only memory (EEPROM) for storing state definitions, providing
63 individual states, each with a 64-bit word (one state is reserved).
At power-up, the first state is loaded from the SE EEPROM into
the engine itself. When the conditions of this state are met, the
next state is loaded from the EEPROM into the engine, and so
on. The loading of each new state takes approximately 10 μs.
To alter a state, the required changes must be made directly to
the EEPROM. RAM for each state does not exist. The relevant
alterations must be made to the 64-bit word, which is then
uploaded directly to the EEPROM.
INTERNAL REGISTERS
The ADM1065 contains a large number of data registers. The
principal registers are the address pointer register and the
configuration registers.
Address Pointer Register
The address pointer register contains the address that selects
one of the other internal registers. When writing to the ADM1065,
the first byte of data is always a register address that is written to
the address pointer register.
Configuration Registers
The configuration registers provide control and configuration
for various operating parameters of the ADM1065.
EEPROM
The ADM1065 has two 512-byte cells of nonvolatile EEPROM
from Register Address 0xF800 to Register Address 0xFBFF. The
EEPROM is used for permanent storage of data that is not lost
when the ADM1065 is powered down. One EEPROM cell contains
the configuration data of the device; the other contains the state
definitions for the SE. Although referred to as read-only memory,
the EEPROM can be written to, as well as read from, using the
serial bus in exactly the same way as the other registers.
The major differences between the EEPROM and other registers
are as follows:
• An EEPROM location must be blank before it can be
written to. If it contains data, the data must first be erased.
• Writing to the EEPROM is slower than writing to the RAM.
• Writing to the EEPROM should be restricted because it has
a limited write/cycle life of typically 10,000 write operations,
due to the usual EEPROM wear-out mechanisms.
The first EEPROM is split into 16 (0 to 15) pages of 32 bytes each.
Page 0 to Page 6, starting at Address 0xF800, hold the configuration
data for the applications on the ADM1065 (such as the SFDs and
PDOs). These EEPROM addresses are the same as the RAM
register addresses, prefixed by F8. Page 7 is reserved. Page 8 to
Page 15 are for customer use.
Data can be downloaded from the EEPROM to the RAM in one
of the following ways:
• At power-up, when Page 0 to Page 6 are downloaded
• By setting Bit 0 of the UDOWNLD register (0xD8), which
performs a user download of Page 0 to Page 6
SERIAL BUS INTERFACE
The ADM1065 is controlled via the serial system management
bus (SMBus) and is connected to this bus as a slave device under
the control of a master device. It takes approximately 1 ms after
power-up for the ADM1065 to download from its EEPROM.
Therefore, access to the ADM1065 is restricted until the
download is complete.
Identifying the ADM1065 on the SMBus
The ADM1065 has a 7-bit serial bus slave address (see Tabl e 9 ).
The device is powered up with a default serial bus address.
The five MSBs of the address are set to 01011; the two LSBs are
determined by the logical states of Pin A1 and Pin A0. This
allows the connection of four ADM1065s to one SMBus.
Table 9. Serial Bus Slave Address
A1 Pin A0 Pin Hex Address 7-Bit Address
Low Low 0x58 0101100x1
Low High 0x5A 0101101x1
High Low 0x5C 0101110x1
High High 0x5E 0101111x1
1 x = Read/Write bit. The address is shown only as the first 7 MSBs.
ADM1065
Rev. D | Page 21 of 28
The device also has several identification registers (read-only)
that can be read across the SMBus. Table 1 0 lists these registers
with their values and functions.
Table 10. Identification Register Values and Functions
Name Address Value Function
MANID 0xF4 0x41 Manufacturer ID for Analog
Devices
REVID 0xF5 0x02 Silicon revision
MARK1 0xF6 0x00 Software brand
MARK2 0xF7 0x00 Software brand
General SMBus Timing
Figure 26, Figure 27, and Figure 28 are timing diagrams for
general read and write operations using the SMBus. The SMBus
specification defines specific conditions for different types of
read and write operations, which are discussed in the Wr ite
Operations and Read Operations sections.
The general SMBus protocol operates as follows:
Step 1
The master initiates data transfer by establishing a start condition,
defined as a high-to-low transition on the serial data-line SDA,
while the serial clock-line SCL remains high. This indicates that
a data stream follows. All slave peripherals connected to the serial
bus respond to the start condition and shift in the next eight bits,
consisting of a 7-bit slave address (MSB first) plus an R/W bit. This
bit determines the direction of the data transfer, that is, whether
data is written to or read from the slave device (0 = write, 1 = read).
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the acknowledge
bit (ACK), and holding it low during the high period of this
clock pulse.
All other devices on the bus remain idle while the selected device
waits for data to be read from or written to it. If the R/W bit is a 0,
the master writes to the slave device. If the R/W bit is a 1, the
master reads from the slave device.
Step 2
Data is sent over the serial bus in sequences of nine clock pulses:
eight bits of data followed by an acknowledge bit from the slave
device. Data transitions on the data line must occur during the
low period of the clock signal and remain stable during the high
period because a low-to-high transition when the clock is high
could be interpreted as a stop signal. If the operation is a write
operation, the first data byte after the slave address is a command
byte. This command byte tells the slave device what to expect next.
It may be an instruction telling the slave device to expect a block
write, or it may be a register address that tells the slave where
subsequent data is to be written. Because data can flow in only
one direction, as defined by the R/W bit, sending a command
to a slave device during a read operation is not possible. Before
a read operation, it may be necessary to perform a write operation
to tell the slave what sort of read operation to expect and the
address from which data is to be read.
Step 3
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line high
during the 10th clock pulse to assert a stop condition. In read
mode, the master device releases the SDA line during the low
period before the ninth clock pulse, but the slave device does
not pull it low. This is known as a no acknowledge. The master
then takes the data line low during the low period before the
10th clock pulse and then high during the 10th clock pulse to
assert a stop condition.
04634-036
19 91
1919
START BY
MASTER ACK. BY
SLAVE ACK. B Y
SLAVE
ACK. B Y
SLAVE ACK. BY
SLAVE
FRAME 2
COMM AND CO DE
FRAME 1
SLAVE ADDRESS
FRAME N
DATA BYTE
FRAME 3
DATA BYTE
SCL
SDA R/W
STOP
BY
MASTER
SCL
(CONTINUED)
SDA
(CONTINUED)
D7A0A11010 1 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 26. General SMBus Write Timing Diagram
ADM1065
Rev. D | Page 22 of 28
9
04634-037
19 91
191
START BY
MASTER ACK. BY
SLAVE ACK. B Y
MASTER
ACK. B Y
MASTER NO ACK.
FRAME 2
DATA BYTE
FRAME 1
SLAVE ADDRESS
FRAME N
DATA BYTE
FRAME 3
DATA BYTE
SCL
SDA R/W
STOP
BY
MASTER
SCL
(CONTINUED)
SDA
(CONTINUED)
D7A0A11010 1 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 27. General SMBus Read Timing Diagram
04634-038
SCL
SDA
PS S P
tSU;STO
tHD;STA
tSU;STA
tSU;DAT
tHD;DAT
tHD;STA tHIGH
tBUF
tLOW
tRtF
Figure 28. Serial Bus Timing Diagram
ADM1065
Rev. D | Page 23 of 28
SMBus PROTOCOLS FOR RAM AND EEPROM
The ADM1065 contains volatile registers (RAM) and nonvolatile
registers (EEPROM). User RAM occupies Address 0x00 to
Address 0xDF; the EEPROM occupies Address 0xF800 to
Address 0xFBFF.
Data can be written to and read from both the RAM and the
EEPROM as single data bytes. Data can be written only to
unprogrammed EEPROM locations. To write new data to
a programmed location, the location contents must first be
erased. EEPROM erasure cannot be done at the byte level. The
EEPROM is arranged as 32 pages of 32 bytes each, and an entire
page must be erased.
Page erasure is enabled by setting Bit 2 in the UPDCFG register
(Address 0x90) to 1. If this bit is not set, page erasure cannot
occur, even if the command byte (0xFE) is programmed across
the SMBus.
WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The following abbreviations
are used in Figure 29 to Figure 37:
• S = Start
• P = Stop
• R = Read
• W = Write
• A = Acknowledge
• A = No acknowledge
The ADM1065 uses the following SMBus write protocols.
Send Byte
In a send byte operation, the master device sends a single
command byte to a slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by
the write bit (low).
3. The addressed slave device asserts an acknowledge (ACK)
on SDA.
4. The master sends a command code.
5. The slave asserts an ACK on SDA.
6. The master asserts a stop condition on SDA and
the transaction ends.
In the ADM1065, the send byte protocol is used for two purposes:
• To write a register address to the RAM for a subsequent
single byte read from the same address or for a block read
or a block write starting at that address, as shown in Figure 29.
04634-039
2413 5
SLAVE
ADDRESS RAM
ADDRESS
(0x00 TO 0xDF)
SWA A
6
P
Figure 29. Setting a RAM Address for Subsequent Read
• To erase a page of EEPROM memory. EEPROM memory
can be written to only if it is unprogrammed. Before writing
to one or more EEPROM memory locations that are already
programmed, the page(s) containing those locations must
first be erased. EEPROM memory is erased by writing a
command byte.
The master sends a command code telling the slave device to
erase the page. The ADM1065 command code for a page
erasure is 0xFE (1111 1110). Note that for a page erasure to
take place, the page address must be given in the previous
write word transaction (see the Write Byte/Word section).
In addition, Bit 2 in the UPDCFG register (Address 0x90)
must be set to 1.
04634-040
2413
SLAVE
ADDRESS COMMAND
BYTE
(0xFE)
SWA A
56
P
Figure 30. EEPROM Page Erasure
As soon as the ADM1065 receives the command byte,
page erasure begins. The master device can send a stop
command as soon as it sends the command byte. Page
erasure takes approximately 20 ms. If the ADM1065 is
accessed before erasure is complete, it responds with
a no acknowledge (NACK).
ADM1065
Rev. D | Page 24 of 28
8
Write Byte/Word
In a write byte/word operation, the master device sends a
command byte and one or two data bytes to the slave device,
as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts an ACK on SDA.
4. The master sends a command code.
5. The slave asserts an ACK on SDA.
6. The master sends a data byte.
7. The slave asserts an ACK on SDA.
8. The master sends a data byte or asserts a stop condition.
9. The slave asserts an ACK on SDA.
10. The master asserts a stop condition on SDA to end the
transaction.
In the ADM1065, the write byte/word protocol is used for three
purposes:
• To write a single byte of data to the RAM. In this case, the
command byte is RAM Address 0x00 to RAM Address
0xDF, and the only data byte is the actual data, as shown in
Figure 31.
04634-041
SLAVE
ADDRESS RAM
ADDRESS
(0x00 TO 0xDF)
S W A DATAAPA
2413 576
Figure 31. Single Byte Write to the RAM
• To set up a 2-byte EEPROM address for a subsequent read,
write, block read, block write, or page erase. In this case,
the command byte is the high byte of EEPROM Address
0xF8 to EEPROM Address 0xFB. The only data byte is the
low byte of the EEPROM address, as shown in Figure 32.
04634-042
SLAVE
ADDRESS
EEPROM
ADDRESS
HIGH BYTE
(0xF8 TO 0xFB)
SWA EEPROM
ADDRESS
LOW BYTE
(0x00 TO 0xFF)
APA
2413 5 76 8
Figure 32. Setting an EEPROM Address
Because a page consists of 32 bytes, only the three MSBs of the
address low byte are important for page erasure. The lower
five bits of the EEPROM address low byte specify the
addresses within a page and are ignored during an erase
operation.
• To write a single byte of data to the EEPROM. In this case,
the command byte is the high byte of EEPROM Address 0xF8
to EEPROM Address 0xFB. The first data byte is the low
byte of the EEPROM address, and the second data byte is
the actual data, as shown in Figure 33.
04634-043
SLAVE
ADDRESS
EEPROM
ADDRESS
HIGH BYTE
(0xF8 TO 0xFB)
SWA EEPROM
ADDRESS
LOW BYTE
(0x00 TO 0xFF)
APA
2413 5 7
A
9
DATA
86 10
Figure 33. Single Byte Write to the EEPROM
Block Write
In a block write operation, the master device writes a block of data
to a slave device. The start address for a block write must be set
previously. In the ADM1065, a send byte operation sets a RAM
address, and a write byte/word operation sets an EEPROM address,
as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by
the write bit (low).
3. The addressed slave device asserts an ACK on SDA.
4. The master sends a command code that tells the slave
device to expect a block write. The ADM1065 command
code for a block write is 0xFC (1111 1100).
5. The slave asserts an ACK on SDA.
6. The master sends a data byte that tells the slave device how
many data bytes are being sent. The SMBus specification
allows a maximum of 32 data bytes in a block write.
7. The slave asserts an ACK on SDA.
8. The master sends N data bytes.
9. The slave asserts an ACK on SDA after each data byte.
10. The master asserts a stop condition on SDA to end the
transaction.
04634-044
SLAVE
ADDRESS
SWA
2
COMMAND 0xFC
(BLOCK WRITE)
413
A
5
BYTE
COUNT
6
A
7
A
910
A PA
DATA
1
8
DATA
N
DATA
2
Figure 34. Block Write to the EEPROM or RAM
Unlike some EEPROM devices that limit block writes to within
a page boundary, there is no limitation on the start address
when performing a block write to EEPROM, except when
• There must be at least N locations from the start address to
the highest EEPROM address (0xFBFF) to avoid writing to
invalid addresses.
• An address crosses a page boundary. In this case, both
pages must be erased before programming.
Note that the ADM1065 features a clock extend function for writes
to the EEPROM. Programming an EEPROM byte takes approxi-
mately 250 μs, which limits the SMBus clock for repeated or
block write operations. The ADM1065 pulls SCL low and extends
the clock pulse when it cannot accept any more data.
ADM1065
Rev. D | Page 25 of 28
6
9. The ADM1065 sends a byte-count data byte that tells the
master how many data bytes to expect. The ADM1065
always returns 32 data bytes (0x20), which is the maximum
allowed by the SMBus Version 1.1 specification.
READ OPERATIONS
The ADM1065 uses the following SMBus read protocols.
Receive Byte
10. The master asserts an ACK on SDA.
In a receive byte operation, the master device receives a single
byte from a slave device, as follows: 11. The master receives 32 data bytes.
12. The master asserts an ACK on SDA after each data byte.
1. The master device asserts a start condition on SDA. 13. The master asserts a stop condition on SDA to end the
transaction.
2. The master sends the 7-bit slave address followed by the
read bit (high).
3. The addressed slave device asserts an ACK on SDA.
04634-046
SLAVE
ADDRESS
SWA
2
COMMAND 0xFD
(BLO CK READ)
413
A
5
S
6
SLAVE
ADDRESS
7
BYTE
COUNT
91011
ARA
8
DATA
1
DATA
32
12
A
13
P
A
4. The master receives a data byte.
5. The master asserts a NACK on SDA.
6. The master asserts a stop condition on SDA, and the
transaction ends.
In the ADM1065, the receive byte protocol is used to read a
single byte of data from a RAM or EEPROM location whose
address has previously been set by a send byte or write byte/word
operation, as shown in Figure 35.
Figure 36. Block Read from the EEPROM or RAM
Error Correction
The ADM1065 provides the option of issuing a packet error
correction (PEC) byte after a write to the RAM, a write to the
EEPROM, a block write to the RAM/EEPROM, or a block read
from the RAM/ EEPROM. This option enables the user to verify
that the data received by or sent from the ADM1065 is correct.
The PEC byte is an optional byte sent after the last data byte is
written to or read from the ADM1065. The protocol is the same
as a block read for Step 1 to Step 12 and then proceeds as follows:
04634-045
23145
SLAVE
ADDRESS
S R DATA PA A
Figure 35. Single Byte Read from the EEPROM or RAM
Block Read
In a block read operation, the master device reads a block of
data from a slave device. The start address for a block read must
have been set previously. In the ADM1065, this is done by a
send byte operation to set a RAM address, or a write byte/word
operation to set an EEPROM address. The block read operation
itself consists of a send byte operation that sends a block read
command to the slave, immediately followed by a repeated start
and a read operation that reads out multiple data bytes, as follows:
13. The ADM1065 issues a PEC byte to the master. The master
checks the PEC byte and issues another block read, if the PEC
byte is incorrect.
14. A NACK is generated after the PEC byte to signal the end
of the read.
15. The master asserts a stop condition on SDA to end the
transaction.
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low). Note that the PEC byte is calculated using CRC-8. The frame
check sequence (FCS) conforms to CRC-8 by the polynomial
3. The addressed slave device asserts an ACK on SDA. C(x) = x8 + x2 + x1 + 1
4. The master sends a command code that tells the slave
device to expect a block read. The ADM1065 command
code for a block read is 0xFD (1111 1101).
See the SMBus Version 1.1 specification for details.
An example of a block read with the optional PEC byte is shown
in Figure 37.
5. The slave asserts ACK on SDA.
6. The master asserts a repeat start condition on SDA.
04634-047
SLAVE
ADDRESS
SWA
2
COMMAND 0xFD
(BLOCK READ)
413
A
5
S
6
SLAVE
ADDRESS
7
BYTE
COUNT
910 1211
ARA
8
DATA
1
DATA
32 A
13
PEC
14
A
15
P
A
7. The master sends the 7-bit slave address followed by the
read bit (high).
8. The slave asserts an ACK on SDA.
Figure 37. Block Read from the EEPROM or RAM with PEC
ADM1065
Rev. D | Page 26 of 28
OUTLINE DIMENSIONS
1
40
10
11
31
30
21
20
4.25
4.10 SQ
3.95
TOP
VIEW
6.00
BSC SQ
PIN 1
INDICATOR 5.75
BSC SQ
12° MAX
0.30
0.23
0.18 0.20 REF
SEATING
PLANE
1.00
0.85
0.80
0.05 M AX
0.02 NOM
COPLANARITY
0.08
0.80 MAX
0.65 TY P
4.50
REF
0.50
0.40
0.30
0.50
BSC
PIN 1
INDICATOR
0.60 MAX
0.60 MAX
0.25 MI N
EXPOSED
PAD
(BO TTOM VIEW)
COM P LI ANT TO JEDE C STANDARDS MO -220-V JJD- 2
072108-A
FOR PROPER CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE P IN CO NFI GURATION AND
FUNCTI ON DES CRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 38. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MS-026ABC
0.50
BSC
LEAD PITCH
0.27
0.22
0.17
9.00
BSC SQ
7.00
BSC SQ
1.20
MAX
TOP VIEW
(PINS DOWN)
1
12 13 25
24
36
37
48
0.75
0.60
0.45
PIN 1
VIEW A
1.05
1.00
0.95
0.20
0.09
0.08 MAX
COPLANARITY
SEATING
PLANE
0° MIN
7°
3.5°
0°
0.15
0.05
VIEW A
ROTATED 90° CCW
Figure 39. 48-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADM1065ACPZ −40°C to +85°C 40-Lead LFCSP_VQ CP-40-1
ADM1065ASUZ −40°C to +85°C 48-Lead TQFP SU-48
EVAL-ADM1065TQEBZ Evaluation Kit (TQFP Version)
1 Z = RoHS Compliant Part.
ADM1065
Rev. D | Page 27 of 28
NOTES
ADM1065
Rev. D | Page 28 of 28
NOTES
©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04634-0-6/11(D)
