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STRUCTURE Silicon Monolithic Integrated Circuit
PRODUCT NAME Overvoltage Protection Controller with Internal FET
MODEL NAME BD6042GUL
FEATURES ●Overvoltage Protection up to 28V
●Internal Low Ron (125m Ω) FET
●Over voltage Lockout (OVLO)
●Under voltage Lockout(U VLO)
●Internal 2msec Startup Delay
●Over Current Protect
●Thermal Shut Down
●Small package : VCSP50L1( 1. 6mm x 1.6mm, height=0.55mm)
● Absolute maximum ratings (Ta=25℃)
Contents Symbol Rating Unit Conditions
Input supply voltage 1 Vmax1 -0.3～30 V IN
Input supply voltage 2 Vmax2 -0.3～7 V other
Power dissipation Pd 725 mW
Operating temperature range Topr -35～+85 ℃
Storage temperature range Tstr -55～+150 ℃
※1 When using more than at Ta=25℃, it is reduced 5.8 mW per 1℃.
ROHM specification boar d 50mm× 58mm mounting.
● Operating range (Ta=-35～+85℃)
Parameter Symbol Range Unit Usage
Input voltage range Vin 2.2～28 V
※ This product is not especially designed to be protected from radioactivity.
Status of this document.
The Japanese version of this document is the formal specification.
A customer may use this translation version only for reference to help reading the formal version.
If there are any differences in translation version of this document, formal version takes priority.
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● Electrical Characteristics (Unless otherwise noted, Ta = 25°C, IN=5V)
Parameter Symbol Rating Unit Conditions
Min. Typ. Max.
● ELECTRICAL
Input Voltage Range VIN - - 28 V
Supply Quiescent Current ICC 45 90
μ
A
Under Voltage Lockout UVLO 2.53 2.65 2.77 V IN=decreasing
Under Voltage Lockout Hysteresis UVLOh 50 100 150 mV IN=increasing
Over Voltage Lockout OVLO 6.0 6.2 6.4 V IN=increasing
Over Voltage Lockout Hysteresis OVLOh 50 100 150 mV IN=decreasing
Current limit ILM 1.2 - - A
Vin vs. Vout Res. RON - 125 150 m
Ω
OK Output Low Voltage OKVO - - 400 mV SINK=1mA
OK Leakage Current OKleak - - 1
μ
A
EN input voltage (H) ENH 1.45 - - V
EN input voltage (L) ENL - - 0.5 V
EN input current ENC 12 25 50
μ
A
EN=1.5V
● TIMINGS
Start Up Delay Ton - 2 4 msec
OK Going Up Delay Tok - 10 15 msec
Output T urn Off Ti me Tof f - 2 10
μ
sec
Alert Delay Tovp - 1.5 10
μ
sec
* This product is not especially designed to be protected from radioactivity.
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● Block Diagram ● PIN number/PIN name
● PIN DESCRIPTIONS
PIN NAME FUNCTION
A2, A3
B2, B3 IN1, 2,
3, 4 Input voltage Pin. A 1
μ
F low ESR capacitor,
or larger must be connected between this pin and GND
A1, B1 OUT1, 2 Output Voltage Pin
C1 OK Active-low open drain output to signal if the adapter voltage is correct
C3 GND Ground Pin
C2 EN Enable input Drive EN high to turn off OUT (Hi-z output)
● Package Dimensions (VCSP50L1)
Pin
number Pin name
A2 IN1
A3 IN2
B2 IN3
B3 IN4
A1 OUT1
B1 OUT2
C3 GND
C1 OK
C2 EN
6042
LOT No.
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●Use-related Cautions
(1) Absolute maximum ratings
If applied voltage (VDD, VIN), operating temperature range (Topr), or other absolute maximum ratings are exceeded, there is a risk of
damage.Since it is not possible to identify short, open, or other damage modes, if special modes in which absolute maximum ratings are exceeded
are assumed, consider applying fuses or other physical safety measures.
(2) Recommended operating range
This is the range within which it is possible to obtain roughly the expected characteristics. For electrical characteristics, it is those that are
guaranteed under the conditions for each parameter. Even when these are within the recommended operating range, voltage and temperature
characteristics are indicated.
(3) Reverse connection of power supply connector
There is a risk of damaging the LSI by reverse connection of the power supply connector. For protection from reverse connection, take measures
such as externally placing a diode between the power supply and the power supply pin of the LSI.
(4) Power supply lines
In the design of the board pattern, make power supply and GND line wiring low impedance.
When doing so, although the digital power supply and analog power supply are the same potential, separate the digital power supply pattern and
analog power supply pattern to deter digital noise from entering the analog power supply due to the common impedance of the wiring patterns.
Similarly take pattern design into account for GND lines as well.
Furthermore, for all power supply pins of the LSI, in conjunction with inserting capacitors between power supply and GND pins, when using
electrolytic capacitors, determine constants upon adequately confirming that capacitance loss occurring at low temperatures is not a problem for
various characteristics of the capacitors used.
(5) GND voltage
Make the potential of a GND pin such that it will be the lowest potential even if operating below that. In addition, confirm that there are no pins
for which the potential becomes less than a GND by actually including transition phenomena.
(6) Shorts between pins and misinstallation
When installing in the set board, pay adequate attention to orientation and placement discrepancies of the LSI. If it is installed erroneously, there
is a risk of LSI damage. There also is a risk of damage if it is shorted by a foreign substance getting between pins or between a pin and a power
supply or GND.
(7) Operation in strong magnetic fields
Be careful when using the LSI in a strong magnetic field, since it may malfunction.
(8) Inspection in set board
When inspecting the LSI in the set board, since there is a risk of stress to the LSI when capacitors are connected to low impedance LSI pins, be
sure to discharge for each process. Moreover, when getting it on and off of a jig in the inspection process, always connect it after turning off the
power supply, perform the inspection, and remove it after turning off the power supply. Furthermore, as countermeasures against static elect ricit y,
use grounding in the assembly process and take appropriate care in transport and storage.
(9) Input pins
Parasitic elements inevitably are formed on an LSI structure due to pote ntial relationships. Because parasitic elements operate, they give rise to
interference with circuit operation and may be the cause of malfunctions as well as damage. Accordingly, take care not to apply a lower voltage
than GND to an input pin or use the LSI in other ways such that parasitic elements operate. Moreover, do not apply a voltage to an input pin
when the power supply voltage is not being applied to the LSI. Furthermore, when the power supply voltage is being applied, make each input
pin a voltage less than the power supply voltage as well as within the guaranteed values of electrical characteristics.
(10) Ground wiring pattern
When there is a small signal GND and a large current GND, it is recommended that you separate the large current GND pattern and small signal
GND pattern and provide single point grounding at the reference point of the set so that voltage variation due to resistance components of the
pattern wiring and large currents do not cause the small signal GND voltage to change. Take care that the GND wiring pattern of externally
attached components also does not change.
(11) Externally attached capacitors
When using ceramic capacitors for externally attached capacitors, deter mine constants upon taking into account a lowering of the rated capacitance
due to DC bias and capacitance change due to factors such as temperature.
(12) Thermal shutdown circuit (TSD)
When the junction temperature reaches the defined value, the ther mal shutdown circuit operat es and turns a swi t ch OFF. The thermal shutdown
circuit, which is aimed at isolating the LSI from thermal runaway as much as possible, is not aimed at the protection or guarantee of the LSI.
Therefore, do not continuously use the LSI with this circuit operating or use the LSI assuming its operation.
(13) Thermal design
Perform therma l design in which there are adequate margins by taking into account the permissible dissipation (Pd) in actual states of use.
Appendix-Rev4.0
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Appendix
Notes
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wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM
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sponsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples
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