Ultralow Distortion Differential ADC Driver ADA4938-1/ADA4938-2 Data Sheet FUNCTIONAL BLOCK DIAGRAMS FEATURES ADA4938-1 Extremely low harmonic distortion (HD) -106 dBc HD2 @ 10 MHz -82 dBc HD2 @ 50 MHz -109 dBc HD3 @ 10 MHz -82 dBc HD3 @ 50 MHz Low input voltage noise: 2.6 nV/Hz High speed -3 dB bandwidth of 1000 MHz, G = +1 Slew rate: 4700 V/s 0.1 dB gain flatness to 150 MHz Fast overdrive recovery of 4 ns 1 mV typical offset voltage Externally adjustable gain Differential-to-differential or single-ended-to-differential operation Adjustable output common-mode voltage Wide supply voltage range: +5 V to 5 V Single or dual amplifier configuration available 13 -VS 14 -VS 16 -VS -FB 1 12 PD +IN 2 11 -OUT -IN 3 10 +OUT 06592-001 VOCM +VS 8 +VS 7 +VS 6 9 +VS 5 +FB 4 Figure 1. ADA4938-1 Functional Block Diagram ADA4938-2 19 -OUT1 21 -VS1 20 PD1 22 -VS1 24 +IN1 23 -FB1 TOP VIEW -IN1 1 18 +OUT1 +FB1 2 17 VOCM1 +VS1 3 16 -VS2 +VS1 4 15 -VS2 -FB2 5 14 PD2 +IN2 6 +OUT2 12 +VS2 10 VOCM2 11 +VS2 9 -IN2 7 13 -OUT2 +FB2 8 ADC drivers Single-ended-to-differential converters IF and baseband gain blocks Differential buffers Line drivers 06592-202 APPLICATIONS Figure 2. ADA4938-2 Functional Block Diagram -50 GENERAL DESCRIPTION G = +2, G = +2, G = +2, G = +2, -60 The ADA4938-1/ADA4938-2 are fabricated using the Analog Devices, Inc., proprietary third generation, high voltage XFCB process, enabling it to achieve very low levels of distortion with an input voltage noise of only 2.6 nV/Hz. The low dc offset and excellent dynamic performance of the ADA4938-1/ADA4938-2 -80 -90 -100 -110 -120 -130 1 10 FREQUENCY (MHz) 100 06592-002 Full differential and single-ended-to-differential gain configurations are easily realized with the ADA4938-1/ADA4938-2. A simple external feedback network of four resistors determines the closed-loop gain of the amplifier. VO, dm = 5V p-p VO, dm = 3.2V p-p VO, dm = 2V p-p VO, dm = 1V p-p -70 SFDR (dBc) The ADA4938-1/ADA4938-2 are low noise, ultralow distortion, high speed differential amplifiers. It is an ideal choice for driving high performance ADCs with resolutions up to 16 bits from dc to 27 MHz, or up to 12 bits from dc to 74 MHz. The output common-mode voltage is adjustable over a wide range, allowing the ADA4938-1/ADA4938-2 to match the input of the ADC. The internal common-mode feedback loop also provides exceptional output balance as well as suppression of even-order harmonic distortion products. Rev. B 15 -VS TOP VIEW Figure 3. SFDR vs. Frequency and Output Voltage makes them well-suited for a wide variety of data acquisition and signal processing applications. The ADA4938-1 (single amplifier) is available in a Pb-free, 3 mm x 3 mm, 16-lead LFCSP. The ADA4938-2 (dual amplifier) is available in a Pb-free, 4 mm x 4 mm, 24-lead LFCSP. The pinouts have been optimized to facilitate layout and minimize distortion. The devices are specified to operate over the extended industrial temperature range of -40C to +85C. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2007-2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADA4938-1/ADA4938-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 19 Applications ....................................................................................... 1 Analyzing an Application Circuit ............................................ 19 General Description ......................................................................... 1 Setting the Closed-Loop Gain .................................................. 19 Functional Block Diagrams ............................................................. 1 Estimating the Output Noise Voltage ...................................... 19 Revision History ............................................................................... 2 The Impact of Mismatches in the Feedback Networks ......... 20 Specifications..................................................................................... 3 Calculating the Input Impedance of an Application Circuit ..... 20 Dual-Supply Operation ............................................................... 3 Single-Supply Operation ............................................................. 5 Input Common-Mode Voltage Range in Single-Supply Applications ................................................................................ 20 Absolute Maximum Ratings............................................................ 7 Terminating a Single-Ended Input .......................................... 21 Thermal Resistance ...................................................................... 7 Setting the Output Common-Mode Voltage .......................... 21 ESD Caution .................................................................................. 7 Layout, Grounding, and Bypassing .............................................. 23 Pin Configurations and Function Descriptions ........................... 8 High Performance ADC Driving ................................................. 24 Typical Performance Characteristics ............................................. 9 Outline Dimensions ....................................................................... 25 Test Circuts ...................................................................................... 17 Ordering Guide .......................................................................... 25 Terminology .................................................................................... 18 6/2016--Rev. A to Rev. B Changed CP-16-2 to CP-16-21, CP-24-1 to CP-24-10.. Throughout Changed ADA4938-x to ADA4938-1/ADA4938-2 .. Throughout Changes to Figure 1 and Figure 2 ................................................... 1 Changes to Figure 5 and Figure 6 ................................................... 8 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 25 Added Settling Time Parameter, Table 3 ........................................5 Changes to Linear Output Current Parameter, Table 3 ................5 Changes to Figure 5 and Figure 6 ....................................................8 Added EP Row to Table 7 and EP Row to Table 8 ........................8 Changes to Figure 41...................................................................... 14 Added New Figure 53, Renumbered Sequentially ..................... 16 Changes to Table 9.......................................................................... 19 Added Exposed Pad Notation to Outline Dimensions ............. 25 Changes to Ordering Guide .......................................................... 25 10/2009--Rev. 0 to Rev. A Added Settling Time Parameter, Table 1 ....................................... 3 Changes to Linear Output Current Parameter, Table 1 ............... 3 11/2007--Revision 0: Initial Version REVISION HISTORY Rev. B | Page 2 of 26 Data Sheet ADA4938-1/ADA4938-2 SPECIFICATIONS DUAL-SUPPLY OPERATION TA = 25C, +VS = 5 V, -VS = -5 V, VOCM = 0 V, RT = 61.9 , RG = RF = 200 , G = +1, RL, dm = 1 k, unless otherwise noted. All specifications refer to single-ended input and differential output, unless otherwise noted. For gains other than G = +1, values for RF and RG are shown in Table 11. DIN to OUT Performance Table 1. Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness Large Signal Bandwidth Slew Rate Settling Time Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE Second Harmonic Third Harmonic IMD IP3 Input Voltage Noise Noise Figure Input Current Noise Crosstalk (ADA4938-2) INPUT CHARACTERISTICS Offset Voltage Conditions Min Input Capacitance Input Common-Mode Voltage CMRR OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Output Balance Error Max Unit VOUT = 0.1 V p-p VOUT = 2 V p-p VOUT = 2 V p-p VOUT = 2 V p-p VOUT = 2 V p-p VIN = 5 V to 0 V step, G = +2 1000 150 800 4700 6.5 4 MHz MHz MHz V/s ns ns VOUT = 2 V p-p, 10 MHz VOUT = 2 V p-p, 50 MHz VOUT = 2 V p-p, 10 MHz VOUT = 2 V p-p, 50 MHz f1 = 30.0 MHz, f2 = 30.1 MHz f = 30 MHz, RL, dm = 100 f = 10 MHz G = +4, f = 10 MHz f = 10 MHz f = 100 MHz -106 -82 -109 -82 89 45 2.6 15.8 4.8 -85 dBc dBc dBc dBc dBc dBm nV/Hz dB pA/Hz dB VOS, dm = VOUT, dm/2; VDIN+ = VDIN- = 0 V TMIN to TMAX variation VOUT, dm/VIN, cm; VIN, cm = 1 V, f = 1 MHz 1 4 -13 -0.01 6 3 1 -VS + 0.3 to +VS - 1.6 -75 Maximum VOUT; single-ended output Per amplifier, RL, dm = 20 , f = 10 MHz VOUT, cm/VOUT, dm; VOUT, dm = 1 V; f = 10 MHz -VS + 1.2 to +VS - 1.2 75 -60 Input Bias Current Input Resistance Typ -18 TMIN to TMAX variation Differential Common mode Rev. B | Page 3 of 26 4 mV V/C A A/C M M pF V dB V mA dB ADA4938-1/ADA4938-2 Data Sheet VOCM to OUT Performance Table 2. Parameter VOCM DYNAMIC PERFORMANCE -3 dB Bandwidth Slew Rate Input Voltage Noise (RTI) VOCM INPUT CHARACTERISTICS Input Voltage Range Input Resistance Input Offset Voltage Input Bias Current VOCM CMRR Gain POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio POWER DOWN (PD) PD Input Voltage Turn-Off Time Turn-On Time PD Bias Current Enabled Disabled Conditions Min VIN = -3.4 V to +3.4 V, 25% to 75% VOS, cm = VOUT, cm; VDIN+ = VDIN- = 0 V VOUT, dm/VOCM; VOCM = 1 V VOUT, cm/VOCM; VOCM = 1 V 0.95 Typ Max Unit 230 1700 7.5 MHz V/s nV/Hz -VS + 1.3 to +VS - 1.3 10 3 0.5 -81 1.00 V k mV A dB V/V 4.5 1.05 11 40 V mA A/C mA dB Per amplifier TMIN to TMAX variation Powered down VOUT, dm/VS; VS = 1 V 37 40 2.0 -80 Powered down Enabled 2.5 3 1 200 V V s ns PD = 5 V PD = -5 V 1 -760 A A OPERATING TEMPERATURE RANGE -40 Rev. B | Page 4 of 26 3.0 +85 C Data Sheet ADA4938-1/ADA4938-2 SINGLE-SUPPLY OPERATION TA = 25C, +VS = 5 V, -VS = 0 V, VOCM = +VS/2, RT = 61.9 , RG = RF = 200 , G = +1, RL, dm = 1 k, unless otherwise noted. All specifications refer to single-ended input and differential output, unless otherwise noted. For gains other than G = 1, values for RF and RG are shown in Table 11. DIN to OUT Performance Table 3. Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness Large Signal Bandwidth Slew Rate Settling Time Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE Second Harmonic Third Harmonic Input Voltage Noise Noise Figure Input Current Noise Crosstalk (ADA4938-2) INPUT CHARACTERISTICS Offset Voltage Conditions Min Input Capacitance Input Common-Mode Voltage CMRR OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Output Balance Error Max Unit VOUT = 0.1 V p-p VOUT = 2 V p-p VOUT = 2 V p-p VOUT = 2 V p-p VOUT = 2 V p-p VIN = 2.5 V to 0 V step, G = +2 1000 150 750 3900 6.5 4 MHz MHz MHz V/s ns ns VOUT = 2 V p-p, 10 MHz VOUT = 2 V p-p, 50 MHz VOUT = 2 V p-p, 10 MHz VOUT = 2 V p-p, 50 MHz f = 10 MHz G = +4, f = 10 MHz f = 10 MHz f = 100 MHz -110 -79 -100 -79 2.6 15.8 4.8 -85 dBc dBc dBc dBc nV/Hz dB pA/Hz dB VOS, dm = VOUT, dm/2; VDIN+ = VDIN- = VOCM = 2.5 V TMIN to TMAX variation VOUT, dm/VIN, cm; VIN, cm = 1 V 1 4 -13 -0.01 6 3 1 -VS + 0.3 to +VS - 1.6 -80 Maximum VOUT; single-ended output Per amplifier, RL, dm = 20 , f = 10 MHz VOUT, cm/VOUT, dm; VOUT, dm = 1 V -VS + 1.2 to +VS - 1.2 65 -60 Input Bias Current Input Resistance Typ -18 TMIN to TMAX variation Differential Common mode Rev. B | Page 5 of 26 4 mV V/C A A/C M M pF V dB V mA dB ADA4938-1/ADA4938-2 Data Sheet VOCM to OUT Performance Table 4. Parameter VOCM DYNAMIC PERFORMANCE -3 dB Bandwidth Slew Rate Input Voltage Noise (RTI) VOCM INPUT CHARACTERISTICS Input Voltage Range Input Resistance Input Offset Voltage Input Bias Current VOCM CMRR Gain POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio POWER DOWN (PD) PD Input Voltage Turn-Off Time Turn-On Time PD Bias Current Enabled Disabled Conditions Min VIN = 1.6 V to 3.4 V, 25% to 75% VOS, cm = VOUT, cm; VDIN+ = VDIN- = VOCM = 2.5 V VOUT, dm/VOCM; VOCM = 1 V VOUT, cm/VOCM; VOCM = 1 V 0.95 Typ Unit 400 1700 7.5 MHz V/s nV/Hz -VS + 1.3 to +VS - 1.3 10 3 0.5 -89 1.00 V k mV A dB V/V 4.5 34 40 1.0 -80 TMIN to TMAX variation Powered down VOUT, dm/VS; VS = 1 V Max 1.05 11 36.5 1.7 V mA A/C mA dB Powered down Enabled 2.5 3 1 200 V V s ns PD = 5 V PD = 0 V 1 -260 A A OPERATING TEMPERATURE RANGE -40 Rev. B | Page 6 of 26 +85 C Data Sheet ADA4938-1/ADA4938-2 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Power Dissipation Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating 12 V See Figure 4 -65C to +125C -40C to +85C 300C 150C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE JA is specified for the device (including exposed pad) soldered to a high thermal conductivity 4-layer circuit board, as described in EIA/JESD 51-7. The exposed pad is not electrically connected to the device. It is typically soldered to a pad on the PCB that is thermally and electrically connected to an internal ground plane. Table 6. Thermal Resistance Package Type 16-Lead LFCSP (Exposed Pad) 24-Lead LFCSP (Exposed Pad) JA 95 65 Unit C/W C/W The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The power dissipated due to the load drive depends upon the particular application. The power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. RMS voltages and currents must be used in these calculations. Airflow increases heat dissipation, which effectively reduces JA. In addition, more metal directly in contact with the package leads/exposed pad from metal traces, through-holes, ground, and power planes reduces the JA. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the ADA4938-1, 16-lead LFCSP (95C/W) and the ADA4938-2, 24-lead LFCSP (65C/W) on a JEDEC standard 4-layer board. 3.5 MAXIMUM POWER DISSIPATION (W) Table 5. 3.0 2.5 ADA4938-2 2.0 1.5 ADA4938-1 1.0 0.5 The maximum safe power dissipation in the ADA4938-1/ ADA4938-2 packages is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4938-1/ADA4938-2. Exceeding a junction temperature of 150C for an extended period can result in changes in the silicon devices, potentially causing failure. 0 -40 -30 -20 -10 0 10 20 30 40 50 AMBIENT TEMPERATURE (C) 60 70 80 90 06592-103 Maximum Power Dissipation Figure 4. Maximum Power Dissipation vs. Temperature, 4-Layer Board ESD CAUTION Rev. B | Page 7 of 26 ADA4938-1/ADA4938-2 Data Sheet 10 +OUT +VS1 3 9 +VS1 4 20 PD1 TOP VIEW (Not to Scale) -FB2 5 15 -VS2 14 PD2 +IN2 6 VOCM2 11 +OUT2 12 +VS2 10 06592-003 +VS2 9 13 -OUT2 -IN2 7 +VS 8 +VS 7 +VS 6 +VS 5 ADA4938-2 NOTES 1. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED TO THE DEVICE. IT IS TYPICALLY SOLDERED TO GROUND OR A POWER PLANE ON THE PCB THAT IS THERMALLY CONDUCTIVE. Figure 5. ADA4938-1 Pin Configuration Figure 6. ADA4938-2 Pin Configuration Table 7. ADA4938-1 Pin Function Descriptions Table 8. ADA4938-2 Pin Function Descriptions Pin No. 1 2 3 4 5 to 8 9 10 11 12 13 to 16 EP Pin No. 1 2 3, 4 5 6 7 8 9, 10 11 12 13 14 15, 16 17 18 19 20 21, 22 23 24 EP Mnemonic -FB +IN -IN +FB +VS VOCM +OUT -OUT PD -VS 06592-206 TOP VIEW (Not to Scale) NOTES 1. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED TO THE DEVICE. IT IS TYPICALLY SOLDERED TO GROUND OR A POWER PLANE ON THE PCB THAT IS THERMALLY CONDUCTIVE. 19 -OUT1 18 +OUT1 17 VOCM1 16 -VS2 -IN 3 VOCM 22 -VS1 -IN1 1 +FB1 2 ADA4938-1 11 -OUT +FB 4 21 -VS1 24 +IN1 12 PD +IN 2 +FB2 8 -FB 1 23 -FB1 13 -VS 14 -VS 16 -VS 15 -VS PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Description Negative Output Feedback Pin. Positive Input Summing Node. Negative Input Summing Node. Positive Output Feedback Pin. Positive Supply Voltage. Output Common-Mode Voltage. Positive Output for Load Connection. Negative Output for Load Connection. Power-Down Pin. Negative Supply Voltage. Exposed Paddle. The exposed pad is not electrically connected to the device. It is typically soldered to ground or a power plane on the PCB that is thermally conductive. Rev. B | Page 8 of 26 Mnemonic -IN1 +FB1 +VS1 -FB2 +IN2 -IN2 +FB2 +VS2 VOCM2 +OUT2 -OUT2 PD2 -VS2 VOCM1 +OUT1 -OUT1 PD1 -VS1 -FB1 +IN1 Description Negative Input Summing Node 1. Positive Output Feedback Pin 1. Positive Supply Voltage 1. Negative Output Feedback Pin 2. Positive Input Summing Node 2. Negative Input Summing Node 2. Positive Output Feedback Pin 2. Positive Supply Voltage 2. Output Common-Mode Voltage 2. Positive Output 2. Negative Output 2. Power-Down Pin 2. Negative Supply Voltage 2. Output Common-Mode Voltage 1. Positive Output 1. Negative Output 1. Power-Down Pin 1. Negative Supply Voltage 1. Negative Output Feedback Pin 1. Positive Input Summing Node 1. Exposed Paddle. The exposed pad is not electrically connected to the device. It is typically soldered to ground or a power plane on the PCB that is thermally conductive. Data Sheet ADA4938-1/ADA4938-2 TYPICAL PERFORMANCE CHARACTERISTICS 3 0 0 -3 -6 -9 G G G G -12 10 100 1000 FREQUENCY (MHz) = +1 = +2 = +3.16 = +5 1 10 100 1000 FREQUENCY (MHz) Figure 10. Large Signal Frequency Response for Various Gains 3 0 0 -3 -3 GAIN (dB) 3 -6 -6 -9 VS = +5V VS = 5V 10 100 1000 FREQUENCY (MHz) -12 1 0 0 NORMALIZED GAIN (dB) 3 -3 -6 -3 -6 -9 -40C +25C +85C 10 100 FREQUENCY (MHz) Figure 9. Small Signal Frequency Response for Various Temperatures, VOUT = 0.1 V p-p 1000 -40C +25C +85C -12 06592-107 1 1000 Figure 11. Large Signal Response for Various Supplies 3 -12 100 FREQUENCY (MHz) Figure 8. Small Signal Response for Various Supplies, VOUT = 0.1 V p-p -9 10 1 10 100 FREQUENCY (MHz) 1000 06592-110 1 06592-106 -12 VS = +5V VS = 5V 06592-109 -9 NORMALIZED GAIN (dB) G G G G -12 Figure 7. Small Signal Frequency Response for Various Gains, VOUT = 0.1 V p-p GAIN (dB) -6 -9 = +1 = +2 = +3.16 = +5 1 -3 06592-108 NORMALIZED GAIN (dB) 3 06592-105 NORMALIZED GAIN (dB) TA = 25C, +VS = 5 V, -VS = -5 V, VOCM = 0 V, RT = 61.9 , RG = RF = 200 , G = +1, RL, dm = 1 k, unless otherwise noted. All measurements were performed with single-ended input and differential output, unless otherwise noted. For gains other than G = +1, values for RF and RG are shown in Table 11. Figure 12. Large Signal Frequency Response for Various Temperatures Rev. B | Page 9 of 26 Data Sheet 3 0 0 -3 -3 -6 -9 -12 -15 RL = 1k RL = 100 RL = 200 1 10 100 1000 1 0 NORMALIZED GAIN (dB) 0 -3 -6 1 10 100 1000 FREQUENCY (MHz) Figure 14. Small Signal Frequency Response for Various Gains, VS = 5 V, VOUT = 0.1 V p-p -6 NORMALIZED GAIN (dB) 0 -3 -6 = +1 = +2 = +3.16 = +5 FREQUENCY (MHz) 1000 -3 -6 G G G G -12 06592-113 100 1000 0 -9 10 100 Figure 17. Large Signal Frequency Response for Various Gains, VS = 5 V 3 1 10 FREQUENCY (MHz) 3 -12 = +1 = +2 = +3.16 = +5 1 6 G G G G G G G G -12 6 -9 1000 -3 -9 = +1 = +2 = +3.16 = +5 06592-112 -12 100 Figure 16. Large Signal Frequency Response for Various Loads 3 G G G G 10 FREQUENCY (MHz) 3 -9 RL = 1k RL = 100 RL = 200 -21 Figure 13. Small Signal Frequency Response for Various Loads, VOUT = 0.1 V p-p NORMALIZED GAIN (dB) -15 -18 FREQUENCY (MHz) NORMALIZED GAIN (dB) -12 06592-115 -21 -9 1 = +1 = +2 = +3.16 = +5 10 100 1000 FREQUENCY (MHz) Figure 15. Small Signal Response for Various Gains, RF = 402 , VOUT = 0.1 V p-p Rev. B | Page 10 of 26 Figure 18. Large Signal Response for Various Gains, RF = 402 06592-116 -18 -6 06592-114 NORMALIZED GAIN (dB) 3 06592-111 NORMALIZED GAIN (dB) ADA4938-1/ADA4938-2 ADA4938-1/ADA4938-2 6 3 3 0 -3 -6 G G G G -9 -12 = +1 = +2 = +3.16 = +5 1 -3 -6 G G G G -9 10 100 1000 FREQUENCY (MHz) -12 10 100 1000 FREQUENCY (MHz) Figure 22. Large Signal Frequency Response for Various Gains, RF = 402 , VS = 5 V 3 0 0 -3 -3 GAIN (dB) 3 -6 -6 -9 VS = +5V VS = 5V 10 100 1000 FREQUENCY (MHz) 1 GAIN (dB) 100 1000 FREQUENCY (MHz) 06592-119 10 1000 Figure 23. VOUT, cm Large Signal Frequency Response RL, dm = 1k RL, dm = 100 RL, dm = 200 1 100 FREQUENCY (MHz) Figure 20. VOUT, cm Small Signal Frequency Response, VOUT = 0.1 V p-p 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 10 Figure 21. 0.1 dB Flatness Response for Various Loads, ADA4938-1, VOUT = 0.1 V p-p 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 RL, dm = 1k RL, dm = 100 RL, dm = 200 1 10 100 1000 FREQUENCY (MHz) Figure 24. 0.1 dB Flatness Response for Various Loads, ADA4938-2, VOUT = 0.1 V p-p Rev. B | Page 11 of 26 06592-122 1 VS = +5V VS = 5V -12 06592-118 -12 06592-121 -9 NORMALIZED GAIN (dB) = +1 = +2 = +3.16 = +5 1 Figure 19. Small Signal Frequency Response for Various Gains, RF = 402 , VS = 5 V, VOUT = 0.1 V p-p GAIN (dB) 0 06592-120 NORMALIZED GAIN (dB) 6 06592-117 NORMALIZED GAIN (dB) Data Sheet ADA4938-1/ADA4938-2 HD2, HD3, HD2, HD3, -50 -60 -70 -80 -90 -90 -110 -110 -120 06592-123 10 100 FREQUENCY (MHz) 0 HD2, HD3, HD2, HD3, HD2, HD3, -50 -60 -70 G G G G G G -40 = +1 = +1 = +2 = +2 = +5 = +5 -60 -90 -100 4 5 6 7 8 9 RL RL RL RL RL RL = 1k = 1k = 200 = 200 = 100 = 100 -70 -80 -90 -110 -120 10 100 -120 FREQUENCY (MHz) 1 100 FREQUENCY (MHz) Figure 26. Harmonic Distortion vs. Frequency and Gain HD2, HD3, HD2, HD3, 10 06592-127 1 06592-124 -130 Figure 29. Harmonic Distortion vs. Frequency for Various Loads -40 10MHz 10MHz 70MHz 70MHz HD2, HD3, HD2, HD3, -50 10MHz 10MHz 70MHz 70MHz -60 DISTORTION (dBc) -70 -80 -90 -100 -70 -80 -90 -100 -110 -110 -130 -3.3 -2.7 -2.1 -1.5 -0.9 -0.3 0.3 0.9 1.5 2.1 2.7 VOCM (V) 3.3 06592-128 -120 -120 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 VOCM (V) Figure 30. Harmonic Distortion vs. VOCM and Frequency, VS = 5 V Figure 27. Harmonic Distortion vs. VOCM and Frequency Rev. B | Page 12 of 26 06592-125 -60 3 -100 -110 -50 HD2, HD3, HD2, HD3, HD2, HD3, -50 -80 -40 2 Figure 28. Harmonic Distortion vs. VOUT and Supply Voltage DISTORTION (dBc) -40 1 VOUT, dm (V) Figure 25. Harmonic Distortion vs. Frequency and Supply Voltage DISTORTION (dBc) -80 -100 -120 DISTORTION (dBc) -70 -100 1 HD2, +5V HD3, +5V HD2, 5V HD3, 5V -50 DISTORTION (dBc) DISTORTION (dBc) -60 -40 VS = +5V VS = +5V VS = 5V VS = 5V 06592-126 -40 Data Sheet Data Sheet ADA4938-1/ADA4938-2 0 -10 -30 -40 PSRR (dB) -50 -60 -70 -80 -90 -110 29.5 29.6 29.7 29.8 29.9 30.0 30.1 30.2 30.3 30.4 30.5 FREQUENCY (MHz) 06592-129 -100 1 10 100 1000 Figure 34. PSRR vs. Frequency -20 0 -25 -5 -30 -10 -35 -15 RETURN LOSS (dB) -40 -45 -50 -55 VS = 5V -60 -65 -25 S22 -30 -35 -40 VS = +5V -70 -20 S11 -45 -75 -50 -80 1 10 100 1000 FREQUENCY (MHz) -55 06592-130 -85 0.1 1 100 1000 FREQUENCY (MHz) Figure 32. VIN CMRR vs. Frequency Figure 35. Return Loss (S11, S22) vs. Frequency -15 -40 RL = 1k RL = 200 RL = 100 RL = 200 -20 10 06592-134 VIN CMRR (dB) +PSRR FREQUENCY (MHz) Figure 31. Intermodulation Distortion -50 -25 -60 -30 SFDR (dBc) -35 -40 -45 -70 -80 -90 -50 -100 -55 -110 -60 -65 1 10 100 FREQUENCY (MHz) 1000 06592-131 OUTPUT BALANCE (dB) -PSRR Figure 33. Output Balance vs. Frequency -120 1 10 100 FREQUENCY (MHz) Figure 36. SFDR vs. Frequency for Various Loads Rev. B | Page 13 of 26 06592-135 DISTORTION (dBc) -20 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 0.1 06592-132 10 ADA4938-1/ADA4938-2 Data Sheet 26 100 24 INPUT VOLTAGE NOISE (nV/ Hz) G = +1 NOISE FIGURE (dB) 22 20 G = +2 18 G = +4 16 14 10 100 500 FREQUENCY (MHz) 1 10 06592-136 10 10 10k 100k 1M 10M 100M Figure 40. Input Voltage Noise vs. Frequency 10 4.0 8 3.5 6 3.0 4 PD INPUT VOLTAGE (V) 2.5 2 0 -2 2.0 1.5 1.0 -4 NEGATIVE OUTPUT 0.5 -6 0 5 10 15 20 25 30 35 40 45 50 55 60 TIME (5ns/DIV) -0.5 06592-137 -10 06592-140 0 VIN x 3.16 VOUT, dm -8 TIME (200ns/DIV) Figure 41. Power-Down Response Time Figure 38. Overdrive Recovery Time (Pulse Input) 45 12 10 40 8 +85C +25C -40C 35 6 CURRENT (mA) 4 VOLTAGE (V) 1k FREQUENCY (Hz) Figure 37. Noise Figure vs. Frequency VOLTAGE (V) 100 06592-039 12 2 0 -2 -4 -6 30 25 20 15 10 -8 0 50 100 150 200 250 300 TIME (50ns/DIV) 350 400 450 500 0 2.0 06592-138 -12 Figure 39. Overdrive Amplitude Characteristics (Triangle Wave Input) 2.2 2.4 2.6 2.8 3.0 3.2 VOLTAGE (V) 3.4 3.6 3.8 4.0 06592-141 5 VIN x 3.16 VOUT, dm -10 Figure 42. Supply Current vs. Power-Down Voltage and Temperature Rev. B | Page 14 of 26 Data Sheet ADA4938-1/ADA4938-2 0.20 3.0 2.5 0.15 2.0 1.5 1.0 0.05 VOLTAGE (V) 0 -0.05 0.5 0 -0.5 -1.0 -0.10 -1.5 -2.0 -0.15 -3.0 TIME (1ns/DIV) Figure 46. Large Signal Transient Response 2.5 0.08 2.0 0.06 1.5 0.04 1.0 VOLTAGE (V) 0.10 0.02 0 -0.02 0.5 0 -0.5 -0.04 -1.0 -0.06 -1.5 -0.08 -2.0 -0.10 06592-043 VOLTAGE (V) Figure 43. Small Signal Transient Response, VOUT = 0.1 V p-p TIME (2ns/DIV) -2.5 Figure 44. VOCM Small Signal Transient Response, VOUT = 0.1 V p-p CURRENT (mA) 50 3 +85C +25C -40C ALL CURVES ARE NORMALIZED TO VOCM = 0V 0 40 30 20 -3 VOCM = -3.7V VOCM = -3.5V VOCM = -3V VOCM = 0V VOCM = +3V VOCM = +3.5V VOCM = +3.7V -6 -9 10 2.2 2.4 2.6 2.8 3.0 3.2 VOLTAGE (V) 3.4 3.6 3.8 4.0 -12 06592-144 0 2.0 TIME (2ns/DIV) Figure 47. VOCM Large Signal Transient Response CLOSED-LOOP GAIN (dB) 60 06592-046 TIME (1ns/DIV) 06592-145 06592-142 -2.5 -0.20 Figure 45. Supply Current vs. Power-Down Voltage and Temperature, VS = 5 V 1 10 100 FREQUENCY (MHz) 1000 06592-048 VOLTAGE (V) 0.10 Figure 48. VOUT, dm Small Signal Frequency Response for Various VOCM, VOUT = 0.1 V p-p Rev. B | Page 15 of 26 ADA4938-1/ADA4938-2 Data Sheet -40 55 -50 -60 50 CROSSTALK (dB) IP3 100 45 40 -80 -90 -100 INPUT2, OUTPUT1 -110 -120 06592-049 35 30 10 -130 -140 0.3 100 FREQUENCY (MHz) 10 100 1000 FREQUENCY (MHz) Figure 49. IP3 vs. Frequency 3 1 06592-888 IP3 (dBm) INPUT1, OUTPUT2 -70 Figure 52. Crosstalk vs. Frequency for ADA4938-2 2 ALL CURVES ARE NORMALIZED TO VOCM = 0V 1.0 VIN 0 0.1 0 -0.1 VOCM = -3.7V VOCM = -3.5V VOCM = -3V VOCM = 0V VOCM = +3V VOCM = +3.5V VOCM = +3.7V -12 1 -1 10 100 1000 FREQUENCY (MHz) Figure 50. VOUT, dm Large Signal Frequency Response for Various VOCM 100 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 100M 06592-051 10 Figure 51. Input Current Noise vs. Frequency Rev. B | Page 16 of 26 SETTLING ERROR -2 -0.5 -1.0 TIME (1ns/DIV) Figure 53. 0.1% Settling Time SETTLING ERROR (%) 0.5 06592-153 VIN (V) -6 -9 INPUT CURRENT NOISE (pA/ Hz) 1 -3 06592-50 CLOSED-LOOP GAIN (dB) 0 Data Sheet ADA4938-1/ADA4938-2 TEST CIRCUTS 200 +5V 50 200 VIN VOCM 61.9 ADA4938 1k 200 06592-246 27.5 -5V 200 Figure 54. Equivalent Basic Test Circuit 200 +5V 50 200 VIN 50 VOCM 61.9 ADA4938 200 50 06592-247 27.5 -5V 200 Figure 55. Test Circuit for Output Balance 200 +5V VIN FILTER 61.9 0.1F 200 VOCM 412 FILTER ADA4938 0.1F 200 412 27.5 -5V 200 Figure 56. Test Circuit for Distortion Measurements Rev. B | Page 17 of 26 06592-248 50 ADA4938-1/ADA4938-2 Data Sheet TERMINOLOGY Common-Mode Voltage The common-mode voltage is the average of two node voltages. The output common-mode voltage is defined as -FB RG RF ADA4938 +IN -OUT VOCM RL, dm VOUT, dm RF -IN +OUT +FB VOUT, cm = (V+OUT + V-OUT)/2 06592-004 RG Figure 57. Circuit Definitions Differential Voltage The differential voltage is the difference between two node voltages. For example, the output differential voltage (or equivalently, output differential-mode voltage) is defined as VOUT, dm = (V+OUT - V-OUT) where V+OUT and V-OUT refer to the voltages at the +OUT and -OUT terminals with respect to a common reference. Balance Balance is a measure of how well differential signals are matched in amplitude and are exactly 180 apart in phase. Balance is most easily determined by placing a well-matched resistor divider between the differential voltage nodes and comparing the magnitude of the signal at the midpoint of the divider with the magnitude of the differential signal. By this definition, output balance is the magnitude of the output common-mode voltage divided by the magnitude of the output differential mode voltage. Output Balance Error = Rev. B | Page 18 of 26 VOUT , cm VOUT , dm Data Sheet ADA4938-1/ADA4938-2 THEORY OF OPERATION The ADA4938-1/ADA4938-2 differ from conventional op amps in that they have two outputs whose voltages move in opposite directions. Like an op amp, it relies on open-loop gain and negative feedback to force these outputs to the desired voltages. The ADA4938-1/ADA4938-2 behave much like a standard voltage feedback op amp and makes it easier to perform singleended-to-differential conversions, common-mode level shifting, and amplifications of differential signals. Also like an op amp, the ADA4938-1/ADA4938-2 have high input impedance and low output impedance. Two feedback loops are employed to control the differential and common-mode output voltages. The differential feedback, set with external resistors, controls only the differential output voltage. The common-mode feedback controls only the commonmode output voltage. This architecture makes it easy to set the output common-mode level to any arbitrary value. It is forced, by internal common-mode feedback, to be equal to the voltage applied to the VOCM input, without affecting the differential output voltage. The ADA4938-1/ADA4938-2 architecture results in outputs that are highly balanced over a wide frequency range without requiring tightly matched external components. The commonmode feedback loop forces the signal component of the output common-mode voltage to zero, which results in nearly perfectly balanced differential outputs that are identical in amplitude and are exactly 180 apart in phase. SETTING THE CLOSED-LOOP GAIN The differential-mode gain of the circuit in Figure 57 can be determined by VOUT , dm VIN , dm = RF RG This assumes the input resistors (RG) and feedback resistors (RF) on each side are equal. ESTIMATING THE OUTPUT NOISE VOLTAGE The differential output noise of the ADA4938-1/ADA4938-2 can be estimated using the noise model in Figure 58. The inputreferred noise voltage density, vnIN, is modeled as a differential input, and the noise currents, inIN- and inIN+, appear between each input and ground. The noise currents are assumed to be equal and produce a voltage across the parallel combination of the gain and feedback resistances. vn, cm is the noise voltage density at the VOCM pin. Each of the four resistors contributes (4kTR)1/2. Table 9 summarizes the input noise sources, the multiplication factors, and the output-referred noise density terms. VnRG1 RG1 VnRF1 RF1 inIN+ + inIN- VnIN ADA4938 ANALYZING AN APPLICATION CIRCUIT VnOD The ADA4938-1/ADA4938-2 use open-loop gain and negative feedback to force its differential and common-mode output voltages in such a way as to minimize the differential and common-mode error voltages. The differential error voltage is defined as the voltage between the differential inputs labeled +IN and -IN (see Figure 57). For most purposes, this voltage can be assumed to be zero. Similarly, the difference between the actual output common-mode voltage and the voltage applied to VOCM can also be assumed to be zero. Starting from these two assumptions, any application circuit can be analyzed. VnRG2 RG2 RF2 VnCM VnRF2 06592-005 VOCM Figure 58. ADA4938-1/ADA4938-2 Noise Model Table 9. Output Noise Voltage Density Calculations Input Noise Contribution Differential Input Inverting Input Noninverting Input VOCM Input Gain Resistor, RG1 Gain Resistor, RG2 Feedback Resistor, RF1 Feedback Resistor, RF2 Input Noise Term vnIN inIN- inIN+ vn, cm vnRG1 vnRG2 vnRF1 vnRF2 Input Noise Voltage Density vnIN inIN- x (RG2||RF2) inIN+ x (RG1||RF1) vn, cm (4kTRG1)1/2 (4kTRG2)1/2 (4kTRF1)1/2 (4kTRF2)1/2 Rev. B | Page 19 of 26 Output Multiplication Factor GN GN GN GN(1 - 2) GN(1 - 1) GN(1 - 2) 1 1 Output Noise Voltage Density Term vnO1 = GN(vnIN) vnO2 = GN[inIN- x (RG2||RF2)] vnO3 = GN[inIN+ x (RG1||RF1)] vnO4 = GN(1 - 2)(vnCM) vnO5 = GN(1 - 1)(4kTRG1)1/2 vnO6 = GN(1 - 2)(4kTRG2)1/2 vnO7 = (4kTRF1)1/2 vnO8 = (4kTRF2)1/2 ADA4938-1/ADA4938-2 Data Sheet Similar to the case of a conventional op amp, the output noise voltage densities can be estimated by multiplying the inputreferred terms at +IN and -IN by the appropriate output factor, where: 2 GN is the circuit noise gain. 1 2 RG1 RG2 1 and 2 are the feedback factors. RF1 RG1 RF2 RG2 CALCULATING THE INPUT IMPEDANCE OF AN APPLICATION CIRCUIT The effective input impedance of a circuit depends on whether the amplifier is being driven by a single-ended or differential signal source. For balanced differential input signals, as shown in Figure 59, the input impedance (RIN, dm) between the inputs (+DIN and -DIN) is simply RIN, dm = 2 x RG. RF ADA4938 When RF1/RG1 = RF2/RG2, 1 = 2 = , and the noise gain becomes +DIN 1 R 1 F RG -DIN Note that the output noise from VOCM goes to zero in this case. The total differential output noise density, vnOD, is the root-sumsquare of the individual output noise terms. VOCM RG VOUT, dm -IN RF Figure 59. ADA4938-1/ADA4938-2 Configured for Balanced (Differential) Inputs For an unbalanced, single-ended input signal (see Figure 60), the input impedance is 8 2 vnOi i 1 THE IMPACT OF MISMATCHES IN THE FEEDBACK NETWORKS RIN , cm As previously mentioned, even if the external feedback networks (RF/RG) are mismatched, the internal common-mode feedback loop still forces the outputs to remain balanced. The amplitudes of the signals at each output remain equal and 180 out of phase. The input-to-output, differential mode gain varies proportionately to the feedback mismatch, but the output balance is unaffected. RF +VS RG RS VOCM RT ADA4938 VOUT, dm RG As well as causing a noise contribution from VOCM, ratio matching errors in the external resistors result in a degradation of the ability of the circuit to reject input common-mode signals, much the same as for a four-resistor difference amplifier made from a conventional op amp. In addition, if the dc levels of the input and output commonmode voltages are different, matching errors result in a small differential-mode output offset voltage. When G = +1, with a ground referenced input signal and the output common-mode level set to 2.5 V, an output offset of as much as 25 mV (1% of the difference in common-mode levels) can result if 1% tolerance resistors are used. Resistors of 1% tolerance result in a worst-case input CMRR of about 40 dB, a worst-case differential-mode output offset of 25 mV due to 2.5 V level-shift, and no significant degradation in output balance error. R G RF 1 2 R R F G RS RT RF 06592-007 v nOD +IN 06592-006 GN +VS RG Figure 60. ADA4938-1/ADA4938-2 Configured for Unbalanced (Single-Ended) Input The input impedance of the circuit is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the Input Gain Resistor RG. INPUT COMMON-MODE VOLTAGE RANGE IN SINGLE-SUPPLY APPLICATIONS The ADA4938-1/ADA4938-2 is optimized for level-shifting, ground-referenced input signals. As such, the center of the input common-mode range is shifted approximately 1 V down from midsupply. The input common-mode range at the summing nodes of the amplifier is from 0.3 V above -VS to 1.6 V below +VS. To avoid clipping at the outputs, the voltage swing at the +IN and -IN terminals must be confined to these ranges. Rev. B | Page 20 of 26 Data Sheet ADA4938-1/ADA4938-2 RF TERMINATING A SINGLE-ENDED INPUT 200 +VS Using an example with an input source of 2 V, a source resistance of 50 , and an overall gain of 1 V/V, four simple steps must be followed to terminate a single-ended input to the ADA4938-1/ADA4938-2. VTH 1.1V RTH RG 27.4 200 VOCM 1. The input impedance is calculated using the formula RF RTS 27.4 VS 2V +VS 200 Figure 64. Balancing Gain Resistor RG To make the output voltage VO = 1 V, RF is calculated using a. RG 50 200 VOCM ADA4938 RL VO V (RG RTS ) 1 (200 27.4) RF O 207 VTH 1.1 RG 200 200 To return the overall gain to 1 V/V (VO = VS = 2 V), RF should be b. 06592-081 -VS RF V (RG RTS ) 2 (200 27.4) RF O 414 VTH 1.1 Figure 61. Single-Ended Input Impedance 2. To provide a 50 termination for the source, the Resistor RT is calculated such that RT || RIN = 50 , or RT = 61.9 . RF RF RS VS 2V +VS 200 +VS 50 RS RG 50 RT 61.9 VS 2V 200 VOCM ADA4938 RL RTS 27.4 200 VOCM ADA4938 RL -VS 06592-082 RF 200 3. To compensate for the imbalance of the gain resistors, a correction resistor (RTS) is added in series with the inverting Input Gain Resistor RG. RTS is equal to the Thevenin equivalent of the source resistance (RS||RT). RTH The VOCM pin of the ADA4938-1/ADA4938-2 is internally biased at a voltage approximately equal to the midsupply point (average value of the voltages on V+ and V-). Relying on this internal bias results in an output common-mode voltage that is within about 100 mV of the expected value. In cases where more accurate control of the output commonmode level is required, it is recommended that an external source or resistor divider (10 k or greater resistors) be used. 27.4 06592-083 VTH 1.1V Figure 65. Complete Single-Ended-to-Differential System SETTING THE OUTPUT COMMON-MODE VOLTAGE Figure 62. Adding Termination Resistor RT RS VO 200 RF -VS VS 2V RG RT 61.9 RG 200 RT 61.9 50 VO RG 50 06592-084 -VS RF 4. Finally, the feedback resistor is recalculated to adjust the output voltage to the desired level. 200 RS 200 06592-085 RIN 267 VO RL 0.97V RG R 200 G 267 200 RF 1 2 R R 1 2 (200 200) F G R IN ADA4938 Figure 63. Calculating Thevenin Equivalent RTS = RTH = RS || RT = 27.4 . Note that VTH is not equal to VS/2, which would be the case if the amplifier circuit did not affect the termination. It is also possible to connect the VOCM input to a common-mode level (CML) output of an ADC. However, care must be taken to ensure that the output has sufficient drive capability. The input impedance of the VOCM pin is approximately 10 k. If multiple ADA4938-1/ADA4938-2 devices share one reference output, it is recommended that a buffer be used. Rev. B | Page 21 of 26 ADA4938-1/ADA4938-2 Data Sheet Table 10 and Table 11 list several common gain settings, associated resistor values, input impedances, and output noise densities for both balanced and unbalanced input configurations. Also shown are the input common-mode voltages under the given conditions for different VOCM settings for both a 10 V single supply and 5 V dual supplies. Table 10. Differential Ground-Referenced Input, DC-Coupled; See Figure 59 Nominal Gain (V/V) 1 2 3.16 5 RF () 200 402 402 402 RG () 200 200 127 80.6 RIN, dm () 400 400 254 161 Differential Output Noise Density (nV/Hz) 6.5 10.4 13.4 18.2 Common-Mode Level at +IN, -IN (V) +VS = 10 V, -VS = 0 V +VS = 5 V, -VS = -5 V VOUT, dm = 2.0 V p-p VOUT, dm = 2.0 V p-p VOCM = 2.5 V VOCM = 3.5 V VOCM = 1.0 V VOCM = 3.2 V 1.25 1.75 0.50 1.60 0.83 1.16 0.33 1.06 0.60 0.84 0.24 0.77 0.42 0.58 0.17 0.53 Table 11. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 ; See Figure 60 Nominal Gain (V/V) 1 2 3.16 5 1 2 RF () 200 402 402 402 RG1 () 200 200 127 80.6 RT () 60.4 60.4 66.5 76.8 RIN,se () 267 300 205 138 RG2 () 1 226 226 158 110 Overall Gain (V/V) 2 0.9 1.8 2.5 3.6 Differential Output Noise Density (nV/Hz) 6.2 9.8 11.8 14.7 RG2 = RG1 + RTS. Includes effects of termination match. Rev. B | Page 22 of 26 Common-Mode Swing at +IN, -IN (V) +VS = 10 V, -VS = 0 V VOUT, dm = 2.0 V p-p VOCM = 2.5 V VOCM = 3.5 V 1.00 to 1.50 1.50 to 2.00 0.66 to 1.00 1.00 to 1.33 0.48 to 0.72 0.72 to 0.96 0.33 to 0.50 0.50 to 0.67 +VS = 5 V, -VS = -5 V VOUT, dm = 2.0 V p-p VOCM = 0 V VOCM = 2.0 V -0.25 to +0.25 0.75 to 1.25 -0.17 to +0.17 0.50 to 0.83 -0.12 to +0.12 0.36 to 0.60 -0.08 to +0.08 0.25 to 0.42 Data Sheet ADA4938-1/ADA4938-2 LAYOUT, GROUNDING, AND BYPASSING As high speed devices, the ADA4938-1/ADA4938-2 are sensitive to the PCB environment in which it operates. Realizing its superior performance requires attention to the details of high speed PCB design. Bypass the power supply pins as close to the device as possible and directly to a nearby ground plane. Use high frequency ceramic chip capacitors. It is recommended that two parallel bypass capacitors (1000 pF and 0.1 F) be used for each supply with the 1000 pF capacitor placed closer to the device; if further away, provide low frequency bypassing using 10 F tantalum capacitors from each supply to ground. The first requirement is a solid ground plane that covers as much of the board area around the ADA4938-1/ADA4938-2 as possible. However, the area near the feedback resistors (RF), input gain resistors (RG), and the input summing nodes should be cleared of all ground and power planes (see Figure 66). Clearing the ground and power planes minimizes any stray capacitance at these nodes and prevents peaking of the response of the amplifier at high frequencies. Signal routing should be short and direct to avoid parasitic effects. Wherever complementary signals exist, provide a symmetrical layout to maximize balanced performance. When routing differential signals over a long distance, keep PCB traces close together and twist any differential wiring to minimize loop area. Doing this reduces radiated energy and makes the circuit less susceptible to interference. The thermal resistance, JA, is specified for the device, including the exposed pad, soldered to a high thermal conductivity 4-layer circuit board, as described in EIA/JESD 51-7. The exposed pad is electrically isolated from the device; therefore, it can be connected to a ground plane using vias. Examples of the thermal attach pad and via structure for the ADA4938-1 are shown in Figure 67 and Figure 68. 1.30 0.80 06592-060 1.30 0.80 06592-008 Figure 67. Recommended PCB Thermal Attach Pad (ADA4938-1) (Dimensions in mm) Figure 66. Ground and Power Plane Voiding in Vicinity of RF and RG 1.30 TOP METAL GROUND PLANE 0.30 PLATED VIA HOLE 06592-061 POWER PLANE BOTTOM METAL Figure 68. Cross-Section of a 4-Layer PCB (ADA4938-1) Showing a Thermal Via Connection to the Buried Ground Plane (Dimensions in mm) Rev. B | Page 23 of 26 ADA4938-1/ADA4938-2 Data Sheet HIGH PERFORMANCE ADC DRIVING The circuit in Figure 70 shows a simplified front-end connection for an ADA4938-1/ADA4938-2 driving an AD9246, 14-bit, 125 MSPS ADC. The AD9246 achieves its optimum performance when it is driven differentially. The ADA4938-1/ ADA4938-2 eliminate the need for a transformer to drive the ADC, performs a single-ended-to-differential conversion, buffers the driving signal, and provides appropriate level shifting for dc coupling. The ADA4938-1/ADA4938-2 are configured with dual 5 V supplies and a gain of ~2 V/V for a single-ended input to differential output. The 76.8 termination resistor, in parallel with the single-ended input impedance of 137 , provides a 50 dc termination for the source. The additional 30.1 (120 total) at the inverting input balances the parallel dc impedance of the 50 source and the termination resistor driving the noninverting input. The signal generator has a symmetric, ground-referenced bipolar output. The VOCM pin of the ADA4938-1/ADA4938-2 is connected to the CML pin of the AD9246 to set the output common-mode level at the appropriate point. A portion of this is fed back to the summing nodes, biasing -IN and +IN at 0.55 V. For a common-mode voltage of 0.9 V, each ADA4938-1/ ADA4938-2 output swings between 0.4 V and 1.4 V, providing a 2 V p-p differential output. The output is dc-coupled to a single-pole, low-pass filter. The filter reduces the noise bandwidth of the amplifier and provides some level of isolation from the switched capacitor inputs of the ADC. The AD9246 is set for a 2 V p-p full-scale input by connecting the SENSE pin to AGND. The inputs of the AD9246 are biased at 1 V by connecting the CML output, as shown in Figure 70. The ADA4938-1/ADA4938-2 are ideally suited for dc-coupled baseband applications. The circuit in Figure 69 shows a front-end connection for an ADA4938-1/ADA4938-2 driving an AD9446, 16-bit, 80 MSPS ADC. The AD9446 achieves its optimum performance when it is driven differentially. The ADA4938-1/ ADA4938-2 eliminate the need for a transformer to drive the ADC, performs a single-ended-to-differential conversion, buffers the driving signal, and provides appropriate level shifting for dc coupling. The ADA4938-1/ADA4938-2 are configured with a single 10 V supply and unity gain for a single-ended input to differential output. The 61.9 termination resistor, in parallel with the single-ended input impedance of 267 , provides a 50 termination for the source. The additional 26 (226 total) at the inverting input balances the parallel impedance of the 50 source and the termination resistor driving the noninverting input. The signal generator has a symmetric, ground-referenced bipolar output. The VOCM pin of the ADA4938-1/ADA4938-2 is biased with an external resistor divider to obtain the desired 3.5 V output common-mode. One-half of the common-mode voltage is fed back to the summing nodes, biasing -IN and +IN at 1.75 V. For a common-mode voltage of 3.5 V, each ADA4938-1/ADA4938-2 output swings between 2.7 V and 4.3 V, providing a 3.2 V p-p differential output. The output of the amplifier is dc-coupled to the ADC through a second-order, low-pass filter with a -3 dB frequency of 50 MHz. The filter reduces the noise bandwidth of the amplifier and isolates the driver outputs from the ADC inputs. The AD9446 is configured for a 4.0 V p-p full-scale input by setting R1 = R2 = 1 k between the VREF pin and SENSE pin in Figure 69. 10V 200 5V (A) 3.3V (A) 3.3V (D) 10V 61.9 SIGNAL GENERATOR VOCM 30nH + ADA4938 AVDD2 AVDD1 DRVDD VIN+ BUFFER T/H 24.3 47pF ADC 24.3 30nH 226 AD9446 16 VIN- CLOCK/ TIMING 200 AGND REF SENSE R1 VREF 06592-054 200 50 R2 Figure 69. ADA4938-1/ADA4938-2 Driving an AD9446, 16-Bit, 80 MSPS ADC 200 VIN 90 VOCM 90 33 + ADA4938 DRVDD AD9246 VIN+ 33 0.1F AVDD VIN- 10pF D13 TO D0 AGND SENSE CML 30.1 -5V 200 06592-056 50 1.8V +5V 76.8 Figure 70. ADA4938-1/ADA4938-2 Driving an AD9246, a 14-Bit, 125 MSPS ADC Rev. B | Page 24 of 26 Data Sheet ADA4938-1/ADA4938-2 OUTLINE DIMENSIONS 3.10 3.00 SQ 2.90 PIN 1 INDICATOR 0.30 0.23 0.18 13 0.50 BSC PIN 1 INDICATOR 16 1 12 EXPOSED PAD 1.45 1.30 SQ 1.15 4 9 0.80 0.75 0.70 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.25 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 111808-A TOP VIEW 5 8 0.50 0.40 0.30 COMPLIANT TO JEDEC STANDARDS MO-220-WEED. Figure 71. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body and 0.75 mm Package Height (CP-16-21) Dimensions shown in millimeters 0.30 0.25 0.20 0.50 BSC PIN 1 INDICATOR 24 19 18 1 EXPOSED PAD TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 13 12 2.20 2.10 SQ 2.00 6 7 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY 0.08 0.20 REF SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8. 06-11-2012-A PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 72. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm x 4 mm Body, and 0.75 mm Package Height (CP-24-10) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADA4938-1ACPZ-R2 ADA4938-1ACPZ-RL ADA4938-1ACPZ-R7 ADA4938-2ACPZ-R2 ADA4938-2ACPZ-RL ADA4938-2ACPZ-R7 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 16-Lead LFCSP 16-Lead LFCSP 16-Lead LFCSP 24-Lead LFCSP 24-Lead LFCSP 24-Lead LFCSP Z = RoHS Compliant Part Rev. B | Page 25 of 26 Package Option CP-16-21 CP-16-21 CP-16-21 CP-24-10 CP-24-10 CP-24-10 Ordering Quantity 250 5,000 1,500 250 5,000 1,500 Branding H11 H11 H11 ADA4938-1/ADA4938-2 Data Sheet NOTES (c)2007-2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06592-0-6/16(B) Rev. B | Page 26 of 26 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: ADA4938-2ACP-EBZ