Ultralow Distortion
Differential ADC Driver
Data Sheet ADA4938-1/ADA4938-2
Rev. B Document Feedback
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FEATURES
Extremely low harmonic distortion (HD)
−106 dBc HD2 @ 10 MHz
−82 dBc HD2 @ 50 MHz
−109 dBc HD3 @ 10 MHz
−82 dBc HD3 @ 50 MHz
Low input voltage noise: 2.6 nV/√Hz
High speed
−3 dB bandwidth of 1000 MHz, G = +1
Slew rate: 4700 V/μs
0.1 dB gain flatness to 150 MHz
Fast overdrive recovery of 4 ns
1 mV typical offset voltage
Externally adjustable gain
Differential-to-differential or single-ended-to-differential
operation
Adjustable output common-mode voltage
Wide supply voltage range: +5 V to ±5 V
Single or dual amplifier configuration available
APPLICATIONS
ADC drivers
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
Line drivers
GENERAL DESCRIPTION
The ADA4938-1/ADA4938-2 are low noise, ultralow distortion,
high speed differential amplifiers. It is an ideal choice for
driving high performance ADCs with resolutions up to 16 bits
from dc to 27 MHz, or up to 12 bits from dc to 74 MHz. The
output common-mode voltage is adjustable over a wide range,
allowing the ADA4938-1/ADA4938-2 to match the input of the
ADC. The internal common-mode feedback loop also provides
exceptional output balance as well as suppression of even-order
harmonic distortion products.
Full differential and single-ended-to-differential gain configurations
are easily realized with the ADA4938-1/ADA4938-2. A simple
external feedback network of four resistors determines the
closed-loop gain of the amplifier.
The ADA4938-1/ADA4938-2 are fabricated using the Analog
Devices, Inc., proprietary third generation, high voltage XFCB
process, enabling it to achieve very low levels of distortion with
an input voltage noise of only 2.6 nV/√Hz. e low dc oset and
excellent dynamic performance of the ADA4938-1/ADA4938-2
FUNCTIONAL BLOCK DIAGRAMS
PD
06592-001
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
A
DA4938-1
TOP VIEW
–FB
+IN
–IN
+FB
–V
S
–V
S
–V
S
–V
S
–OUT
+OUT
V
OCM
+V
S
+V
S
+V
S
+V
S
Figure 1. ADA4938-1 Functional Block Diagram
06592-202
PD2
PD1
2
1
3
4
5
6
18
17
16
15
14
13
+IN2
–
FB2
+V
S1
+V
S1
+
FB1
–IN1
–OUT2
–V
S2
–V
S2
V
OCM1
+OUT1
8
9
10
11
7
+FB2
+V
S2
+V
S2
V
OCM2
12
+OUT2
–IN2
20
19
21
–OUT1
–V
S1
22 –V
S1
23 –FB1
24 +IN1
ADA4938-2
TOP VIEW
Figure 2. ADA4938-2 Functional Block Diagram
06592-002
–
50
–60
–70
–80
–90
–100
–110
–120
–130
1 10 100
SFDR (dBc)
FREQUENCY (MHz)
G = +2, V
O, dm
= 1V p-p
G = +2, V
O, dm
= 2V p-p
G = +2, V
O, dm
= 3.2V p-p
G = +2, V
O, dm
= 5V p-p
Figure 3. SFDR vs. Frequency and Output Voltage
makes them well-suited for a wide variety of data acquisition and
signal processing applications.
The ADA4938-1 (single amplifier) is available in a Pb-free,
3 mm × 3 mm, 16-lead LFCSP. The ADA4938-2 (dual
amplifier) is available in a Pb-free, 4 mm × 4 mm, 24-lead
LFCSP. The pinouts have been optimized to facilitate layout and
minimize distortion. The devices are specified to operate over
the extended industrial temperature range of −40°C to +85°C.
ADA4938-1/ADA4938-2 Data Sheet
Rev. B | Page 2 of 26
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Dual-Supply Operation ............................................................... 3
Single-Supply Operation ............................................................. 5
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Test Circuts ...................................................................................... 17
Terminology .................................................................................... 18
Theory of Operation ...................................................................... 19
Analyzing an Application Circuit ............................................ 19
Setting the Closed-Loop Gain .................................................. 19
Estimating the Output Noise Voltage ...................................... 19
The Impact of Mismatches in the Feedback Networks ......... 20
Calculating the Input Impedance of an Application Circuit ..... 20
Input Common-Mode Voltage Range in Single-Supply
Applications ................................................................................ 20
Terminating a Single-Ended Input .......................................... 21
Setting the Output Common-Mode Voltage .......................... 21
Layout, Grounding, and Bypassing .............................................. 23
High Performance ADC Driving ................................................. 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
6/2016—Rev. A to Rev. B
Changed CP-16-2 to CP-16-21, CP-24-1 to CP-24-10 .. Throughout
Changed ADA4938-x to ADA4938-1/ADA4938-2 .. Throughout
Changes to Figure 1 and Figure 2 ................................................... 1
Changes to Figure 5 and Figure 6 ................................................... 8
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 25
10/2009—Rev. 0 to Rev. A
Added Settling Time Parameter, Table 1 ....................................... 3
Changes to Linear Output Current Parameter, Table 1 ............... 3
Added Settling Time Parameter, Table 3 ........................................ 5
Changes to Linear Output Current Parameter, Table 3 ................ 5
Changes to Figure 5 and Figure 6 .................................................... 8
Added EP Row to Table 7 and EP Row to Table 8 ........................ 8
Changes to Figure 41 ...................................................................... 14
Added New Figure 53, Renumbered Sequentially ..................... 16
Changes to Table 9 .......................................................................... 19
Added Exposed Pad Notation to Outline Dimensions ............. 25
Changes to Ordering Guide .......................................................... 25
11/2007—Revision 0: Initial Version
Data Sheet ADA4938-1/ADA4938-2
Rev. B | Page 3 of 26
SPECIFICATIONS
DUAL-SUPPLY OPERATION
TA = 25°C, +VS = 5 V, −V S = −5 V, VOCM = 0 V, RT = 61.9 Ω, RG = RF = 200 Ω, G = +1, RL, dm = 1 kΩ, unless otherwise noted.
All specifications refer to single-ended input and differential output, unless otherwise noted. For gains other than G = +1, values for RF
and RG are shown in Table 11.
±DIN to ±OUT Performance
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth VOUT = 0.1 V p-p 1000 MHz
Bandwidth for 0.1 dB Flatness VOUT = 2 V p-p 150 MHz
Large Signal Bandwidth VOUT = 2 V p-p 800 MHz
Slew Rate VOUT = 2 V p-p 4700 V/µs
Settling Time VOUT = 2 V p-p 6.5 ns
Overdrive Recovery Time VIN = 5 V to 0 V step, G = +2 4 ns
NOISE/HARMONIC PERFORMANCE
Second Harmonic VOUT = 2 V p-p, 10 MHz −106 dBc
VOUT = 2 V p-p, 50 MHz −82 dBc
Third Harmonic VOUT = 2 V p-p, 10 MHz −109 dBc
VOUT = 2 V p-p, 50 MHz −82 dBc
IMD
f
1
= 30.0 MHz, f
2
= 30.1 MHz
89
dBc
IP3 f = 30 MHz, RL, dm = 100 Ω 45 dBm
Input Voltage Noise f = 10 MHz 2.6 nV/√Hz
Noise Figure G = +4, f = 10 MHz 15.8 dB
Input Current Noise f = 10 MHz 4.8 pA/√Hz
Crosstalk (ADA4938-2) f = 100 MHz −85 dB
INPUT CHARACTERISTICS
Offset Voltage VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = 0 V 1 4 mV
TMIN to TMAX variation ±4 µV/°C
Input Bias Current −18 −13 µA
TMIN to TMAX variation −0.01 µA/°C
Input Resistance Differential 6 MΩ
Common mode 3 MΩ
Input Capacitance 1 pF
Input Common-Mode Voltage
−V
S
+ 0.3 to +V
S
− 1.6
V
CMRR ∆VOUT, dm/∆VIN, cm; ∆VIN, cm = ±1 V, f = 1 MHz −75 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Maximum ∆VOUT; single-ended output −VS + 1.2 to +VS − 1.2 V
Linear Output Current Per amplifier, RL, dm = 20 Ω, f = 10 MHz ±75 mA
Output Balance Error ∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V; f = 10 MHz −60 dB
ADA4938-1/ADA4938-2 Data Sheet
Rev. B | Page 4 of 26
VOCM to ±OUT Performance
Table 2.
Parameter Conditions Min Typ Max Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth 230 MHz
Slew Rate VIN = −3.4 V to +3.4 V, 25% to 75% 1700 V/µs
Input Voltage Noise (RTI) 7.5 nV/√Hz
V
OCM
INPUT CHARACTERISTICS
Input Voltage Range −VS + 1.3 to +VS − 1.3 V
Input Resistance 10 kΩ
Input Offset Voltage VOS, cm = VOUT, cm; VDIN+ = VDIN− = 0 V 3 mV
Input Bias Current 0.5 µA
VOCM CMRR ∆VOUT, dm/∆VOCM; ∆VOCM = ±1 V −81 dB
Gain ∆VOUT, cm/∆VOCM; ∆VOCM = ±1 V 0.95 1.00 1.05 V/V
POWER SUPPLY
Operating Range 4.5 11 V
Quiescent Current Per amplifier 37 40 mA
TMIN to TMAX variation 40 µA/°C
Powered down 2.0 3.0 mA
Power Supply Rejection Ratio ∆VOUT, dm/∆VS; ∆VS = ±1 V −80 dB
POWER DOWN (PD)
PD Input Voltage Powered down ≤2.5 V
Enabled ≥3 V
Turn-Off Time 1 µs
Turn-On Time
200
ns
PD Bias Current
Enabled PD = 5 V 1 µA
Disabled PD = −5 V −760 µA
OPERATING TEMPERATURE RANGE −40 +85 °C
Data Sheet ADA4938-1/ADA4938-2
Rev. B | Page 5 of 26
SINGLE-SUPPLY OPERATION
TA = 25°C, +VS = 5 V, −V S = 0 V, V OCM = +VS/2, RT = 61.9 Ω, RG = RF = 200 Ω, G = +1, RL, dm = 1 kΩ, unless otherwise noted.
All specifications refer to single-ended input and differential output, unless otherwise noted. For gains other than G = 1, values for RF and
RG are shown in Table 11.
±DIN to ±OUT Performance
Table 3.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth VOUT = 0.1 V p-p 1000 MHz
Bandwidth for 0.1 dB Flatness VOUT = 2 V p-p 150 MHz
Large Signal Bandwidth VOUT = 2 V p-p 750 MHz
Slew Rate VOUT = 2 V p-p 3900 V/µs
Settling Time VOUT = 2 V p-p 6.5 ns
Overdrive Recovery Time VIN = 2.5 V to 0 V step, G = +2 4 ns
NOISE/HARMONIC PERFORMANCE
Second Harmonic VOUT = 2 V p-p, 10 MHz −110 dBc
VOUT = 2 V p-p, 50 MHz −79 dBc
Third Harmonic VOUT = 2 V p-p, 10 MHz −100 dBc
VOUT = 2 V p-p, 50 MHz −79 dBc
Input Voltage Noise f = 10 MHz 2.6 nV/√Hz
Noise Figure G = +4, f = 10 MHz 15.8 dB
Input Current Noise f = 10 MHz 4.8 pA/√Hz
Crosstalk (ADA4938-2) f = 100 MHz −85 dB
INPUT CHARACTERISTICS
Offset Voltage VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = VOCM = 2.5 V 1 4 mV
T
MIN
to T
MAX
variation
±4
µV/°C
Input Bias Current −18 −13 µA
TMIN to TMAX variation −0.01 µA/°C
Input Resistance Differential 6 MΩ
Common mode 3 MΩ
Input Capacitance 1 pF
Input Common-Mode Voltage −VS + 0.3 to +VS − 1.6 V
CMRR ∆VOUT, dm/∆VIN, cm; ∆VIN, cm = ±1 V −80 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Maximum ∆VOUT; single-ended output −VS + 1.2 to +VS − 1.2 V
Linear Output Current Per amplifier, RL, dm = 20 Ω, f = 10 MHz ±65 mA
Output Balance Error ∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V −60 dB
ADA4938-1/ADA4938-2 Data Sheet
Rev. B | Page 6 of 26
VOCM to ±OUT Performance
Table 4.
Parameter Conditions Min Typ Max Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth 400 MHz
Slew Rate VIN = 1.6 V to 3.4 V, 25% to 75% 1700 V/µs
Input Voltage Noise (RTI) 7.5 nV/√Hz
V
OCM
INPUT CHARACTERISTICS
Input Voltage Range −VS + 1.3 to +VS − 1.3 V
Input Resistance 10 kΩ
Input Offset Voltage VOS, cm = VOUT, cm; VDIN+ = VDIN– = VOCM = 2.5 V 3 mV
Input Bias Current 0.5 µA
VOCM CMRR ∆VOUT, dm/∆VOCM; ∆VOCM = ±1 V −89 dB
Gain ∆VOUT, cm/∆VOCM; ∆VOCM = ±1 V 0.95 1.00 1.05 V/V
POWER SUPPLY
Operating Range 4.5 11 V
Quiescent Current 34 36.5 mA
TMIN to TMAX variation 40 µA/°C
Powered down 1.0 1.7 mA
Power Supply Rejection Ratio ∆VOUT, dm/∆VS; ∆VS = ±1 V −80 dB
POWER DOWN (PD)
PD Input Voltage Powered down ≤2.5 V
Enabled ≥3 V
Turn-Off Time 1 µs
Turn-On Time
200
ns
PD Bias Current
Enabled PD = 5 V 1 µA
Disabled PD = 0 V −260 µA
OPERATING TEMPERATURE RANGE −40 +85 °C
Data Sheet ADA4938-1/ADA4938-2
Rev. B | Page 7 of 26
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Supply Voltage 12 V
Power Dissipation
See Figure 4
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the device (including exposed pad) soldered
to a high thermal conductivity 4-layer circuit board, as described in
EIA/JESD 51-7. The exposed pad is not electrically connected to
the device. It is typically soldered to a pad on the PCB that is
thermally and electrically connected to an internal ground plane.
Table 6. Thermal Resistance
Package Type θJA Unit
16-Lead LFCSP (Exposed Pad) 95 °C/W
24-Lead LFCSP (Exposed Pad) 65 °C/W
Maximum Power Dissipation
The maximum safe power dissipation in the ADA4938-1/
ADA4938-2 packages is limited by the associated rise in
junction temperature (TJ) on the die. At approximately 150°C,
which is the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature limit
can change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the
ADA4938-1/ADA4938-2. Exceeding a junction temperature of
150°C for an extended period can result in changes in the silicon
devices, potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the voltage
between the supply pins (VS) times the quiescent current (IS).
The power dissipated due to the load drive depends upon the
particular application. The power due to load drive is calculated
by multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used in
these calculations.
Airflow increases heat dissipation, which effectively reduces θJA.
In addition, more metal directly in contact with the package
leads/exposed pad from metal traces, through-holes, ground,
and power planes reduces the θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the ADA4938-1,
16-lead LFCSP (95°C/W) and the ADA4938-2, 24-lead LFCSP
(65°C/W) on a JEDEC standard 4-layer board.
3.5
2.5
3.0
2.0
1.5
1.0
0.5
0
–40 –30 –20 –10 010 20 30 40 50 60 70 80 90
MAXIMUM POWER DISSIPATIO N (W)
AMBI ENT T E M P E RATURE ( °C)
06592-103
ADA4938-1
ADA4938-2
Figure 4. Maximum Power Dissipation vs. Temperature, 4-Layer Board
ESD CAUTION
ADA4938-1/ADA4938-2 Data Sheet
Rev. B | Page 8 of 26
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NOTES
1. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED
TO THE DEVICE. IT IS TYPICALLY SOLDERED TO GROUND
OR A POWER PLANE ON THE PCB THAT IS THERMALLY
CONDUCTIVE.
PD
06592-003
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
–FB
+IN
–IN
+FB
–V
S
–V
S
–V
S
–V
S
–OUT
+OUT
V
OCM
+V
S
+V
S
+V
S
+V
S
ADA4938-1
TOP VIEW
(Not to Scale)
Figure 5. ADA4938-1 Pin Configuration
06592-206
NOTES
1. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED
TO THE DEVICE. IT IS TYPICALLY SOLDERED TO GROUND
OR A POWER PLANE ON THE PCB THAT IS THERMALLY
CONDUCTIVE.
PD2
PD1
2
1
3
4
5
6
18
17
16
15
14
13
+IN2
–FB2
+V
S1
+V
S1
+FB1
–IN1
–OUT2
–V
S2
–V
S2
V
OCM1
+OUT1
8
9
10
11
7
+FB2
+V
S2
+V
S2
V
OCM2
12
+OUT2
–IN2
20
19
21
–OUT1
–V
S1
22 –V
S1
23 –FB1
24 +IN1
ADA4938-2
TOP VIEW
(Not to Scale)
Figure 6. ADA4938-2 Pin Configuration
Table 7. ADA4938-1 Pin Function Descriptions
Pin No. Mnemonic Description
1 −FB Negative Output Feedback Pin.
2 +IN Positive Input Summing Node.
3 −IN Negative Input Summing Node.
4 +FB Positive Output Feedback Pin.
5 to 8 +VS Positive Supply Voltage.
9 VOCM Output Common-Mode Voltage.
10 +OUT Positive Output for Load Connection.
11 −OUT Negative Output for Load Connection.
12 PD Power-Down Pin.
13 to 16 −VS Negative Supply Voltage.
EP Exposed Paddle. The exposed pad is not
electrically connected to the device. It is
typically soldered to ground or a
power plane on the PCB that is
thermally conductive.
Table 8. ADA4938-2 Pin Function Descriptions
Pin No. Mnemonic Description
1 −IN1 Negative Input Summing Node 1.
2 +FB1 Positive Output Feedback Pin 1.
3, 4 +VS1 Positive Supply Voltage 1.
5 −FB2 Negative Output Feedback Pin 2.
6 +IN2 Positive Input Summing Node 2.
7 −IN2 Negative Input Summing Node 2.
8 +FB2 Positive Output Feedback Pin 2.
9, 10 +VS2 Positive Supply Voltage 2.
11 VOCM2 Output Common-Mode Voltage 2.
12 +OUT2 Positive Output 2.
13 −OUT2
Negative Output 2.
14 PD2 Power-Down Pin 2.
15, 16 −
V
S2 Negative Supply Voltage 2.
17
V
OCM1 Output Common-Mode Voltage 1.
18 +OUT1 Positive Output 1.
19 −OUT1 Negative Output 1.
20 PD1 Power-Down Pin 1.
21, 22 −VS1 Negative Supply Voltage 1.
23 −FB1 Negative Output Feedback Pin 1.
24 +IN1 Positive Input Summing Node 1.
EP Exposed Paddle. The exposed pad is
not electrically connected to the
device. It is typically soldered to
ground or a power plane on the PCB
that is thermally conductive.
Data Sheet ADA4938-1/ADA4938-2
Rev. B | Page 9 of 26
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, +VS = 5 V, −VS = −5 V, VOCM = 0 V, RT = 61.9 , RG = RF = 200 , G = +1, RL, dm = 1 kΩ, unless otherwise noted.
All measurements were performed with single-ended input and differential output, unless otherwise noted. For gains other than G = +1,
values for RF and RG are shown in Table 11.
3
0
–3
–6
–9
–12
1 10 100 1000
NORMALIZED GAIN (dB)
FREQUENCY (MHz)
G = +1
G = +2
G = +3.16
G = +5
06592-105
Figure 7. Small Signal Frequency Response for Various Gains, VOUT = 0.1 V p-p
3
0
–3
–6
–9
–12
1 10 100 1000
GAIN (dB)
FREQUENCY (MHz)
V
S
= +5V
V
S
= ±5V
06592-106
Figure 8. Small Signal Response for Various Supplies, VOUT = 0.1 V p-p
3
0
–3
–6
–9
–12
1 10 100 1000
NORMALIZED GAIN (dB)
FREQUENCY (MHz)
–40°C
+25°C
+85°C
06592-107
Figure 9. Small Signal Frequency Response for
Various Temperatures, VOUT = 0.1 V p-p
3
0
–3
–6
–9
–12
1 10 100 1000
NORMALIZED GAIN (dB)
FREQUENCY (MHz)
G = +1
G = +2
G = +3.16
G = +5
06592-108
Figure 10. Large Signal Frequency Response for Various Gains
3
0
–3
–6
–9
–12
1 10 100 1000
GAIN (dB)
FREQUENCY (MHz)
V
S
= +5V
V
S
= ±5V
06592-109
Figure 11. Large Signal Response for Various Supplies
3
0
–3
–6
–9
–12
1 10 100 1000
NORMALIZED GAIN (dB)
FREQUENCY (MHz)
–40°C
+25°C
+85°C
06592-110
Figure 12. Large Signal Frequency Response for Various Temperatures
ADA4938-1/ADA4938-2 Data Sheet
Rev. B | Page 10 of 26
1 10 100 1000
3
0
–21
–18
–15
–12
–9
–6
–3
NORMALIZED GAIN (dB)
FREQUENCY (MHz)
R
L
= 1kΩ
R
L
= 100Ω
R
L
= 200Ω
06592-111
Figure 13. Small Signal Frequency Response for
Various Loads, VOUT = 0.1 V p-p
3
0
–3
–6
–9
–12
1 10 100 1000
NORMALIZED GAIN (dB)
FREQUENCY (MHz)
G = +1
G = +2
G = +3.16
G = +5
06592-112
Figure 14. Small Signal Frequency Response for
Various Gains, VS = 5 V, VOUT = 0.1 V p-p
6
–12
–9
–6
–3
0
3
1 10 100 1000
NORMALIZED GAIN (dB)
FREQUENCY (MHz)
G = +1
G = +2
G = +3.16
G = +5
06592-113
Figure 15. Small Signal Response for Various Gains, RF = 402 Ω, VOUT = 0.1 V p-p
1 10 100 1000
3
0
–21
–18
–15
–12
–9
–6
–3
NORMALIZED GAIN (dB)
FREQUENCY (MHz)
R
L
= 1kΩ
R
L
= 100Ω
R
L
= 200Ω
06592-114
Figure 16. Large Signal Frequency Response for Various Loads
3
0
–3
–6
–9
–12
1 10 100 1000
NORMALIZED GAIN (dB)
FREQUENCY (MHz)
G = +1
G = +2
G = +3.16
G = +5
06592-115
Figure 17. Large Signal Frequency Response for Various Gains, VS = 5 V
6
–12
–9
–6
–3
0
3
1 10 100 1000
NORMALIZED GAIN (dB)
FREQUENCY (MHz)
G = +1
G = +2
G = +3.16
G = +5
06592-116
Figure 18. Large Signal Response for Various Gains, RF = 402 Ω
Data Sheet ADA4938-1/ADA4938-2
Rev. B | Page 11 of 26
1 10 100 1000
6
–12
–9
–6
–3
3
0
NORMALIZED GAIN (dB)
FREQUENCY (MHz)
G = +1
G = +2
G = +3.16
G = +5
06592-117
Figure 19. Small Signal Frequency Response for Various Gains, RF = 402 Ω,
VS = 5 V, VOUT = 0.1 V p-p
3
–12
–9
–6
–3
0
1 10 100 1000
GAIN (dB)
FREQUENCY (MHz)
V
S
= +5V
V
S
= ±5V
06592-118
Figure 20. VOUT, cm Small Signal Frequency Response, VOUT = 0.1 V p-p
1 10 100 1000
1.0
–1.0
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
NORMALIZED GAIN (dB)
FREQUENCY (MHz)
R
L, dm
= 1kΩ
R
L, dm
= 100Ω
R
L, dm
= 200Ω
06592-119
Figure 21. 0.1 dB Flatness Response for Various Loads, ADA4938-1,
VOUT = 0.1 V p-p
1 10 100 1000
6
3
0
–3
–6
–9
–12
NORMALIZED GAIN (dB)
FREQUENCY (MHz)
G = +1
G = +2
G = +3.16
G = +5
06592-120
Figure 22. Large Signal Frequency Response for Various Gains, RF = 402 Ω,
VS = 5 V
3
–12
–9
–6
–3
0
1 10 100 1000
GAIN (dB)
FREQUENCY (MHz)
V
S
= +5V
V
S
= ±5V
06592-121
Figure 23. VOUT, cm Large Signal Frequency Response
1 10 100 1000
1.5
1.4
1.3
1.2
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
GAIN (dB)
FREQUENCY (MHz)
R
L, dm
= 1kΩ
R
L, dm
= 100Ω
R
L, dm
= 200Ω
06592-122
Figure 24. 0.1 dB Flatness Response for Various Loads, ADA4938-2,
VOUT = 0.1 V p-p
ADA4938-1/ADA4938-2 Data Sheet
Rev. B | Page 12 of 26
1 10 100
–
40
–120
–110
–100
–90
–80
–70
–60
–50
DISTORTION (dBc)
FREQUENCY (MHz)
HD2, V
S
= +5V
HD3, V
S
= +5V
HD2, V
S
= ±5V
HD3, V
S
= ±5V
06592-123
Figure 25. Harmonic Distortion vs. Frequency and Supply Voltage
1 10 100
–
40
–130
–120
–100
–110
–90
–80
–70
–60
–50
DISTORTION (dBc)
FREQUENCY (MHz)
HD2, G = +1
HD3, G = +1
HD2, G = +2
HD3, G = +2
HD2, G = +5
HD3, G = +5
06592-124
Figure 26. Harmonic Distortion vs. Frequency and Gain
–3.3 –2.7 –2.1 –1.5 –0.9 –0.3 0.3 0.9 1.5 2.1 2.7 3.3
–
40
–130
–120
–110
–100
–90
–80
–70
–60
–50
DISTORTION (dBc)
V
OCM
(V)
HD2, 10MHz
HD3, 10MHz
HD2, 70MHz
HD3, 70MHz
06592-128
Figure 27. Harmonic Distortion vs. VOCM and Frequency
0987654312
–
40
–120
–110
–100
–90
–80
–70
–60
–50
DISTORTION (dBc)
V
OUT, dm
(V)
HD2, +5V
HD3, +5V
HD2, ±5V
HD3, ±5V
06592-126
Figure 28. Harmonic Distortion vs. VOUT and Supply Voltage
1 10 100
–
40
–120
–110
–100
–90
–80
–70
–60
–50
DISTORTION (dBc)
FREQUENCY (MHz)
HD2, R
L
= 1kΩ
HD3, R
L
= 1kΩ
HD2, R
L
= 200Ω
HD3, R
L
= 200Ω
HD2, R
L
= 100Ω
HD3, R
L
= 100Ω
06592-127
Figure 29. Harmonic Distortion vs. Frequency for Various Loads
1.7 3.33.12.92.72.52.32.11.9
–
40
–120
–110
–100
–90
–80
–70
–60
–50
DISTORTION (dBc)
V
OCM
(V)
06592-125
HD2, 10MHz
HD3, 10MHz
HD2, 70MHz
HD3, 70MHz
Figure 30. Harmonic Distortion vs. VOCM and Frequency, VS = 5 V
Data Sheet ADA4938-1/ADA4938-2
Rev. B | Page 13 of 26
10
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
29.5 30.530.430.330.230.130.029.929.829.729.6
DISTORTION (dBc)
FREQUENCY (MHz)
06592-129
Figure 31. Intermodulation Distortion
–
20
–85
–80
–75
–70
–65
–60
–55
–50
–45
–40
–35
–30
–25
0.1 1000100101
V
IN
CMRR (dB)
FREQUENCY (MHz)
06592-130
V
S
= +5V
V
S
= ±5V
Figure 32. VIN CMRR vs. Frequency
–
15
–65
–60
–55
–50
–45
–40
–35
–30
–25
–20
1 100010010
OUTPUT BALANCE (dB)
FREQUENCY (MHz)
06592-131
R
L
= 200Ω
Figure 33. Output Balance vs. Frequency
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
0.1 1000100101
PSRR (dB)
FREQUENCY (MHz)
06592-132
+PSRR
–PSRR
Figure 34. PSRR vs. Frequency
0
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
1 10 100 1000
RETURN LOSS (dB)
FREQUENCY (MHz)
S11
S22
06592-134
Figure 35. Return Loss (S11, S22) vs. Frequency
1 10 100
–
40
–120
–110
–100
–90
–80
–70
–60
–50
SFDR (dBc)
FREQUENCY (MHz)
R
L
= 1kΩ
R
L
= 200Ω
R
L
= 100Ω
06592-135
Figure 36. SFDR vs. Frequency for Various Loads
ADA4938-1/ADA4938-2 Data Sheet
Rev. B | Page 14 of 26
26
24
22
20
18
16
14
12
1010 500100
NOISE FIGURE (dB)
FREQUENCY (MHz)
06592-136
G = +1
G = +2
G = +4
Figure 37. Noise Figure vs. Frequency
060555045403530252015105
10
–10
–8
–6
–4
–2
0
2
4
6
8
VOLTAGE (V)
TIME (5ns/DIV)
VIN × 3.16
VOUT, dm
06592-137
Figure 38. Overdrive Recovery Time (Pulse Input)
0500450400350300
25020015010050
12
–12
–10
–8
–6
–4
–2
0
2
4
6
8
10
VOLTAGE (V)
TIME (50ns/DIV)
V
IN
× 3.16
V
OUT
, dm
06592-138
Figure 39. Overdrive Amplitude Characteristics (Triangle Wave Input)
06592-039
100
10
110 100 1k 10k 100M100k 1M 10M
INPUT VOLTAGE NOISE (nV/ Hz)
FREQUENCY ( Hz )
Figure 40. Input Voltage Noise vs. Frequency
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
VOLTAGE (V)
TI ME (200ns/ DIV)
PD INP UT
NEGATIVE OUTPUT
06592-140
Figure 41. Power-Down Response Time
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
45
40
35
30
25
20
15
10
5
0
CURRENT (mA)
VOLTAGE (V)
+85°C
+25°C
–40°C
06592-141
Figure 42. Supply Current vs. Power-Down Voltage and Temperature
Data Sheet ADA4938-1/ADA4938-2
Rev. B | Page 15 of 26
0.20
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
VOLTAGE (V)
TIME (1ns/DIV)
06592-142
Figure 43. Small Signal Transient Response, VOUT = 0.1 V p-p
06592-043
0.10
0.08
0.04
0.06
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
VOLTAGE (V)
TIME (2ns/DIV)
Figure 44. VOCM Small Signal Transient Response, VOUT = 0.1 V p-p
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0
60
50
40
30
20
10
0
CURRENT (mA)
VOLTAGE (V)
+85°C
+25°C
–40°C
06592-144
Figure 45. Supply Current vs. Power-Down Voltage and Temperature, VS = 5 V
3.0
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
VOLTAGE (V)
TIME (1ns/DIV)
06592-145
Figure 46. Large Signal Transient Response
06592-046
2.5
2.0
1.0
1.5
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
VOLTAGE (V)
TIME (2ns/DIV)
Figure 47. VOCM Large Signal Transient Response
3
0
–3
–6
–9
–12
1 10 100 1000
CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
VOCM = –3.7V
ALL CURVES ARE
NORMALIZED TO VOCM = 0V
VOCM = –3.5V
VOCM = –3V
VOCM = 0V
VOCM = +3V
VOCM = +3.5V
VOCM = +3.7V
06592-048
Figure 48. VOUT, dm Small Signal Frequency Response for Various VOCM,
VOUT = 0.1 V p-p
ADA4938-1/ADA4938-2 Data Sheet
Rev. B | Page 16 of 26
55
50
45
40
35
30
06592-049
IP3 (dBm)
10 100
FREQUENCY (MHz)
IP3 100Ω
Figure 49. IP3 vs. Frequency
3
0
–3
–6
–9
–12
1 10 100 1000
CLOSED-LOOP GAIN (dB)
FREQUENCY (MHz)
V
OCM
= –3.7V
ALL CURVES ARE
NORMALIZED TO V
OCM
= 0V
V
OCM
= –3.5V
V
OCM
= –3V
V
OCM
= 0V
V
OCM
= +3V
V
OCM
= +3.5V
V
OCM
= +3.7V
06592-50
Figure 50. VOUT, dm Large Signal Frequency Response for Various VOCM
06592-051
100
10
110 100 1k 10k 100M100k 1M 10M
INPUT CURRENT NOISE (pA/ Hz)
FREQUENCY (Hz)
Figure 51. Input Current Noise vs. Frequency
06592-888
–
40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
0.3 1 10 100 1000
CROSSTALK (dB)
FREQUENCY (MHz)
INPUT1, OUTPUT2
INPUT2, OUTPUT1
Figure 52. Crosstalk vs. Frequency for ADA4938-2
2
1
–2
1.0
–1.0
–0.5
VIN
0
0.5
0.1
–0.1
–1
0
VIN (V)
SETTLING ERROR (%)
TIME (1ns/DIV)
06592-153
SETTLING ERROR
Figure 53. 0.1% Settling Time
Data Sheet ADA4938-1/ADA4938-2
Rev. B | Page 17 of 26
TEST CIRCUTS
ADA4938
1kΩ
+5V
–5V
200Ω
200Ω50Ω
200Ω
27.5Ω
200Ω
V
OCM
61.9Ω
V
IN
06592-246
Figure 54. Equivalent Basic Test Circuit
ADA4938
+5V
–5V
200Ω
200Ω50Ω
200Ω
50Ω
50Ω
27.5Ω
200Ω
V
OCM
61.9Ω
V
IN
06592-247
Figure 55. Test Circuit for Output Balance
0
6592-248
ADA4938
+5V
–5V
200
Ω
200Ω50Ω
200Ω
412Ω
412Ω
27.5Ω
200Ω
V
OCM
61.9Ω
V
IN
FILTER
0.1µF
0.1µF
FILTER
Figure 56. Test Circuit for Distortion Measurements
ADA4938-1/ADA4938-2 Data Sheet
Rev. B | Page 18 of 26
TERMINOLOGY
ADA4938
+IN
–IN +OUT
–OUT
–FB
+FB
VOCM
RGRF
RG
VOUT, dm
RL, dm
RF
06592-004
Figure 57. Circuit Definitions
Differential Voltage
The differential voltage is the difference between two node
voltages. For example, the output differential voltage (or
equivalently, output differential-mode voltage) is defined as
VOUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT terminals with respect to a common reference.
Common-Mode Voltage
The common-mode voltage is the average of two node voltages.
The output common-mode voltage is defined as
VOUT, cm = (V+OUT + V−OUT)/2
Balance
Balance is a measure of how well differential signals are matched in
amplitude and are exactly 180° apart in phase. Balance is most
easily determined by placing a well-matched resistor divider
between the differential voltage nodes and comparing the
magnitude of the signal at the midpoint of the divider with
the magnitude of the differential signal. By this definition,
output balance is the magnitude of the output common-mode
voltage divided by the magnitude of the output differential
mode voltage.
dmOUT
cmOUT
V
V
ErrorBalanceOutput
,
,
=
Data Sheet ADA4938-1/ADA4938-2
Rev. B | Page 19 of 26
THEORY OF OPERATION
The ADA4938-1/ADA4938-2 differ from conventional op amps
in that they have two outputs whose voltages move in opposite
directions. Like an op amp, it relies on open-loop gain and
negative feedback to force these outputs to the desired voltages.
The ADA4938-1/ADA4938-2 behave much like a standard
voltage feedback op amp and makes it easier to perform single-
ended-to-differential conversions, common-mode level shifting,
and amplifications of differential signals. Also like an op amp,
the ADA4938-1/ADA4938-2 have high input impedance and
low output impedance.
Two feedback loops are employed to control the differential and
common-mode output voltages. The differential feedback, set
with external resistors, controls only the differential output
voltage. The common-mode feedback controls only the common-
mode output voltage. This architecture makes it easy to set the
output common-mode level to any arbitrary value. It is forced,
by internal common-mode feedback, to be equal to the voltage
applied to the VOCM input, without affecting the differential
output voltage.
The ADA4938-1/ADA4938-2 architecture results in outputs
that are highly balanced over a wide frequency range without
requiring tightly matched external components. The common-
mode feedback loop forces the signal component of the output
common-mode voltage to zero, which results in nearly perfectly
balanced differential outputs that are identical in amplitude and
are exactly 180° apart in phase.
ANALYZING AN APPLICATION CIRCUIT
The ADA4938-1/ADA4938-2 use open-loop gain and negative
feedback to force its differential and common-mode output
voltages in such a way as to minimize the differential and
common-mode error voltages. The differential error voltage is
defined as the voltage between the differential inputs labeled
+IN and −IN (see Figure 57). For most purposes, this voltage
can be assumed to be zero. Similarly, the difference between the
actual output common-mode voltage and the voltage applied to
VOCM can also be assumed to be zero. Starting from these two
assumptions, any application circuit can be analyzed.
SETTING THE CLOSED-LOOP GAIN
The differential-mode gain of the circuit in Figure 57 can be
determined by
G
F
dmIN
dmOUT
R
R
V
V=
,
,
This assumes the input resistors (RG) and feedback resistors (RF)
on each side are equal.
ESTIMATING THE OUTPUT NOISE VOLTAGE
The differential output noise of the ADA4938-1/ADA4938-2
can be estimated using the noise model in Figure 58. The input-
referred noise voltage density, vnIN, is modeled as a differential
input, and the noise currents, inIN− and inIN+, appear between
each input and ground. The noise currents are assumed to be
equal and produce a voltage across the parallel combination of
the gain and feedback resistances. vn, cm is the noise voltage
density at the VOCM pin. Each of the four resistors contributes
(4kTR)1/2. Table 9 summarizes the input noise sources, the
multiplication factors, and the output-referred noise density terms.
ADA4938
+
RF2
VnOD
VnCM
VOCM
VnIN
RF1
RG2
RG1 VnRF1
VnRF2
VnRG1
VnRG2
inIN+
inIN–
06592-005
Figure 58. ADA4938-1/ADA4938-2 Noise Model
Table 9. Output Noise Voltage Density Calculations
Input Noise Contribution Input Noise Term
Input Noise
Voltage Density
Output
Multiplication Factor
Output Noise
Voltage Density Term
Differential Input vnIN vnIN GN vnO1 = GN(vnIN)
Inverting Input inIN− inIN− × (RG2||RF2) GN vnO2 = GN[inIN− × (RG2||RF2)]
Noninverting Input inIN+ inIN+ × (RG1||RF1) GN vnO3 = GN[inIN+ × (RG1||RF1)]
V
OCM
Input
v
n, cm
v
n, cm
G
N
(β
1
− β
2
)
v
nO4
= G
N
(β
1
− β
2
)(v
nCM
)
Gain Resistor, RG1 vnRG1 (4kTRG1)1/2 GN(1 − β1) vnO5 = GN(1 − β1)(4kTRG1)1/2
Gain Resistor, RG2 vnRG2 (4kTRG2)1/2 GN(1 − β2) vnO6 = GN(1 − β2)(4kTRG2)1/2
Feedback Resistor, RF1 vnRF1 (4kTRF1)1/2 1 vnO7 = (4kTRF1)1/2
Feedback Resistor, RF2 vnRF2 (4kTRF2)1/2 1 vnO8 = (4kTRF2)1/2
ADA4938-1/ADA4938-2 Data Sheet
Rev. B | Page 20 of 26
Similar to the case of a conventional op amp, the output noise
voltage densities can be estimated by multiplying the input-
referred terms at +IN and −IN by the appropriate output factor,
where:
21
Nββ
G
2is the circuit noise gain.
G1
F1
G1
1RR
R
β
and
G2
F2
G2
2RR
R
β
are the feedback factors.
When RF1/RG1 = RF2/RG2, β1 = β2 = β, and the noise gain
becomes
G
F
NR
R
β
G 1
1
Note that the output noise from VOCM goes to zero in this case.
The total differential output noise density, vnOD, is the root-sum-
square of the individual output noise terms.
8
1i
2
nOinOD vv
THE IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
As previously mentioned, even if the external feedback networks
(RF/RG) are mismatched, the internal common-mode feedback
loop still forces the outputs to remain balanced. The amplitudes
of the signals at each output remain equal and 180° out of phase.
The input-to-output, differential mode gain varies proportionately
to the feedback mismatch, but the output balance is unaffected.
As well as causing a noise contribution from VOCM, ratio matching
errors in the external resistors result in a degradation of the
ability of the circuit to reject input common-mode signals, much
the same as for a four-resistor difference amplifier made from a
conventional op amp.
In addition, if the dc levels of the input and output common-
mode voltages are different, matching errors result in a small
differential-mode output offset voltage. When G = +1, with a
ground referenced input signal and the output common-mode
level set to 2.5 V, an output offset of as much as 25 mV (1% of
the difference in common-mode levels) can result if 1% tolerance
resistors are used. Resistors of 1% tolerance result in a worst-case
input CMRR of about 40 dB, a worst-case differential-mode
output offset of 25 mV due to 2.5 V level-shift, and no significant
degradation in output balance error.
CALCULATING THE INPUT IMPEDANCE OF AN
APPLICATION CIRCUIT
The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
in Figure 59, the input impedance (RIN, dm) between the inputs
(+DIN and −DIN) is simply RIN, dm = 2 × RG.
+V
S
ADA4938
+IN
–IN
R
F
R
F
+D
IN
–D
IN
V
OCM
R
G
R
G
V
OUT, dm
06592-006
Figure 59. ADA4938-1/ADA4938-2 Configured for Balanced (Differential) Inputs
For an unbalanced, single-ended input signal (see Figure 60),
the input impedance is
F
G
F
G
cmIN
RR
R
R
R
2
1
,
R
T
R
S
ADA4938
+V
S
R
F
R
G
R
S
R
G
R
F
V
OCM
R
T
V
OUT, dm
06592-007
Figure 60. ADA4938-1/ADA4938-2 Configured for Unbalanced
(Single-Ended) Input
The input impedance of the circuit is effectively higher than it
would be for a conventional op amp connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
the voltage across the Input Gain Resistor RG.
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
The ADA4938-1/ADA4938-2 is optimized for level-shifting,
ground-referenced input signals. As such, the center of the input
common-mode range is shifted approximately 1 V down from
midsupply. The input common-mode range at the summing
nodes of the amplifier is from 0.3 V above −VS to 1.6 V below
+VS. To avoid clipping at the outputs, the voltage swing at the
+IN and −IN terminals must be confined to these ranges.
Data Sheet ADA4938-1/ADA4938-2
Rev. B | Page 21 of 26
TERMINATING A SINGLE-ENDED INPUT
Using an example with an input source of 2 V, a source
resistance of 50 Ω, and an overall gain of 1 V/V, four simple
steps must be followed to terminate a single-ended input to the
ADA4938-1/ADA4938-2.
1. The input impedance is calculated using the formula
267
200)(2002
200
1
200
2
1
F
G
F
G
IN
RR
R
R
R
06592-081
ADA4938
R
L
V
O
+V
S
–V
S
R
S
50Ω
R
G
200Ω
R
G
200Ω
R
F
200Ω
R
F
200Ω
V
OCM
V
S
2V
R
IN
267Ω
Figure 61. Single-Ended Input Impedance
2. To provide a 50 Ω termination for the source, the Resistor RT
is calculated such that RT || RIN = 50 Ω, or RT = 61.9 Ω.
06592-082
ADA4938
R
L
V
O
+V
S
–V
S
R
S
50Ω
R
G
200Ω
R
G
200Ω
R
F
200Ω
R
F
200Ω
V
OCM
V
S
2V
50Ω
R
T
61.9Ω
Figure 62. Adding Termination Resistor RT
3. To compensate for the imbalance of the gain resistors, a correc-
tion resistor (RTS) is added in series with the inverting Input
Gain Resistor RG. RTS is equal to the Thevenin equivalent of
the source resistance (RS||RT).
06592-083
R
S
50Ω
V
S
2V
R
T
61.9Ω
R
TH
27.4Ω
V
TH
1.1V
Figure 63. Calculating Thevenin Equivalent
RTS = RTH = RS || RT = 27.4 Ω. Note that VTH is not equal to
VS/2, which would be the case if the amplifier circuit did
not affect the termination.
06592-084
ADA4938
R
L
V
O
0.97V
+V
S
–V
S
R
TH
27.4Ω
R
G
200Ω
R
G
200Ω
R
F
200Ω
R
F
200Ω
V
OCM
V
TH
1.1V
R
TS
27.4Ω
Figure 64. Balancing Gain Resistor RG
4. Finally, the feedback resistor is recalculated to adjust the
output voltage to the desired level.
a. To make the output voltage VO = 1 V, RF is calculated
using
207
1.1
27.4)(2001
)(
TH
TS
GO
FV
RRV
R
b. To return the overall gain to 1 V/V (VO = VS = 2 V), RF
should be
414
1.1
27.4)(2002
)(
TH
TS
GO
FV
RRV
R
06592-085
ADA4938
R
L
V
O
+V
S
–V
S
R
S
50Ω
R
G
200Ω
R
G
200Ω
R
F
R
F
V
OCM
V
S
2V
R
T
61.9Ω
R
TS
27.4Ω
Figure 65. Complete Single-Ended-to-Differential System
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The VOCM pin of the ADA4938-1/ADA4938-2 is internally
biased at a voltage approximately equal to the midsupply point
(average value of the voltages on V+ and V−). Relying on this
internal bias results in an output common-mode voltage that is
within about 100 mV of the expected value.
In cases where more accurate control of the output common-
mode level is required, it is recommended that an external
source or resistor divider (10 kΩ or greater resistors) be used.
It is also possible to connect the VOCM input to a common-mode
level (CML) output of an ADC. However, care must be taken to
ensure that the output has sufficient drive capability. The input
impedance of the VOCM pin is approximately 10 kΩ. If multiple
ADA4938-1/ADA4938-2 devices share one reference output, it is
recommended that a buffer be used.
ADA4938-1/ADA4938-2 Data Sheet
Rev. B | Page 22 of 26
Table 10 and Table 11 list several common gain settings, associated
resistor values, input impedances, and output noise densities for
both balanced and unbalanced input configurations. Also shown
are the input common-mode voltages under the given conditions
for different VOCM settings for both a 10 V single supply and
±5 V dual supplies.
Table 10. Differential Ground-Referenced Input, DC-Coupled; See Figure 59
Nominal
Gain (V/V) RF (Ω) RG (Ω) RIN, dm (Ω)
Differential
Output
Noise Density
(nV/√Hz)
Common-Mode Level at +IN, −IN (V)
+V
S
= 10 V, −V
S
= 0 V
VOUT, dm = 2.0 V p-p
+V
S
= 5 V, −V
S
= −5 V
VOUT, dm = 2.0 V p-p
VOCM = 2.5 V VOCM = 3.5 V VOCM = 1.0 V VOCM = 3.2 V
1
200
200
400
6.5
1.25
1.75
0.50
1.60
2 402 200 400 10.4 0.83 1.16 0.33 1.06
3.16 402 127 254 13.4 0.60 0.84 0.24 0.77
5 402 80.6 161 18.2 0.42 0.58 0.17 0.53
Table 11. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω; See Figure 60
Nominal
Gain (V/V) RF (Ω) RG1 (Ω) RT (Ω) RIN,se (Ω) RG2 (Ω)1
Overall
Gain (V/V)2
Differential
Output
Noise
Density
(nV/√Hz)
Common-Mode Swing at +IN, −IN (V)
+VS = 10 V, −VS = 0 V
VOUT, dm = 2.0 V p-p
+VS = 5 V, −VS = −5 V
VOUT, dm = 2.0 V p-p
VOCM = 2.5 V VOCM = 3.5 V VOCM = 0 V VOCM = 2.0 V
1 200 200 60.4 267 226 0.9 6.2 1.00 to 1.50 1.50 to 2.00 −0.25 to +0.25 0.75 to 1.25
2
402
200
60.4
300
226
1.8
9.8
0.66 to 1.00
1.00 to 1.33
−0.17 to +0.17
0.50 to 0.83
3.16 402 127 66.5 205 158 2.5 11.8 0.48 to 0.72 0.72 to 0.96 −0.12 to +0.12 0.36 to 0.60
5 402 80.6 76.8 138 110 3.6 14.7 0.33 to 0.50 0.50 to 0.67 −0.08 to +0.08 0.25 to 0.42
1 RG2 = RG1 + RTS.
2 Includes effects of termination match.
Data Sheet ADA4938-1/ADA4938-2
Rev. B | Page 23 of 26
LAYOUT, GROUNDING, AND BYPASSING
As high speed devices, the ADA4938-1/ADA4938-2 are
sensitive to the PCB environment in which it operates.
Realizing its superior performance requires attention to the
details of high speed PCB design.
The first requirement is a solid ground plane that covers as much of
the board area around the ADA4938-1/ADA4938-2 as possible.
However, the area near the feedback resistors (RF), input gain
resistors (RG), and the input summing nodes should be cleared
of all ground and power planes (see Figure 66). Clearing the
ground and power planes minimizes any stray capacitance at
these nodes and prevents peaking of the response of the
amplifier at high frequencies.
The thermal resistance, θJA, is specified for the device, including
the exposed pad, soldered to a high thermal conductivity 4-layer
circuit board, as described in EIA/JESD 51-7. The exposed pad
is electrically isolated from the device; therefore, it can be con-
nected to a ground plane using vias. Examples of the thermal
attach pad and via structure for the ADA4938-1 are shown in
Figure 67 and Figure 68.
06592-008
Figure 66. Ground and Power Plane Voiding in Vicinity of RF and RG
Bypass the power supply pins as close to the device as possible
and directly to a nearby ground plane. Use high frequency ceramic
chip capacitors. It is recommended that two parallel bypass capa-
citors (1000 pF and 0.1 μF) be used for each supply with the
1000 pF capacitor placed closer to the device; if further away,
provide low frequency bypassing using 10 μF tantalum capacitors
from each supply to ground.
Signal routing should be short and direct to avoid parasitic
effects. Wherever complementary signals exist, provide a
symmetrical layout to maximize balanced performance.
When routing differential signals over a long distance, keep
PCB traces close together and twist any differential wiring to
minimize loop area. Doing this reduces radiated energy and
makes the circuit less susceptible to interference.
06592-060
1.30
0.80
0.80
1.30
Figure 67. Recommended PCB Thermal Attach Pad (ADA4938-1)
(Dimensions in mm)
06592-061
0.30
PLATED
VIA HOLE
1.30
GROUND PLANE
POWER PLANE
BOTTOM METAL
TOP METAL
Figure 68. Cross-Section of a 4-Layer PCB (ADA4938-1) Showing a Thermal Via Connection to the Buried Ground Plane (Dimensions in mm)
ADA4938-1/ADA4938-2 Data Sheet
Rev. B | Page 24 of 26
HIGH PERFORMANCE ADC DRIVING
The ADA4938-1/ADA4938-2 are ideally suited for dc-coupled
baseband applications. The circuit in Figure 69 shows a front-end
connection for an ADA4938-1/ADA4938-2 driving an AD9446,
16-bit, 80 MSPS ADC. The AD9446 achieves its optimum
performance when it is driven differentially. The ADA4938-1/
ADA4938-2 eliminate the need for a transformer to drive the
ADC, performs a single-ended-to-differential conversion,
buffers the driving signal, and provides appropriate level
shifting for dc coupling.
The ADA4938-1/ADA4938-2 are configured with a single 10 V
supply and unity gain for a single-ended input to differential
output. The 61.9 Ω termination resistor, in parallel with the
single-ended input impedance of 267 Ω, provides a 50 Ω
termination for the source. The additional 26 Ω (226 Ω total) at the
inverting input balances the parallel impedance of the 50 Ω
source and the termination resistor driving the noninverting
input.
The signal generator has a symmetric, ground-referenced bipolar
output. The VOCM pin of the ADA4938-1/ADA4938-2 is biased
with an external resistor divider to obtain the desired 3.5 V output
common-mode. One-half of the common-mode voltage is fed
back to the summing nodes, biasing −IN and +IN at 1.75 V. For a
common-mode voltage of 3.5 V, each ADA4938-1/ADA4938-2
output swings between 2.7 V and 4.3 V, providing a 3.2 V p-p
differential output.
The output of the amplifier is dc-coupled to the ADC through a
second-order, low-pass filter with a −3 dB frequency of 50 MHz.
The filter reduces the noise bandwidth of the amplifier and
isolates the driver outputs from the ADC inputs.
The AD9446 is configured for a 4.0 V p-p full-scale input by
setting R1 = R2 = 1 kΩ between the VREF pin and SENSE pin
in Figure 69.
The circuit in Figure 70 shows a simplified front-end connection
for an ADA4938-1/ADA4938-2 driving an AD9246, 14-bit,
125 MSPS ADC. The AD9246 achieves its optimum
performance when it is driven differentially. The ADA4938-1/
ADA4938-2 eliminate the need for a transformer to drive the
ADC, performs a single-ended-to-differential conversion,
buffers the driving signal, and provides appropriate level
shifting for dc coupling.
The ADA4938-1/ADA4938-2 are configured with dual ±5 V
supplies and a gain of ~2 V/V for a single-ended input to
differential output. The 76.8 Ω termination resistor, in parallel
with the single-ended input impedance of 137 Ω, provides a 50 Ω
dc termination for the source. The additional 30.1 Ω (120 Ω total)
at the inverting input balances the parallel dc impedance of the
50 Ω source and the termination resistor driving the
noninverting input.
The signal generator has a symmetric, ground-referenced
bipolar output. The VOCM pin of the ADA4938-1/ADA4938-2 is
connected to the CML pin of the AD9246 to set the output
common-mode level at the appropriate point. A portion of this
is fed back to the summing nodes, biasing −IN and +IN at 0.55 V.
For a common-mode voltage of 0.9 V, each ADA4938-1/
ADA4938-2 output swings between 0.4 V and 1.4 V, providing a
2 V p-p differential output.
The output is dc-coupled to a single-pole, low-pass filter. The filter
reduces the noise bandwidth of the amplifier and provides some
level of isolation from the switched capacitor inputs of the ADC.
The AD9246 is set for a 2 V p-p full-scale input by connecting the
SENSE pin to AGND. The inputs of the AD9246 are biased at
1 V by connecting the CML output, as shown in Figure 70.
VIN+
VIN–
47pF
30nH
30nH
24.3Ω
24.3Ω
50Ω
SIGNAL
GENERATOR 226Ω
200Ω
V
OCM
10V
ADA4938
+
61.9Ω
200Ω
200Ω
16
BUFFER T/H
ADC
CLOCK/
TIMING REF
SENSEAGND VREF
AD9446
3.3V (A)
AVDD1
5V (A)
AVDD2
3.3V (D)
DRVDD
06592-054
10V
R1 R2
Figure 69. ADA4938-1/ADA4938-2 Driving an AD9446, 16-Bit, 80 MSPS ADC
1.8V
DRVDDAVDD
VIN–
VIN+
AD9246
AGND CMLSENSE
D13 TO
D0
10pF
33Ω
V
OCM
33Ω
50Ω
V
IN
90Ω
90Ω
76.8Ω+5V
–5V
ADA4938
+
200Ω
200Ω
30.1Ω
0.1µF
06592-056
Figure 70. ADA4938-1/ADA4938-2 Driving an AD9246, a 14-Bit, 125 MSPS ADC
Data Sheet ADA4938-1/ADA4938-2
Rev. B | Page 25 of 26
OUTLINE DIMENSIONS
1.45
1.30 SQ
1.15
111808-A
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12 13
4
EXPOSED
PAD
PIN 1
INDICATOR
3.10
3.00 SQ
2.90
0.50
0.40
0.30
SEATING
PLANE
0.05 M AX
0.02 NO M
0.20 REF
0.25 M IN
COPLANARITY
0.08
PIN 1
INDICATOR
0.30
0.23
0.18
COMPLIANT
TO
JEDEC STANDARDS M O-220- WEED.
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFI G URATI ON AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
0.80
0.75
0.70
Figure 71. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-21)
Dimensions shown in millimeters
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.20
COMPLIANT
TO
JEDEC STANDARDS M O-220- WGGD-8.
06-11-2012-A
BOTTOM VIEWTOP VIEW
EXPOSED
PAD
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70
0.20 REF
0.25 M IN
COPLANARITY
0.08
PIN 1
INDICATOR
2.20
2.10 SQ
2.00
1
24
7
12
13
1819
6
FOR PRO P E R CONNECT IO N OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFI G URATI ON AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
0.05 M AX
0.02 NO M
Figure 72. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body, and 0.75 mm Package Height
(CP-24-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Ordering Quantity Branding
ADA4938-1ACPZ-R2
−40°C to +85°C
16-Lead LFCSP
CP-16-21
250
H11
ADA4938-1ACPZ-RL −40°C to +85°C 16-Lead LFCSP CP-16-21 5,000 H11
ADA4938-1ACPZ-R7 −40°C to +85°C 16-Lead LFCSP CP-16-21 1,500 H11
ADA4938-2ACPZ-R2 −40°C to +85°C 24-Lead LFCSP CP-24-10 250
ADA4938-2ACPZ-RL −40°C to +85°C 24-Lead LFCSP CP-24-10 5,000
ADA4938-2ACPZ-R7 −40°C to +85°C 24-Lead LFCSP CP-24-10 1,500
1 Z = RoHS Compliant Part
