TOSHIBA TC9322FA/FB TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC9322FA, TC9322FB SINGLE CHIP DTS MICROCONTROLLER (DTS-21) The TC9322FA and TC9322FB are a 4bit CMOS microcontroller for signal chip digital tuning systems. It is capable of functioning at a low voltage of 3V and features a built-in prescaler of operating 230MHz, PLL and LCD drivers. The CPU has 4bit parallel addition and subtraction instructions (e.g., Al, SI), logic operation instructions (e.g., OR, AND), composite judging and compare instructions (e.g., TM, SL), and time-base functions. The package is an pin 64, 0.5/0.65-mm-pitch quad flat pack package. In addition to various input/output ports and a dedicated key-input port, which are controlled by powerful input/output instructions (IN 1, 2, OUT 1, 2), there are many dedicated LCD pins, a buzzer port, a 6bit A/D converter, an IF counter, and other pins. Low-voltage and low-current consumption make this microcontroller suitable for portable DTS equipment. FEATURES Abit microcontroller for digital tuning systems. Operating voltage Vpp=1.8~3.6V, with low current consumption because of CMOS circuitry (with only CPU operating, when Vpp = 3V, Ipp = 804A Max.) Built-in prescaler (1/2 fixed divider +2 modulus prescaler TC9322FA LQFP64-P-1010-0.50 TC9322FB QFP64-P-1212-0.65 Weight LQFP64-P-1010-0.50 : 0.329 (Typ.) QFP64-P-1212-0.65 _: 0.45g (Typ.) : fmax= 230MHz) Features built-in 1/3-duty, 1/2-bias LCD drivers and a built-in 3V booster circuit for the display. Data memory (RAM) and ports are easily backed up. Program memory (ROM): 16bit x 3072 steps Data memory (RAM) : Abit x 192 words 62-instruction set (all one-word instructions) 2001-06-19TOSHIBA TC9322FA/FB Instruction execution time : 40s (with 75kHz crystal) (MVGS, DAL instructions : 80s) @ Many addition and subtraction instructions (12 types addition, 12 types subtraction) @ Powerful composite judging instructions (TMTR, TMFR, TMT, TMF, TMTN, TMFN) @ Data can be transmitted between addresses on the same row. (MVSR instruction) Register indirect transfer available (MVGD, MVGS instruction). @ 16 powerful general registers (located in RAM) Stack levels : 2 @ JUMP or CAL instruction can be used anywhere in the 3072 steps of program memory (ROM) as there are no pages or fields. @ 16bit of any address in the 1024 steps in program memory (ROM) can be referenced (DAL instruction). @ Features independent frequency input pins (FMjj and AMjj,) and two (DO1 and DO2) phase comparison outputs for FM/VHF and AM. @ Seven reference frequencies can be selected by program. @ Powerful input/output instructions (IN 1, 2, OUT 1, 2) Dedicated input ports (Kg~K3) for key input. 26 LCD drive pins (69 segments maximum) available. @ 17 1/0 ports : 10 with input/output programmable in 1bit units, and 7 output-only port. The 2 IFixy. and DO1 pins can be switched by instruction to IN (input-only) or OT (output-only). @ Three back-up modes available by instruction : only CPU operation, crystal oscillation only, clock stop. @ Features a built-in 2Hz timer F/F and a built-in 10/100Hz interval pulse output (internal port for time base). @ Allows PLL lock status detection. 8 of the LCD segment outputs (S4g~523) can also operate as key return timing outputs (KRg~KR7). The 1/O ports are not dedicated key return timing outputs but can have other uses as well. @ Built-in 20bit, general-purpose IF counter can detect stations during auto-tuning by counting the intermediate frequencies of each band. @ Built-in 8bit buzzer output circuit can produce 254 different tone signals. @ Features a built-in 2-channel, 6bit A/D converter. @ To prevent CPU malfunctions, a built-in supply voltage drop detection circuit shuts down the CPU when voltage falls below 1.5V. 2 2001-06-19TOSHIBA TC9322FA/FB PIN CONNECTION BUZR Output A/D Converter | re l ca A Nn = < 22 Ss bo 0 2 644 re Pe oO Mn H OM N KH OD wn Po uo Dammann nn Nn g- - - - OH tT HN FF B a oOo O98 oO 0D O09 Of D BD FF KF F Radio ON/OFF O- HOLD 1/0 Port Key Return Ty Timing IF Signal -- IFijy/IN Output Port L_ To Phase D01/0T K3 Comparison Output ~ _ )D02 Key Input Kp Port ._ an Ky Local >i _FMIn Ko Oscillator Signal rk _ AMin $23 /KRo Battery oT Vpb (TOP VIEW) $22/KRq 75kH RESET $21/KR2 2 Key Return x Wr OUT Timing S29/KR3 joa XIN Output Port Sig/KRq js VxT Sig/KRs5 4r Vic $17/KRg Cy S16/KR 16/KR7 Co $15 4H Vee LCD Driver (3x23 =69max. SEGMENT) $14 cr Nm tT DH Oo he DOD Hh D-H NM ny nn FH HF YF YM HM - - - = YF YF A WY cOoM1 COM2 CcOM3 3 2001-06-19TOSHIBA BLOCK DIAGRAM HOLD XOuUT XIN VXT FMIN AMIN IFin/IN > v 2 co = mo a o oO v @ a 10Hz CPU Timing Gene. 2Hz F/F Reference Divider MPX/La. 1kHz PLL OFF Abit Swallow 1/15, 16 Counter /La. HF 1kHz 20bit IF Counter DATA BUS CODE BUS ROM (16x 3072 Step) Instruction Dec. Prog. Counter 12 Stack Reg. (2Level) S00Hz KEY SCAN TIMING GENE. Vv Segment Driver/La. Data La $19/KR5 23/ Ko Ky K2 K3 TC9322FA/FB UNLOCK F/F DO1/OT DO2 Phase Com. La. MUTE MUTE Cont. 12bit Programmable Counter /La. 1/O-1 8bit BUZR P3-1/BUZR RAM P3-0 (4x 192 word) P2-3 / DC-REF 4 P2-2/AD|N2 R/W Buf P2-1/ADiN1 P2-0 4 6bit A/D VEE P1-3 P1-2 P1-1 P1-0 RESET Power ON RESET Vpp GND Doubler Circuit To % T2 T3 T4 T5 uu No uu UY > VLceD 2001-06-19TOSHIBA TC9322FA/FB EXPLANATION OF FUNCTION PIN No. SYMBOL PIN NAME FUNCTION AND OPERATION REMARKS cOM1 CcCOM2 CcOM3 LCD common output Output common signals to the LCD panel. Through a matrix with pins $1~S23, a maximum of 69 segments can be displayed. Three levels, Vicp, Veg, and GND, are output at 83Hz every 2ms. Veg is output after SYSTEM RESET and CLOCK STOP are released, and a common signal is output after the DISP OFF bit is set to "0". 4~18 $1~515 LCD segment output 19~26 $16 /KR7 5 $23/KRg LCD segment output / Key return timing output Segment signal output pins for the LCD panel. Together with COM1, COM2, and COM3, a matrix is formed that can display a maximum of 69 segments. The signals for the key matrix and the segment signals from pins $16 /KR7~S$23 / KRg are output on a time division basis. 4x8=32 key matrix can be created in conjunction with key input ports Kg~K3. VLCD 27~30 Kg~K3 Key input ports Abit input ports for key matrix input. Combined in a matrix with key return timing outputs of the LCD segment pins, data from a maximum of 4x8 = 32 keys can be input and pins are pulled up. On the key seteutining output pins, data from 4x6=24 keys can be input and pins are pulled down. The WAIT mode is released when high level is applied to key input ports set to pull-down. 31~36 Tg~T5 Key return timing output port These ports output the timing signal for key matrix. To form the key matrix, load resistance has been built-in the N-channel side. When the key matrix combined with push-key, that does not need a key matrix diode. RON 37~40 1/O port 1 The input and output of these 4bit 1/O ports can be programmed in 1bit units. By altering the input to |/O ports set to input, the CLOCK STOP and WAIT modes can be released, and the MUTE bit of the MUTE pin can be set to "1". 2001-06-19TOSHIBA TC9322FA/FB PIN No.| SYMBOL PIN NAME FUNCTION AND OPERATION REMARKS P2-0 P2-1/ ADIN1 41~44 | 599 / AD|N2 P2-3 / DC-REF 1/O port 2 /AD analog voltage input /AD analog voltage input / Reference voltage input Abit |/O ports. Input and output may be programmed in 1bit units. Pins P2-1 through P2-2 can also be used for analog input to the built-in 6bit, 2- channel A/D converter. Conversion time of the built-in A/D converter using the successive comparison method is 280s. The necessary pin can be programmed to AD analog input in 1bit units, and P2-3 can be set to the reference voltage input. Internal power supply (Vpp) or constant voltage (VEE) can be used as the reference voltage. In addition, constant voltage (VEE) can be input to the AD analog input so battery voltage, etc., can be easily detected. The reference voltage input, for which a built-in operational amp is used, has high impedance. The A/D converter, and their control are all executed by program. To A/D converter (P2-0 pin is excluded) P3-0 45~46 P3-1/ BUZR 1/O port 3 /Buzzer output 2bit |1/O ports, whose input/output can be programmed in 1bit units. The P3-1 pin also functions as the output for the built-in buzzer circuit. The buzzer sound can be output in 254 different tones between 18.75kHz and 147Hz, and at a duty of 50%. The buzzer output, and all associated controls can be programmed. 47 MUTE Muting output port 1bit output port. Normally, this port is used for muting control signal output. This pin can set the internal MUTE bit to "1" according to a change in the input of 1/O port 1. MUTE bit output logic can be changed ; PLL phase difference can also be output using this pin. 48 TEST TEST mode control input Input pin used for controlling TEST mode. High level indicates TEST mode, while low level indicates normal operation. The pin is normally used at low level or no-connection (NC). (A pull- down resistor is built-in). RIN2 2001-06-19TOSHIBA TC9322FA/FB PIN No. SYMBOL PIN NAME FUNCTION AND OPERATION REMARKS 49 HOLD mode control input Input pin for request/release HOLD mode. Normally, this pin is used to input radio mode selection signals or battery detection signals. HOLD mode includes CLOCK STOP mode (stops crystal oscillation) and WAIT mode (halts CPU). Setting is implemented with the CKSTP instruction or the WAIT instruction. When the CKSTP instruction is executed, request/release of the HOLD mode depends on the internal MODE bit. If the MODE bit is 0 (MODE-Q), executing the CKSTP instruction while the HOLD pin is at low level stops the clock generator and the CPU and changes to memory back-up mode. If the MODE bit is 1 (MODE-1), executing the CKSTP instruction enters memory back-up mode regardless of the level of the HOLD pin. Memory back-up is released when the HOLD pin goes high in MODE-O, or when the level of the HOLD pin level in MODE-1. When memory back-up mode is entered by executing a WAIT instruction, any change in the HOLD pin input releases the mode. In memory back-up mode, current consumption is low (below 104A), and all the output pins (e.g., display output, output ports) are automatically set to low level. 50 [FIN / IN IF signal input/ Input port IF counters IF signal input pin for counting the IF signals of the FM and AM bands and detecting the automatic stop position. The input frequency is between 0.35~12MHz (0.2Vp-p (Min) ). A built-in input amp and C coupling allow operation at low-level input. The IF counter is a 20bit counter with optional gate times of 1, 4, 16, and 64ms. 20 bits of data can be readily stored in memory. This input pin can be programmed for use as an input port (IN port). CMOS input is used when the pin is set as an IN port. Rein2 2001-06-19TOSHIBA TC9322FA/FB PIN No. SYMBOL PIN NAME FUNCTION AND OPERATION REMARKS 51 52 DO1/0T DO2 Phase comparison output / Output port Phase comparison output PLLs phase comparison tri-state output pins. When the programmable counters prescaler output is higher than the reference frequency, output is at high level. When output is lower than the reference frequency, output is at low level. When output equals the reference frequency, high impedance output is obtained. Because DO1 and DO2 are output in parallel, optimal filter constants can be designed for the FM/VHF and AM bands. Pin DO1 can be programmed to high impedance or programmed as an output port (OT). Thus, the pins can be used to improve lock-up time or used as output ports. 56 VDD 53 GND Power-supply pins Pins to which power is applied. Normally, Vpp = 1.8~3.6V (3.0V Typ.) is applied. In back-up mode (when CKSTP instructions are being executed), voltage can be lowered to 1.0V. If voltage falls below 1.5V while the CPU is operating, the CPU stops to prevent malfunction (STOP mode). When the voltage rises above 1.5V, the CPU restarts. STOP mode can be detected by checking the STOP F/F bit. If necessary, execute initialization or adjust clock by program. When detecting or preventing CPU malfunctions using an external circuit, STOP mode can be invalidated and rendered non-operative by program. In that case, all four bits of the internal TEST port should be set to 1. If more than 1.8V is applied when the pin voltage is 0, the device's system is reset and the program starts from address 0. (Power on reset) (Note) To operate the power on reset, the power supply should start up in 10~100ms. { VpD 1 GND 2001-06-19TOSHIBA TC9322FA/FB PIN No.| SYMBOL PIN NAME FUNCTION AND OPERATION REMARKS 54 FMin FM programmable counter input Programmable counter input pin for FM, VHF band. The 1/2+ pulse swallow system (VHF mode) and the pulse swallow system (FM mode) are selectable freely by program. At the VHF mode, local oscillation output (VCO output) of 50~230MHz (0.2Vp-p (Min)) is input and FM mode, 40~130MHz (0.2Vp.p (Min) ) is input. A built-in input amp and C coupling allow operation at low-level input. (Note) When in the PLL OFF mode or when set to AMjy input, the input is pulled down. Rint 55 AMIN AM local oscillator signal input Programmable counter input pin for AM band. The pulse swallow system (HF mode) and direct dividing system (LF mode) are freely selectable by program. At the HF mode, local oscillation output (VCO output) of 1~45MHz (0.2Vp-p (Min) ) is input and LF mode, 0.5~12MHz (0.2Vp-p (Min) ) is input. Built-in input amp operates with low- level input using a C coupling. (Note) When in PLL OFF mode or when set to FMjy input, the input is pulled down. Rint 57 RESET Reset input Input pin for system reset signals. RESET takes place while at low level ; at high level, the program starts from address Q". Normally, if more than 1.8V is supplied to Vpp when the voltage is 0, the system is reset (Power on reset). Accordingly, this pin should be set to high level during operation. Hf, 58 XOUT 59 XIN 60 VyXT Crystal oscillator pins Crystal oscillator pins. A reference 75kHz crystal oscillator is connected to the Xiyy and XgyT pins. The oscillator stops oscillating during CKSTP instruction execution. The VyT pin is the power supply for the crystal oscillator. A stabilizing capacitor (0.47 F Typ.) is connected. O ROUT Xout _ Rext | VXT XIN 2001-06-19TOSHIBA TC9322FA/FB PIN No.| SYMBOL PIN NAME FUNCTION AND OPERATION REMARKS Voltage doubler boosting pin for driving the LCD. 61 VLCD A capacitor (0.14F Typ.) is connected to boost the voltage. The Vicp pin outputs voltage (3.0V), which has been doubled from the constant voltage (Veg : 1.5V) using the Voltage . capacitors connected between Cy and Cp. ee 62 Cy doubler ys . boosting pin That potential is supplied to the LCD drivers. If the internal VLcp OFF bit is set to 1 by program, an external power supply can be input through the Vicp pin to drive the LCD. 63 C2 At this time, the Vicp/2 potential, whose Vicp voltage is divided using registers, is output from the C3 pin. 1.5V constant voltage supply pin for Constant A statlizing capacitor (O.14F Typ.) is 64 VEE voltage supply connected. This is a reference voltage for i pin the A/D converter, key input, and the LCD common outputs bias potential. (Note 1) When the device is reset (voltage higher than 1.8V, or when RESET = low-high) 1/O ports are set to input, the pins for |1/O ports and additional functions (e.g., A/D converter) are set to 1/O port input pins, while the IFiy/IN pins become IF input pins. (Note 2) When in PLL OFF mode (when the three bits in the internal reference ports all show "1"), the IFix_y and FMjy, AMiy pins are pulled down, and DO1 and DO2 are at high impedance. (Note 3) When in CLOCK STOP mode (during execution of CKSTP instruction), the output ports and the LCD output pins are all at low level, while the constant voltage circuit (Veg), the voltage doubler circuit (VLcp), and the power supply for the crystal oscillator (VyTq) are all off. (Note 4) When the device is being reset, the contents of the output ports and internal ports are undefined and initialization by program is necessary. 10 2001-06-19TOSHIBA TC9322FA/FB MAXIMUM RATINGS (Ta = 25C) CHARACTERISTIC SYMBOL RATING UNIT Supply Voltage Vpp -0.3~4.0 Vv Input Voltage VIN -0.3~Vpp + 0.3 V Power Dissipation Pp 100 mw Operating Temperature Topr - 10~60 C Storage Temperature Tstg -55~125 C ELECTRICAL CHARACTERISTICS (Unless otherwise noted, Ta =25C, Vpp = 3.0V) TEST CHARACTERISTIC SYMBOL | CIR- TEST CONDITION MIN. | TYP. | MAX. | UNIT CUIT Range Of Operating Vv _ * 1. . . Supply Voltage DD 8 3.0) 36 Vv Range Of Memory Vv Crystal ocillation stopped 10| ~ 36 Retention Voltage HD (CKSTP instruction executed) . . Under ordinary operation and PLL on operation, no output | Vpp=3.0V; 7.0 12 load | FM = 230MHz input mA DDI ~~ |Under ordinary operation and PLL on operation, no output | Vpp=3.0V; 6.0 10 load FMN = 130MHz input Operating Current Under CPU operation only IDD2 (PLL off, display VDD =3.0V) 40) 80 turned on) Soft Wait mode IDD3 |(Crystal oscllator, display circuit 25 50 |} A operating, CPU stopped, PLL off) Hard Wait mode 15 30 DD4 (Crystal oscillator operating only) Memory Retention Crystal oscillation stopped 0.1 10 Current HD (CKSTP instruction executed) , Crystal Oscillation + Frequency XT 7 i 75) | kHz Crystal Oscillation vgs I lI fyt = 75kH 1. Startup Time tsT Crystal oscillation fyq7 =75kHz 0 s For conditions marked by an asterisk (*), guaranteed when Vpp = 1.8~3.6V, Ta= 10~60C. 11 2001-06-19TOSHIBA TC9322FA/FB TEST CHARACTERISTIC SYMBOL| CIR- TEST CONDITION MIN. | TYP. | MAX.) UNIT CUIT Voltage doubler circuit Voltage Doubler Vv ND ref V 1. 1. 1.7 Reference Voltage EE G reference (Veg) 3 > V Constant Voltage Temperature Dy |GND reference (Vef) -5; Imv/c Characteristics Voltage Doubler Vv ND ref V 2. . A Boosting Voltage LCD GND reference (Vicp) 6]; 3.0] 3 Vv Operating frequency ranges for programmable counter and IF counter FM in (VHF Mode) fVHF |Sine wave input when Vin =0.2Vp.p 50) ~ 230 FMin (FM Mode) fFM |Sine wave input when Vin =0.2Vp.p 40; ~ 130 AM|n (HF Mode) fHL |Sine wave input when Viy =0.2Vp-p 1} ~ 45 | MHz AM|n (LF Mode) fLF |Sine wave input when Vij =0.2Vp.p 0.5) ~ 12 IFIN fiF |Sine wave input when Vin =0.2Vp.p 0.35; ~ 12 . . Vv Input Amplitude VIN |FMin, AM|N, !FiN input 0.2]; ~ OR Vp-p LCD common output/segment output (COM1~COM3, $1~5S23) Output "H Level | loH1 |Vicp =3V, VOH =2.7V -0.5) -1.0) mA Current [L Level | loi |Vicp =3V, VoL =0.3V 0.5{ 1.0) Output Voltage 1/2 | | _ | No load 1.3} 15; 17) Vv Level HOLD input port Input Leak Current ILI |VIH=3.0V, ViL=0V _ 1.0) A Input H Level | Vin4 2.4, ~ 3.0 V Voltage |L" Level | ViL4 Oo; ~ 1.2 A/D converter (A/Din1, A/DjnN2, DC-REF) Analog Input Voltage V |AD\n1, AD Oo} ~ V Vv Range AD IN1 IN2 DD Anal Ref V nalog nererence Veer | |DC-REF, Vpp =2.0~3.6V 1.0} ~ | P| vy Voltage Range x0.9 Resolution Vres | 6.0) bit Conversion Total | |Vpp=2.0~3.6v | 10] +4.) LsB Error VIH =3.0V, Vip =0V + Analog Input Leak Nut | (Adina, ADjN>, DC-REF) | 1.0) A For conditions marked by an asterisk (*), guaranteed when Vpp = 1.8~3.6V, Ta= 10~60C. 12 2001-06-19TOSHIBA TC9322FA/FB TEST CHARACTERISTIC SYMBOL] CIR- TEST CONDITION MIN. | TYP. |MAX.) UNIT CUIT KEY input port (Kg~K3) N-ch/P-ch Input . R 75] 150} 300) kO, Resistance IN1 Input H" Level | Viq2 | |When input with pull-down resistance 1.8) ~ 3.0 V Voltage |L" Level | ViL2 |When input with pull-down resistance 0) ~ 0.3 Input H" Level | Vin3 |When input with pull-up resistance 2.7, ~ 3.0 V Voltage |L" Level | ViL3 |When input with pull-up resistance 0) ~ 1.2 When input resistance off | Leak | , a A nput Leak Current LI Vin =3.0V, Vj, =0V 0} 4 Timing output port (TO~T5) Output H" Level IOH1 _ VOH =2.7V -~0.5| -1.0 _ mA Current | L" Level lout |Vo_=0.3V, Use LCD key-return mode 0.5} 1.0) N-ch Load Resistance | Ron |No used LCD key-return mode 75| 150} 300} kQ, DO1/OT, DO2 output ; MUTE output Output "H" Level | loH1 |VOH =2.7V -0.5] -1.0) mA Current ["L Level | lou, | [VoL =0.3V 0.5] 1.0; Output Off Leak _ = = _ {+ Current ITL VTLH =3.0V, VTLL=OV (DO1, DO2) +100) nA General-purpose |/O ports (P1-0~P3-1) Output |H" Level | lon1 | |VoH=2.7V -0.5] - 1.0] A Current |L Level | lo.y | |Vo_=0.3V 0.5/1.0) | Input Leak Current ILI |VipH =3.0V, Vi_=O0V 1.0) A Input "H" Level | Ving 2.4, ~ 3.0 V Voltage |L Level | Vita Oo; ~ 0.6 IN, RESET input port Input Leak Current ll | Vip =3.0V, Vi_L=OV _ 1.0) A Input H" Level | Vina 2.4, ~ 3.0 V Voltage |L" Level | Vita 0} ~ 0.6 13 2001-06-19TOSHIBA TC9322FA/FB TEST CHARACTERISTIC |SYMBOL| CIR- TEST CONDITION MIN. | TYP. | MAX. | UNIT CUIT Others Input Pull-Down Resistance RiIn2 | (TEST) 25 50} 100} kQ XIN Amp Feedback Resistance RexT | | &in-Xour) ~~ 20) | MO XOUT Output Resistance Rout | | our) ~~ 3) | ko Input Amp Feedback | RfIN1 |(FMin, AMIN) 150} 300] 600 KO Resistance Reinz | | (Fin) 500] 1000] 2000 Voltage Used To Detect Supply Voltage | Vstp |(Vpp) 1.3] 1.5] 1.6) V Drop Supply Voltage Drop Detection Temperature] Ds |(Vpp) -2) Imv/c Characteristics 14 2001-06-19TC9322FA/FB TOSHIBA PACKAGE DIMENSIONS LQFP64-P-1010-0.50 Unit : mm 12.0+0.2 - 10.0+0.2 1.25TYP 10.040.2 12.0+0.2 Ht 16 1.25TYP .2+0. 0.08 (uy Weight : 0.32g (Typ.) 2001-06-19 15TOSHIBA TC9322FA/FB PACKAGE DIMENSIONS QFP64-P-1212-0.65 Unit : mm 14.0+0.2 ; 12.0+0.2 ; 48 33 S| RASHRRRRP ARAB AR WD iP S Nia 49 =} En 32 om Ho tro CTT} co Cro oo IO nN N oy Fo 5 om Hor S| & co F344 ao o om 1 al wz on hoo ~~ cm [TT oo CT oo rTT co Coo 64 oh po 17 HHERRERRERERHERE L fo | 16 1.125TYP: | | | 0.340.1 610.130) 0.65 13.010.2 Weight : 0.45g (Typ.) 16 2001-06-19TOSHIBA TC9322FA/FB RESTRICTIONS ON PRODUCT USE 000707EBA @ TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the Handling Guide for Semiconductor Devices, or TOSHIBA Semiconductor Reliability Handbook etc.. @ The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (Unintended Usage). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. @ The products described in this document are subject to the foreign exchange and foreign trade laws. @ The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 17 2001-06-19