FM24CL64B
64-Kbit (8 K × 8) Serial (I2C) F-RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-84458 Rev. *E Revised November 11, 2014
256-Kbit (32 K × 8) Serial (I2C) nvSRAM
Features
■64-Kbit ferroelectric random access memory (F-RAM) logically
organized as 8 K × 8
❐High-endurance 100 trillion (1014) read/writes
❐151-year data retention (See the Data Retention and
Endurance table)
❐NoDelay™ writes
❐Advanced high-reliability ferroelectric process
■Fast 2-wire Serial interface (I2C)
❐Up to 1-MHz frequency
❐Direct hardware replacement for serial (I2C) EEPROM
❐Supports legacy timings for 100 kHz and 400 kHz
■Low power consumption
❐100 A (typ) active current at 100 kHz
❐3 A (typ) standby current
■Voltage operation: VDD = 2.7 V to 3.65 V
■Industrial temperature: –40 C to +85 C
■Packages
❐8-pin small outline integrated circuit (SOIC) package
❐8-pin thin dual flat no leads (TDFN) package
■Restriction of hazardous substances (RoHS) compliant
Functional Overview
The FM24CL64B is a 64-Kbit nonvolatile memory employing an
advanced ferroelectric process. A ferroelectric random access
memory or F-RAM is nonvolatile and performs reads and writes
similar to a RAM. It provides reliable data retention for 151 years
while eliminating the complexities, overhead, and system-level
reliability problems caused by EEPROM and other nonvolatile
memories.
Unlike EEPROM, the FM24CL64B perf orms write operations at
bus speed. No write delays are incurred. Data is written to the
memory array immediately after each byte is successfully
transferred to the device. The next bus cycle can commence
without the need for data polling. In addition, the product offers
substantial write endurance compared with other nonvolatile
memories. Also, F-RAM exhibits much lower power during writes
than EEPROM since write operations do not require an internally
elevated power supply voltage for write circuits. The
FM24CL64B is capable of supporting 1014 read/write cycles, or
100 million times more write cycles than EEPROM.
These capabilities make the FM24CL64B ideal for nonvolatile
memory applications, requiring frequent or rapid writes.
Examples range from data logging, where the number of write
cycles may be critical, to demanding industrial controls where the
long write time of EEPROM can cause data loss. The
combination of features allows more frequent data writing with
less overhead for the system.
The FM24CL64B provides substantial benefits to users of serial
(I2C) EEPROM as a hardware drop-in rep lacement. T he device
specifications are guaranteed over an industrial temperature
range of –40 C to +85 C.
For a complete list of related documentation, click here.
Logic Block Diagram
Address
Latch 8 K x 8
F-RAM Array
Data Latch
8
SDA
Counter
Serial to Parallel
Converter
Control Logic
SCL
WP
A2-A0
13
8
FM24CL64B
Document Number: 001-84458 Rev. *E Page 2 of 19
Contents
Pinouts ..............................................................................3
Pin Definitions ..................................................................3
Overview ............................................................................4
Memory Architecture ................... ... .............. ... .............. ...4
I2C Interface ......................................................................4
STOP Condition (P) .....................................................4
START Condition (S) ...................................................4
Data/Address Transfer .............. ... .............. ... .. ............5
Acknowledge / No-acknowledge .................................5
Slave Device Address .................................................6
Addressing Overview ..................................................6
Data Transfer .................... .............. .. .............. ... .........6
Memory Operation ....................... ... .............. ... .............. ...6
Write Operation ........ ... .............. ... .............. ... ..............6
Read Operation ...........................................................7
Endurance .........................................................................8
Maximum Ratings .............................................................9
Operating Range ..................... .. .............. ... .............. ... ......9
DC Electrical Characteristics ......................... .................9
Data Retention and Endurance .....................................10
Capacitance ....................................................................10
Thermal Resistance ........................................................10
AC Test Loads and Waveforms .....................................11
AC Test Conditions .................... .............. ... .............. .. ...11
AC Switching Characteristi cs ......................... ..............12
Power Cycle Timing .......................................................13
Ordering Information ......................................................14
Ordering Code Definitions .........................................14
Package Diagrams ..........................................................15
Acronyms ........................................................................ 17
Document Conventions ............... ... ... .............. ... ...........17
Units of Measure ........................ ... ... .............. ... ... .....17
Document History Page ........................ ... .............. ... .. ...18
Sales, Solutions, and Legal Information ......................19
Worldwide Sales and Design Support .......................19
Products .................................................................... 19
PSoC® Solutions ......................................................19
Cypress Developer Community ...................... ... ........19
Technical Support .....................................................19
FM24CL64B
Document Number: 001-84458 Rev. *E Page 3 of 19
Pinouts Figure 1. 8-pin SOIC pinout
Figure 2. 8-pin TDF N pinout
WP
SCL
1
2
3
4 5
A0 8
7
6
VDD
SDA
A1
Top View
not to scale
V
SS
A2
A1
A0
V
SS
A2
SDA
VDD
SCL
WP
1
2
45
6
7
8
3
O
PAD
EXPOSED
Top View
not to scale
Pin Definitions
Pin Name I/O Type Description
A2-A0 Input Device Select Address 2-0. These pins are used to select one of up to 8 devices of the same type on
the same I2C bus. To select the device, the address value on the three pins must match the corre-
sponding bits contained in the slave address. The address pins are pulled down internally.
SDA Input/Output Serial Data/Address. This is a bi-directi onal pi n for the I 2C interface. It is open-drain and is intended
to be wire-AND'd with other devices on the I2C bus. The input buffer incorporates a Schmitt trigger for
noise immunity and the output driver includes slope control for falling edges. An external pull-up resistor
is required.
SCL Input Serial Clock. The serial clock pin for the I2C interface. Data is clocked out of the device on the falling
edge, and into the device o n the rising edge. T he SCL inp ut also incorporates a Schmitt trigger in put
for noise immunity.
WP Input Write Protect. When tied to VDD, addre sses in the entire memory map will be wri te-protected. Whe n
WP is connected to ground, all addresses are write enabled. This pin is pulled down internally.
VSS Power supply Ground for the device. Must be connected to the ground of the system.
VDD Power supply Power supply input to the devic e.
EXPOSED
PAD No connect The EXPOSED PAD on the bottom of 8-pin TDFN package is not connected to the die. The EXPOSED
PAD should be left floating.
FM24CL64B
Document Number: 001-84458 Rev. *E Page 4 of 19
Overview
The FM24CL64B is a serial F-RAM memory. The memory array
is logically organized as 8,192 × 8 bits and is accessed using an
industry-standard I2C interface. The functional operation of the
F-RAM is similar to serial (I2C) EEPROM. The major difference
between the FM24CL64B and a serial (I2C) EEPROM with the
same pinout is the F-RAM's superior write performance, high
endurance, and low power consumption.
Memory Architecture
When accessing the FM24CL64B, the user addresses 8K
locations of eight data bits each. These eight data bits are shifted
in or out serially. The addresses are accessed using the I2C
protocol, which includes a slave address (to distinguish other
non-memory devices) and a two-byte address. The upper 3 bits
of the address range are 'don't care' values. The complete
address of 13 bits specifies each byte address uniquely.
The access time for the memory operation is essentially zero,
beyond the time needed for the serial protocol. That is, the
memory is read or written at the speed of the I2C bus. Unlike a
serial (I2C) EEPROM, it is not necessary to poll the device for a
ready condition because writes occur at bus speed. By the time
a new bus transaction can be shifted into the device, a write
operation is complete. This is explained in more detail in the
interface secti on.
I2C Interface
The FM24CL64B employs a bi-directional I2C bus protocol using
few pins or board space. Figure 3 illustrates a typical system
configuration using the FM24CL64B in a microcontroller-based
system. The industry standard I2C bus is familiar to many users
but is described in this section.
By convention, any device that is sending data onto the bus is
the transmitter while the target device for this data is the receiver.
The device that is controlli ng the bus is the master. The master
is responsible for generatin g the clock signal for all operations.
Any device on the bus that is being controlled is a slave. The
FM24CL64B is always a slave device.
The bus protocol is controlled by transition states in the SDA and
SCL signals. There are four conditions including START, STOP,
data bit, or acknowledge. Figure 4 and Figure 5 illustrates the
signal conditions that specify the four states. Detailed timing
diagrams are shown in the electrical specifications section.
STOP Condition (P)
A STOP cond i ti on is i ndi ca te d w h en th e bu s ma ste r dri ve s SDA
from LOW to HIGH while the SCL signal is HIGH. All operations
using the FM24CL64B should end with a STOP condition. If an
operation is in progress when a STOP is asserted, the operation
will be aborted. The master must have control of SDA in order to
assert a STOP condition.
START Condition (S)
A ST AR T condition is indicated when the bus master drives SDA
from HIGH to LOW while the SCL signal is HIGH. All commands
should be preceded by a START condition. An operation in
progress can be aborted by asserting a START condition at any
time. Aborting an operation using the ST AR T condition will ready
the FM24CL64B for a new operation.
If during operation the power supply drops below the specified
VDD minimum, the system should issue a START condition prior
to performing another operation.
Figure 3. System Configuration using Serial (I2C) nvSRAM
SDA
SCL
DD
0A0A0A
A1 A1 A1
LCSLCSLCS
SDA ADSADS
PWPWPW
#0 #1 #7
A2 A2 A2
Microcontroller
V
DD
V
DD
V
RPmin = (VDD - VOLmax) / IOL
RPmax = tr / (0.8473 * Cb)
FM24CL64B
Document Number: 001-84458 Rev. *E Page 5 of 19
Data/Address Tran sf er
All data transfers (including addresses) take place while the SCL
signal is HIGH. Except under the three conditions described
above, the SDA signal should no t change while SCL is HIGH.
Acknowledge / No-acknowledge
The acknowledge takes place after the 8th data bit has been
transferred in any transaction. During this state the transmitter
should release the SDA bus to allow the receiver to drive it. The
receiver drives the SDA signal LOW to acknowledge receipt of
the byte. If the receiver does n ot drive SDA LOW, the condition
is a no-acknowledge and the operation is aborted .
The receiver would fail to acknowledge for two distinct reasons.
First is that a byte transfer fails. In this case, the no-acknowledge
ceases the current operation so that the device can be
addressed again. This allows the last byte to be recovered in the
event of a communication error.
Second and most common, th e receiver does not acknowledge
to deliberately end an operation. For example, during a read
operation, the FM24CL64B will continu e to place data onto the
bus as long as the receiver sends acknowledges (and clocks).
When a read operation is complete and no more data is needed,
the receiver must not acknowledge the last byte. If the receiver
acknowledges the last byte, this will cause the FM24CL64B to
attempt to drive the bus on the next clock while the master is
sending a new command such as STOP.
Figure 4. START and STOP Conditions
full pagewidth
SDA
SCL
P
STOP Condition
SDA
SCL
S
START Condition
Figure 5. Data Transfer on the I2C Bus
handbook, full pagewidth
S
or
P
SDA
S
P
SCL
STOP or
START
condition
S
START
condition
2 3 4 - 8 9
ACK
9
ACK
78
12
MSB Acknowledgement
signal from slave
Byte complete
Acknowledgement
signal from receiver
1
Figure 6. Acknowledge on th e I2C Bus
handbook, full pagewidth
S
START
Condition
9821
Clock pulse for
acknowledgement
No Acknowledge
Acknowledge
DATA OUTPUT
BY MASTER
DATA OUTPUT
BY SLAVE
SCL FROM
MASTER
FM24CL64B
Document Number: 001-84458 Rev. *E Page 6 of 19
Slave Device Address
The first byte that the FM24CL64B expects after a START
condition is the slave address. As shown in Figure 7, the slave
address contains the device type or slave ID, the device select
address bits, and a bit that specifies if the transaction is a read
or a write.
Bits 7-4 are the device type (slave ID) and should be set to 1010b
for the FM24CL64B. These bits allow other function types to
reside on the I2C bus within an identical address range. Bits 3-1
are the device select add ress bits. They must match the corre-
sponding value on the external address pins to select the device.
Up to eight FM24CL64B devices can reside on the same I2C bus
by assigning a different add ress to each. Bit 0 is the read/write
bit (R/W). R/W = ‘1’ indicates a read operation and R/W = ‘0’
indicates a write operation.
Addressing Overview
After the FM24CL64B (as receiver) acknowledges the slave
address, the master can place the memory address on the bus
for a write operation. The address requires two bytes. The
complete 13-bit address is latched internally. Each access
causes the latched address value to be incremented automati-
cally. The current address is the value that is held in the latch;
either a newly written value or the address following the last
access. The current address will be held for as long as power
remains or until a new value is written. Reads always use the
current address. A random read address can be loaded by
beginning a write operation as explained below.
After transmission of each data byte, just prior to the
acknowledge, the F M24CL64B increments the internal address
latch. This allows the next sequential byte to be accessed with
no additional addressing. After the last address (1FFFh) is
reached, the address latch will roll over to 0000h. There is no
limit to th e number of bytes that can be accessed with a sin gle
read or write operation.
Data Transfer
After the address bytes have been transmitted, data transfer
between the bus master an d the FM24CL64B can begin. For a
read operation the FM24CL64B will place 8 data bits on the bus
then wait for an acknowledge from the master. If the
acknowledge occurs, the FM24CL64B will transfer the next
sequential byte. If the acknowledge is not sent, the FM24CL64B
will end the read operation. For a write operation, the
FM24CL64B will accept 8 data bits from the master then send an
acknowledge. All data transfer occurs MSB (most significant bit)
first.
Memory Operation
The FM24CL64B is designed to operate in a manner very similar
to other I2C interface memory products. The major differences
result from the higher performance write capability of F-RAM
technology. These improvements result in some differences
between the FM24CL64B and a similar configuration EEPROM
during writes. The complete operation for both writes and reads
is explained below.
Write Operation
All writes begin with a slave address, then a memory address.
The bus master indicates a write operation by setting the LSB of
the slave address (R/W bit) to a '0'. After addressing, the bus
master sends each byte of data to the memory and the memory
generates an acknowledge condition. Any number of sequential
bytes may be written. If the end of the address range is reached
internally, the address counter will wrap from 1FFFh to 0000h.
Unlike other nonvolatile memory technologies, there is no
effective write delay with F-RAM. Since the read and write
access times of the underlying memory are the same , the user
experiences no delay through the bus. The entire memory cycle
occurs in less time than a single bus clock. Therefore, any
operation including read or write can occur immediately following
a write. Acknowledge polling, a techn ique used with EEPROMs
to determine if a write is complete is unnecessary and will always
return a ready condition.
Internally, an actual memory write occurs after the 8th data bit is
transferred. It will be complete before the acknowledge is sent.
Therefore, if the user desires to abort a write without altering the
memory contents, this should be done using START or STOP
condition prior to the 8th data bit. The FM24CL64B uses no page
buffering.
The memory array can be write-protected using the WP pin.
Setting the WP pin to a HIGH condition (VDD) will write-protect
all addresses. The FM24CL64B will not acknowledge data bytes
that are written to protected addresses. In addition, the address
counter will not increment if writes are attempted to these
addresses. Setting WP to a LOW state (VSS) will disable the write
protect. WP is pulled down internally.
Figure 8 and Figure 9 below illustrate a single-byte and
multiple-byte write cycles.
Figure 7. Memory Slave Device Address
handbook, halfpage
R/W
LSBMSB
Slave ID
10 10A2 A0A1
Device Select
Figure 8. Single-Byte Write
S ASlave Address 0Address MSB AData Byte A P
By Master
By F-RAM
Start Address & Data Stop
Acknowledge
Address LSB A
FM24CL64B
Document Number: 001-84458 Rev. *E Page 7 of 19
Read Operation
There are two basic types of read ope rations. They are current
address read and selective address read. In a current address
read, the FM24CL64B uses the i nternal a ddress l atch to su ppl y
the address. In a selective read, the us er performs a procedure
to set the address to a specific value.
Current Address & Sequential Read
As mentioned above the FM24CL64B uses an internal latch to
supply the address for a read operation. A current address read
uses the existing value in the address latch as a starting place
for the read operation. The system reads from the address
immediately following that of the last operation.
To perform a current address read, the bus master supplies a
slave address with the LSB set to a '1'. This indicates that a read
operation is requested. After receiving the complete slave
address, the FM24CL64B will begin shifting out data from the
current address on the next clock. The current address is the
value held in the internal address latch.
Beginning with the current address, the bus master can read any
number of bytes. Thus, a sequential read is simply a current
address read with multiple byte transfers. After each byte the
internal address counter will be incremen ted.
Note Each time the bus master acknowledges a byte, this
indicates that the FM24CL64B should read out the next
sequential byte.
There are four ways to properly terminate a read operation.
Failing to properly terminate the read will most likely create a bus
contention as the FM24CL64B attempts to read out additional
data onto the bus. The four valid methods are:
1. The bus master issues a no-acknowledge in the 9th clock
cycle and a STOP in the 10th clock cycle. This is illustrated in
the diagrams below. This is preferred.
2. The bus master issues a no-acknowledge in the 9th clock
cycle and a START in the 10th.
3. The bus master issues a STOP in the 9th clock cycle.
4. The bus master issues a START in the 9th clock cycle.
If the internal address reaches 1FFFh, it will wrap around to
0000h on the next read cycle. Figure 10 and Figure 11 below
show the proper operation for current address reads.
Figure 9. Multi-Byte Write
S ASlave Address 0Address MSB AData Byte A P
By Master
By F-RAM
Start
Address & Data Stop
Acknowledge
Address LSB AData Byte A
Figure 10. Current Address Read
S ASlave Address 1Data Byte 1 P
By Master
By F-RAM
Start Address Stop
Acknowledge
No
Acknowledge
Data
Figure 11. Sequential Read
S ASlave Address 1Data Byte 1 P
By Master
By F-RAM
Start Address Stop
Acknowledge
No
Acknowledge
Data
Data ByteA
Acknowledge
FM24CL64B
Document Number: 001-84458 Rev. *E Page 8 of 19
Selective (Random) Read
There is a simple technique that allows a user to select a random
address location as the starting point for a read operation. Thi s
involves using the first three bytes of a write operation to set the
internal address followed by subsequent read operations.
To perform a selective read, the bus master sends out the slave
address with the LSB (R/W) set to 0. This specifies a write
operation. According to the write proto col, the bus master then
sends the address bytes that are loaded into the internal address
latch. After the FM24CL64B acknowledges the address, the bus
master issues a START condition. This simultaneously aborts
the write operation and allows the read command to be issued
with the slave address LSB set to a '1 '. The operation is now a
current address read.
Endurance
The FM24C64B internally operates with a read and restore
mechanism. Therefore, endurance cycles are applied for each
read or write cycle. The memory architecture is based on an
array of rows and columns. Each read or write access causes an
endurance cycle for an entire row . In the FM24C64B, a row is 64
bits wide. Every 8-byte boundary marks the beginning of a new
row. Endurance can be optimized by ensuring frequently
accessed data is located in different rows. Regardless, FRAM
read and write endurance is effectively unlimited at the 1MHz I2C
speed. Even at 3000 accesses per second to the same
segment, 10 years time will elapse before 1 trillion endurance
cycles occur.
Figure 12. Selective (Random) Read
S ASlave Address 1Data Byte 1 P
By Master
By F-RAM
Start Address Stop
No
Acknowledge
Data
S ASlave Address 0Address MSB A
Start Address
Acknowledge
Address LSB A
FM24CL64B
Document Number: 001-84458 Rev. *E Page 9 of 19
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –55 C to +125 C
Maximum junction temperature ................................... 95 C
Supply voltage on VDD relative to VSS .........–1.0 V to +5.0 V
Input voltage .......... –1.0 V to + 5.0 V and VIN < VDD + 1.0 V
DC voltage applied to outputs
in High-Z state ....................... .............–0.5 V to VDD + 0.5 V
Transient voltage (< 20 ns) on
any pin to ground potential .................–2.0 V to VDD + 2.0 V
Package power dissipation
capability (TA = 25 °C) .................................... ... ..........1.0 W
Surface mount lead soldering
temperature (10 seconds) ....................................... +260 C
Electrostatic Discharge Voltage
Human Body Model (AEC-Q100-002 Rev. E) ..................... 4 kV
Charged Device Model (AEC-Q100-011 Rev. B) ............. 1.25 kV
Machine Model (AEC-Q100-003 Rev. E) ............................300 V
Latch-up current ....................................................> 140 mA
* Exception: The "VIN < VDD + 1.0 V" restriction does not appl y
to the SCL and SDA inputs.
Operating Range
Range Ambient Temperature (TA) VDD
Industrial –40 C to +85 C 2.7 V to 3.65 V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions Min Typ [1] Max Unit
VDD Power supply 2.7 3.3 3.65 V
IDD Average VDD current SCL toggling
between
VDD – 0.3 V and VSS,
other inputs VSS or
VDD – 0.3 V.
fSCL = 100 kHz – – 100 A
fSCL = 400 kHz – – 170 A
fSCL = 1 MHz – – 300 A
ISB Standby current SCL = SDA = VDD. All
other inputs VSS or
VDD. Stop command
issued.
–36A
ILI Input leakage current
(Except WP and A2-A0) VSS < VIN < VDD –1 – +1 A
Input leakage current
(for WP and A2-A0) VSS < VIN < VDD –1 – +100 A
ILO Output leakage current VSS < VIN < VDD –1 – +1 A
VIH Input HIGH voltage 0.7 × VDD –V
DD + 0.3 V
VIL Input LOW voltage – 0.3 – 0.3 × VDD V
VOL Output LOW voltage IOL = 3 mA – – 0.4 V
Rin[2] Input resistance (WP, A2-A0) For VIN = VIL (Max) 40 – – k
For VIN = VIH (Min) 1––M
VHYS[3] Input hysteresis 0.05 × VDD ––V
Notes
1. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested.
2. The input pull-down circuit is strong (40 k) when the input voltage is below VIL and weak (1 M) when the input voltage is above VIH.
3. This parameter is guaranteed by design and is not tested.
FM24CL64B
Document Number: 001-84458 Rev. *E Page 10 of 19
Data Retention and Endurance
Parameter Description Test condition Min Max Unit
TDR Dat a re tention TA = 85 C10–Years
TA = 75 C38–
TA = 65 C 151 –
NVCEndurance Over operating temperature 1014 – Cycles
Capacitance
Parameter [4] Description Test Conditions Max Unit
COOutput pin capacitance (SDA) TA = 25 C, f = 1 MHz, VDD = VDD(typ) 8 pF
CIInput pin capacitance 6pF
Thermal Resist ance
Parameter [4] Description Test Conditions 8-pin SOIC 8-pin TDFN Unit
JA Thermal resistance
(junction to ambient) Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA / JESD51.
147 28 C/W
JC Thermal resistance
(junction to case) 47 30 C/W
Note
4. This parameter is periodically sampled and not 100 % tested.
FM24CL64B
Document Number: 001-84458 Rev. *E Page 11 of 19
AC Test Conditions
Input pulse levels .................................10% and 90% of VDD
Input rise and fall times .................................................10 ns
Input and output timing reference levels ................0.5 × VDD
Output load capacitance ............................................100 pF
AC Test Loads and Waveforms
Figure 13. AC Test Loads and Waveforms
3.6 V
OUTPUT
100 pF
1.1 k
FM24CL64B
Document Number: 001-84458 Rev. *E Page 12 of 19
AC Switching Characteristics
Over the Operating Range
Parameter[5] Alt.
Parameter Description Min Max Min Max Min Max Unit
fSCL[6] SCL clock frequency – 0.1 – 0.4 – 1.0 MHz
tSU; STA Start condition setup for repea ted Start 4.7 – 0.6 – 0.25 – s
tHD;STA Start condition hold time 4.0 – 0.6 – 0.25 – s
tLOW Clock LOW period 4.7 – 1.3 – 0.6 – s
tHIGH Clock HIGH period 4.0–0.6–0.4–s
tSU;DAT tSU;DATA Data in setup 250 – 100 – 100 – ns
tHD;DAT tHD;DATA Data in hold 0 – 0 – 0 – ns
tDH Data output hold (from SCL @ VIL)0–0–0–ns
tR[7] trInput rise time – 1000 – 300 – 300 ns
tF[7] tfInput fall time – 300 – 300 – 100 ns
tSU;STO STOP condition setup 4.0 – 0.6 – 0.25 – s
tAA tVD;DATA SCL LOW to SDA Data Out Valid – 3 – 0.9 – 0.55 s
tBUF Bus free before new transmission 4.7 – 1.3 – 0.5 – s
tSP Noise suppression time constant on SCL, SDA – 50 – 50 – 50 ns
Figure 14. Read Bus Timing Diagram
Figure 15. Write Bus Timing Diagram
tSU:SDA
Start
tR`tF
Stop Start
tBUF
tHIGH
1/fSCL
tLOW tSP tSP
Acknowledge
tHD:DAT
tSU:DAT
tAA tDH
SCL
SDA
tSU:STO
Start Stop Start Acknowledge
tAA
tHD:DAT
tHD:STA tSU:DAT
SCL
SDA
Notes
5. Test conditions assume signal transition time of 10 n s or l ess, timing reference level s of V DD/2, input pulse levels of 0 t o VDD(typ), and output loading of the spe cified
IOL and load capacitance shown in Figure 13.
6. The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from DC to fSCL (max).
7. These parameters are guaranteed by design and are not tested .
FM24CL64B
Document Number: 001-84458 Rev. *E Page 13 of 19
Power Cycle Timing
Over the Operating Range
Parameter Description Min Max Unit
tPU Power-up VDD(min) to first access (START condition) 1 – ms
tPD Last access (STOP condition) to power-down (VDD(min)) 0 – µs
tVR [8, 9] VDD power-up ramp rate 30 –µs/V
tVF [8, 9] VDD power-down ramp rate 30 –µs/V
Figure 16. Power Cycle Timing
SDA
~
~
~
~
tPU
tVR tVF
VDD
VDD(min)
tPD
VDD(min)
I C START
2I C STOP
2
Note
8. Slope measured at any point on the VDD waveform.
9. Guaranteed by design.
FM24CL64B
Document Number: 001-84458 Rev. *E Page 14 of 19
Ordering Information
Ordering Code Package
Diagram Package Type Operating
Range
FM24CL64B-G 001-85066 8-pin SOIC Industrial
FM24CL64B-GTR
All these parts are Pb-free. Contact your local Cypress sales representative for availability of these part s.
Ordering Code Definitions
Option:
Blank = Standard; T = Tape and Reel
Package Type: G = 8-pin SOIC
Die Revision = B
Density: 64 = 64-kbit
Voltage: CL = 2.7 V to 3.65 V
I2C F-RAM
Cypress
24FM CL 64 B G TR-
FM24CL64B
Document Number: 001-84458 Rev. *E Page 15 of 19
Package Diagrams Figure 17. 8-pin SOIC (150 mils) Package Outline, 51-85066
51-85066 *F 51-85066 *F
FM24CL64B
Document Number: 001-84458 Rev. *E Page 16 of 19
Figure 18. 8-pin DFN (4.0 × 4.5 × 0.8 mm) Packag e Outline, 001-85260
Package Diagrams (continued)
001-85260 *A
FM24CL64B
Document Number: 001-84458 Rev. *E Page 17 of 19
Acronyms Document Conventions
Units of Measure
Acronym Description
ACK Acknowledge
CMOS Complementary Metal Oxide Semiconductor
EIA Electronic Industries Alliance
I2C Inter-Integrated Circuit
I/O Input/Output
JEDEC Joint Electron Devices Engine ering Council
LSB Least Significant Bit
MSB Most Significant Bit
NACK No Acknowledge
RoHS Restriction of Hazardous Substances
R/W Read/Write
SCL Serial Clock Line
SDA Serial Data Access
SOIC Small Outline Integrated Circuit
WP Write Protect
TDFN Thin Dual Flat No-lead
Symbol Unit of Measure
°C degree Celsius
Hz hertz
Kb 1024 bit
kHz kilohertz
kkilohm
MHz megahertz
Mmegaohm
Amicroampere
smicrosecond
mA milliampere
ms millisecond
ns nanosecond
ohm
%percent
pF picofarad
Vvolt
Wwatt
FM24CL64B
Document Number: 001-84458 Rev. *E Page 18 of 19
Document History Page
Document Title: FM24CL64B, 64-Kbit (8 K × 8) Serial (I2C) F-RAM
Document Number: 001-84458
Rev. ECN No. Submission
Date Orig. of
Change Description of Change
** 3902082 02/25/2013 GVCH New spec
*A 3924523 03/07/2013 GVCH Changed tPU spec value from 10 ms to 1 ms
*B 3996669 05/13/2013 GVCH Added Appen dix A - Errata for FM24CL64B
*C 4045469 06/30/2013 GVCH All errata items are fixed and the errata is removed.
*D 4283420 02/19/2014 GVCH Converted to Cypress standard format
Updated Pinouts
- Updated Figure 2 (Added EXPOSED PAD details)
Updated Pin Defini tions
- Added EXPOSED PAD details
Updated Maximum Ratings table
- Removed Moisture Sensitivity Level (MSL)
- Added junction temperature and latch up current
Added Input leakage current (ILI) for WP and A2-A0
Updated Data Retention and Endura nce tab le
Added Thermal Resistance table
Removed Package Marking Scheme (top mark)
Removed Ramtron revision history
Completing Sunset Review
*E 4564960 11/10/2014 GVCH Added related documentation hyperlink in page 1.
Document Number: 001-84458 Rev. *E Revised November 11, 2014 Page 19 of 19
All products and company names mentioned in this document may be the trademarks of their respective holders.
FM24CL64B
© Cypress Semicondu ctor Corpor ation, 2013-2014. The informatio n contai ned herei n is subject to chan ge without no tice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypre ss prod uc ts are n ot war r ant ed no r inte nd ed to be used fo r
medical, life supp or t, l if e savin g, cr it ical control or saf ety ap pl ic at io ns, unless pursuant to a n express written ag re em en t with Cypress. Furthermor e, Cyp ress doe s not author iz e its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protect ion (Unit ed States and fore ign),
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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee pr oduct to be used only in conjunction with a Cyp ress
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the express written permission of Cypress.
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a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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