100328PC - Fairchild Semiconductor

April 1989

Revised August 2000

100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch

100328

Low Power Octal ECL/T TL B i-Directional Translator

with Latch

General Description

The 100328 is an octal latched bi-directional translator

designed to convert TTL logic levels to 100K ECL logic lev-

els and vice versa. The direction of this translation is deter-

mined by the DIR input. A LOW on the outp ut enable input

(OE) ho lds the ECL ou tputs in a cut- off state and the TT L

outputs at a high impedance level. A HIGH on the latch

enable input (LE) latches the data at both inputs even

though on ly one output is enabled at the time. A LOW on

LE makes the 100328 transparent.

The cut-off state is designed to be more negative than a

normal ECL LOW l evel. This al lows the output emitte r-fol-

lowers to turn off when the termination supply is −2.0V, pre-

senting a high impedance to the data bus. This high

impedance reduces termination power and prevents loss of

low state noise margin when several loads share the bus.

The 100328 is designed with FAST TTL output buffers,

featurin g optima l DC drive an d capabl e of quickly cha rging

and discharging highly capacitive loads. All inputs have

50 kΩ pull-down resistors.

Features

■Identical performance to the 100128 at 50% of the

supply current

■Bi-directional translation

■2000V ESD protection

■Latched outputs

■FAST TTL outp uts

■3-STATE outputs

■Voltage compensated operating range = −4.2V to −5.7V

■Available to industrial grade temperature range

Ordering Code:

Devices also available in Tape and R eel. Speci fy by appending the s uffix let t er “X” to the o rdering code.

Logic Symbol Pin Descriptions

All pins function at 100K ECL levels except for T0–T7.

FAST is a register ed t radem ark of F airchild Semicon ductor Corporation.

Order Number Package Number Package Description

100328SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

100328PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

100328QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

100328QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (−40°C to +85°C)

Pin Names Description

E0–E7ECL Data I/O

T0–T7TTL Data I/O

OE Output Enable Input

LE Latch Enab le Input

DIR Direction Control Input

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100328

Connection Diagrams

24-Pin DIP/SOIC

28-Pin PLCC

Truth Table

H = HIGH Voltage Le ve l

L = LOW Voltage Level

X = Don’t Care

Z = High Impeda nc e

Note 1: ECL input to TTL output mode.

Note 2: TTL input to ECL output mode.

Note 3: Retains data present before LE set HIGH.

Note 4: Latch is transpar ent.

Functional Diagram

Note: LE, DIR, and OE use EC L logic le v els

Detail

OE DIR LE ECL TTL Notes

Port Port

LXLLOW Z

(Cut-Off)

L L H Input Z (Note 1)(Note 3)

LHHLOWInput

(Note 2)(Note 3)

(Cut-Off)

H L L L L (Note 1)(Note 4)

H L L H H (Note 1)(Note 4)

H L H X Latched (Note 1)(Note 3)

H H L L L (Note 2)(Note 4)

H H L H H (Note 2)(Note 4)

H H H Latched X (Note 2)(Note 4)

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100328

Absolute Maximum Ratings(Note 5) Recommended Operating

Conditions

Note 5: The “A bsolute Maximum Ratings” are those value s beyond whic h

the saf ety of the device cannot be gu aranteed. Th e device shou ld not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum rating.

The “R ecomm ended Ope rating Co ndition s” table will define the condit ions

for actu al device operation.

Note 6: Eith er v oltage lim it or c urrent limit is sufficie nt to protect inputs.

Note 7: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version

TTL-to-ECL DC Ele ctrical Characteristics (Note 8)

VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C, VTTL = +4.5V to +5.5V

Note 8: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional

noise immunity an d gu ardband ing c an be achi eved by d ecre asin g the al l owable syste m operating ranges. Conditi ons fo r t estin g shown i n the tables are ch o-

sen to guarante e operation under “worst case” conditions.

Storage Temperature (TSTG)−65°C to +150°C

Maximu m Junct i on Tem per atu re (T J)+150°C

VEE Pin Potential to Ground Pin −7.0V to +0.5V

VTTL Pin Potential to Ground Pin −0.5V to +6.0V

ECL Input Voltage (DC) VEE to +0.5V

ECL Output Current

(DC Output HIGH) −50 mA

TTL Input Voltage (Note 6) −0.5V to +6.0V

TTL Input Current (Note 6) −30 mA to +5.0 mA

Voltage Applied to Output

in HIGH State

3-STATE Output −0.5V to +5.5V

Current Applied to TTL

Output in LOW State (Max) twice the rated IOL (mA)

ESD (Note 7) ≥2000V

Case Temperature (TC)

Commercial 0°C to +85°C

Industrial −40°C to +85°C

ECL Supply Voltage (VEE)−5.7V to −4.2V

TTL Supply Voltage (VTTL)+4.5V to +5.5V

Symbol Parameter Min Typ Max Units Conditions

VOH Output HIGH Voltage −1025 −955 −870 mV VIN = VIH(Max) or VIL(Min)

VOL Output LOW Voltage −1830 −1705 −1620 mV Loading with 50Ω to − 2V

Cutoff Voltage OE or DIR LOW,

−2000 −1950 mV VIN = VIH(Max) or VIL(Min),

Loading with 50Ω to −2V

VOHC Output HIGH Voltage −1035 mV

Corner Point HIGH VIN = VIH(Min) or VIL(Max)

VOLC Output LOW Voltage −1610 mV Loading with 50Ω to −2V

Corner Point LOW

VIH Input HIGH Voltage 2.0 5.0 V Over VTTL, VEE, TC Range

VIL Input LOW Voltage 0 0.8 V Over VTTL, VEE, TC Ra nge

IIH Input HIGH Current 70 µAV

IN = +2.7V

Breakdown Test 1.0 mA VIN = +5.5V

IIL Input LOW Current −700 µAV

IN = +0.5V

VFCD Input Clamp Diode Voltage −1.2 V IIN = −18 mA

IEE VEE Supply Current LE LOW, OE and DIR HIGH

Inputs OPEN

−159 −75 mA VEE = −4.2V to −4.8V

−169 −75 VEE = −4.2V to −5.7V

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100328

Commercial Version (Continued)

ECL-to-TTL DC Electrical Cha racteristics (Note 9)

VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C, CL = 50 pF, VTTL = +4.5V to +5.5V

DIP TTL-to-ECL AC Electrical Characteristics (Note 9)

VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND

Note 9: The specified limits represe nt the “worst” case value for the parameter. Since these values normally occur at the temperature extremes, additional

noise immunity and guard bandi ng can be achi ev ed by decre asin g t he all owable syste m op era ti ng r anges. Co ndi ti ons fo r t est ing shown in the ta ble s are cho-

sen to guarant ee opera t ion under “worst case” conditions .

Symbol Parameter Min Typ Max Units Conditions

VOH Output HIGH Voltage 2.7 3.1 VIOH = −3 mA, VTTL = 4.75V

2.4 2.9 IOH = −3 mA, VTTL = 4.50V

VOL Output LOW Voltage 0.3 0.5 V IOL = 24 mA, VTTL = 4.50V

VIH Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal for All Inputs

VIL Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal for All Inputs

IIH Input HIGH Current 350 µAV

IN = VIH (Max)

IIL Input LOW Current 0.50 µAV

IN = VIL (Min)

IOZHT 3-STATE Current Output HIGH 70 µAV

OUT = +2.7V

IOZLT 3-STATE Current Output LOW −700 µAV

OUT = +0.5V

IOS Output Short-Circuit Current −150 −60 mA VOUT = 0.0V, VTTL = +5.5V

ITTL VTTL Supply Current 74 mA TTL Outputs LOW

49 mA TTL Outputs HIGH

67 mA TTL Outputs in 3-STATE

Symbol Parameter TC = 0°CT

C = 25°CT

C = 85°CUnits Conditions

Min Max Min Max Min Max

tPLH TN to En1.1 3.5 1.1 3.6 1.1 3.8 ns Figures 1, 2

tPHL (Transparent)

tPLH LE to En1.7 3.6 1.7 3.7 1.9 3.9 ns Figures 1, 2

tPHL

tPZH OE to En1.3 4.2 1.5 4.4 1.7 4.8 ns Figures 1, 2

(Cutoff to HIGH)

tPHZ OE to En1.5 4.5 1.6 4.5 1.6 4.6 ns Figures 1, 2

(HIGH to Cutoff)

tPHZ DIR to En1.6 4.3 1.6 4.3 1.7 4.5 ns Figures 1, 2

(HIGH to Cutoff)

tSET Tn to LE 1.1 1.1 1.1 ns Figures 1, 2

tHOLD Tn to LE 1.1 1.1 1.1 ns Figures 1, 2

tPW(H) Pulse Width LE 2.1 2.1 2.1 ns Figures 1, 2

tTLH Transition Time 0.6 1.6 0.6 1.6 0.6 1.6 ns Figures 1, 2

tTHL 20% to 80%, 80% to 20%

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100328

Commercial Version (Continued)

DIP ECL-to-TTL AC Electri cal Characteristics

VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND, CL = 50 pF

SOIC and PLCC TTL-to-ECL AC Electrical Characteristics

VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V

Note 10: O utput-to-O utput Ske w is define d as the ab solute valu e of the di fferen ce betwee n the actua l propagat ion delay for a ny outpu ts within the same

packaged dev ic e. T he spec if ic at ions apply to an y output s s w it c hing in the same direction either HIGH-t o-LOW (t OSHL), or LOW-to-HIGH (tOSLH), or in oppo-

site directions both HL and LH (tOST). Parameters tOST and tps guaranteed by design.

Symbol Parameter TC = 0°CT

C = 25°CT

C = 85°CUnits Conditions

Min Max Min Max Min Max

tPLH En to Tn2.3 5.6 2.4 5.6 2.6 5.9 ns Figures 3, 4

tPHL (Transparent)

tPLH LE to Tn3.1 7.2 3.1 7.2 3.3 7.7 ns Figures 3, 4

tPHL

tPZH OE to Tn3.4 8.45 3.7 8.95 4.0 9.7 ns Figures 3, 5

tPZL (Enable Time) 3.8 9.2 4.0 9.2 4.3 9.95

tPHZ OE to Tn3.2 8.95 3.3 8.95 3.5 9.2 ns Figures 3, 5

tPLZ (Disable Time) 3.0 7.7 3.4 8.7 4.1 9.95

tPHZ DIR to Tn2.7 8.2 2.8 8.7 3.1 8.95 ns Figures 3, 6

tPLZ (Disable Time) 2.8 7.45 3.1 7.95 4.0 9.2

tSET En to LE 1.1 1.1 1.1 ns Figures 3, 6

tHOLD En to LE 2.1 2.1 2.6 ns Figures 3, 4

tPW(H) Pulse Width LE 4.1 4.1 4.1 ns Figures 3, 7

Symbol Parameter TC = 0°CT

C = 25°CT

C = 85°CUnits Conditions

Min Max Min Max Min Max

tPLH Tn to En1.1 3.3 1.1 3.4 1.1 3.6 ns Figures 1, 2

tPHL (Transparent)

tPLH LE to En1.7 3.4 1.7 3 .5 1.9 3.7 ns Figures 1, 2

tPHL

tPZH OE to En1.3 4.0 1.5 4.2 1.7 4.6 ns Figures 1, 2

(Cutoff to HIGH)

tPHZ OE to En1.5 4.3 1.6 4.3 1.6 4.4 ns Figures 1, 2

(HIGH to Cutoff)

tPHZ DIR to En1.6 4.1 1.6 4.1 1.7 4.3 ns Figures 1, 2

(HIGH to Cutoff)

tSET Tn to LE 1.0 1.0 1.0 ns Figures 1, 2

tHOLD Tn to LE 1.0 1.0 1.0 ns Figures 1, 2

tPW(H) Pulse Width LE 2.0 2.0 2.0 ns Figures 1, 2

tTLH Transition Time 0.6 1.6 0.6 1.6 0.6 1.6 ns Figures 1, 2

tTHL 20% to 80%, 80% to 20%

tOSHL Maximum Skew Common Edge PLCC Only

Output-to-Output Variation 200 200 200 ps (Note 10)

Data to Output Path

tOSLH Maximum Skew Common Edge PLCC Only

Output-to-Output Variation 200 200 200 ps (Note 10)

Data to Output Path

tOST Maximum Skew Opposite Edge PLCC Only

Output-to-Output Variation 650 650 650 ps (Note 10)

Data to Output Path

tPS Maximum Skew PLCC Only

Pin (Signal) Transition Variation 650 650 650 ps (Note 10)

Data to Output Path

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100328

Commercial Version (Continued)

SOIC and PLCC ECL-to-TTL AC Electrical Characteristics

VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, CL = 50 pF

Note 11: Outpu t-to-Outpu t Skew is defined as t he absolu te value of the difference between the actua l propagat ion delay f or any ou tputs within the same

packaged device. T he spec if ic at ions apply to any outp ut s s w it c hing in the same direct ion either HIGH-t o-LOW (t OSHL), or LOW-to- H IG H (t OSLH), or in oppo-

site directions both HL an d LH (tOST). Parameters tOST and t PS guaranteed by design.

Symbol Parameter TC = 0°CT

C = 25°CT

C = 85°CUnits Conditions

Min Max Min Max Min Max

tPLH En to Tn2.3 5.4 2.4 5.4 2.6 5.7 ns Figures 3, 4

tPHL (Transparent)

tPLH LE to Tn3.1 7.0 3.1 7.0 3.3 7.5 ns Figures 3, 4

tPHL

tPZH OE to Tn3.4 8.25 3.7 8.75 4.0 9.5 ns Figures 3, 5

tPZL (Enable Time) 3.8 9.0 4.0 9.0 4.3 9.75

tPHZ OE to Tn3.2 8.75 3.3 8.75 3.5 9.0 ns Figures 3, 5

tPLZ (Disable Time) 3.0 7.5 3.4 8.5 4.1 9.75

tPHZ DIR to Tn2.7 8.0 2.8 8.5 3.1 8.75 ns Figures 3, 6

tPLZ (Disable Time) 2.8 7.25 3.1 7.75 4.0 9.0

tSET En to LE 1.0 1.0 1.0 ns Figures 3, 4

tHOLD En to LE 2.0 2.0 2.5 ns Figures 3, 4

tPW(H) Pulse Width LE 4.0 4.0 4.0 ns Figures 3, 4

tOSHL Maximum Skew Common Edge PLCC Only

Output-to-Output Variation 600 600 600 ps (Note 11)

Data to Output Path

tOSLH Maximum Skew Common Edge PLCC Only

Output-to-Output Variation 850 850 850 ps (Note 11)

Data to Output Path

tOST Maximum Skew Opposite Edge PLCC Only

Output-to-Output Variation 1350 1350 1350 ps (Note 11)

Data to Output Path

tPS Maximum Skew PLCC Only

Pin (Signal) Transition Variation 950 950 950 ps (Note 11)

Data to Output Path

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100328

Industri a l Version

PLCC TTL-to-ECL DC Electrical Characteristics (Note 12)

VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C, VTTL = +4.5V to +5.5V

PLCC ECL-to-TTL DC Electrica l Characteristics (Note 12)

VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C, CL = 50 pF, VTTL = +4.5V to +5.5V

Note 12: The specif ied limits represent the “worst case” v alue for t he parameter. Since th es e values norma lly occur a t t he tempe rature ex t remes, additional

noise immunity an d gu ardband ing c an be achi eved by d ecre asin g the al l owable syste m operating ranges. Conditi ons fo r t estin g shown i n the tables are ch o-

sen to guarante e operation under “worst case” conditions.

Symbol Parameter TC = −40°CT

C = 0°C to +85°CUnits Conditions

Min Max Min Max

VOH Output HIGH Voltage −1085 −870 −1025 −870 mV VIN = VIH(Max) or VIL(Min)

VOL Output LOW Voltage −1830 −1575 −1830 −1620 mV Loading with 50Ω to −2V

Cutoff Voltage OE or DIR LOW,

−1900 −1950 mV VIN= VIH(Max) or VIL(Min),

Loading with 50Ω to −2V

VOHC Output HIGH Voltage −1095 −1035 mV

Corner Point HIGH VIN = VIH(Min) or VIL(Max)

VOLC Output LOW Voltage −1565 −1610 mV Loading with 50Ω to −2V

Corner Point LOW

VIH Input HIGH Voltage 2.0 5.0 2.0 5.0 V Over VTTL, VEE, TC Range

VIL Input LOW Voltage 0 0.8 0 0.8 V Over VTTL, VEE, TC Range

IIH Input HIGH Current 70 70 µAV

IN = +2.7V

Breakdown Test 1.0 1.0 mA VIN = +5.5V

IIL Input LOW Current −700 −700 µAV

IN = +0.5V

VFCD Input Clamp Diode Voltage −1.2 −1.2 V IIN = −18 mA

IEE VEE Supply Current LE LOW, OE and DIR HIGH

Inputs OPEN

−159 −70 −159 −75 mA VEE = −4.2V to −4.8V

−169 −70 −169 −75 VEE = −4. 2V to −5.7V

Symbol Parameter TC = −40°CT

C = 0°C to +85°CUnits Conditions

Min Max Min Max

VOH Output HIGH Voltage 2.7 2.7 VIOH = −3 mA, VTTL = 4.75V

2.4 2.4 IOH = −3 mA, VTTL = 4.50V

VOL Output LOW Voltage 0.5 0.5 V IOL = 24 mA, VTTL = 4.50V

VIH Input HIGH V olta ge −1170 −870 −1165 −870 mV Guaranteed HIGH Signal for All Inputs

VIL Input LOW V olta ge −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal for All Inputs

IIH Input HIGH Current 425 350 µAV

IN = VIH (Max)

IIH Input LOW Current 0.50 0.50 µAV

IN = VIH (Min)

IOZHT 3-STATE Current Output HIGH 70 70 µAV

OUT = +2.7V

IOZLT 3-STATE Current Output LOW −700 −700 µAV

OUT = +0.5V

IOS Output Short-Circuit Current −150 −60 −150 −60 mA VOUT = 0.0V, VTTL = +5.5V

ITTL VTTL Supply Current 74 74 mA TTL Outputs LOW

49 49 TTL Outputs HIGH

67 67 TTL Outputs in 3-STATE

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100328

Industrial Vers ion (Continued)

PLCC TTL-to-ECL AC Electrical Characteristics

VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V

PLCC ECL-to-TTL AC Electrical Characteristics

VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, CL = 50 pF

Symbol Parameter TC = −40°CT

C = 25°CT

C = 85°CUnits Conditions

Min Max Min Max Min Max

tPLH Tn to En1.0 3.3 1.1 3.4 1.1 3.6 ns Figures 1, 2

tPHL (Transparent)

tPLH LE to En1.7 3.4 1.7 3.5 1.9 3.7 ns Figures 1, 2

tPHL

tPZH OE to En1.2 4.0 1.5 4.2 1.7 4.6 ns Figures 1, 2

(Cutoff to HIGH)

tPHZ OE to En1.5 4.5 1.6 4.3 1.6 4.4 ns Figures 1, 2

(HIGH to Cutoff)

tPHZ DIR to En1.6 4.1 1.6 4.1 1.7 4.3 ns Figures 1, 2

(HIGH to Cutoff)

tSET Tn to LE 2.5 1.0 1.0 ns Figures 1, 2

tHOLD Tn to LE 1.0 1.0 1.0 ns Figures 1, 2

tPW(H) Pulse Width LE 2.5 2.0 2.0 ns Figures 1, 2

tTLH Transition Time 0.4 2.3 0.6 1.6 0.6 1.6 ns Figures 1, 2

tTHL 20% to 80%, 80% to 20%

Symbol Parameter TC = 0°CT

C = 25°CT

C = 85°CUnits Conditions

Min Max Min Max Min Max

tPLH En to Tn2.3 5.4 2.4 5.4 2.6 5.7 ns Figures 3, 4

tPHL (Transparent)

tPLH LE to Tn3.1 7.4 3.1 7.0 3.3 7.5 ns Figures 3, 4

tPHL

tPZH OE to Tn3.4 8.3 3.7 8.75 4.0 9.5 ns Figures 3, 5

tPZL (Enable Time) 3.7 9.0 4.0 9.0 4.3 9.75

tPHZ OE to Tn3.2 9.0 3.3 8.75 3.5 9.0 ns Figures 3, 5

tPLZ (Dis able Time) 3.0 7.5 3.4 8.5 4.1 9.75

tPHZ DIR to Tn2.7 8.0 2.8 8.5 3.1 8.75 ns Figures 3, 5

tPLZ (Dis able Time) 2.8 7.3 3.1 7.75 4.0 9.0

tSET En to LE 2.5 1.0 1.0 ns Figures 3, 4

tHOLD En to LE 2.3 2.0 2.5 ns Figures 3, 4

tPW(H) Pulse Width LE 4.0 4.0 4.0 ns Figures 3, 4

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100328

Test Circuitry (TTL-to-ECL)

Note:

•Rt = 50Ω terminati on. Whe n an input o r output i s being m onito red by a scop e, Rt is supplied by the scope's 50Ω resist ance. W hen an input or ou t p ut is not

being m onitor ed, an extern al 50Ω resis ta nc e must be applied t o s erve as Rt.

•TTL and ECL for c e s ignals are brought to th e DUT via 50Ω coax lines .

•VTTL is decoupled to ground with 0.1 µF t o ground, VEE is de c oupled to ground w it h 0. 01 µF and VCC is connected to ground.

•For ECL input pins , t he equivalent force/ s ense circ uitry is opt ional.

FIGURE 1. TTL-to-ECL AC Test Circuit

Switching Waveforms (TTL-to-ECL)

FIGURE 2. TTL to ECL Transition—Propagation Delay and Transition Times

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100328

Test Circuitry (ECL-to-TTL)

Note:

•Rt = 50Ω termination. When an input or output is being monitored by a scope, Rt is supplied by the scope's 50Ω resi s t ance. W hen an input or ou t put i s not

being m onitored, an external 50Ω resistance m ust be ap plied to serv e as Rt.

•The TT L 3-State pull up sw it ch is co nnected to +7V only for ZL and LZ tests.

•TTL and ECL forc e signals are broug ht to th e D U T v ia 50Ω coax lines.

•VTTL is decoupled to ground with 0.1 µF, VEE is decoupled to ground with 0.01 µF and VCC is connected to ground.

FIGURE 3. ECL-to-TTL AC Test Circuit

Switching Waveforms (ECL-to-TTL)

Note: DIR is LOW, and OE is HIGH

FIGURE 4. ECL-to-TTL Transition—Propagation Delay and Transition Times

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100328

Switching Waveforms (ECL-to-TTL) (Continued)

Note: DIR is LOW, LE is HIGH

FIGURE 5. ECL-to-TTL Transition, OE to TTL Output, Enable and Disable Times

Note: OE is HIGH, LE is HIGH FIGURE 6. ECL-to-TTL Transition, DIR to TTL Output, Disable Time

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100328

Applications

FIGURE 7. Applications Diagram—MOS/TTL SRAM Interface Using 100328 ECL–TTL Latc hed Translator

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100328

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M24B

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

Package Number N24E

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100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Package Number V28A

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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